diff options
Diffstat (limited to 'tests/long/se')
15 files changed, 8902 insertions, 8910 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index 0c54e3227..bf75cb6d5 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.062553 # Number of seconds simulated -sim_ticks 62552970500 # Number of ticks simulated -final_tick 62552970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 62553193500 # Number of ticks simulated +final_tick 62553193500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 423901 # Simulator instruction rate (inst/s) -host_op_rate 426012 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 292664487 # Simulator tick rate (ticks/s) -host_mem_usage 404124 # Number of bytes of host memory used -host_seconds 213.74 # Real time elapsed on the host +host_inst_rate 434587 # Simulator instruction rate (inst/s) +host_op_rate 436752 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 300043763 # Simulator tick rate (ticks/s) +host_mem_usage 405580 # Number of bytes of host memory used +host_seconds 208.48 # Real time elapsed on the host sim_insts 90602850 # Number of instructions simulated sim_ops 91054081 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 947264 # Number of bytes read from this memory system.physmem.bytes_read::total 996736 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 49472 # Nu system.physmem.num_reads::cpu.inst 773 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14801 # Number of read requests responded to by this memory system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 790882 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 15143390 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15934271 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 790882 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 790882 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 790882 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 15143390 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15934271 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 790879 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 15143336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15934214 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 790879 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 790879 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 790879 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 15143336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15934214 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15574 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 62552869500 # Total gap between requests +system.physmem.totGap 62553092500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -201,12 +201,12 @@ system.physmem.bytesPerActivate::768-895 41 2.66% 50.78% # By system.physmem.bytesPerActivate::896-1023 66 4.29% 55.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 692 44.94% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1540 # Bytes accessed per row activation -system.physmem.totQLat 211081250 # Total ticks spent queuing -system.physmem.totMemAccLat 503093750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 211075250 # Total ticks spent queuing +system.physmem.totMemAccLat 503087750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13553.44 # Average queueing delay per DRAM burst +system.physmem.avgQLat 13553.05 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32303.44 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 32303.05 # Average memory access latency per DRAM burst system.physmem.avgRdBW 15.93 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 15.93 # Average system read bandwidth in MiByte/s @@ -221,24 +221,24 @@ system.physmem.readRowHits 14027 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 90.07 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4016493.48 # Average gap between requests +system.physmem.avgGap 4016507.80 # Average gap between requests system.physmem.pageHitRate 90.07 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 6047580 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 3202980 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 58533720 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 210821520.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 136599930 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 8776800 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 736788270 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 212075520 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 14428808400 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 15801654720 # Total energy per rank (pJ) -system.physmem_0.averagePower 252.612376 # Core power per rank (mW) -system.physmem_0.totalIdleTime 62230500750 # Total Idle time Per DRAM Rank +system.physmem_0.actBackEnergy 136590810 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 8775360 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 736795110 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 212078880 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 14428861800 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 15801707760 # Total energy per rank (pJ) +system.physmem_0.averagePower 252.612326 # Core power per rank (mW) +system.physmem_0.totalIdleTime 62230723750 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 9906000 # Time in different power states system.physmem_0.memoryStateTime::REF 89372000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 60062510500 # Time in different power states +system.physmem_0.memoryStateTime::SREF 60062733500 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 552254250 # Time in different power states system.physmem_0.memoryStateTime::ACT 223131000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 1615796750 # Time in different power states @@ -247,21 +247,21 @@ system.physmem_1.preEnergy 2641320 # En system.physmem_1.readEnergy 52664640 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 256919520.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 136420380 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 13274400 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 827381220 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 248160000 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 14377425165 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 15919954335 # Total energy per rank (pJ) -system.physmem_1.averagePower 254.503567 # Core power per rank (mW) -system.physmem_1.totalIdleTime 62217855000 # Total Idle time Per DRAM Rank +system.physmem_1.actBackEnergy 136418100 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 13273920 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 827375520 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 248165280 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 14377479765 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 15920005755 # Total energy per rank (pJ) +system.physmem_1.averagePower 254.503484 # Core power per rank (mW) +system.physmem_1.totalIdleTime 62218080000 # Total Idle time Per DRAM Rank system.physmem_1.memoryStateTime::IDLE 20713000 # Time in different power states system.physmem_1.memoryStateTime::REF 109118000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 59758396500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 646214750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 203977250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 1814551000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.physmem_1.memoryStateTime::SREF 59758619500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 646225750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 203975250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 1814542000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 20808248 # Number of BP lookups system.cpu.branchPred.condPredicted 17115636 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 756798 # Number of conditional branches incorrect @@ -276,7 +276,7 @@ system.cpu.branchPred.indirectHits 24795 # Nu system.cpu.branchPred.indirectMisses 1416 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 665 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -306,7 +306,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -336,7 +336,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -366,7 +366,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -397,16 +397,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 62552970500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 125105941 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 62553193500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 125106387 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90602850 # Number of instructions committed system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed system.cpu.discardedOps 2182224 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.380817 # CPI: cycles per instruction -system.cpu.ipc 0.724209 # IPC: instructions per cycle +system.cpu.cpi 1.380822 # CPI: cycles per instruction +system.cpu.ipc 0.724206 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 63822829 70.09% 70.09% # Class of committed instruction system.cpu.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction @@ -446,16 +446,16 @@ system.cpu.op_class_0::FloatMemWrite 22 0.00% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 91054081 # Class of committed instruction -system.cpu.tickCycles 110521627 # Number of cycles that the object actually ticked -system.cpu.idleCycles 14584314 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 110521789 # Number of cycles that the object actually ticked +system.cpu.idleCycles 14584598 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 946101 # number of replacements -system.cpu.dcache.tags.tagsinuse 3621.108293 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26274912 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3621.109986 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26274729 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 950197 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 27.652068 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 27.651875 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 20754063500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3621.108293 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 3621.109986 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.884060 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.884060 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -465,9 +465,9 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 1662 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 55461283 # Number of tag accesses system.cpu.dcache.tags.data_accesses 55461283 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 21605963 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21605963 # number of ReadReq hits +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 21605780 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21605780 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 4660667 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 4660667 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits @@ -476,28 +476,28 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 26266630 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26266630 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26267138 # number of overall hits -system.cpu.dcache.overall_hits::total 26267138 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 906313 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 906313 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 26266447 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26266447 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26266955 # number of overall hits +system.cpu.dcache.overall_hits::total 26266955 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 906496 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 906496 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 74314 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 74314 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 980627 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 980627 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 980631 # number of overall misses -system.cpu.dcache.overall_misses::total 980631 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11831745500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11831745500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2760211000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2760211000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14591956500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14591956500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14591956500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14591956500 # number of overall miss cycles +system.cpu.dcache.demand_misses::cpu.data 980810 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 980810 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 980814 # number of overall misses +system.cpu.dcache.overall_misses::total 980814 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11832179000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11832179000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2760205500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2760205500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14592384500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14592384500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14592384500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14592384500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 22512276 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22512276 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) @@ -512,24 +512,24 @@ system.cpu.dcache.demand_accesses::cpu.data 27247257 # system.cpu.dcache.demand_accesses::total 27247257 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 27247769 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 27247769 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040259 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040259 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040267 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040267 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015695 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.015695 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.035990 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.035990 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.035989 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.035989 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13054.811638 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13054.811638 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37142.543801 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37142.543801 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14880.231219 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14880.231219 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14880.170523 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14880.170523 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.035997 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.035997 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.035996 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.035996 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13052.654397 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13052.654397 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37142.469790 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37142.469790 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14877.891233 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14877.891233 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14877.830557 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14877.830557 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -538,14 +538,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 943282 # number of writebacks system.cpu.dcache.writebacks::total 943282 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2883 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2883 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3066 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3066 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27550 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 27550 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 30433 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 30433 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 30433 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 30433 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 30616 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 30616 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 30616 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 30616 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903430 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 903430 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses @@ -556,16 +556,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 950194 system.cpu.dcache.demand_mshr_misses::total 950194 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 950197 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 950197 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10889954000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10889954000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1596188500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1596188500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10889871500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10889871500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1596189500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1596189500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 170000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 170000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12486142500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12486142500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12486312500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12486312500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12486061000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12486061000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12486231000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12486231000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040131 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040131 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses @@ -576,24 +576,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034873 system.cpu.dcache.demand_mshr_miss_rate::total 0.034873 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034872 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034872 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12054.009719 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12054.009719 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34132.847917 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34132.847917 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12053.918400 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12053.918400 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34132.869301 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34132.869301 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 56666.666667 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 56666.666667 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13140.624441 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13140.624441 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13140.761863 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13140.761863 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13140.538669 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13140.538669 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13140.676091 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13140.676091 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 5 # number of replacements -system.cpu.icache.tags.tagsinuse 689.568004 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 689.568187 # Cycle average of tags in use system.cpu.icache.tags.total_refs 27835083 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 801 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 34750.415730 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 689.568004 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 689.568187 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.336703 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.336703 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 796 # Occupied blocks per task id @@ -604,7 +604,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 740 system.cpu.icache.tags.occ_task_id_percent::1024 0.388672 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 55672569 # Number of tag accesses system.cpu.icache.tags.data_accesses 55672569 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 27835083 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 27835083 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 27835083 # number of demand (read+write) hits @@ -617,12 +617,12 @@ system.cpu.icache.demand_misses::cpu.inst 801 # n system.cpu.icache.demand_misses::total 801 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 801 # number of overall misses system.cpu.icache.overall_misses::total 801 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 71410000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 71410000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 71410000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 71410000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 71410000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 71410000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 71410500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 71410500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 71410500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 71410500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 71410500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 71410500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 27835884 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 27835884 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 27835884 # number of demand (read+write) accesses @@ -635,12 +635,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 89151.061174 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 89151.061174 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 89151.061174 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 89151.061174 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 89151.061174 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 89151.061174 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 89151.685393 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 89151.685393 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 89151.685393 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 89151.685393 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 89151.685393 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 89151.685393 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -655,36 +655,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 801 system.cpu.icache.demand_mshr_misses::total 801 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 801 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 801 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 70609000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 70609000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 70609000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 70609000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 70609000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 70609000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 70609500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 70609500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 70609500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 70609500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 70609500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 70609500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 88151.061174 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 88151.061174 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 88151.061174 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 88151.061174 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 88151.061174 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 88151.061174 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 88151.685393 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 88151.685393 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 88151.685393 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 88151.685393 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 88151.685393 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 88151.685393 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 11307.978899 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 11307.993669 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1881373 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15574 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 120.802170 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.572897 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 10633.406002 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.573080 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 10633.420588 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020586 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.324506 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.345092 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.345093 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 15574 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id @@ -694,7 +694,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15454 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475281 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 15191206 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 15191206 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 943282 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 943282 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 4 # number of WritebackClean hits @@ -723,18 +723,18 @@ system.cpu.l2cache.demand_misses::total 15581 # nu system.cpu.l2cache.overall_misses::cpu.inst 774 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14807 # number of overall misses system.cpu.l2cache.overall_misses::total 15581 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1182252000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1182252000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 69100500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 69100500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1182247000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1182247000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 69101000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 69101000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49237000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 49237000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 69100500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1231489000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1300589500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 69100500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1231489000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1300589500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 69101000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1231484000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1300585000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 69101000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1231484000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1300585000 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 943282 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 943282 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 4 # number of WritebackClean accesses(hits+misses) @@ -763,18 +763,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.016384 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.966292 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015583 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016384 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81287.953795 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81287.953795 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89277.131783 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89277.131783 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81287.610011 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81287.610011 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89277.777778 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89277.777778 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 187212.927757 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 187212.927757 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89277.131783 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83169.379348 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 83472.787369 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89277.131783 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83169.379348 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 83472.787369 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89277.777778 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83169.041669 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 83472.498556 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89277.777778 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83169.041669 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 83472.498556 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -803,18 +803,18 @@ system.cpu.l2cache.demand_mshr_misses::total 15574 system.cpu.l2cache.overall_mshr_misses::cpu.inst 773 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14801 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1036812000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1036812000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 61297000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 61297000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1036807000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1036807000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 61297500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 61297500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 46234000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 46234000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 61297000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1083046000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1144343000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 61297000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1083046000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1144343000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 61297500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1083041000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1144338500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 61297500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1083041000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1144338500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311008 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311008 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for ReadCleanReq accesses @@ -827,25 +827,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016376 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015577 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016376 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71287.953795 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71287.953795 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79297.542044 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79297.542044 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71287.610011 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71287.610011 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79298.188875 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79298.188875 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 179898.832685 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 179898.832685 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79297.542044 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73173.839605 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73477.783485 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79297.542044 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73173.839605 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73477.783485 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79298.188875 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73173.501790 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73477.494542 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79298.188875 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73173.501790 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73477.494542 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 1897104 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 946122 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 904234 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 943282 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution @@ -885,7 +885,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1030 # Transaction distribution system.membus.trans_dist::ReadExReq 14544 # Transaction distribution system.membus.trans_dist::ReadExResp 14544 # Transaction distribution @@ -906,7 +906,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 15574 # Request fanout histogram -system.membus.reqLayer0.occupancy 21777000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 21778500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 82137500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 4f68c8fbf..2da35dc4f 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,117 +1,117 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058675 # Number of seconds simulated -sim_ticks 58675371500 # Number of ticks simulated -final_tick 58675371500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058681 # Number of seconds simulated +sim_ticks 58681066500 # Number of ticks simulated +final_tick 58681066500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 241655 # Simulator instruction rate (inst/s) -host_op_rate 242858 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 156520643 # Simulator tick rate (ticks/s) -host_mem_usage 492304 # Number of bytes of host memory used -host_seconds 374.87 # Real time elapsed on the host +host_inst_rate 243006 # Simulator instruction rate (inst/s) +host_op_rate 244216 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 157411271 # Simulator tick rate (ticks/s) +host_mem_usage 492224 # Number of bytes of host memory used +host_seconds 372.79 # Real time elapsed on the host sim_insts 90589799 # Number of instructions simulated sim_ops 91041030 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 44736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 218240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 923072 # Number of bytes read from this memory -system.physmem.bytes_read::total 1186048 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 44736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 44736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6656 # Number of bytes written to this memory -system.physmem.bytes_written::total 6656 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 699 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3410 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 14423 # Number of read requests responded to by this memory -system.physmem.num_reads::total 18532 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 104 # Number of write requests responded to by this memory -system.physmem.num_writes::total 104 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 762432 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3719448 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 15731848 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 20213728 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 762432 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 762432 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 113438 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 113438 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 113438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 762432 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3719448 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 15731848 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 20327166 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 18533 # Number of read requests accepted -system.physmem.writeReqs 104 # Number of write requests accepted -system.physmem.readBursts 18533 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 104 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1180480 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5632 # Total number of bytes read from write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 44800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 219520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 922368 # Number of bytes read from this memory +system.physmem.bytes_read::total 1186688 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44800 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6784 # Number of bytes written to this memory +system.physmem.bytes_written::total 6784 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 700 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3430 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 14412 # Number of read requests responded to by this memory +system.physmem.num_reads::total 18542 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 106 # Number of write requests responded to by this memory +system.physmem.num_writes::total 106 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 763449 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3740900 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 15718324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 20222673 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 763449 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 763449 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 115608 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 115608 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 115608 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 763449 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3740900 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 15718324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 20338281 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 18543 # Number of read requests accepted +system.physmem.writeReqs 106 # Number of write requests accepted +system.physmem.readBursts 18543 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 106 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1180544 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6208 # Total number of bytes read from write queue system.physmem.bytesWritten 4608 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1186112 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6656 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 88 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3 # Number of DRAM write bursts merged with an existing one +system.physmem.bytesReadSys 1186752 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6784 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 97 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 6 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 3245 # Per bank write bursts system.physmem.perBankRdBursts::1 921 # Per bank write bursts -system.physmem.perBankRdBursts::2 952 # Per bank write bursts +system.physmem.perBankRdBursts::2 954 # Per bank write bursts system.physmem.perBankRdBursts::3 1031 # Per bank write bursts system.physmem.perBankRdBursts::4 1065 # Per bank write bursts -system.physmem.perBankRdBursts::5 1118 # Per bank write bursts -system.physmem.perBankRdBursts::6 1097 # Per bank write bursts -system.physmem.perBankRdBursts::7 1096 # Per bank write bursts +system.physmem.perBankRdBursts::5 1115 # Per bank write bursts +system.physmem.perBankRdBursts::6 1093 # Per bank write bursts +system.physmem.perBankRdBursts::7 1100 # Per bank write bursts system.physmem.perBankRdBursts::8 1024 # Per bank write bursts system.physmem.perBankRdBursts::9 962 # Per bank write bursts -system.physmem.perBankRdBursts::10 932 # Per bank write bursts +system.physmem.perBankRdBursts::10 933 # Per bank write bursts system.physmem.perBankRdBursts::11 899 # Per bank write bursts system.physmem.perBankRdBursts::12 904 # Per bank write bursts system.physmem.perBankRdBursts::13 895 # Per bank write bursts system.physmem.perBankRdBursts::14 1401 # Per bank write bursts -system.physmem.perBankRdBursts::15 903 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankRdBursts::15 904 # Per bank write bursts +system.physmem.perBankWrBursts::0 2 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 3 # Per bank write bursts -system.physmem.perBankWrBursts::3 3 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts system.physmem.perBankWrBursts::4 12 # Per bank write bursts -system.physmem.perBankWrBursts::5 10 # Per bank write bursts -system.physmem.perBankWrBursts::6 15 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 8 # Per bank write bursts +system.physmem.perBankWrBursts::6 10 # Per bank write bursts +system.physmem.perBankWrBursts::7 7 # Per bank write bursts system.physmem.perBankWrBursts::8 1 # Per bank write bursts system.physmem.perBankWrBursts::9 0 # Per bank write bursts system.physmem.perBankWrBursts::10 1 # Per bank write bursts -system.physmem.perBankWrBursts::11 3 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts system.physmem.perBankWrBursts::12 5 # Per bank write bursts system.physmem.perBankWrBursts::13 12 # Per bank write bursts -system.physmem.perBankWrBursts::14 7 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 8 # Per bank write bursts +system.physmem.perBankWrBursts::15 6 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58675363000 # Total gap between requests +system.physmem.totGap 58681058000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 18533 # Read request sizes (log2) +system.physmem.readPktSize::6 18543 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 104 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 12556 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 3396 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 496 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 410 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 314 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 300 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 298 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 296 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 280 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 99 # What read queue length does an incoming req see +system.physmem.writePktSize::6 106 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 12536 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 3413 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 499 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 407 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 316 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 301 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 299 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 278 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 100 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -162,7 +162,7 @@ system.physmem.wrQLenPdf::24 5 # Wh system.physmem.wrQLenPdf::25 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 4 # What write queue length does an incoming req see @@ -198,24 +198,24 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2974 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 397.815736 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 217.392167 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 406.651837 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 841 28.28% 28.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 992 33.36% 61.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 92 3.09% 64.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 59 1.98% 66.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 59 1.98% 68.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 62 2.08% 70.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 53 1.78% 72.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 59 1.98% 74.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 757 25.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2974 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 2972 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 398.104980 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 217.970166 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 405.874685 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 839 28.23% 28.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 987 33.21% 61.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 89 2.99% 64.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 64 2.15% 66.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 64 2.15% 68.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 65 2.19% 70.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 54 1.82% 72.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 55 1.85% 74.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 755 25.40% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2972 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 4542 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 1434.998534 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 7438.956513 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 4544.500000 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 1447.547305 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 7502.381200 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-511 2 50.00% 50.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1536-2047 1 25.00% 75.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-15871 1 25.00% 100.00% # Reads before turning the bus around for writes @@ -225,82 +225,82 @@ system.physmem.wrPerTurnAround::mean 18 # Wr system.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::18 4 100.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4 # Writes before turning the bus around for reads -system.physmem.totQLat 819558662 # Total ticks spent queuing -system.physmem.totMemAccLat 1165402412 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 92225000 # Total ticks spent in databus transfers -system.physmem.avgQLat 44432.57 # Average queueing delay per DRAM burst +system.physmem.totQLat 829373528 # Total ticks spent queuing +system.physmem.totMemAccLat 1175236028 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 92230000 # Total ticks spent in databus transfers +system.physmem.avgQLat 44962.24 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 63182.57 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 63712.24 # Average memory access latency per DRAM burst system.physmem.avgRdBW 20.12 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.08 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 20.21 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.11 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 20.22 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.12 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.16 # Data bus utilization in percentage system.physmem.busUtilRead 0.16 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing -system.physmem.avgWrQLen 17.01 # Average write queue length when enqueuing -system.physmem.readRowHits 15523 # Number of row buffer hits during reads -system.physmem.writeRowHits 12 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.16 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 11.88 # Row buffer hit rate for writes -system.physmem.avgGap 3148326.61 # Average gap between requests -system.physmem.pageHitRate 83.76 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 15986460 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8481825 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 75141360 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 224460 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1848222480.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 457291620 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 99494880 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 3995273070 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 3179264640 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 10079734425 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 19762775190 # Total energy per rank (pJ) -system.physmem_0.averagePower 336.815504 # Core power per rank (mW) -system.physmem_0.totalIdleTime 57405272063 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 196297250 # Time in different power states -system.physmem_0.memoryStateTime::REF 786242000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 40364411250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 8279321820 # Time in different power states -system.physmem_0.memoryStateTime::ACT 287560187 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 8761538993 # Time in different power states -system.physmem_1.actEnergy 5305020 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2804505 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 56548800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 151380 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 250773120.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 129702360 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 13640160 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 769421340 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 250623360 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 13483521390 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 14962606875 # Total energy per rank (pJ) -system.physmem_1.averagePower 255.006594 # Core power per rank (mW) -system.physmem_1.totalIdleTime 58353889098 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 22210250 # Time in different power states -system.physmem_1.memoryStateTime::REF 106530000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 56015166500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 652672389 # Time in different power states -system.physmem_1.memoryStateTime::ACT 191421152 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 1687371209 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 28234010 # Number of BP lookups -system.cpu.branchPred.condPredicted 23266490 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 835433 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11829728 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11748003 # Number of BTB hits +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 19.34 # Average write queue length when enqueuing +system.physmem.readRowHits 15527 # Number of row buffer hits during reads +system.physmem.writeRowHits 11 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.18 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 11.00 # Row buffer hit rate for writes +system.physmem.avgGap 3146606.15 # Average gap between requests +system.physmem.pageHitRate 83.78 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 15943620 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8459055 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 75134220 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 203580 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1849451760.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 458311920 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 99516480 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 3997068570 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 3182851200 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 10077393330 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 19767987555 # Total energy per rank (pJ) +system.physmem_0.averagePower 336.871642 # Core power per rank (mW) +system.physmem_0.totalIdleTime 57408712347 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 196273000 # Time in different power states +system.physmem_0.memoryStateTime::REF 786774000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 40354533250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 8288648060 # Time in different power states +system.physmem_0.memoryStateTime::ACT 289307153 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 8765531037 # Time in different power states +system.physmem_1.actEnergy 5333580 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2819685 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 56563080 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 172260 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 259378080.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 131548590 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 14205120 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 785395590 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 262919520 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 13470232590 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 14988765045 # Total energy per rank (pJ) +system.physmem_1.averagePower 255.427603 # Core power per rank (mW) +system.physmem_1.totalIdleTime 58353780091 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 23548250 # Time in different power states +system.physmem_1.memoryStateTime::REF 110212000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 55948105250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 684663397 # Time in different power states +system.physmem_1.memoryStateTime::ACT 192205159 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 1722332444 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 28234239 # Number of BP lookups +system.cpu.branchPred.condPredicted 23266690 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 835421 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11829840 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11748052 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.309156 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 74546 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 99.308630 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 74543 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 96 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 27219 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 25475 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1744 # Number of indirect misses. +system.cpu.branchPred.indirectLookups 27224 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 25476 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1748 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 245 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -330,7 +330,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -360,7 +360,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -390,7 +390,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -421,132 +421,132 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 58675371500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 117350744 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 117362134 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 746331 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 134908246 # Number of instructions fetch has processed -system.cpu.fetch.Branches 28234010 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11848024 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 115699810 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1674291 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 849 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 926 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 32275670 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 568 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 117285061 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.155401 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.317679 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 746504 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 134908625 # Number of instructions fetch has processed +system.cpu.fetch.Branches 28234239 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11848071 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 115710996 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1674249 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 874 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 948 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 32275841 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 569 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 117296446 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.155292 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.317650 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 59749210 50.94% 50.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 13933958 11.88% 62.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9228354 7.87% 70.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 34373539 29.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 59759710 50.95% 50.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13934020 11.88% 62.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9230571 7.87% 70.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 34372145 29.30% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 117285061 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.240595 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.149616 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8835265 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 65049836 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 33012809 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9561722 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 825429 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4097911 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 117296446 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.240574 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.149507 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8834504 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 65062525 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 33013030 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9560979 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 825408 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4097904 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 11817 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 114395758 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1985288 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 825429 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15272092 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 50298480 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 112986 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 35409562 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15366512 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110872789 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1412207 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 11133815 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1555614 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2094363 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 506230 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 129945991 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 483154289 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 119447702 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 431 # Number of floating rename lookups +system.cpu.decode.DecodedInsts 114396314 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1984657 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 825408 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15270391 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 50319403 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 113009 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35408802 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15359433 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110873352 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1412133 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 11133960 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1550028 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2088318 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 507009 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 129946854 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 483157007 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 119448195 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 430 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22633072 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 22633935 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 4409 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 4401 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 21514760 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26805262 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5347320 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 521988 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 256188 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 109667585 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 21513701 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26805540 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5347415 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 519015 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 253842 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 109668195 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 8283 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 101366888 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1074694 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18634838 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41670017 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 101366364 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1074602 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18635448 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41675725 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 65 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 117285061 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.864278 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.988233 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 117296446 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.864190 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.988217 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 55650042 47.45% 47.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 31364266 26.74% 74.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22008003 18.76% 92.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7064697 6.02% 98.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1197740 1.02% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 313 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 55661536 47.45% 47.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 31364227 26.74% 74.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22008293 18.76% 92.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7064324 6.02% 98.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1197751 1.02% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 315 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 117285061 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 117296446 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9783493 48.67% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 50 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9615891 47.83% 96.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 702910 3.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9780929 48.66% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 50 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9614642 47.84% 96.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 702971 3.50% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemRead 3 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemWrite 24 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 71970995 71.00% 71.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 71970702 71.00% 71.00% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 10697 0.01% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued @@ -571,90 +571,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.01% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 54 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 57 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 124 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24337764 24.01% 95.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5047220 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24337480 24.01% 95.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5047270 4.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 8 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 22 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 101366888 # Type of FU issued -system.cpu.iq.rate 0.863794 # Inst issue rate -system.cpu.iq.fu_busy_cnt 20102384 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.198313 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 341195448 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128311397 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 99608403 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 467 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 626 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 113 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 121469025 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 247 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 288057 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 101366364 # Type of FU issued +system.cpu.iq.rate 0.863706 # Inst issue rate +system.cpu.iq.fu_busy_cnt 20098632 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.198277 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 341201935 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128312613 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 99607782 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 473 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 622 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 121464746 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 250 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 288157 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4329351 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1498 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1351 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 602476 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4329629 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1502 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1344 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 602571 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 7583 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 130798 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 130792 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 825429 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8290686 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 768265 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 109688691 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 825408 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8297291 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 773487 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 109689301 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26805262 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5347320 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 26805540 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5347415 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 4395 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 180386 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 424316 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1351 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 435090 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 412415 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 847505 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 100109953 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23803133 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1256935 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 182523 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 427569 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1344 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 435014 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 412394 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 847408 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 100110032 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23803163 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1256332 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 12823 # number of nop insts executed -system.cpu.iew.exec_refs 28718801 # number of memory reference insts executed -system.cpu.iew.exec_branches 20621332 # Number of branches executed -system.cpu.iew.exec_stores 4915668 # Number of stores executed -system.cpu.iew.exec_rate 0.853083 # Inst execution rate -system.cpu.iew.wb_sent 99693665 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 99608516 # cumulative count of insts written-back -system.cpu.iew.wb_producers 59691499 # num instructions producing a value -system.cpu.iew.wb_consumers 95528314 # num instructions consuming a value -system.cpu.iew.wb_rate 0.848810 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.624857 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 17363350 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 28718949 # number of memory reference insts executed +system.cpu.iew.exec_branches 20621210 # Number of branches executed +system.cpu.iew.exec_stores 4915786 # Number of stores executed +system.cpu.iew.exec_rate 0.853001 # Inst execution rate +system.cpu.iew.wb_sent 99693474 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 99607900 # cumulative count of insts written-back +system.cpu.iew.wb_producers 59692176 # num instructions producing a value +system.cpu.iew.wb_consumers 95528763 # num instructions consuming a value +system.cpu.iew.wb_rate 0.848723 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.624861 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 17363908 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 823717 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 114597116 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.794554 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.732042 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 823705 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 114608461 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.794476 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.731976 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 78173194 68.22% 68.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18611100 16.24% 84.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 7154015 6.24% 90.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3469592 3.03% 93.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1644807 1.44% 95.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 541237 0.47% 95.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 703127 0.61% 96.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 178794 0.16% 96.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4121250 3.60% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 78183874 68.22% 68.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18612814 16.24% 84.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 7153278 6.24% 90.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3469165 3.03% 93.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1644308 1.43% 95.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 541542 0.47% 95.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 703493 0.61% 96.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 179022 0.16% 96.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4120965 3.60% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 114597116 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 114608461 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602408 # Number of instructions committed system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -704,80 +704,80 @@ system.cpu.commit.op_class_0::FloatMemWrite 22 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction -system.cpu.commit.bw_lim_events 4121250 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 218887121 # The number of ROB reads -system.cpu.rob.rob_writes 219522508 # The number of ROB writes -system.cpu.timesIdled 581 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 65683 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 4120965 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 218899309 # The number of ROB reads +system.cpu.rob.rob_writes 219523661 # The number of ROB writes +system.cpu.timesIdled 582 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 65688 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589799 # Number of Instructions Simulated system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.295408 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.295408 # CPI: Total CPI of All Threads -system.cpu.ipc 0.771958 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.771958 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 108097860 # number of integer regfile reads -system.cpu.int_regfile_writes 58692141 # number of integer regfile writes +system.cpu.cpi 1.295534 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.295534 # CPI: Total CPI of All Threads +system.cpu.ipc 0.771883 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.771883 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 108098001 # number of integer regfile reads +system.cpu.int_regfile_writes 58691976 # number of integer regfile writes system.cpu.fp_regfile_reads 58 # number of floating regfile reads -system.cpu.fp_regfile_writes 93 # number of floating regfile writes -system.cpu.cc_regfile_reads 369004584 # number of cc regfile reads -system.cpu.cc_regfile_writes 58686965 # number of cc regfile writes -system.cpu.misc_regfile_reads 28409767 # number of misc regfile reads +system.cpu.fp_regfile_writes 98 # number of floating regfile writes +system.cpu.cc_regfile_reads 369004563 # number of cc regfile reads +system.cpu.cc_regfile_writes 58686890 # number of cc regfile writes +system.cpu.misc_regfile_reads 28409682 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 5470621 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.769293 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18249382 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 5471133 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 3.335576 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 38111500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.769293 # Average occupied blocks per requestor +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 5470632 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.769242 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18249828 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5471144 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 3.335651 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 38122500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.769242 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999549 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999549 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 338 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 334 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 61907171 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 61907171 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 13887260 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13887260 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4353834 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4353834 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 61906996 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 61906996 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 13887361 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13887361 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4354163 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4354163 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3873 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3873 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 18241094 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18241094 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18241616 # number of overall hits -system.cpu.dcache.overall_hits::total 18241616 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9587475 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9587475 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 381147 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 381147 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 18241524 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18241524 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18242046 # number of overall hits +system.cpu.dcache.overall_hits::total 18242046 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9587281 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9587281 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 380818 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 380818 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 14 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 14 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9968622 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9968622 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9968629 # number of overall misses -system.cpu.dcache.overall_misses::total 9968629 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 89371349000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 89371349000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4092576700 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4092576700 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9968099 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9968099 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9968106 # number of overall misses +system.cpu.dcache.overall_misses::total 9968106 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 89375617500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 89375617500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4089956224 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4089956224 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 302000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 302000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 93463925700 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 93463925700 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 93463925700 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 93463925700 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23474735 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23474735 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 93465573724 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 93465573724 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 93465573724 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 93465573724 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23474642 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23474642 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) @@ -786,307 +786,307 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28209716 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28209716 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28210245 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28210245 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408417 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.408417 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080496 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.080496 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 28209623 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28209623 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28210152 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28210152 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408410 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.408410 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080427 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.080427 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003602 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003602 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.353375 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.353375 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.353369 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.353369 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9321.677397 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9321.677397 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10737.528303 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10737.528303 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.353358 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.353358 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.353352 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.353352 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9322.311248 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9322.311248 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10739.923596 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10739.923596 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21571.428571 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21571.428571 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9375.811993 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9375.811993 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9375.805409 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9375.805409 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 331977 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 129797 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 121610 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9376.469247 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9376.469247 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9376.462662 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9376.462662 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 331655 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 128757 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 121530 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 12840 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.729850 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 10.108801 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 5470621 # number of writebacks -system.cpu.dcache.writebacks::total 5470621 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4338830 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4338830 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158660 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158660 # number of WriteReq MSHR hits +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.728997 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 10.027804 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 5470632 # number of writebacks +system.cpu.dcache.writebacks::total 5470632 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4338725 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4338725 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158229 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 158229 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 14 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4497490 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4497490 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4497490 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4497490 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248645 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5248645 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222487 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 222487 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4496954 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4496954 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4496954 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4496954 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248556 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5248556 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222589 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 222589 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 5471132 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 5471132 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 5471136 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 5471136 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43817219500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 43817219500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2296823105 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2296823105 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 5471145 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 5471145 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 5471149 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 5471149 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43819499500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43819499500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2297613115 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2297613115 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 235500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 235500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46114042605 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 46114042605 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46114278105 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 46114278105 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223587 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223587 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046988 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046988 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46117112615 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 46117112615 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46117348115 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 46117348115 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223584 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223584 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047009 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047009 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193945 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.193945 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193941 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.193941 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8348.291702 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8348.291702 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10323.403637 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10323.403637 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193946 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.193946 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193943 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.193943 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8348.867670 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8348.867670 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10322.222190 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10322.222190 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 58875 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 58875 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8428.610862 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 8428.610862 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8428.647744 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 8428.647744 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8429.151963 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8429.151963 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8429.188844 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8429.188844 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 448 # number of replacements -system.cpu.icache.tags.tagsinuse 427.600534 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 32274508 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 427.601453 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 32274679 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 906 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 35623.077263 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 35623.266004 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 427.600534 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.835157 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.835157 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 427.601453 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.835159 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.835159 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 458 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.894531 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 64552224 # Number of tag accesses -system.cpu.icache.tags.data_accesses 64552224 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 32274508 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 32274508 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 32274508 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 32274508 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 32274508 # number of overall hits -system.cpu.icache.overall_hits::total 32274508 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1151 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1151 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1151 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1151 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1151 # number of overall misses -system.cpu.icache.overall_misses::total 1151 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 79113980 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 79113980 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 79113980 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 79113980 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 79113980 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 79113980 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 32275659 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 32275659 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 32275659 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 32275659 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 32275659 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 32275659 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 64552564 # Number of tag accesses +system.cpu.icache.tags.data_accesses 64552564 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 32274679 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 32274679 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 32274679 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 32274679 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 32274679 # number of overall hits +system.cpu.icache.overall_hits::total 32274679 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1150 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1150 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1150 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1150 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1150 # number of overall misses +system.cpu.icache.overall_misses::total 1150 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 79102980 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 79102980 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 79102980 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 79102980 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 79102980 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 79102980 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 32275829 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 32275829 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 32275829 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 32275829 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 32275829 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 32275829 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000036 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000036 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000036 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68734.995656 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68734.995656 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68734.995656 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68734.995656 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68734.995656 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68734.995656 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 21173 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 759 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 225 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68785.200000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68785.200000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68785.200000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68785.200000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68785.200000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68785.200000 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 21255 # 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Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 14496 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 49 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 477 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3389 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9672 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 11153.900503 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 66.098130 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.680780 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004034 # 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number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 5457195 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 5457195 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 11011 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 11011 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 5 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 226170 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 226170 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 907 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::total 907 # 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number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 5472040 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 5471144 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 5472051 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002229 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.002229 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.772878 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.772878 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000591 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000591 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.772878 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.000659 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.000787 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.772878 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.000659 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.000787 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21166.666667 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21166.666667 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 126989.108911 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 126989.108911 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82895.149786 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82895.149786 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 198809.354839 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 198809.354839 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82895.149786 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 188748.543689 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 171516.024152 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82895.149786 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 188748.543689 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 171516.024152 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002215 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.002215 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.773980 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.773980 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000594 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000594 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.773980 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.000661 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.000790 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.773980 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.000661 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.000790 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21300 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21300 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127617.764471 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127617.764471 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82794.159544 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82794.159544 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 198613.694676 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 198613.694676 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82794.159544 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 188785.299807 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 171565.725526 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82794.159544 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 188785.299807 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 171565.725526 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1094,167 +1094,167 @@ system.cpu.l2cache.blocked::no_targets 0 # nu system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.unused_prefetches 3 # number of HardPF blocks evicted w/o reference -system.cpu.l2cache.writebacks::writebacks 104 # number of writebacks -system.cpu.l2cache.writebacks::total 104 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 162 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 162 # number of ReadExReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 106 # number of writebacks +system.cpu.l2cache.writebacks::total 106 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 158 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 158 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 32 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 32 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 30 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 30 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 194 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 195 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 188 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 189 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 194 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 195 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316848 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 316848 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 634858500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1079223443 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1767930443 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 701 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 701 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 3088 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 3088 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 701 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3431 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 4132 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 701 # 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number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 53854500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 591148000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 591148000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53854500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 636757000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 690611500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53854500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 636757000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1087453464 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1778064964 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001514 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001514 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.771775 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.771775 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000585 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000585 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.771775 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000623 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.000751 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.771775 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000623 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001517 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001517 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.772878 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.772878 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000589 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000589 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.772878 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000627 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.000755 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.772878 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000627 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.058654 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3406.123577 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3406.123577 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15166.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15166.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 133078.717201 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 133078.717201 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76926.428571 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76926.428571 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 192051.010430 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 192051.010430 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76926.428571 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 186120.932278 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167527.852104 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76926.428571 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 186120.932278 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3406.123577 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 5508.275023 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 10943112 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471085 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2875 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 302425 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302424 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.058618 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3434.482939 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3434.482939 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15300 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15300 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 132970.845481 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 132970.845481 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76825.249643 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76825.249643 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 191433.937824 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 191433.937824 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76825.249643 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185589.332556 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167137.342691 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76825.249643 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185589.332556 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3434.482939 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 5543.287704 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 10943136 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471098 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2874 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 302216 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302215 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 5245519 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 5457385 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 13788 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 36 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 318720 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 226520 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 226520 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 5245880 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 5457301 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 13885 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 42 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 318509 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 226170 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 226170 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 907 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244613 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244974 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2261 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412897 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16415158 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412936 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16415197 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700272512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 700359168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 318864 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6912 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 5790903 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.052723 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.223481 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700274048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 700360704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 318663 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 7168 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 5790713 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.052689 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.223412 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5485590 94.73% 94.73% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 305312 5.27% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5485610 94.73% 94.73% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 305102 5.27% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5790903 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10942625015 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 5790713 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10942648026 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 18.6 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 6019 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 9032 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1360996 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1361495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 8206704493 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 8206721993 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 14.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 18677 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 3023 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 18697 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 3032 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 18190 # Transaction distribution -system.membus.trans_dist::WritebackDirty 104 # Transaction distribution -system.membus.trans_dist::CleanEvict 36 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 18200 # Transaction distribution +system.membus.trans_dist::WritebackDirty 106 # Transaction distribution +system.membus.trans_dist::CleanEvict 42 # Transaction distribution +system.membus.trans_dist::UpgradeReq 6 # Transaction distribution system.membus.trans_dist::ReadExReq 342 # Transaction distribution system.membus.trans_dist::ReadExResp 342 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 18191 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37209 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 37209 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1192704 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1192704 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 18201 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37239 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 37239 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1193472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1193472 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 18537 # Request fanout histogram +system.membus.snoop_fanout::samples 18549 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 18537 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 18549 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 18537 # Request fanout histogram -system.membus.reqLayer0.occupancy 29625930 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 18549 # Request fanout histogram +system.membus.reqLayer0.occupancy 29669004 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 97326818 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 97336094 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 48f2e7ba9..716a9adc9 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,78 +1,78 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.066079 # Number of seconds simulated -sim_ticks 66079350000 # Number of ticks simulated -final_tick 66079350000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.065833 # Number of seconds simulated +sim_ticks 65832730500 # Number of ticks simulated +final_tick 65832730500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 185548 # Simulator instruction rate (inst/s) -host_op_rate 326721 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 77606283 # Simulator tick rate (ticks/s) -host_mem_usage 417148 # Number of bytes of host memory used -host_seconds 851.47 # Real time elapsed on the host +host_inst_rate 190384 # Simulator instruction rate (inst/s) +host_op_rate 335236 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 79331786 # Simulator tick rate (ticks/s) +host_mem_usage 416808 # Number of bytes of host memory used +host_seconds 829.84 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 69696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1892800 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 69952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1892544 # Number of bytes read from this memory system.physmem.bytes_read::total 1962496 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 69696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 69696 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 19520 # Number of bytes written to this memory -system.physmem.bytes_written::total 19520 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1089 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29575 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 69952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 69952 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 19776 # Number of bytes written to this memory +system.physmem.bytes_written::total 19776 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1093 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29571 # Number of read requests responded to by this memory system.physmem.num_reads::total 30664 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 305 # Number of write requests responded to by this memory -system.physmem.num_writes::total 305 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1054732 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 28644350 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 29699081 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1054732 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1054732 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 295402 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 295402 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 295402 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1054732 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 28644350 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 29994484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::writebacks 309 # Number of write requests responded to by this memory +system.physmem.num_writes::total 309 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1062572 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28747767 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29810339 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1062572 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1062572 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 300398 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 300398 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 300398 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1062572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 28747767 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 30110736 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 30664 # Number of read requests accepted -system.physmem.writeReqs 305 # Number of write requests accepted +system.physmem.writeReqs 309 # Number of write requests accepted system.physmem.readBursts 30664 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 305 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1952768 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9728 # Total number of bytes read from write queue +system.physmem.writeBursts 309 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1954304 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8192 # Total number of bytes read from write queue system.physmem.bytesWritten 18368 # Total number of bytes written to DRAM system.physmem.bytesReadSys 1962496 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 19520 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 152 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytesWrittenSys 19776 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 128 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1940 # Per bank write bursts -system.physmem.perBankRdBursts::1 2080 # Per bank write bursts -system.physmem.perBankRdBursts::2 2040 # Per bank write bursts -system.physmem.perBankRdBursts::3 1947 # Per bank write bursts -system.physmem.perBankRdBursts::4 2062 # Per bank write bursts +system.physmem.perBankRdBursts::0 1947 # Per bank write bursts +system.physmem.perBankRdBursts::1 2076 # Per bank write bursts +system.physmem.perBankRdBursts::2 2053 # Per bank write bursts +system.physmem.perBankRdBursts::3 1954 # Per bank write bursts +system.physmem.perBankRdBursts::4 2067 # Per bank write bursts system.physmem.perBankRdBursts::5 1911 # Per bank write bursts system.physmem.perBankRdBursts::6 1975 # Per bank write bursts -system.physmem.perBankRdBursts::7 1870 # Per bank write bursts -system.physmem.perBankRdBursts::8 1951 # Per bank write bursts -system.physmem.perBankRdBursts::9 1941 # Per bank write bursts +system.physmem.perBankRdBursts::7 1868 # Per bank write bursts +system.physmem.perBankRdBursts::8 1952 # Per bank write bursts +system.physmem.perBankRdBursts::9 1938 # Per bank write bursts system.physmem.perBankRdBursts::10 1805 # Per bank write bursts system.physmem.perBankRdBursts::11 1794 # Per bank write bursts system.physmem.perBankRdBursts::12 1792 # Per bank write bursts system.physmem.perBankRdBursts::13 1799 # Per bank write bursts system.physmem.perBankRdBursts::14 1826 # Per bank write bursts system.physmem.perBankRdBursts::15 1779 # Per bank write bursts -system.physmem.perBankWrBursts::0 26 # Per bank write bursts -system.physmem.perBankWrBursts::1 125 # Per bank write bursts -system.physmem.perBankWrBursts::2 27 # Per bank write bursts -system.physmem.perBankWrBursts::3 24 # Per bank write bursts +system.physmem.perBankWrBursts::0 25 # Per bank write bursts +system.physmem.perBankWrBursts::1 120 # Per bank write bursts +system.physmem.perBankWrBursts::2 28 # Per bank write bursts +system.physmem.perBankWrBursts::3 32 # Per bank write bursts system.physmem.perBankWrBursts::4 54 # Per bank write bursts -system.physmem.perBankWrBursts::5 3 # Per bank write bursts -system.physmem.perBankWrBursts::6 18 # Per bank write bursts -system.physmem.perBankWrBursts::7 1 # Per bank write bursts +system.physmem.perBankWrBursts::5 2 # Per bank write bursts +system.physmem.perBankWrBursts::6 17 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts system.physmem.perBankWrBursts::8 0 # Per bank write bursts system.physmem.perBankWrBursts::9 6 # Per bank write bursts system.physmem.perBankWrBursts::10 3 # Per bank write bursts @@ -83,7 +83,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 66079146500 # Total gap between requests +system.physmem.totGap 65832525500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -97,12 +97,12 @@ system.physmem.writePktSize::2 0 # Wr system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 305 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 29931 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 435 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 98 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see +system.physmem.writePktSize::6 309 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 29955 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 437 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 101 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -147,12 +147,12 @@ system.physmem.wrQLenPdf::13 1 # Wh system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 14 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see @@ -160,18 +160,18 @@ system.physmem.wrQLenPdf::26 16 # Wh system.physmem.wrQLenPdf::27 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see @@ -194,355 +194,355 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2875 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 685.122783 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 477.283945 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 398.354531 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 431 14.99% 14.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 281 9.77% 24.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 140 4.87% 29.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 134 4.66% 34.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 130 4.52% 38.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 125 4.35% 43.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 77 2.68% 45.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 84 2.92% 48.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 1473 51.23% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2875 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 2862 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 688.995108 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 484.121076 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 395.829774 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 415 14.50% 14.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 275 9.61% 24.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 149 5.21% 29.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 128 4.47% 33.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 140 4.89% 38.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 122 4.26% 42.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 77 2.69% 45.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 86 3.00% 48.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 1470 51.36% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2862 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 16 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 1904.687500 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 23.337942 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 7552.888425 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 1905.625000 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 24.516989 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 7552.373489 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 15 93.75% 93.75% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::29696-30719 1 6.25% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 16 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 16 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 17.937500 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.900644 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.181454 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3 18.75% 18.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 10 62.50% 81.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1 6.25% 87.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 2 12.50% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.914548 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.928709 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2 12.50% 12.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 12 75.00% 87.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1 6.25% 93.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1 6.25% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 16 # Writes before turning the bus around for reads -system.physmem.totQLat 407578000 # Total ticks spent queuing -system.physmem.totMemAccLat 979678000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 152560000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13357.96 # Average queueing delay per DRAM burst +system.physmem.totQLat 411710000 # Total ticks spent queuing +system.physmem.totMemAccLat 984260000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 152680000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13482.77 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32107.96 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 29.55 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 32232.77 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 29.69 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.28 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 29.70 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 29.81 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.30 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.23 # Data bus utilization in percentage system.physmem.busUtilRead 0.23 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 15.50 # Average write queue length when enqueuing -system.physmem.readRowHits 27718 # Number of row buffer hits during reads -system.physmem.writeRowHits 199 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.84 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 65.25 # Row buffer hit rate for writes -system.physmem.avgGap 2133719.09 # Average gap between requests -system.physmem.pageHitRate 90.59 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 11095560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 5886045 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 112990500 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 14.03 # Average write queue length when enqueuing +system.physmem.readRowHits 27751 # Number of row buffer hits during reads +system.physmem.writeRowHits 206 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.88 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.67 # Row buffer hit rate for writes +system.physmem.avgGap 2125481.08 # Average gap between requests +system.physmem.pageHitRate 90.64 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 11059860 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 5878455 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 113176140 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 1451160 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 311007840.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 261882510 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 17017920 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 979925760 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 266852640 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 15064489440 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 17032599375 # Total energy per rank (pJ) -system.physmem_0.averagePower 257.759790 # Core power per rank (mW) -system.physmem_0.totalIdleTime 65460562250 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 23034750 # Time in different power states -system.physmem_0.memoryStateTime::REF 131986000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 62616842500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 694916500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 463599750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 2148970500 # Time in different power states -system.physmem_1.actEnergy 9481920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 5024580 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 104865180 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 315310320.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 256763340 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 17698560 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 981638610 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 270128640 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 15008515620 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 16981623105 # Total energy per rank (pJ) +system.physmem_0.averagePower 257.950589 # Core power per rank (mW) +system.physmem_0.totalIdleTime 65223686000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 24830750 # Time in different power states +system.physmem_0.memoryStateTime::REF 133713250 # Time in different power states +system.physmem_0.memoryStateTime::SREF 62367507500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 703478750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 450500500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 2152699750 # Time in different power states +system.physmem_1.actEnergy 9403380 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 4982835 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 104850900 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 46980 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 381691440.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 255809160 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 19980960 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 1151008410 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 399268320 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 14907041175 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 17234823375 # Total energy per rank (pJ) -system.physmem_1.averagePower 260.820111 # Core power per rank (mW) -system.physmem_1.totalIdleTime 65463256000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 30077000 # Time in different power states -system.physmem_1.memoryStateTime::REF 162078000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 61901089500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 1039749000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 422083750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 2524272750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 40670761 # Number of BP lookups -system.cpu.branchPred.condPredicted 40670761 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1447235 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 26704882 # Number of BTB lookups +system.physmem_1.refreshEnergy 389067120.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 256987920 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 20546880 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 1156119600 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 409490400 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 14841811380 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 17194149375 # Total energy per rank (pJ) +system.physmem_1.averagePower 261.179341 # Core power per rank (mW) +system.physmem_1.totalIdleTime 65212352000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 31901000 # Time in different power states +system.physmem_1.memoryStateTime::REF 165222000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 61612056250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 1066374000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 421666750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 2535510500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 40426123 # Number of BP lookups +system.cpu.branchPred.condPredicted 40426123 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1402729 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 26580139 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6058055 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 92918 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 26704882 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 21174798 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5530084 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 547932 # Number of mispredicted indirect branches. +system.cpu.branchPred.usedRAS 6011508 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 87453 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 26580139 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 21161652 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5418487 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 517301 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 66079350000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 132158701 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 65832730500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 131665462 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30720551 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 221310466 # Number of instructions fetch has processed -system.cpu.fetch.Branches 40670761 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 27232853 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 99729501 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3011659 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 476 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 6367 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 115460 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 59 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 223 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 29905952 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 367398 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.icacheStallCycles 30553171 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 219967171 # Number of instructions fetch has processed +system.cpu.fetch.Branches 40426123 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 27173160 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 99460538 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2919977 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 306 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 5927 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 105822 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 73 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 157 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 29763575 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 354176 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 15 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 132078466 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.949325 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.409240 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 131585982 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.941987 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.406730 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 66113924 50.06% 50.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4057337 3.07% 53.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3620378 2.74% 55.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6125698 4.64% 60.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7769884 5.88% 66.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5562288 4.21% 70.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3378570 2.56% 73.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2898316 2.19% 75.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 32552071 24.65% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 65985920 50.15% 50.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4028379 3.06% 53.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3611314 2.74% 55.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6113229 4.65% 60.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7745533 5.89% 66.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5553246 4.22% 70.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3377028 2.57% 73.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2847646 2.16% 75.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 32323687 24.56% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 132078466 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.307742 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.674581 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15424627 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 64723504 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 40539404 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9885102 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1505829 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 364367574 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1505829 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 20975204 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 11377644 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 18396 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 44575622 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 53625771 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 354569179 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 16511 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 791289 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 46695905 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5223216 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 357047318 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 939748965 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 578695140 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 22535 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 131585982 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.307037 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.670652 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15243618 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64765794 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 40224064 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9892518 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1459988 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 362269877 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1459988 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 20789530 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11237370 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 18362 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 44279240 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 53801492 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 352719757 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 16498 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 793095 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 46882908 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5193491 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 355158766 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 934950269 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 575705414 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 24139 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 77834571 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 494 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 495 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 64563941 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 112883257 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 38651230 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 51754424 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9024100 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 345545955 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4258 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 318634973 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 172634 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 67357749 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 104786759 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3813 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 132078466 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.412467 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.166876 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 75946019 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 487 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 484 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 64820498 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 112428453 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 38501164 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 51645718 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9056873 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 344114716 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4351 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 317908509 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 166833 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 65926603 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 102202913 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3906 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 131585982 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.415976 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.164934 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 36007190 27.26% 27.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 20156467 15.26% 42.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17165000 13.00% 55.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17631185 13.35% 68.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 15357300 11.63% 80.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 12905365 9.77% 90.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 6726655 5.09% 95.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4095436 3.10% 98.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2033868 1.54% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 35686444 27.12% 27.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 20105227 15.28% 42.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17162197 13.04% 55.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17623881 13.39% 68.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 15350950 11.67% 80.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 12863479 9.78% 90.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6692822 5.09% 95.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4078738 3.10% 98.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2022244 1.54% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 132078466 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 131585982 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 366214 8.93% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3544032 86.41% 95.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 189377 4.62% 99.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 6 0.00% 99.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 1660 0.04% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 364988 8.91% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.91% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3541451 86.44% 95.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 188937 4.61% 99.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 10 0.00% 99.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 1524 0.04% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33340 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 182328648 57.22% 57.23% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11540 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 353 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 275 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101489286 31.85% 89.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 34764932 10.91% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 469 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 6130 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 181836417 57.20% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11458 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 362 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 334 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101309174 31.87% 89.08% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 34711229 10.92% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 553 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 5642 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 318634973 # Type of FU issued -system.cpu.iq.rate 2.411003 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4101289 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012871 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 773603045 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 412934380 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 314305089 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 19290 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 34996 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 4478 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 322694382 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8540 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 57471685 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 317908509 # Type of FU issued +system.cpu.iq.rate 2.414517 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4096910 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012887 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 771648435 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 410069961 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 313720076 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 18308 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 36184 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 4316 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 321964016 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8063 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 57535034 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 22103872 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 67270 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 64283 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 7211478 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 21649068 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 67666 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 63141 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7061412 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3969 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 140998 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4025 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 141941 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1505829 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8247421 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3042364 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 345550213 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 133191 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 112883257 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 38651230 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1745 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2963 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3048582 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 64283 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 545574 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1082259 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1627833 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 316133024 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100718075 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2501949 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1459988 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8072611 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3068372 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 344119067 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 127232 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 112428453 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 38501164 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1782 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2921 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3074772 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 63141 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 534039 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1041947 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1575986 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 315496434 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100557512 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2412075 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 135067596 # number of memory reference insts executed -system.cpu.iew.exec_branches 32155475 # Number of branches executed -system.cpu.iew.exec_stores 34349521 # Number of stores executed -system.cpu.iew.exec_rate 2.392071 # Inst execution rate -system.cpu.iew.wb_sent 314966910 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 314309567 # cumulative count of insts written-back -system.cpu.iew.wb_producers 238188610 # num instructions producing a value -system.cpu.iew.wb_consumers 344086280 # num instructions consuming a value -system.cpu.iew.wb_rate 2.378274 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692235 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 67483313 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 134869578 # number of memory reference insts executed +system.cpu.iew.exec_branches 32108537 # Number of branches executed +system.cpu.iew.exec_stores 34312066 # Number of stores executed +system.cpu.iew.exec_rate 2.396197 # Inst execution rate +system.cpu.iew.wb_sent 314359591 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 313724392 # cumulative count of insts written-back +system.cpu.iew.wb_producers 237724315 # num instructions producing a value +system.cpu.iew.wb_consumers 343443925 # num instructions consuming a value +system.cpu.iew.wb_rate 2.382739 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692178 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 66051294 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1453904 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 122408865 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.272650 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.045643 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1408834 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 122136825 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.277712 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.048100 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 57244612 46.77% 46.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16526306 13.50% 60.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11253907 9.19% 69.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8747083 7.15% 76.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2074138 1.69% 78.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1764583 1.44% 79.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 930878 0.76% 80.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 726504 0.59% 81.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 23140854 18.90% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 57021615 46.69% 46.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16508640 13.52% 60.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11210798 9.18% 69.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8746505 7.16% 76.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2078517 1.70% 78.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1759712 1.44% 79.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 926228 0.76% 80.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 725763 0.59% 81.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 23159047 18.96% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 122408865 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 122136825 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -592,451 +592,451 @@ system.cpu.commit.op_class_0::FloatMemWrite 14 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction -system.cpu.commit.bw_lim_events 23140854 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 444943788 # The number of ROB reads -system.cpu.rob.rob_writes 701094607 # The number of ROB writes -system.cpu.timesIdled 892 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 80235 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 23159047 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 443221536 # The number of ROB reads +system.cpu.rob.rob_writes 698006714 # The number of ROB writes +system.cpu.timesIdled 877 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 79480 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.836508 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.836508 # CPI: Total CPI of All Threads -system.cpu.ipc 1.195446 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.195446 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 503639899 # number of integer regfile reads -system.cpu.int_regfile_writes 248370602 # number of integer regfile writes -system.cpu.fp_regfile_reads 4288 # number of floating regfile reads -system.cpu.fp_regfile_writes 677 # number of floating regfile writes -system.cpu.cc_regfile_reads 109192725 # number of cc regfile reads -system.cpu.cc_regfile_writes 65564647 # number of cc regfile writes -system.cpu.misc_regfile_reads 202344104 # number of misc regfile reads +system.cpu.cpi 0.833386 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.833386 # CPI: Total CPI of All Threads +system.cpu.ipc 1.199924 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.199924 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 502917784 # number of integer regfile reads +system.cpu.int_regfile_writes 247848787 # number of integer regfile writes +system.cpu.fp_regfile_reads 4075 # number of floating regfile reads +system.cpu.fp_regfile_writes 819 # number of floating regfile writes +system.cpu.cc_regfile_reads 109098841 # number of cc regfile reads +system.cpu.cc_regfile_writes 65494445 # number of cc regfile writes +system.cpu.misc_regfile_reads 201957201 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2073334 # number of replacements -system.cpu.dcache.tags.tagsinuse 4067.317880 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 71743454 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2077430 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 34.534715 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 21320595500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4067.317880 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.992998 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.992998 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2073306 # number of replacements +system.cpu.dcache.tags.tagsinuse 4067.354566 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 71520008 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2077402 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 34.427621 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 21024099500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.354566 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993006 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993006 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 505 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3441 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 500 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3447 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 151138894 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 151138894 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 40397499 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 40397499 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31345955 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31345955 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 71743454 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 71743454 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 71743454 # number of overall hits -system.cpu.dcache.overall_hits::total 71743454 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2693481 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2693481 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 93797 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 93797 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2787278 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2787278 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2787278 # number of overall misses -system.cpu.dcache.overall_misses::total 2787278 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32417345000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32417345000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3182155993 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3182155993 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35599500993 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35599500993 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35599500993 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35599500993 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 43090980 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 43090980 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 150691296 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 150691296 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 40173982 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 40173982 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31346026 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31346026 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 71520008 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 71520008 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 71520008 # number of overall hits +system.cpu.dcache.overall_hits::total 71520008 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2693213 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2693213 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 93726 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 93726 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2786939 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2786939 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2786939 # number of overall misses +system.cpu.dcache.overall_misses::total 2786939 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32416728500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32416728500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3181034987 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3181034987 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35597763487 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35597763487 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35597763487 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35597763487 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 42867195 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 42867195 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 74530732 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 74530732 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 74530732 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 74530732 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.062507 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.062507 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002983 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002983 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037398 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037398 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037398 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037398 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12035.483079 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12035.483079 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33925.989029 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33925.989029 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12772.138622 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12772.138622 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12772.138622 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12772.138622 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 219409 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 74306947 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 74306947 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 74306947 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 74306947 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.062827 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.062827 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002981 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002981 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037506 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037506 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037506 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037506 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12036.451814 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12036.451814 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33939.728432 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33939.728432 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12773.068764 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12773.068764 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12773.068764 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12773.068764 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 220832 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 385 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 43429 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 43178 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.052131 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.114456 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 96.250000 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2066585 # number of writebacks -system.cpu.dcache.writebacks::total 2066585 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 697929 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 697929 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11919 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 11919 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 709848 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 709848 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 709848 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 709848 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1995552 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1995552 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81878 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 81878 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2077430 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2077430 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2077430 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2077430 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24266554500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24266554500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3024734993 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3024734993 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27291289493 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 27291289493 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27291289493 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27291289493 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046310 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046310 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002604 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002604 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027873 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.027873 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027873 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027873 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12160.321806 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12160.321806 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36941.974560 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36941.974560 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13137.044085 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13137.044085 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13137.044085 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13137.044085 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 94 # number of replacements -system.cpu.icache.tags.tagsinuse 871.416193 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 29904477 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1117 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 26772.136974 # Average number of references to valid blocks. +system.cpu.dcache.writebacks::writebacks 2066926 # number of writebacks +system.cpu.dcache.writebacks::total 2066926 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 697625 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 697625 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11912 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 11912 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 709537 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 709537 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 709537 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 709537 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1995588 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1995588 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81814 # 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number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27295077987 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27295077987 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046553 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046553 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002602 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002602 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027957 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.027957 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027957 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027957 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12162.444603 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12162.444603 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36960.049466 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36960.049466 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13139.044820 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13139.044820 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13139.044820 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13139.044820 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 93 # number of replacements +system.cpu.icache.tags.tagsinuse 878.108473 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 29762089 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1121 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 26549.588760 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 871.416193 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.425496 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.425496 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1023 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 878.108473 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.428764 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.428764 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1028 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 37 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 905 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.499512 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 59813021 # Number of tag accesses -system.cpu.icache.tags.data_accesses 59813021 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 29904477 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 29904477 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 29904477 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 29904477 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 29904477 # number of overall hits -system.cpu.icache.overall_hits::total 29904477 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1475 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1475 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1475 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1475 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1475 # number of overall misses -system.cpu.icache.overall_misses::total 1475 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 154630499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 154630499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 154630499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 154630499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 154630499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 154630499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 29905952 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 29905952 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 29905952 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 29905952 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 29905952 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 29905952 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000049 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000049 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000049 # 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number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353937 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353937 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.974933 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.974933 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000290 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000290 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.974933 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014236 # mshr miss rate for demand accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2055891000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2055891000 # 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number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.354193 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.354193 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.975022 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.975022 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000291 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000291 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.975022 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014235 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.014753 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.974933 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014236 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.975022 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014235 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.014753 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70899.937925 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70899.937925 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 93924.701561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 93924.701561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 141690.311419 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 141690.311419 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 93924.701561 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72283.431953 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73051.999087 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 93924.701561 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72283.431953 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73051.999087 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4151975 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073430 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 19 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 331 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 331 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70917.247327 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70917.247327 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 93284.537969 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 93284.537969 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 149534.423408 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 149534.423408 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 93284.537969 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72461.888337 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73204.099270 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 93284.537969 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72461.888337 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73204.099270 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4151922 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073402 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 20 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 335 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 335 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1996620 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2066890 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 94 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 7138 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 81927 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 81927 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1117 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1995503 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2328 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6228194 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6230522 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265216960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 265294464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1996675 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2067235 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 93 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6765 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 81848 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 81848 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1121 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1995554 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2335 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6228110 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6230445 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265236992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 265314688 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 694 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 19520 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2079241 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000169 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.013010 # Request fanout histogram +system.cpu.toL2Bus.snoopTraffic 19776 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2079217 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000172 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.013121 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2078889 99.98% 99.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 352 0.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2078859 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 358 0.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2079241 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4142666500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2079217 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4142980000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1675999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1681500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3116145000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3116103000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 4.7 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 31027 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 363 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 31023 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 359 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1667 # Transaction distribution -system.membus.trans_dist::WritebackDirty 305 # Transaction distribution -system.membus.trans_dist::CleanEvict 58 # Transaction distribution -system.membus.trans_dist::ReadExReq 28997 # Transaction distribution -system.membus.trans_dist::ReadExResp 28997 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1667 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61691 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61691 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 61691 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1982016 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1982016 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1982016 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1674 # Transaction distribution +system.membus.trans_dist::WritebackDirty 309 # Transaction distribution +system.membus.trans_dist::CleanEvict 50 # Transaction distribution +system.membus.trans_dist::ReadExReq 28990 # Transaction distribution +system.membus.trans_dist::ReadExResp 28990 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1674 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61687 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61687 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 61687 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1982272 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1982272 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1982272 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 30664 # Request fanout histogram @@ -1049,9 +1049,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 30664 # Request fanout histogram -system.membus.reqLayer0.occupancy 43847500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 43676000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 161573250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 161581250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 3b6bf0c6f..5f5ab2bca 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.368600 # Number of seconds simulated -sim_ticks 368600034500 # Number of ticks simulated -final_tick 368600034500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 368600047500 # Number of ticks simulated +final_tick 368600047500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 368828 # Simulator instruction rate (inst/s) -host_op_rate 399489 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 268368313 # Simulator tick rate (ticks/s) -host_mem_usage 276836 # Number of bytes of host memory used -host_seconds 1373.49 # Real time elapsed on the host +host_inst_rate 377886 # Simulator instruction rate (inst/s) +host_op_rate 409300 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 274959159 # Simulator tick rate (ticks/s) +host_mem_usage 276756 # Number of bytes of host memory used +host_seconds 1340.56 # Real time elapsed on the host sim_insts 506579366 # Number of instructions simulated sim_ops 548692589 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 179840 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9053376 # Number of bytes read from this memory system.physmem.bytes_read::total 9233216 # Number of bytes read from this memory @@ -27,16 +27,16 @@ system.physmem.num_reads::total 144269 # Nu system.physmem.num_writes::writebacks 97528 # Number of write requests responded to by this memory system.physmem.num_writes::total 97528 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 487900 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 24561517 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25049417 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 24561516 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25049416 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 487900 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 487900 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 16933780 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 16933780 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 16933780 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 487900 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 24561517 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 41983197 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 24561516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 41983196 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 144269 # Number of read requests accepted system.physmem.writeReqs 97528 # Number of write requests accepted system.physmem.readBursts 144269 # Number of DRAM read bursts, including those serviced by the write queue @@ -83,7 +83,7 @@ system.physmem.perBankWrBursts::14 6013 # Pe system.physmem.perBankWrBursts::15 6102 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 368600009000 # Total gap between requests +system.physmem.totGap 368600022000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -228,12 +228,12 @@ system.physmem.wrPerTurnAround::23 1 0.02% 99.97% # Wr system.physmem.wrPerTurnAround::24 1 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::26 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5740 # Writes before turning the bus around for reads -system.physmem.totQLat 3577413000 # Total ticks spent queuing -system.physmem.totMemAccLat 6280300500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3577410500 # Total ticks spent queuing +system.physmem.totMemAccLat 6280298000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 720770000 # Total ticks spent in databus transfers -system.physmem.avgQLat 24816.61 # Average queueing delay per DRAM burst +system.physmem.avgQLat 24816.59 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43566.61 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 43566.59 # Average memory access latency per DRAM burst system.physmem.avgRdBW 25.03 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 16.93 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 25.05 # Average system read bandwidth in MiByte/s @@ -248,47 +248,47 @@ system.physmem.readRowHits 110541 # Nu system.physmem.writeRowHits 67141 # Number of row buffer hits during writes system.physmem.readRowHitRate 76.68 # Row buffer hit rate for reads system.physmem.writeRowHitRate 68.84 # Row buffer hit rate for writes -system.physmem.avgGap 1524419.28 # Average gap between requests +system.physmem.avgGap 1524419.34 # Average gap between requests system.physmem.pageHitRate 73.52 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 229615260 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 122028225 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 512851920 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 252929880 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 7711888080.000002 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3985238790 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 353652480 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 24742370760 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 8329193280 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 68838779610 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 115080424995 # Total energy per rank (pJ) -system.physmem_0.averagePower 312.209476 # Core power per rank (mW) -system.physmem_0.totalIdleTime 358934915250 # Total Idle time Per DRAM Rank +system.physmem_0.actBackEnergy 3985232520 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 353635200 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 24742392420 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 8329190880 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 68838786810 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 115080429525 # Total energy per rank (pJ) +system.physmem_0.averagePower 312.209478 # Core power per rank (mW) +system.physmem_0.totalIdleTime 358934929250 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 533175250 # Time in different power states system.physmem_0.memoryStateTime::REF 3272498000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 282985145000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 21690770000 # Time in different power states -system.physmem_0.memoryStateTime::ACT 5858999750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 54259446500 # Time in different power states +system.physmem_0.memoryStateTime::SREF 282985158000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 21690772000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 5858998750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 54259445500 # Time in different power states system.physmem_1.actEnergy 227194800 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 120737925 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 516407640 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 256056660 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 7588960080.000002 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3990658350 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 342745440 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 24389253480 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 8128930080 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 69135041760 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 114698280525 # Total energy per rank (pJ) -system.physmem_1.averagePower 311.172732 # Core power per rank (mW) -system.physmem_1.totalIdleTime 358951286500 # Total Idle time Per DRAM Rank +system.physmem_1.actBackEnergy 3990680010 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 342748800 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 24389261460 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 8128903200 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 69135043560 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 114698287785 # Total energy per rank (pJ) +system.physmem_1.averagePower 311.172742 # Core power per rank (mW) +system.physmem_1.totalIdleTime 358951299500 # Total Idle time Per DRAM Rank system.physmem_1.memoryStateTime::IDLE 511434000 # Time in different power states system.physmem_1.memoryStateTime::REF 3220288000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 284296674500 # Time in different power states +system.physmem_1.memoryStateTime::SREF 284296687500 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 21168817000 # Time in different power states system.physmem_1.memoryStateTime::ACT 5916972250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 53485848750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 132103819 # Number of BP lookups system.cpu.branchPred.condPredicted 98193306 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 5910048 # Number of conditional branches incorrect @@ -303,7 +303,7 @@ system.cpu.branchPred.indirectHits 3883028 # Nu system.cpu.branchPred.indirectMisses 8547 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 54138 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -333,7 +333,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -363,7 +363,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -393,7 +393,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -424,8 +424,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 368600034500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 737200069 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 368600047500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 737200095 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 506579366 # Number of instructions committed @@ -473,16 +473,16 @@ system.cpu.op_class_0::FloatMemWrite 16 0.00% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 548692589 # Class of committed instruction -system.cpu.tickCycles 694074439 # Number of cycles that the object actually ticked -system.cpu.idleCycles 43125630 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 694074449 # Number of cycles that the object actually ticked +system.cpu.idleCycles 43125646 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1141337 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.214597 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 171083824 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4070.214598 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 171083823 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1145433 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 149.361703 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 5072633500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.214597 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.214598 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.993705 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.993705 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -491,11 +491,11 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 system.cpu.dcache.tags.age_task_id_blocks_1024::2 543 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 3507 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 346338045 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 346338045 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 114566013 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114566013 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 346338043 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 346338043 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 114566012 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114566012 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 53537935 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 53537935 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 2794 # number of SoftPFReq hits @@ -504,10 +504,10 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168103948 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168103948 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168106742 # number of overall hits -system.cpu.dcache.overall_hits::total 168106742 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 168103947 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168103947 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168106741 # number of overall hits +system.cpu.dcache.overall_hits::total 168106741 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 811353 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 811353 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 701114 # number of WriteReq misses @@ -518,16 +518,16 @@ system.cpu.dcache.demand_misses::cpu.data 1512467 # n system.cpu.dcache.demand_misses::total 1512467 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1512482 # number of overall misses system.cpu.dcache.overall_misses::total 1512482 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14511838000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14511838000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24015669000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24015669000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 38527507000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 38527507000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 38527507000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 38527507000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 115377366 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 115377366 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14511839000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14511839000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24015670000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24015670000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 38527509000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 38527509000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 38527509000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 38527509000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 115377365 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 115377365 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2809 # number of SoftPFReq accesses(hits+misses) @@ -536,10 +536,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 169616415 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 169616415 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 169619224 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 169619224 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 169616414 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 169616414 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 169619223 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 169619223 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007032 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.007032 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012926 # miss rate for WriteReq accesses @@ -550,14 +550,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.008917 system.cpu.dcache.demand_miss_rate::total 0.008917 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.008917 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.008917 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17885.973183 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17885.973183 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34253.586435 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34253.586435 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25473.287682 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25473.287682 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25473.035051 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25473.035051 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17885.974416 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17885.974416 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34253.587862 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34253.587862 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25473.289004 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25473.289004 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25473.036373 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25473.036373 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -584,16 +584,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1145421 system.cpu.dcache.demand_mshr_misses::total 1145421 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1145433 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1145433 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13416891000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 13416891000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12196191000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12196191000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13416892000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 13416892000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12196191500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12196191500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 4297000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 4297000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25613082000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 25613082000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25617379000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 25617379000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25613083500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 25613083500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25617380500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 25617380500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006839 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006839 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006571 # mshr miss rate for WriteReq accesses @@ -604,24 +604,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006753 system.cpu.dcache.demand_mshr_miss_rate::total 0.006753 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006753 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006753 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17004.220356 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17004.220356 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34221.665713 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34221.665713 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17004.221623 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17004.221623 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34221.667116 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34221.667116 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 358083.333333 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 358083.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22361.282009 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22361.282009 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22364.799163 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22364.799163 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22361.283319 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22361.283319 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22364.800473 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22364.800473 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 18178 # number of replacements -system.cpu.icache.tags.tagsinuse 1186.508914 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 199149017 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1186.508929 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 199149019 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 20050 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 9932.619302 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 9932.619401 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1186.508914 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1186.508929 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.579350 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.579350 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id @@ -631,45 +631,45 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 57 system.cpu.icache.tags.age_task_id_blocks_1024::3 311 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1400 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 398358184 # Number of tag accesses -system.cpu.icache.tags.data_accesses 398358184 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 199149017 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 199149017 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 199149017 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 199149017 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 199149017 # number of overall hits -system.cpu.icache.overall_hits::total 199149017 # number of overall hits +system.cpu.icache.tags.tag_accesses 398358188 # Number of tag accesses +system.cpu.icache.tags.data_accesses 398358188 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 199149019 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 199149019 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 199149019 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 199149019 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 199149019 # number of overall hits +system.cpu.icache.overall_hits::total 199149019 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 20050 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 20050 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 20050 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 20050 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 20050 # number of overall misses system.cpu.icache.overall_misses::total 20050 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 544281000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 544281000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 544281000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 544281000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 544281000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 544281000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 199169067 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 199169067 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 199169067 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 199169067 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 199169067 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 199169067 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 544279500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 544279500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 544279500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 544279500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 544279500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 544279500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 199169069 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 199169069 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 199169069 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 199169069 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 199169069 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 199169069 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000101 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000101 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000101 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000101 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000101 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000101 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27146.184539 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27146.184539 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27146.184539 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27146.184539 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27146.184539 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27146.184539 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27146.109726 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27146.109726 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27146.109726 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27146.109726 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27146.109726 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27146.109726 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -684,34 +684,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 20050 system.cpu.icache.demand_mshr_misses::total 20050 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 20050 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 20050 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 524231000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 524231000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 524231000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 524231000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 524231000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 524231000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 524229500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 524229500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 524229500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 524229500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 524229500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 524229500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000101 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000101 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000101 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26146.184539 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26146.184539 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26146.184539 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 26146.184539 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26146.184539 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 26146.184539 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26146.109726 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26146.109726 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26146.109726 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 26146.109726 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26146.109726 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 26146.109726 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 112761 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29076.847904 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 29076.848035 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2174458 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 145529 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 14.941750 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 102118428000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 133.889042 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 307.541070 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28635.417793 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 133.889045 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 307.541066 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28635.417923 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.004086 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009385 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.873884 # Average percentage of cache occupancy @@ -724,7 +724,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31589 system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 18705537 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 18705537 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 1068942 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 1068942 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 17940 # number of WritebackClean hits @@ -753,17 +753,17 @@ system.cpu.l2cache.demand_misses::total 144283 # nu system.cpu.l2cache.overall_misses::cpu.inst 2811 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 141472 # number of overall misses system.cpu.l2cache.overall_misses::total 144283 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8979653000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8979653000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 312477500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 312477500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4360667500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4360667500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 312477500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13340320500 # number of demand (read+write) miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8979653500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8979653500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 312476000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 312476000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4360668500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4360668500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 312476000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 13340322000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 13652798000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 312477500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13340320500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 312476000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 13340322000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 13652798000 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 1068942 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 1068942 # number of WritebackDirty accesses(hits+misses) @@ -793,17 +793,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.123797 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.140200 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.123510 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.123797 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88926.825645 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88926.825645 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 111162.397723 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 111162.397723 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 107686.756063 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 107686.756063 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 111162.397723 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94296.542779 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88926.830597 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88926.830597 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 111161.864105 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 111161.864105 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 107686.780758 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 107686.780758 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 111161.864105 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94296.553382 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 94625.132552 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 111162.397723 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94296.542779 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 111161.864105 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94296.553382 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 94625.132552 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -835,17 +835,17 @@ system.cpu.l2cache.demand_mshr_misses::total 144269 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2810 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 141459 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 144269 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7969873000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7969873000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 284302500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 284302500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3953965500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3953965500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 284302500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11923838500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7969873500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7969873500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 284301000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 284301000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3953966500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3953966500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 284301000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11923840000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 12208141000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 284302500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11923838500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 284301000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11923840000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 12208141000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283139 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283139 # mshr miss rate for ReadExReq accesses @@ -859,17 +859,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.123785 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.140150 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123498 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.123785 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78926.825645 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78926.825645 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 101175.266904 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 101175.266904 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 97674.600430 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 97674.600430 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 101175.266904 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84291.833676 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78926.830597 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78926.830597 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 101174.733096 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 101174.733096 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 97674.625133 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 97674.625133 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 101174.733096 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84291.844280 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84620.680812 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 101175.266904 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84291.833676 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 101174.733096 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84291.844280 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84620.680812 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 2324998 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159585 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -877,7 +877,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4997 system.cpu.toL2Bus.snoop_filter.tot_snoops 2618 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2615 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 808845 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 1166470 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 18178 # Transaction distribution @@ -917,7 +917,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 43291 # Transaction distribution system.membus.trans_dist::WritebackDirty 97528 # Transaction distribution system.membus.trans_dist::CleanEvict 12615 # Transaction distribution @@ -940,9 +940,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 144269 # Request fanout histogram -system.membus.reqLayer0.occupancy 685124000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 685127000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 765885250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 765884750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 36fb98963..3dfc36814 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.236034 # Number of seconds simulated -sim_ticks 236034256000 # Number of ticks simulated -final_tick 236034256000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.236024 # Number of seconds simulated +sim_ticks 236023688000 # Number of ticks simulated +final_tick 236023688000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 253188 # Simulator instruction rate (inst/s) -host_op_rate 274292 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 118283576 # Simulator tick rate (ticks/s) -host_mem_usage 302048 # Number of bytes of host memory used -host_seconds 1995.49 # Real time elapsed on the host +host_inst_rate 256452 # Simulator instruction rate (inst/s) +host_op_rate 277829 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 119803336 # Simulator tick rate (ticks/s) +host_mem_usage 301968 # Number of bytes of host memory used +host_seconds 1970.09 # Real time elapsed on the host sim_insts 505234934 # Number of instructions simulated sim_ops 547348155 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 637184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10497472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 16389440 # Number of bytes read from this memory -system.physmem.bytes_read::total 27524096 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 637184 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 637184 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18641536 # Number of bytes written to this memory -system.physmem.bytes_written::total 18641536 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 9956 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 164023 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 256085 # Number of read requests responded to by this memory -system.physmem.num_reads::total 430064 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 291274 # Number of write requests responded to by this memory -system.physmem.num_writes::total 291274 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2699540 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 44474358 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 69436701 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 116610599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2699540 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2699540 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 78978095 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 78978095 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 78978095 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2699540 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 44474358 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 69436701 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 195588695 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 430064 # Number of read requests accepted -system.physmem.writeReqs 291274 # Number of write requests accepted -system.physmem.readBursts 430064 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 291274 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 27360896 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 163200 # Total number of bytes read from write queue -system.physmem.bytesWritten 18638848 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 27524096 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18641536 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2550 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 11 # Number of DRAM write bursts merged with an existing one +system.physmem.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 640832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10509760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 16394496 # Number of bytes read from this memory +system.physmem.bytes_read::total 27545088 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 640832 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 640832 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18630208 # Number of bytes written to this memory +system.physmem.bytes_written::total 18630208 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 10013 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 164215 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 256164 # Number of read requests responded to by this memory +system.physmem.num_reads::total 430392 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 291097 # Number of write requests responded to by this memory +system.physmem.num_writes::total 291097 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2715117 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 44528412 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 69461231 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 116704761 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2715117 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2715117 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 78933637 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 78933637 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 78933637 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2715117 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 44528412 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 69461231 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 195638397 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 430392 # Number of read requests accepted +system.physmem.writeReqs 291097 # Number of write requests accepted +system.physmem.readBursts 430392 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 291097 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 27379648 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 165440 # Total number of bytes read from write queue +system.physmem.bytesWritten 18628032 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 27545088 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18630208 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2585 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 6 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 27217 # Per bank write bursts -system.physmem.perBankRdBursts::1 26580 # Per bank write bursts -system.physmem.perBankRdBursts::2 25459 # Per bank write bursts -system.physmem.perBankRdBursts::3 32933 # Per bank write bursts -system.physmem.perBankRdBursts::4 28005 # Per bank write bursts -system.physmem.perBankRdBursts::5 30095 # Per bank write bursts -system.physmem.perBankRdBursts::6 25324 # Per bank write bursts -system.physmem.perBankRdBursts::7 24336 # Per bank write bursts -system.physmem.perBankRdBursts::8 25637 # Per bank write bursts -system.physmem.perBankRdBursts::9 25661 # Per bank write bursts -system.physmem.perBankRdBursts::10 25768 # Per bank write bursts -system.physmem.perBankRdBursts::11 26242 # Per bank write bursts -system.physmem.perBankRdBursts::12 27581 # Per bank write bursts -system.physmem.perBankRdBursts::13 26014 # Per bank write bursts -system.physmem.perBankRdBursts::14 24864 # Per bank write bursts -system.physmem.perBankRdBursts::15 25798 # Per bank write bursts -system.physmem.perBankWrBursts::0 18651 # Per bank write bursts -system.physmem.perBankWrBursts::1 18268 # Per bank write bursts -system.physmem.perBankWrBursts::2 17926 # Per bank write bursts -system.physmem.perBankWrBursts::3 17983 # Per bank write bursts -system.physmem.perBankWrBursts::4 18558 # Per bank write bursts -system.physmem.perBankWrBursts::5 18375 # Per bank write bursts -system.physmem.perBankWrBursts::6 17786 # Per bank write bursts -system.physmem.perBankWrBursts::7 17681 # Per bank write bursts -system.physmem.perBankWrBursts::8 18027 # Per bank write bursts -system.physmem.perBankWrBursts::9 17737 # Per bank write bursts -system.physmem.perBankWrBursts::10 18114 # Per bank write bursts -system.physmem.perBankWrBursts::11 18781 # Per bank write bursts -system.physmem.perBankWrBursts::12 18716 # Per bank write bursts -system.physmem.perBankWrBursts::13 18163 # Per bank write bursts -system.physmem.perBankWrBursts::14 18303 # Per bank write bursts -system.physmem.perBankWrBursts::15 18163 # Per bank write bursts +system.physmem.perBankRdBursts::0 27300 # Per bank write bursts +system.physmem.perBankRdBursts::1 26589 # Per bank write bursts +system.physmem.perBankRdBursts::2 25489 # Per bank write bursts +system.physmem.perBankRdBursts::3 32817 # Per bank write bursts +system.physmem.perBankRdBursts::4 28238 # Per bank write bursts +system.physmem.perBankRdBursts::5 30052 # Per bank write bursts +system.physmem.perBankRdBursts::6 25322 # Per bank write bursts +system.physmem.perBankRdBursts::7 24428 # Per bank write bursts +system.physmem.perBankRdBursts::8 25638 # Per bank write bursts +system.physmem.perBankRdBursts::9 25508 # Per bank write bursts +system.physmem.perBankRdBursts::10 25695 # Per bank write bursts +system.physmem.perBankRdBursts::11 26146 # Per bank write bursts +system.physmem.perBankRdBursts::12 27543 # Per bank write bursts +system.physmem.perBankRdBursts::13 26122 # Per bank write bursts +system.physmem.perBankRdBursts::14 24924 # Per bank write bursts +system.physmem.perBankRdBursts::15 25996 # Per bank write bursts +system.physmem.perBankWrBursts::0 18688 # Per bank write bursts +system.physmem.perBankWrBursts::1 18252 # Per bank write bursts +system.physmem.perBankWrBursts::2 17892 # Per bank write bursts +system.physmem.perBankWrBursts::3 17877 # Per bank write bursts +system.physmem.perBankWrBursts::4 18635 # Per bank write bursts +system.physmem.perBankWrBursts::5 18189 # Per bank write bursts +system.physmem.perBankWrBursts::6 17877 # Per bank write bursts +system.physmem.perBankWrBursts::7 17743 # Per bank write bursts +system.physmem.perBankWrBursts::8 17943 # Per bank write bursts +system.physmem.perBankWrBursts::9 17697 # Per bank write bursts +system.physmem.perBankWrBursts::10 18014 # Per bank write bursts +system.physmem.perBankWrBursts::11 18785 # Per bank write bursts +system.physmem.perBankWrBursts::12 18684 # Per bank write bursts +system.physmem.perBankWrBursts::13 18184 # Per bank write bursts +system.physmem.perBankWrBursts::14 18324 # Per bank write bursts +system.physmem.perBankWrBursts::15 18279 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 236034203500 # Total gap between requests +system.physmem.totGap 236023635500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 430064 # Read request sizes (log2) +system.physmem.readPktSize::6 430392 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 291274 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 318869 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 60281 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13267 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8983 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7229 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6032 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3299 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 63 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 12 # What read queue length does an incoming req see +system.physmem.writePktSize::6 291097 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 318668 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 60537 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13344 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8917 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6198 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5201 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4287 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3249 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 78 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -149,37 +149,37 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 14851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 16916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17615 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 18128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 18323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 18440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 18551 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 18644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 18821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 18548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 14859 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16884 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17602 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 18085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 18465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 18609 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 18833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 18532 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17483 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see @@ -198,124 +198,127 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 329061 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 139.787432 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 98.478985 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 178.644390 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 210353 63.93% 63.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 79320 24.10% 88.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 14852 4.51% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7229 2.20% 94.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4899 1.49% 96.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2483 0.75% 96.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1823 0.55% 97.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1564 0.48% 98.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6538 1.99% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 329061 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17032 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.095820 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 145.258821 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17030 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 328591 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 140.009775 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 98.675291 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 178.430270 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 209431 63.74% 63.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 79588 24.22% 87.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14900 4.53% 92.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7308 2.22% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4939 1.50% 96.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2586 0.79% 97.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1820 0.55% 97.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1543 0.47% 98.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6476 1.97% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 328591 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17028 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.118628 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 145.022717 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17026 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::18432-19455 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17032 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17032 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.099108 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.028520 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.818567 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 10039 58.94% 58.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 6203 36.42% 95.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 545 3.20% 98.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 139 0.82% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 59 0.35% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 18 0.11% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 9 0.05% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 2 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 2 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 2 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 3 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 5 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 2 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-61 2 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17028 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17028 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.093199 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.022957 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.821852 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 10045 58.99% 58.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 6192 36.36% 95.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 538 3.16% 98.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 158 0.93% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 50 0.29% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 18 0.11% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 8 0.05% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 3 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 4 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 3 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50-51 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 1 0.01% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::70-71 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-105 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17032 # Writes before turning the bus around for reads -system.physmem.totQLat 14213030846 # Total ticks spent queuing -system.physmem.totMemAccLat 22228918346 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2137570000 # Total ticks spent in databus transfers -system.physmem.avgQLat 33245.77 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::90-91 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-93 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17028 # Writes before turning the bus around for reads +system.physmem.totQLat 14230918095 # Total ticks spent queuing +system.physmem.totMemAccLat 22252299345 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2139035000 # Total ticks spent in databus transfers +system.physmem.avgQLat 33264.81 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 51995.77 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 115.92 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 78.97 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 116.61 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 78.98 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 52014.81 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 116.00 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 78.92 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 116.70 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 78.93 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.52 # Data bus utilization in percentage system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.62 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.65 # Average write queue length when enqueuing -system.physmem.readRowHits 307655 # Number of row buffer hits during reads -system.physmem.writeRowHits 82023 # Number of row buffer hits during writes -system.physmem.readRowHitRate 71.96 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 28.16 # Row buffer hit rate for writes -system.physmem.avgGap 327217.20 # Average gap between requests -system.physmem.pageHitRate 54.21 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1196014260 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 635677680 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1570435860 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 758090160 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 15730481520.000004 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 13398551100 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 618704160 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 46181225010 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 17503538880 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 15597346500 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 113194744170 # Total energy per rank (pJ) -system.physmem_0.averagePower 479.569128 # Core power per rank (mW) -system.physmem_0.totalIdleTime 205028158054 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 920292705 # Time in different power states -system.physmem_0.memoryStateTime::REF 6672444000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 58173065750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 45581110454 # Time in different power states -system.physmem_0.memoryStateTime::ACT 23413245991 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 101274097100 # Time in different power states -system.physmem_1.actEnergy 1153531260 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 613108815 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1482014100 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 762140880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 15061753200.000004 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 13366111830 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 607264320 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 42525061470 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 17168834400 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 17794675410 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 110539948695 # Total energy per rank (pJ) -system.physmem_1.averagePower 468.321620 # Core power per rank (mW) -system.physmem_1.totalIdleTime 205130134268 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 923619714 # Time in different power states -system.physmem_1.memoryStateTime::REF 6390116000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 67161872750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 44710479181 # Time in different power states -system.physmem_1.memoryStateTime::ACT 23590386018 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 93257782337 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 174591760 # Number of BP lookups -system.cpu.branchPred.condPredicted 131058406 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7233420 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90376052 # Number of BTB lookups -system.cpu.branchPred.BTBHits 79001018 # Number of BTB hits +system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.76 # Average write queue length when enqueuing +system.physmem.readRowHits 308090 # Number of row buffer hits during reads +system.physmem.writeRowHits 82180 # Number of row buffer hits during writes +system.physmem.readRowHitRate 72.02 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 28.23 # Row buffer hit rate for writes +system.physmem.avgGap 327134.07 # Average gap between requests +system.physmem.pageHitRate 54.29 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1195143180 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 635214690 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1572477900 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 757698660 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 15717574080.000004 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 13455213090 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 610838880 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 46153778370 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 17481507840 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 15586959435 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 113172096165 # Total energy per rank (pJ) +system.physmem_0.averagePower 479.494648 # Core power per rank (mW) +system.physmem_0.totalIdleTime 204913310074 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 902504711 # Time in different power states +system.physmem_0.memoryStateTime::REF 6666906000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 58174043250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 45524259021 # Time in different power states +system.physmem_0.memoryStateTime::ACT 23540851965 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 101215123053 # Time in different power states +system.physmem_1.actEnergy 1151060820 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 611788155 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1482064080 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 761650200 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 15007050240.000004 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 13420176330 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 597461760 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 42655727700 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 16961144160 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 17790500985 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 110444200560 # Total energy per rank (pJ) +system.physmem_1.averagePower 467.936931 # Core power per rank (mW) +system.physmem_1.totalIdleTime 205025277615 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 898721445 # Time in different power states +system.physmem_1.memoryStateTime::REF 6366412000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 67312288506 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 44168958563 # Time in different power states +system.physmem_1.memoryStateTime::ACT 23733276940 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 93544030546 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 174594111 # Number of BP lookups +system.cpu.branchPred.condPredicted 131059017 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7233933 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 90232346 # Number of BTB lookups +system.cpu.branchPred.BTBHits 78999638 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.413664 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12105632 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104483 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 4688252 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 4674256 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 13996 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 53921 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 87.551351 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12106114 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104453 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 4688512 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 4673325 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 15187 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 53879 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -345,7 +348,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -375,7 +378,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -405,7 +408,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -436,241 +439,241 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 236034256000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 472068513 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 236023688000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 472047377 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7651832 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 727514898 # Number of instructions fetch has processed -system.cpu.fetch.Branches 174591760 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 95780906 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 456008633 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14520873 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 8018 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 72 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 15159 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 235276766 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 36821 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 470944150 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.672513 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.189889 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7665841 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 727531021 # Number of instructions fetch has processed +system.cpu.fetch.Branches 174594111 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 95779077 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 455980909 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14521279 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 6370 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 74 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 14846 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 235277273 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 36996 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 470928679 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.672614 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.189870 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 101233581 21.50% 21.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 132057346 28.04% 49.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 57356975 12.18% 61.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 180296248 38.28% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 101212688 21.49% 21.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 132055507 28.04% 49.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 57355152 12.18% 61.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 180305332 38.29% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 470944150 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.369844 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.541121 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32549558 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 125926098 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 282874913 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 22821432 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6772149 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 23855969 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 495947 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 710956468 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29088219 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6772149 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 63367796 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 61282237 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 40473434 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 273481495 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 25567039 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 682687004 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 12847672 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 10037372 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2522908 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1816731 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 2323927 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 827475029 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3000364097 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 718606364 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 112 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 470928679 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.369866 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.541225 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32549304 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 125870927 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 282926168 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 22809881 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6772399 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 23857268 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 495900 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 710989368 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 29087460 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6772399 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 63357486 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 61253040 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 40466365 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 273530421 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 25548968 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 682720764 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 12849971 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 10025216 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2519363 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1823930 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 2318589 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 827514324 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3000521547 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 718647704 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups system.cpu.rename.CommittedMaps 654095674 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 173379355 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1545861 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1536327 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 43857094 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 142358041 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 67520451 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12908238 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11335045 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 664745436 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2979378 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 608905066 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5749480 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 120376659 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 306522000 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1746 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 470944150 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.292945 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.104492 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 173418650 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1545803 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1536177 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 43812625 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 142363196 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 67528532 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12884136 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11268568 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 664776091 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2979332 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 608934070 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5749195 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 120407268 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 306545068 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1700 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 470928679 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.293049 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.104484 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 154541552 32.82% 32.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 100868277 21.42% 54.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 145535828 30.90% 85.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 63029448 13.38% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6968436 1.48% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 609 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 154505965 32.81% 32.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 100895056 21.42% 54.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 145511490 30.90% 85.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 63049261 13.39% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6966284 1.48% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 623 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 470944150 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 470928679 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 71902487 53.13% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 30 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44305802 32.74% 85.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19132129 14.14% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 12 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 71893204 53.11% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 30 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44308845 32.73% 85.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19163928 14.16% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 14 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemWrite 22 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 412584657 67.76% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 352207 0.06% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 133573188 21.94% 89.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 62394973 10.25% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 22 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 412595854 67.76% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 352107 0.06% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 133581364 21.94% 89.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 62404700 10.25% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 26 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 16 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 608905066 # Type of FU issued -system.cpu.iq.rate 1.289866 # Inst issue rate -system.cpu.iq.fu_busy_cnt 135340482 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.222269 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1829844132 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 788130713 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 594185364 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 112 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 88 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 608934070 # Type of FU issued +system.cpu.iq.rate 1.289985 # Inst issue rate +system.cpu.iq.fu_busy_cnt 135366043 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.222300 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1829911935 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 788191546 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 594211471 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 122 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 100 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 744245476 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 72 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7285563 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 744300035 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 78 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 7286788 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 26474758 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 24641 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29761 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10660231 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 26479913 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 24891 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29414 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10668312 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 224867 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 23122 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 225406 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 23080 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6772149 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 23809987 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 977416 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 669217601 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 6772399 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 23806628 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 967662 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 669248404 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 142358041 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 67520451 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1490836 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 256647 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 583506 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29761 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3591077 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3742851 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7333928 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 598406414 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 129080217 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10498652 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 142363196 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 67528532 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1490790 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 256473 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 573815 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29414 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3591193 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3742987 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7334180 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 598436406 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 129089013 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10497664 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1492787 # number of nop insts executed -system.cpu.iew.exec_refs 189993781 # number of memory reference insts executed -system.cpu.iew.exec_branches 131261458 # Number of branches executed -system.cpu.iew.exec_stores 60913564 # Number of stores executed -system.cpu.iew.exec_rate 1.267626 # Inst execution rate -system.cpu.iew.wb_sent 595430710 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 594185380 # cumulative count of insts written-back -system.cpu.iew.wb_producers 349559163 # num instructions producing a value -system.cpu.iew.wb_consumers 571371780 # num instructions consuming a value -system.cpu.iew.wb_rate 1.258685 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611789 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 107108792 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 1492981 # number of nop insts executed +system.cpu.iew.exec_refs 190011710 # number of memory reference insts executed +system.cpu.iew.exec_branches 131264327 # Number of branches executed +system.cpu.iew.exec_stores 60922697 # Number of stores executed +system.cpu.iew.exec_rate 1.267746 # Inst execution rate +system.cpu.iew.wb_sent 595457934 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 594211487 # cumulative count of insts written-back +system.cpu.iew.wb_producers 349573647 # num instructions producing a value +system.cpu.iew.wb_consumers 571370339 # num instructions consuming a value +system.cpu.iew.wb_rate 1.258796 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611816 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 107140247 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6745133 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 454284606 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.207816 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.884395 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6745693 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 454265599 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.207866 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.884244 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 225505384 49.64% 49.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 116384460 25.62% 75.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43472433 9.57% 84.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 23172184 5.10% 89.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 11521266 2.54% 92.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7756423 1.71% 94.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8277792 1.82% 95.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4245082 0.93% 96.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 13949582 3.07% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 225450125 49.63% 49.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116407668 25.63% 75.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43488632 9.57% 84.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 23202465 5.11% 89.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 11495162 2.53% 92.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7755603 1.71% 94.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8270201 1.82% 95.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4246101 0.93% 96.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 13949642 3.07% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 454284606 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 454265599 # Number of insts commited each cycle system.cpu.commit.committedInsts 506578818 # Number of instructions committed system.cpu.commit.committedOps 548692039 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -720,559 +723,560 @@ system.cpu.commit.op_class_0::FloatMemWrite 16 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 548692039 # Class of committed instruction -system.cpu.commit.bw_lim_events 13949582 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1096128717 # The number of ROB reads -system.cpu.rob.rob_writes 1328290478 # The number of ROB writes -system.cpu.timesIdled 14613 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1124363 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 13949642 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1096141105 # The number of ROB reads +system.cpu.rob.rob_writes 1328357052 # The number of ROB writes +system.cpu.timesIdled 14656 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1118698 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505234934 # Number of Instructions Simulated system.cpu.committedOps 547348155 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.934354 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.934354 # CPI: Total CPI of All Threads -system.cpu.ipc 1.070258 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.070258 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 610109745 # number of integer regfile reads -system.cpu.int_regfile_writes 327329948 # number of integer regfile writes +system.cpu.cpi 0.934313 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.934313 # CPI: Total CPI of All Threads +system.cpu.ipc 1.070306 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.070306 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 610147261 # number of integer regfile reads +system.cpu.int_regfile_writes 327343686 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 2166188285 # number of cc regfile reads -system.cpu.cc_regfile_writes 376531340 # number of cc regfile writes -system.cpu.misc_regfile_reads 217592371 # number of misc regfile reads +system.cpu.cc_regfile_reads 2166295309 # number of cc regfile reads +system.cpu.cc_regfile_writes 376541599 # number of cc regfile writes +system.cpu.misc_regfile_reads 217608578 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2817297 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.628265 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168862807 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2817809 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 59.926988 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 504720000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.628265 # Average occupied blocks per requestor +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2817163 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.628180 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168869146 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2817675 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 59.932088 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 504794000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.628180 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999274 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999274 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 293 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 355255813 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 355255813 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 114160281 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114160281 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 51722579 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 51722579 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2790 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2790 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488560 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488560 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 355269881 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 355269881 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 114167630 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114167630 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 51721570 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 51721570 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2787 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2787 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488559 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488559 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 165882860 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 165882860 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 165885650 # number of overall hits -system.cpu.dcache.overall_hits::total 165885650 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4839703 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4839703 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2516470 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2516470 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 165889200 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 165889200 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 165891987 # number of overall hits +system.cpu.dcache.overall_hits::total 165891987 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4839460 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4839460 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2517479 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2517479 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 11 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 11 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 7356173 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7356173 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7356185 # number of overall misses -system.cpu.dcache.overall_misses::total 7356185 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 63969719500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 63969719500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19897650428 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19897650428 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1356500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 1356500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83867369928 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83867369928 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83867369928 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83867369928 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 118999984 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 118999984 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 7356939 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7356939 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7356950 # number of overall misses +system.cpu.dcache.overall_misses::total 7356950 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 63959252000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 63959252000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19900951428 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19900951428 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1024000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 1024000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 83860203428 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83860203428 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83860203428 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83860203428 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 119007090 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 119007090 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2802 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2802 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488626 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488626 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2798 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2798 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488625 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488625 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 173239033 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 173239033 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 173241835 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 173241835 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040670 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040670 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046396 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.046396 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004283 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.004283 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 173246139 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 173246139 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 173248937 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 173248937 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040665 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040665 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046415 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.046415 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003931 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.003931 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.042463 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.042463 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.042462 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.042462 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13217.695280 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13217.695280 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7906.969059 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7906.969059 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20553.030303 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20553.030303 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 11400.951273 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 11400.951273 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 11400.932675 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 11400.932675 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 25 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1093581 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.042465 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.042465 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.042465 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.042465 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13216.196022 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13216.196022 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7905.111196 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 7905.111196 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15515.151515 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15515.151515 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 11398.790098 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 11398.790098 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 11398.773055 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 11398.773055 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1096029 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 221181 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.333333 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 4.944281 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2817297 # number of writebacks -system.cpu.dcache.writebacks::total 2817297 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2541719 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2541719 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1996628 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1996628 # number of WriteReq MSHR hits +system.cpu.dcache.blocked::no_targets 221098 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 4.957209 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2817163 # number of writebacks +system.cpu.dcache.writebacks::total 2817163 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2541567 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2541567 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1997678 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1997678 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4538347 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4538347 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4538347 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4538347 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2297984 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2297984 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519842 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 519842 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4539245 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4539245 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4539245 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4539245 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2297893 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2297893 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519801 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 519801 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2817826 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2817826 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2817836 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2817836 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32775846000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 32775846000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4786094494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4786094494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1244000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1244000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37561940494 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 37561940494 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37563184494 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 37563184494 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019311 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019311 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 2817694 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2817694 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2817704 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2817704 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32776399000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 32776399000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4786328496 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4786328496 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1261500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1261500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37562727496 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 37562727496 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37563988996 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 37563988996 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019309 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019309 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009584 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009584 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003569 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016266 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016266 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016265 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.016265 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14262.869541 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14262.869541 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9206.825332 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9206.825332 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 124400 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 124400 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13330.113532 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13330.113532 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13330.507700 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13330.507700 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 76619 # number of replacements -system.cpu.icache.tags.tagsinuse 466.071602 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 235190778 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 77131 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3049.238024 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 116612189500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 466.071602 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.910296 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.910296 # Average percentage of cache occupancy +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003574 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003574 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016264 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016264 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016264 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.016264 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14263.675028 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14263.675028 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9208.001708 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9208.001708 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 126150 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 126150 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13331.017313 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13331.017313 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13331.417706 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13331.417706 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 76621 # number of replacements +system.cpu.icache.tags.tagsinuse 466.068009 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 235191085 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 77133 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3049.162939 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 116620130500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 466.068009 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.910289 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.910289 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 118 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 17 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 470630395 # Number of tag accesses -system.cpu.icache.tags.data_accesses 470630395 # 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number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1941915678 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1941915678 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1941915678 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1941915678 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1941915678 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1941915678 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 235276619 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 235276619 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 235276619 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 235276619 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 235276619 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 235276619 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000365 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000365 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000365 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000365 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000365 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000365 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22622.239699 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22622.239699 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22622.239699 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22622.239699 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22622.239699 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22622.239699 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 206659 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 2170 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 7236 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.559840 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 197.272727 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 76619 # number of writebacks -system.cpu.icache.writebacks::total 76619 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8683 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 8683 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 8683 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 8683 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 8683 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 8683 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 77158 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 77158 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 77158 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 77158 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 77158 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 77158 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1536678279 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1536678279 # 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mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.182839 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59931.813204 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 59931.813204 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15462.962963 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15462.962963 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 128569.417340 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 128569.417340 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 96095.771394 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 96095.771394 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87274.576166 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87274.576166 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 96095.771394 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88177.626244 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88630.734037 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 96095.771394 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88177.626244 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59931.813204 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69365.137047 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5788910 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2893955 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23897 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 99240 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 99239 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 2372941 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2643074 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 542116 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 98320 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 402261 # Transaction distribution +system.cpu.l2cache.overall_mshr_miss_rate::total 0.183107 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59945.212612 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 59945.212612 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15568.965517 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15568.965517 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 127356.309362 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 127356.309362 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 95312.144213 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 95312.144213 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87186.572603 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87186.572603 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 95312.144213 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88087.985263 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88503.162523 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 95312.144213 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88087.985263 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59945.212612 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69332.064095 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5788651 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2893810 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 26608 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 99788 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 99240 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 548 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 2372852 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2647414 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 537467 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 98823 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 402669 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 27 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 27 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 522025 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 522025 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 77158 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295784 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230901 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8452970 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8683871 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9839552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360646848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 370486400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 791889 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 18643712 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 3686849 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.033410 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.179705 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeReq 29 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 29 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 521984 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 521984 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 77163 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295691 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230912 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8452572 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8683484 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9839936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360629696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 370469632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 792623 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 18632384 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 3687456 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.034433 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.183151 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3563674 96.66% 96.66% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 123174 3.34% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3561035 96.57% 96.57% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 125873 3.41% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 548 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3686849 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5788371005 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3687456 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5788109505 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 1506 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 115765939 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 115773436 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4226743467 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4226542968 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 819690 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 413483 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 820344 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 413808 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 426481 # Transaction distribution -system.membus.trans_dist::WritebackDirty 291274 # Transaction distribution -system.membus.trans_dist::CleanEvict 98320 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 426709 # Transaction distribution +system.membus.trans_dist::WritebackDirty 291097 # Transaction distribution +system.membus.trans_dist::CleanEvict 98823 # Transaction distribution system.membus.trans_dist::UpgradeReq 32 # Transaction distribution -system.membus.trans_dist::ReadExReq 3582 # Transaction distribution -system.membus.trans_dist::ReadExResp 3582 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 426482 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1249753 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1249753 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46165568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 46165568 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 3682 # Transaction distribution +system.membus.trans_dist::ReadExResp 3682 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 426710 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1250735 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1250735 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46175232 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 46175232 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 430096 # Request fanout histogram +system.membus.snoop_fanout::samples 430424 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 430096 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 430424 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 430096 # Request fanout histogram -system.membus.reqLayer0.occupancy 2210866206 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 430424 # Request fanout histogram +system.membus.reqLayer0.occupancy 2210945378 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2276438586 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2277916539 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 32b980d52..1d6cdc3c5 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.487015 # Number of seconds simulated -sim_ticks 487015166000 # Number of ticks simulated -final_tick 487015166000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.487172 # Number of seconds simulated +sim_ticks 487172057000 # Number of ticks simulated +final_tick 487172057000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 149671 # Simulator instruction rate (inst/s) -host_op_rate 276966 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 88156571 # Simulator tick rate (ticks/s) -host_mem_usage 323840 # Number of bytes of host memory used -host_seconds 5524.43 # Real time elapsed on the host +host_inst_rate 151495 # Simulator instruction rate (inst/s) +host_op_rate 280342 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 89259825 # Simulator tick rate (ticks/s) +host_mem_usage 322228 # Number of bytes of host memory used +host_seconds 5457.91 # Real time elapsed on the host sim_insts 826847303 # Number of instructions simulated sim_ops 1530082520 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 154176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24645952 # Number of bytes read from this memory -system.physmem.bytes_read::total 24800128 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 154176 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 154176 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18907840 # Number of bytes written to this memory -system.physmem.bytes_written::total 18907840 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2409 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 385093 # Number of read requests responded to by this memory -system.physmem.num_reads::total 387502 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 295435 # Number of write requests responded to by this memory -system.physmem.num_writes::total 295435 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 316573 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 50606128 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50922702 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 316573 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 316573 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 38823924 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 38823924 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 38823924 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 316573 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 50606128 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 89746626 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 387502 # Number of read requests accepted -system.physmem.writeReqs 295435 # Number of write requests accepted -system.physmem.readBursts 387502 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 295435 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24780416 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19712 # Total number of bytes read from write queue -system.physmem.bytesWritten 18906304 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24800128 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18907840 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 308 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 155008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24650432 # Number of bytes read from this memory +system.physmem.bytes_read::total 24805440 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 155008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 155008 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18909504 # Number of bytes written to this memory +system.physmem.bytes_written::total 18909504 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2422 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 385163 # Number of read requests responded to by this memory +system.physmem.num_reads::total 387585 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 295461 # Number of write requests responded to by this memory +system.physmem.num_writes::total 295461 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 318179 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 50599027 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50917206 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 318179 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 318179 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 38814837 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 38814837 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 38814837 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 318179 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 50599027 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 89732043 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 387585 # Number of read requests accepted +system.physmem.writeReqs 295461 # Number of write requests accepted +system.physmem.readBursts 387585 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 295461 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24785280 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20160 # Total number of bytes read from write queue +system.physmem.bytesWritten 18907584 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24805440 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18909504 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 315 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24677 # Per bank write bursts -system.physmem.perBankRdBursts::1 26454 # Per bank write bursts -system.physmem.perBankRdBursts::2 24704 # Per bank write bursts -system.physmem.perBankRdBursts::3 24551 # Per bank write bursts -system.physmem.perBankRdBursts::4 23256 # Per bank write bursts -system.physmem.perBankRdBursts::5 23627 # Per bank write bursts -system.physmem.perBankRdBursts::6 24680 # Per bank write bursts -system.physmem.perBankRdBursts::7 24455 # Per bank write bursts -system.physmem.perBankRdBursts::8 23806 # Per bank write bursts -system.physmem.perBankRdBursts::9 23529 # Per bank write bursts -system.physmem.perBankRdBursts::10 24814 # Per bank write bursts -system.physmem.perBankRdBursts::11 23994 # Per bank write bursts -system.physmem.perBankRdBursts::12 23307 # Per bank write bursts -system.physmem.perBankRdBursts::13 23001 # Per bank write bursts -system.physmem.perBankRdBursts::14 24016 # Per bank write bursts -system.physmem.perBankRdBursts::15 24323 # Per bank write bursts -system.physmem.perBankWrBursts::0 19004 # Per bank write bursts -system.physmem.perBankWrBursts::1 19961 # Per bank write bursts -system.physmem.perBankWrBursts::2 19032 # Per bank write bursts -system.physmem.perBankWrBursts::3 19001 # Per bank write bursts -system.physmem.perBankWrBursts::4 18129 # Per bank write bursts -system.physmem.perBankWrBursts::5 18443 # Per bank write bursts -system.physmem.perBankWrBursts::6 19167 # Per bank write bursts -system.physmem.perBankWrBursts::7 19127 # Per bank write bursts -system.physmem.perBankWrBursts::8 18708 # Per bank write bursts -system.physmem.perBankWrBursts::9 17947 # Per bank write bursts -system.physmem.perBankWrBursts::10 18897 # Per bank write bursts -system.physmem.perBankWrBursts::11 17782 # Per bank write bursts -system.physmem.perBankWrBursts::12 17420 # Per bank write bursts -system.physmem.perBankWrBursts::13 16998 # Per bank write bursts -system.physmem.perBankWrBursts::14 17822 # Per bank write bursts -system.physmem.perBankWrBursts::15 17973 # Per bank write bursts +system.physmem.perBankRdBursts::0 24645 # Per bank write bursts +system.physmem.perBankRdBursts::1 26417 # Per bank write bursts +system.physmem.perBankRdBursts::2 24674 # Per bank write bursts +system.physmem.perBankRdBursts::3 24501 # Per bank write bursts +system.physmem.perBankRdBursts::4 23296 # Per bank write bursts +system.physmem.perBankRdBursts::5 23619 # Per bank write bursts +system.physmem.perBankRdBursts::6 24746 # Per bank write bursts +system.physmem.perBankRdBursts::7 24503 # Per bank write bursts +system.physmem.perBankRdBursts::8 23866 # Per bank write bursts +system.physmem.perBankRdBursts::9 23595 # Per bank write bursts +system.physmem.perBankRdBursts::10 24803 # Per bank write bursts +system.physmem.perBankRdBursts::11 23982 # Per bank write bursts +system.physmem.perBankRdBursts::12 23298 # Per bank write bursts +system.physmem.perBankRdBursts::13 23005 # Per bank write bursts +system.physmem.perBankRdBursts::14 24008 # Per bank write bursts +system.physmem.perBankRdBursts::15 24312 # Per bank write bursts +system.physmem.perBankWrBursts::0 19007 # Per bank write bursts +system.physmem.perBankWrBursts::1 19956 # Per bank write bursts +system.physmem.perBankWrBursts::2 19034 # Per bank write bursts +system.physmem.perBankWrBursts::3 18984 # Per bank write bursts +system.physmem.perBankWrBursts::4 18157 # Per bank write bursts +system.physmem.perBankWrBursts::5 18431 # Per bank write bursts +system.physmem.perBankWrBursts::6 19162 # Per bank write bursts +system.physmem.perBankWrBursts::7 19114 # Per bank write bursts +system.physmem.perBankWrBursts::8 18737 # Per bank write bursts +system.physmem.perBankWrBursts::9 17973 # Per bank write bursts +system.physmem.perBankWrBursts::10 18902 # Per bank write bursts +system.physmem.perBankWrBursts::11 17777 # Per bank write bursts +system.physmem.perBankWrBursts::12 17406 # Per bank write bursts +system.physmem.perBankWrBursts::13 16997 # Per bank write bursts +system.physmem.perBankWrBursts::14 17829 # Per bank write bursts +system.physmem.perBankWrBursts::15 17965 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 487015078500 # Total gap between requests +system.physmem.totGap 487171969500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 387502 # Read request sizes (log2) +system.physmem.readPktSize::6 387585 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 295435 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 381038 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 5759 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 352 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 295461 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 381129 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 5721 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 375 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -145,31 +145,31 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 17484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 17495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17672 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 17689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17700 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17708 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17707 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 17727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17713 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17723 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see @@ -194,217 +194,214 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 146349 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 298.501363 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 176.437841 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 325.145824 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 53058 36.25% 36.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 40951 27.98% 64.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13535 9.25% 73.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7606 5.20% 78.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5054 3.45% 82.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3741 2.56% 84.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2872 1.96% 86.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2862 1.96% 88.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16670 11.39% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 146349 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17683 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.896002 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 18.141977 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 216.215491 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17677 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 146660 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 297.911141 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 176.290070 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.324639 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 53183 36.26% 36.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 40977 27.94% 64.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13739 9.37% 73.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7432 5.07% 78.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5223 3.56% 82.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3827 2.61% 84.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2941 2.01% 86.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2699 1.84% 88.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16639 11.35% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 146660 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17684 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.898835 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 18.149529 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 215.763207 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17677 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 3 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17683 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17683 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.705932 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.678736 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.966667 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 11382 64.37% 64.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 280 1.58% 65.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 5890 33.31% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 116 0.66% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 11 0.06% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 2 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17683 # Writes before turning the bus around for reads -system.physmem.totQLat 9773520500 # Total ticks spent queuing -system.physmem.totMemAccLat 17033408000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1935970000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25241.92 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 17684 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17684 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.706119 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.679236 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.959383 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 11362 64.25% 64.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 284 1.61% 65.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 5921 33.48% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 108 0.61% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 8 0.05% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17684 # Writes before turning the bus around for reads +system.physmem.totQLat 9753002000 # Total ticks spent queuing +system.physmem.totMemAccLat 17014314500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1936350000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25183.99 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43991.92 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 43933.99 # Average memory access latency per DRAM burst system.physmem.avgRdBW 50.88 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 38.82 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 38.81 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 50.92 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 38.82 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 38.81 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.70 # Data bus utilization in percentage system.physmem.busUtilRead 0.40 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.30 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.86 # Average write queue length when enqueuing -system.physmem.readRowHits 316194 # Number of row buffer hits during reads -system.physmem.writeRowHits 220049 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.66 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.48 # Row buffer hit rate for writes -system.physmem.avgGap 713118.60 # Average gap between requests -system.physmem.pageHitRate 78.56 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 536506740 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 285137325 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1402324560 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 792730080 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 13527611760.000004 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 8827375680 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 730358400 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 36195677160 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 16995876480 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 84126324885 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 163425034830 # Total energy per rank (pJ) -system.physmem_0.averagePower 335.564568 # Core power per rank (mW) -system.physmem_0.totalIdleTime 465742918500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 1151920500 # Time in different power states -system.physmem_0.memoryStateTime::REF 5744978000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 342106910750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 44260034250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 14374729750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 79376592750 # Time in different power states -system.physmem_1.actEnergy 508517940 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 270257130 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1362240600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 749315340 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 13073392800.000004 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 8818641570 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 720149760 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 34369694130 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 16456043520 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 85412982225 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 161745926205 # Total energy per rank (pJ) -system.physmem_1.averagePower 332.116816 # Core power per rank (mW) -system.physmem_1.totalIdleTime 465789870750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 1150076250 # Time in different power states -system.physmem_1.memoryStateTime::REF 5552712000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 347563722250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 42854288750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14522378750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 75371988000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 298029097 # Number of BP lookups -system.cpu.branchPred.condPredicted 298029097 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 23616389 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 229942542 # Number of BTB lookups +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.76 # Average write queue length when enqueuing +system.physmem.readRowHits 316112 # Number of row buffer hits during reads +system.physmem.writeRowHits 219918 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.63 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.43 # Row buffer hit rate for writes +system.physmem.avgGap 713234.50 # Average gap between requests +system.physmem.pageHitRate 78.51 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 536813760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 285300510 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1402303140 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 792630900 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 13522080000.000004 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 8880806910 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 733930560 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 36188602890 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 17013808320 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 84109110615 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 163471886265 # Total energy per rank (pJ) +system.physmem_0.averagePower 335.552673 # Core power per rank (mW) +system.physmem_0.totalIdleTime 465770843500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 1167963000 # Time in different power states +system.physmem_0.memoryStateTime::REF 5742590000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 342103131000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 44306910500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 14490068000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 79361394500 # Time in different power states +system.physmem_1.actEnergy 510417180 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 271274190 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1362804660 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 749518920 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 13134242160.000004 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 8898960840 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 723582720 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 34400258100 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 16618152960 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 85296284295 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 161971426545 # Total energy per rank (pJ) +system.physmem_1.averagePower 332.472734 # Core power per rank (mW) +system.physmem_1.totalIdleTime 465759347500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 1160536750 # Time in different power states +system.physmem_1.memoryStateTime::REF 5578620000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 347043695250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 43276363250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14673424500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 75439417250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 297986094 # Number of BP lookups +system.cpu.branchPred.condPredicted 297986094 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 23626998 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 229902551 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 40333391 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 4390674 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 229942542 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 119860888 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 110081654 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 11613915 # Number of mispredicted indirect branches. +system.cpu.branchPred.usedRAS 40347150 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 4410395 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 229902551 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 119869207 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 110033344 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 11602477 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 487015166000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 974030333 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 487172057000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 974344115 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 229618225 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1587637398 # Number of instructions fetch has processed -system.cpu.fetch.Branches 298029097 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 160194279 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 719695482 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 48136797 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1337 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 32063 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 398708 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 8912 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 34 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 216378015 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6307023 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 973823159 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.052791 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.491297 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 229691872 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1587782946 # Number of instructions fetch has processed +system.cpu.fetch.Branches 297986094 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 160216357 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 719926348 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 48165553 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1415 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 32240 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 400644 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 8846 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 32 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 216441049 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6311436 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 974144173 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.051993 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.490984 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 482221410 49.52% 49.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 36458558 3.74% 53.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 36184065 3.72% 56.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 33102262 3.40% 60.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28599787 2.94% 63.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 29969705 3.08% 66.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 40168402 4.12% 70.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 37465076 3.85% 74.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 249653894 25.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 482346160 49.51% 49.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 36602331 3.76% 53.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 36258722 3.72% 56.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 33122325 3.40% 60.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28552285 2.93% 63.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 29954375 3.07% 66.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 40147511 4.12% 70.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 37554957 3.86% 74.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 249605507 25.62% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 973823159 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.305975 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.629967 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 165565722 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 390830119 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 312240973 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 81117947 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 24068398 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2744223716 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 24068398 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 201650614 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 200101577 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12340 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 351328141 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 196662089 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2626762649 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 653926 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 121379246 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 22369281 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 44360312 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2707190257 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6592545635 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4207329612 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2546306 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 974144173 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.305832 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.629592 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 165741449 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 390914156 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 312062305 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 81343487 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 24082776 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2744526803 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 24082776 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 201646050 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 200648481 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 15573 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 351553209 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 196198084 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2627040726 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 843366 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 120856771 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 22890286 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 43959941 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2707701926 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6592856104 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4207544155 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2527327 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1616961572 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1090228685 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1055 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 956 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 369291247 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 608349007 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 244126939 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 253380233 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 76614927 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2419683470 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 114601 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1999301644 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3644555 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 889715551 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1510079207 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 114049 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 973823159 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.053044 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.105688 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 1090740354 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1231 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1132 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 368340883 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 608352131 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 244132697 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 253219333 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 76661135 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2419790234 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 118502 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1999387601 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3615961 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 889826216 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1510217601 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 117950 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 974144173 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.052456 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.105356 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 345234545 35.45% 35.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 135418864 13.91% 49.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 129821558 13.33% 62.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 119307207 12.25% 74.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 97554322 10.02% 84.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 67238440 6.90% 91.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 45741413 4.70% 96.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 22594403 2.32% 98.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 10912407 1.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 345565196 35.47% 35.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 135254480 13.88% 49.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 130135429 13.36% 62.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 118774957 12.19% 74.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 97965180 10.06% 84.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 67350848 6.91% 91.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 45621638 4.68% 96.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 22618956 2.32% 98.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 10857489 1.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 973823159 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 974144173 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11212757 43.19% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11247867 43.19% 43.19% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 43.19% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 43.19% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.19% # attempts to use FU when none available @@ -435,22 +432,22 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.19% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.19% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.19% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11924633 45.93% 89.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2727831 10.51% 99.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 98893 0.38% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11962828 45.93% 89.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2737897 10.51% 99.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 96082 0.37% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2915020 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1333663160 66.71% 66.85% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 357468 0.02% 66.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 4798486 0.24% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2913186 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1333691578 66.71% 66.85% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 358355 0.02% 66.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 4798525 0.24% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 2 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 2 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.11% # Type of FU issued @@ -473,84 +470,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.11% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 471201643 23.57% 90.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 185912277 9.30% 99.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 471253849 23.57% 90.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 185928557 9.30% 99.98% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 5 0.00% 99.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 453578 0.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 443541 0.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1999301644 # Type of FU issued -system.cpu.iq.rate 2.052607 # Inst issue rate -system.cpu.iq.fu_busy_cnt 25964114 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012987 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5000734134 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3305993539 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1923953649 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1300982 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4091270 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 238195 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2021798255 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 552483 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 179914916 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1999387601 # Type of FU issued +system.cpu.iq.rate 2.052034 # Inst issue rate +system.cpu.iq.fu_busy_cnt 26044674 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013026 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5001332322 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3306265401 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1924007332 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1247688 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4044576 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 235696 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2021979456 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 539633 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 179731986 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 224265796 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 337750 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 639215 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 94968744 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 224269113 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 336817 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 641986 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94974502 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 31938 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 869 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 32014 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 878 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 24068398 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 149571445 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6693651 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2419798071 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1305719 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 608349109 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 244126939 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 39730 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1462244 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4395107 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 639215 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8704418 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 20695714 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 29400132 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1945833568 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 456792637 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 53468076 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 24082776 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 149888848 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6862033 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2419908736 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1314714 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 608352426 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 244132697 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 41176 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1469227 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4543982 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 641986 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8726699 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 20674839 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 29401538 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1945912356 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 456814163 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 53475245 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 635592905 # number of memory reference insts executed -system.cpu.iew.exec_branches 185215439 # Number of branches executed -system.cpu.iew.exec_stores 178800268 # Number of stores executed -system.cpu.iew.exec_rate 1.997714 # Inst execution rate -system.cpu.iew.wb_sent 1934717341 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1924191844 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1457208218 # num instructions producing a value -system.cpu.iew.wb_consumers 2204046368 # num instructions consuming a value -system.cpu.iew.wb_rate 1.975495 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.661151 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 889791004 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 635656680 # number of memory reference insts executed +system.cpu.iew.exec_branches 185192217 # Number of branches executed +system.cpu.iew.exec_stores 178842517 # Number of stores executed +system.cpu.iew.exec_rate 1.997151 # Inst execution rate +system.cpu.iew.wb_sent 1934768958 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1924243028 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1457137045 # num instructions producing a value +system.cpu.iew.wb_consumers 2204058928 # num instructions consuming a value +system.cpu.iew.wb_rate 1.974911 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.661115 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 889901292 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 23647177 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 841074000 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.819201 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.458814 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 23658010 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 841376599 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.818547 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.459268 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 361210845 42.95% 42.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 184795052 21.97% 64.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 57840397 6.88% 71.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 87376864 10.39% 82.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 30415751 3.62% 85.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26609914 3.16% 88.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10385763 1.23% 90.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9066382 1.08% 91.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 73373032 8.72% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 361645102 42.98% 42.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 184788916 21.96% 64.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 57757386 6.86% 71.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 87297113 10.38% 82.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 30407785 3.61% 85.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26554015 3.16% 88.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10439709 1.24% 90.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9044560 1.07% 91.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 73442013 8.73% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 841074000 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 841376599 # Number of insts commited each cycle system.cpu.commit.committedInsts 826847303 # Number of instructions committed system.cpu.commit.committedOps 1530082520 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -600,495 +597,495 @@ system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1530082520 # Class of committed instruction -system.cpu.commit.bw_lim_events 73373032 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3187574492 # The number of ROB reads -system.cpu.rob.rob_writes 4974168269 # The number of ROB writes -system.cpu.timesIdled 2040 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 207174 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 73442013 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3187918398 # The number of ROB reads +system.cpu.rob.rob_writes 4974407602 # The number of ROB writes +system.cpu.timesIdled 2034 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 199942 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826847303 # Number of Instructions Simulated system.cpu.committedOps 1530082520 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.178005 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.178005 # CPI: Total CPI of All Threads -system.cpu.ipc 0.848893 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.848893 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2928663805 # number of integer regfile reads -system.cpu.int_regfile_writes 1576907134 # number of integer regfile writes -system.cpu.fp_regfile_reads 239166 # number of floating regfile reads -system.cpu.fp_regfile_writes 5 # number of floating regfile writes -system.cpu.cc_regfile_reads 617952960 # number of cc regfile reads -system.cpu.cc_regfile_writes 419967877 # number of cc regfile writes -system.cpu.misc_regfile_reads 1064297744 # number of misc regfile reads +system.cpu.cpi 1.178385 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.178385 # CPI: Total CPI of All Threads +system.cpu.ipc 0.848619 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.848619 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2928729782 # number of integer regfile reads +system.cpu.int_regfile_writes 1576941499 # number of integer regfile writes +system.cpu.fp_regfile_reads 236699 # number of floating regfile reads +system.cpu.fp_regfile_writes 4 # number of floating regfile writes +system.cpu.cc_regfile_reads 617876716 # number of cc regfile reads +system.cpu.cc_regfile_writes 419949697 # number of cc regfile writes +system.cpu.misc_regfile_reads 1064375270 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2546002 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.987212 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 420920584 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2550098 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.060552 # Average number of references to valid blocks. +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2546054 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.989792 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 421112007 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2550150 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.132250 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1890456500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.987212 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.989792 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.998044 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.998044 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 600 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3453 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 594 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3458 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 851091222 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 851091222 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 272551011 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 272551011 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148366737 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148366737 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 420917748 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 420917748 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 420917748 # number of overall hits -system.cpu.dcache.overall_hits::total 420917748 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2561340 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2561340 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 791474 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 791474 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3352814 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3352814 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3352814 # number of overall misses -system.cpu.dcache.overall_misses::total 3352814 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 63063270500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 63063270500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26380612500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 26380612500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 89443883000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 89443883000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 89443883000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 89443883000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 275112351 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 275112351 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 851486020 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 851486020 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 272742549 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 272742549 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148366794 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148366794 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 421109343 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 421109343 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 421109343 # number of overall hits +system.cpu.dcache.overall_hits::total 421109343 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2567175 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2567175 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 791417 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 791417 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3358592 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3358592 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3358592 # number of overall misses +system.cpu.dcache.overall_misses::total 3358592 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 63549852500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 63549852500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 26385909500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 26385909500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 89935762000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 89935762000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 89935762000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 89935762000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 275309724 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 275309724 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 424270562 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 424270562 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 424270562 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 424270562 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009310 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009310 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 424467935 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 424467935 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 424467935 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 424467935 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009325 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009325 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005306 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.005306 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007903 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.007903 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007903 # 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number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 928 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.464440 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 918.615385 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2338096 # number of writebacks -system.cpu.dcache.writebacks::total 2338096 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 794970 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 794970 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 5921 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 5921 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 800891 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 800891 # 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number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25486712000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 25486712000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63082870000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 63082870000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63082870000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 63082870000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006421 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006421 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.007912 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007912 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007912 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007912 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24754.780060 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24754.780060 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33340.084304 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33340.084304 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26777.817014 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26777.817014 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26777.817014 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26777.817014 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 12440 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 10775 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 917 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.565976 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 769.642857 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2337949 # number of writebacks +system.cpu.dcache.writebacks::total 2337949 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 800910 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 800910 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 5810 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 5810 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 806720 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 806720 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 806720 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 806720 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1766265 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1766265 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 785607 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 785607 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2551872 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2551872 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2551872 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2551872 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37580006000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 37580006000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25494312000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 25494312000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63074318000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 63074318000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63074318000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 63074318000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006416 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006416 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005267 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006015 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006015 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006015 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006015 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21284.418327 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21284.418327 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32444.293383 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32444.293383 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24719.738801 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24719.738801 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24719.738801 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24719.738801 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 3937 # number of replacements -system.cpu.icache.tags.tagsinuse 1075.833508 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 216367909 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5646 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 38322.335990 # Average number of references to valid blocks. +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006012 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006012 # 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Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.529803 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.529803 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1715 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 79 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1553 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.834473 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 432763508 # Number of tag accesses -system.cpu.icache.tags.data_accesses 432763508 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 487015166000 # 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number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 562018500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 562018500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 562018500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 562018500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 562018500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 216378014 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 216378014 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 216378014 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 216378014 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 216378014 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 216378014 # 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number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 216441049 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 216441049 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 216441049 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 216441049 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 216441049 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 216441049 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # 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average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 92235.946517 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 92235.946517 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 127512.660855 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84672.837422 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84939.159495 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 127512.660855 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84672.837422 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84939.159495 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5109342 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2551824 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7983 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2956 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2953 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1773620 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2633531 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 3937 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 268382 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 1825 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 1825 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 783958 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 783958 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 7480 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1766140 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16997 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7649848 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7666845 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 609088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312844416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 313453504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 357811 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 19029440 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2915314 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.004397 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.066180 # Request fanout histogram +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.004646 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.004646 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.263696 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.263696 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.429966 # 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average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19875 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78180.069161 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78180.069161 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 130007.018993 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 130007.018993 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 92054.445372 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 92054.445372 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 130007.018993 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84606.357292 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84890.063109 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 130007.018993 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84606.357292 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84890.063109 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5109383 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2550327 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23034 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 3629 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3621 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 8 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1773498 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2633410 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4004 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 268667 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 1722 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 1722 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 784105 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 784105 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 7453 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1766045 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17090 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7649798 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7666888 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 616768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312838336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 313455104 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 357843 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 19025984 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2915348 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.009238 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.095698 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2902498 99.56% 99.56% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12813 0.44% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2888424 99.08% 99.08% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 26916 0.92% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 8 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2915314 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4896765876 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2915348 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4896697394 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 11220998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 11180498 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3826059624 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3826086106 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 740486 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 353479 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 740706 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 353592 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 180710 # Transaction distribution -system.membus.trans_dist::WritebackDirty 295435 # Transaction distribution -system.membus.trans_dist::CleanEvict 57541 # Transaction distribution -system.membus.trans_dist::UpgradeReq 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 206792 # Transaction distribution -system.membus.trans_dist::ReadExResp 206792 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 180710 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1127988 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1127988 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1127988 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43707968 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43707968 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43707968 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 180821 # Transaction distribution +system.membus.trans_dist::WritebackDirty 295461 # Transaction distribution +system.membus.trans_dist::CleanEvict 57651 # Transaction distribution +system.membus.trans_dist::UpgradeReq 9 # Transaction distribution +system.membus.trans_dist::ReadExReq 206764 # Transaction distribution +system.membus.trans_dist::ReadExResp 206764 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 180821 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1128291 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1128291 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1128291 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43714944 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43714944 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43714944 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 387510 # Request fanout histogram +system.membus.snoop_fanout::samples 387594 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 387510 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 387594 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 387510 # Request fanout histogram -system.membus.reqLayer0.occupancy 1995365000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 387594 # Request fanout histogram +system.membus.reqLayer0.occupancy 1998981000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 2050434250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2050982000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index d7f32d52d..b2bc0dd63 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.225207 # Nu sim_ticks 225206521000 # Number of ticks simulated final_tick 225206521000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 284094 # Simulator instruction rate (inst/s) -host_op_rate 341086 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 234325505 # Simulator tick rate (ticks/s) -host_mem_usage 279956 # Number of bytes of host memory used -host_seconds 961.08 # Real time elapsed on the host +host_inst_rate 289736 # Simulator instruction rate (inst/s) +host_op_rate 347860 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 238979319 # Simulator tick rate (ticks/s) +host_mem_usage 279872 # Number of bytes of host memory used +host_seconds 942.37 # Real time elapsed on the host sim_insts 273037855 # Number of instructions simulated sim_ops 327812212 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -201,12 +201,12 @@ system.physmem.bytesPerActivate::768-895 33 2.18% 86.17% # By system.physmem.bytesPerActivate::896-1023 36 2.38% 88.55% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 173 11.45% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1511 # Bytes accessed per row activation -system.physmem.totQLat 232482000 # Total ticks spent queuing -system.physmem.totMemAccLat 374738250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 232471000 # Total ticks spent queuing +system.physmem.totMemAccLat 374727250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 37935000 # Total ticks spent in databus transfers -system.physmem.avgQLat 30642.15 # Average queueing delay per DRAM burst +system.physmem.avgQLat 30640.70 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 49392.15 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 49390.70 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s @@ -228,28 +228,28 @@ system.physmem_0.preEnergy 2504700 # En system.physmem_0.readEnergy 27553260 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 284578320.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 100450530 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 100446540 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 15488640 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 721250640 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 385416480 # Energy for precharge power-down per rank (pJ) +system.physmem_0.actPowerDownEnergy 721249500 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 385420800 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 53424510300 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 54966479550 # Total energy per rank (pJ) -system.physmem_0.averagePower 244.071438 # Core power per rank (mW) -system.physmem_0.totalIdleTime 224945701750 # Total Idle time Per DRAM Rank +system.physmem_0.totalEnergy 54966478740 # Total energy per rank (pJ) +system.physmem_0.averagePower 244.071435 # Core power per rank (mW) +system.physmem_0.totalIdleTime 224945712750 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 29370000 # Time in different power states system.physmem_0.memoryStateTime::REF 121010000 # Time in different power states system.physmem_0.memoryStateTime::SREF 222360521000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 1003697750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 110222000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 1003708750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 110211000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 1581700250 # Time in different power states system.physmem_1.actEnergy 6083280 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 3229545 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 26617920 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 394598880.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 121239570 # Energy for active background per rank (pJ) +system.physmem_1.actBackEnergy 121237860 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 22348800 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 914379180 # Energy for active power-down per rank (pJ) +system.physmem_1.actPowerDownEnergy 914380890 # Energy for active power-down per rank (pJ) system.physmem_1.prePowerDownEnergy 605052000 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 53195794545 # Energy for self refresh per rank (pJ) system.physmem_1.totalEnergy 55289408190 # Total energy per rank (pJ) @@ -446,16 +446,16 @@ system.cpu.op_class_0::FloatMemWrite 27367218 8.35% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 327812212 # Class of committed instruction -system.cpu.tickCycles 434950533 # Number of cycles that the object actually ticked -system.cpu.idleCycles 15462509 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 434950536 # Number of cycles that the object actually ticked +system.cpu.idleCycles 15462506 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1355 # number of replacements -system.cpu.dcache.tags.tagsinuse 3085.768112 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3085.768110 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168654205 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4512 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 37379.034796 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3085.768112 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 3085.768110 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.753361 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.753361 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id @@ -590,12 +590,12 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101521.387411 system.cpu.dcache.overall_avg_mshr_miss_latency::total 101521.387411 # average overall mshr miss latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 38188 # number of replacements -system.cpu.icache.tags.tagsinuse 1924.800725 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1924.800722 # Cycle average of tags in use system.cpu.icache.tags.total_refs 69819801 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 40125 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1740.057346 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1924.800725 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1924.800722 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.939844 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.939844 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id @@ -620,12 +620,12 @@ system.cpu.icache.demand_misses::cpu.inst 40126 # n system.cpu.icache.demand_misses::total 40126 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 40126 # number of overall misses system.cpu.icache.overall_misses::total 40126 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 817901000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 817901000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 817901000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 817901000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 817901000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 817901000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 817900500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 817900500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 817900500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 817900500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 817900500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 817900500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 69859927 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 69859927 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 69859927 # number of demand (read+write) accesses @@ -638,12 +638,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000574 system.cpu.icache.demand_miss_rate::total 0.000574 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000574 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000574 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20383.317550 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20383.317550 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20383.317550 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20383.317550 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20383.317550 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20383.317550 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20383.305089 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20383.305089 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20383.305089 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20383.305089 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20383.305089 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20383.305089 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -658,33 +658,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 40126 system.cpu.icache.demand_mshr_misses::total 40126 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 40126 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 40126 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 777776000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 777776000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 777776000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 777776000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 777776000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 777776000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 777775500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 777775500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 777775500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 777775500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 777775500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 777775500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000574 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000574 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000574 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19383.342471 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19383.342471 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19383.342471 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19383.342471 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19383.342471 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19383.342471 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19383.330010 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19383.330010 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19383.330010 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19383.330010 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19383.330010 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19383.330010 # average overall mshr miss latency system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 6596.216026 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 6596.216022 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 61516 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 7587 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 8.108080 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.840745 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.375281 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.840742 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.375280 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096675 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.104626 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.201301 # Average percentage of cache occupancy @@ -728,16 +728,16 @@ system.cpu.l2cache.overall_misses::cpu.data 4204 # system.cpu.l2cache.overall_misses::total 7630 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 281205000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 281205000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 317313000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 317313000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 317302500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 317302500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 166631000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 166631000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 317313000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 317302500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 447836000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 765149000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 317313000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 765138500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 317302500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 447836000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 765149000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 765138500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 1010 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 1010 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 23270 # number of WritebackClean accesses(hits+misses) @@ -768,16 +768,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.931738 system.cpu.l2cache.overall_miss_rate::total 0.170931 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98530.133146 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98530.133146 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92619.089317 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92619.089317 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92616.024518 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92616.024518 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123430.370370 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123430.370370 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92619.089317 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92616.024518 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 106526.165557 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 100281.651376 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92619.089317 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 100280.275229 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92616.024518 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 106526.165557 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 100281.651376 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 100280.275229 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -808,16 +808,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 4163 system.cpu.l2cache.overall_mshr_misses::total 7587 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 252665000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 252665000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 282924500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 282924500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 282914000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 282914000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 150580000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 150580000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 282924500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 282914000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 403245000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 686169500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 282924500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 686159000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 282914000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 403245000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 686169500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 686159000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for ReadCleanReq accesses @@ -832,16 +832,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922651 system.cpu.l2cache.overall_mshr_miss_rate::total 0.169967 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88530.133146 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88530.133146 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82629.818925 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82629.818925 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82626.752336 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82626.752336 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 115034.377387 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 115034.377387 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82629.818925 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82626.752336 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96864.040356 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90440.160801 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82629.818925 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90438.776855 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82626.752336 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96864.040356 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90440.160801 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90438.776855 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 84181 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 39645 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15035 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -909,7 +909,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7587 # Request fanout histogram -system.membus.reqLayer0.occupancy 9082000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9082500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 40299000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index fc2854304..c49c5de69 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.124291 # Number of seconds simulated -sim_ticks 124290972500 # Number of ticks simulated -final_tick 124290972500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.124349 # Number of seconds simulated +sim_ticks 124348696500 # Number of ticks simulated +final_tick 124348696500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 226846 # Simulator instruction rate (inst/s) -host_op_rate 272354 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 103264191 # Simulator tick rate (ticks/s) -host_mem_usage 292872 # Number of bytes of host memory used -host_seconds 1203.62 # Real time elapsed on the host +host_inst_rate 233440 # Simulator instruction rate (inst/s) +host_op_rate 280271 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 106315167 # Simulator tick rate (ticks/s) +host_mem_usage 292792 # Number of bytes of host memory used +host_seconds 1169.62 # Real time elapsed on the host sim_insts 273037218 # Number of instructions simulated sim_ops 327811600 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 1883840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 14654016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 168640 # Number of bytes read from this memory -system.physmem.bytes_read::total 16706496 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1883840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1883840 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 29435 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 228969 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 2635 # Number of read requests responded to by this memory -system.physmem.num_reads::total 261039 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 15156692 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 117900888 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 1356816 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 134414396 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 15156692 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 15156692 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 15156692 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 117900888 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 1356816 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 134414396 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 261040 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 1887808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 14649536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 167872 # Number of bytes read from this memory +system.physmem.bytes_read::total 16705216 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1887808 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1887808 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 29497 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 228899 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 2623 # Number of read requests responded to by this memory +system.physmem.num_reads::total 261019 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 15181566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 117810129 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 1350010 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 134341706 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 15181566 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 15181566 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 15181566 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 117810129 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 1350010 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 134341706 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 261020 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 261040 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 261020 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 16706560 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 16705280 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 16706560 # Total read bytes from the system interface side +system.physmem.bytesReadSys 16705280 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1259 # Per bank write bursts -system.physmem.perBankRdBursts::1 69986 # Per bank write bursts +system.physmem.perBankRdBursts::0 1258 # Per bank write bursts +system.physmem.perBankRdBursts::1 69987 # Per bank write bursts system.physmem.perBankRdBursts::2 1297 # Per bank write bursts system.physmem.perBankRdBursts::3 10756 # Per bank write bursts -system.physmem.perBankRdBursts::4 42908 # Per bank write bursts +system.physmem.perBankRdBursts::4 42907 # Per bank write bursts system.physmem.perBankRdBursts::5 121816 # Per bank write bursts system.physmem.perBankRdBursts::6 153 # Per bank write bursts -system.physmem.perBankRdBursts::7 261 # Per bank write bursts -system.physmem.perBankRdBursts::8 228 # Per bank write bursts +system.physmem.perBankRdBursts::7 252 # Per bank write bursts +system.physmem.perBankRdBursts::8 224 # Per bank write bursts system.physmem.perBankRdBursts::9 562 # Per bank write bursts system.physmem.perBankRdBursts::10 7773 # Per bank write bursts system.physmem.perBankRdBursts::11 812 # Per bank write bursts system.physmem.perBankRdBursts::12 1213 # Per bank write bursts system.physmem.perBankRdBursts::13 743 # Per bank write bursts -system.physmem.perBankRdBursts::14 662 # Per bank write bursts -system.physmem.perBankRdBursts::15 611 # Per bank write bursts +system.physmem.perBankRdBursts::14 657 # Per bank write bursts +system.physmem.perBankRdBursts::15 610 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -80,14 +80,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 124290963000 # Total gap between requests +system.physmem.totGap 124348687000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 261040 # Read request sizes (log2) +system.physmem.readPktSize::6 261020 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -95,20 +95,20 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 204132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 43333 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 12134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 305 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 233 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 211 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 177 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 64 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 204123 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 43351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 303 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 238 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 212 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 241 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 31 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 24 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -191,29 +191,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67943 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 245.854084 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 180.733686 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 200.637928 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 18270 26.89% 26.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22179 32.64% 59.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 11425 16.82% 76.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6866 10.11% 86.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4751 6.99% 93.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2068 3.04% 96.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1319 1.94% 98.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 392 0.58% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 673 0.99% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67943 # Bytes accessed per row activation -system.physmem.totQLat 4615275409 # Total ticks spent queuing -system.physmem.totMemAccLat 9509775409 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1305200000 # Total ticks spent in databus transfers -system.physmem.avgQLat 17680.34 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 67933 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 245.871432 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 180.817049 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 200.519544 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 18227 26.83% 26.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22195 32.67% 59.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 11448 16.85% 76.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6857 10.09% 86.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4767 7.02% 93.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2062 3.04% 96.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1306 1.92% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 411 0.61% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 660 0.97% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 67933 # Bytes accessed per row activation +system.physmem.totQLat 4577430956 # Total ticks spent queuing +system.physmem.totMemAccLat 9471555956 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1305100000 # Total ticks spent in databus transfers +system.physmem.avgQLat 17536.71 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 36430.34 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 134.41 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 36286.71 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 134.34 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 134.41 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 134.34 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.05 # Data bus utilization in percentage @@ -221,66 +221,66 @@ system.physmem.busUtilRead 1.05 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.60 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 193087 # Number of row buffer hits during reads +system.physmem.readRowHits 193077 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 73.97 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 476137.61 # Average gap between requests +system.physmem.avgGap 476395.25 # Average gap between requests system.physmem.pageHitRate 73.97 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 450177000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 239263365 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1773833040 # Energy for read commands per rank (pJ) +system.physmem_0.actEnergy 450269820 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 239312700 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1773761640 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 9685497120.000002 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4649003790 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 227628000 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 45880019340 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 3639028320 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 957591945 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 67502066010 # Total energy per rank (pJ) -system.physmem_0.averagePower 543.097094 # Core power per rank (mW) -system.physmem_0.totalIdleTime 113501776163 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 155671000 # Time in different power states -system.physmem_0.memoryStateTime::REF 4098592000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 3412225500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 9476337397 # Time in different power states -system.physmem_0.memoryStateTime::ACT 6534800587 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 100613346016 # Time in different power states -system.physmem_1.actEnergy 35000280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 18576525 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 89985420 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 9689184960.000002 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4649576640 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 227532000 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 45899424420 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 3643060800 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 957889500 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 67530012480 # Total energy per rank (pJ) +system.physmem_0.averagePower 543.069721 # Core power per rank (mW) +system.physmem_0.totalIdleTime 113559853415 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 155359000 # Time in different power states +system.physmem_0.memoryStateTime::REF 4100146000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 3415967750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 9487195385 # Time in different power states +system.physmem_0.memoryStateTime::ACT 6533205335 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 100656823030 # Time in different power states +system.physmem_1.actEnergy 34836060 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 18489240 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 89914020 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3070126800.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 722159790 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 122839680 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 10172185800 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 3790789440 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 22016840895 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 40039093920 # Total energy per rank (pJ) -system.physmem_1.averagePower 322.140000 # Core power per rank (mW) -system.physmem_1.totalIdleTime 122386077248 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 197400000 # Time in different power states -system.physmem_1.memoryStateTime::REF 1302732000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 90206777750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 9871788058 # Time in different power states -system.physmem_1.memoryStateTime::ACT 404763252 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 22307511440 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 35978086 # Number of BP lookups -system.cpu.branchPred.condPredicted 19268966 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 984583 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17896722 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13923101 # Number of BTB hits +system.physmem_1.refreshEnergy 3070741440.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 722151240 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 123038400 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 10175174880 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 3785444640 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 22033476180 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 40053946380 # Total energy per rank (pJ) +system.physmem_1.averagePower 322.109899 # Core power per rank (mW) +system.physmem_1.totalIdleTime 122443240524 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 197934000 # Time in different power states +system.physmem_1.memoryStateTime::REF 1303004000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 90271203500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 9858082832 # Time in different power states +system.physmem_1.memoryStateTime::ACT 404517976 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 22313954192 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 35976625 # Number of BP lookups +system.cpu.branchPred.condPredicted 19268286 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 984581 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 17895680 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13922117 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 77.796934 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6952398 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 77.795965 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6952257 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4419 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2517542 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2473672 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 43870 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 129186 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectLookups 2517536 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2473662 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 43874 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 129189 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -310,7 +310,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -340,7 +340,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -370,7 +370,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -401,135 +401,135 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 124290972500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 248581946 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 124348696500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 248697394 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12982171 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 309515100 # Number of instructions fetch has processed -system.cpu.fetch.Branches 35978086 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23349171 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 231243677 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1995433 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1630 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 13177926 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 309504909 # Number of instructions fetch has processed +system.cpu.fetch.Branches 35976625 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23348036 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 231160130 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1995425 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1604 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 63 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3229 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 82227465 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 34636 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 245228486 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.518257 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.300334 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3168 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 82224377 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 34576 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 245340603 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.517503 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.300446 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 84781187 34.57% 34.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 40505386 16.52% 51.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 28011183 11.42% 62.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 91930730 37.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 84898952 34.60% 34.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 40504202 16.51% 51.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 28011427 11.42% 62.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 91926022 37.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 245228486 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.144733 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.245123 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 27310570 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 94773867 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 97190577 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 25089647 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 863825 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6682147 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 245340603 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.144660 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.244504 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 27511038 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 94682480 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 97198198 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 25085064 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 863823 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6682260 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 134191 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 348416966 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3358743 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 863825 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 44033987 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38819082 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 289712 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 104520763 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 56701117 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 344543720 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1460141 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 7869954 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 94767 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 8436803 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 28433094 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 3429388 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 394731046 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2217541719 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 335903437 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 192790757 # Number of floating rename lookups +system.cpu.decode.DecodedInsts 348414004 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3355254 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 863823 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 44231004 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38750016 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 289461 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 104525811 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 56680488 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 344543449 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1457117 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 7869034 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 94704 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 8433947 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 28409379 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 3429059 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 394730853 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2217537837 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 335903225 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 192790660 # Number of floating rename lookups system.cpu.rename.CommittedMaps 372230048 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22500998 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 11600 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11566 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 59469204 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 89978957 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 84398693 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2368147 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1979963 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 343241150 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22616 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 339372334 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 953627 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 15452166 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 36722458 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 496 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 245228486 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.383903 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.138993 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 22500805 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11602 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11569 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 59464824 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89978946 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 84398563 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2367642 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1978869 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 343240723 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22618 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 339371435 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 952430 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 15451741 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 36726619 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 498 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 245340603 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.383266 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.138851 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 64185587 26.17% 26.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 77296840 31.52% 57.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 59648022 24.32% 82.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 34412911 14.03% 96.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 8897509 3.63% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 775021 0.32% 99.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 12596 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 64256390 26.19% 26.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 77349427 31.53% 57.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 59666013 24.32% 82.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 34385256 14.02% 96.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 8895869 3.63% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 775150 0.32% 99.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 12498 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 245228486 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 245340603 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8796506 6.82% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7321 0.01% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 160578 0.12% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 165226 0.13% 7.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 81752 0.06% 7.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 59978 0.05% 7.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 823294 0.64% 7.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 313002 0.24% 8.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 382743 0.30% 8.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.36% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 27474499 21.29% 29.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 41314471 32.01% 61.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 30691566 23.78% 85.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 18785214 14.56% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8783262 6.81% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7311 0.01% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 160118 0.12% 6.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 165260 0.13% 7.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 81600 0.06% 7.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 59605 0.05% 7.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 821029 0.64% 7.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 312918 0.24% 8.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 382736 0.30% 8.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 27486319 21.30% 29.64% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 41316597 32.01% 61.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 30690860 23.78% 85.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 18793838 14.56% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 108168622 31.87% 31.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2148105 0.63% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 108168046 31.87% 31.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2148103 0.63% 32.51% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.51% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.51% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.51% # Type of FU issued @@ -550,93 +550,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.51% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.51% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.51% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6799290 2.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6799230 2.00% 34.51% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8596304 2.53% 37.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3207462 0.95% 37.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1592646 0.47% 38.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20838335 6.14% 44.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7175285 2.11% 46.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7140600 2.10% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8596305 2.53% 37.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3207463 0.95% 37.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1592644 0.47% 38.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20838397 6.14% 44.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7175267 2.11% 46.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7140594 2.10% 48.82% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 175297 0.05% 48.87% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 46512146 13.71% 62.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 55971174 16.49% 79.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 43494368 12.82% 91.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 27552700 8.12% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 46512276 13.71% 62.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 55971076 16.49% 79.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 43494028 12.82% 91.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 27552709 8.12% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 339372334 # Type of FU issued -system.cpu.iq.rate 1.365233 # Inst issue rate -system.cpu.iq.fu_busy_cnt 129056150 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.380279 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 765892553 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 235176629 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 219155615 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 288090378 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 123554179 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 116971321 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 298827775 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 169600709 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5587408 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 339371435 # Type of FU issued +system.cpu.iq.rate 1.364596 # Inst issue rate +system.cpu.iq.fu_busy_cnt 129061453 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.380296 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 766002730 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 235175743 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 219154982 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 288094626 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 123554211 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 116970856 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 298827396 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 169605492 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5587628 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4246682 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7095 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14879 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2023076 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4246671 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7079 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14875 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2022946 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 158632 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 537261 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 158625 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 537538 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 863825 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1349614 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1747627 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 343265167 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 863823 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1349690 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1747618 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 343264743 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 89978957 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 84398693 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 11583 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6712 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1741146 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14879 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 437892 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 454499 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 892391 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 337381646 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 89446380 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1990688 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 89978946 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 84398563 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 11585 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6720 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1741103 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14875 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 437791 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 454404 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 892195 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 337380808 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 89446151 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1990627 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1401 # number of nop insts executed -system.cpu.iew.exec_refs 172578078 # number of memory reference insts executed -system.cpu.iew.exec_branches 31542222 # Number of branches executed -system.cpu.iew.exec_stores 83131698 # Number of stores executed -system.cpu.iew.exec_rate 1.357225 # Inst execution rate -system.cpu.iew.wb_sent 336270787 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 336126936 # cumulative count of insts written-back -system.cpu.iew.wb_producers 153093104 # num instructions producing a value -system.cpu.iew.wb_consumers 267318257 # num instructions consuming a value -system.cpu.iew.wb_rate 1.352178 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.572700 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 14160521 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 1402 # number of nop insts executed +system.cpu.iew.exec_refs 172577891 # number of memory reference insts executed +system.cpu.iew.exec_branches 31542264 # Number of branches executed +system.cpu.iew.exec_stores 83131740 # Number of stores executed +system.cpu.iew.exec_rate 1.356592 # Inst execution rate +system.cpu.iew.wb_sent 336269596 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 336125838 # cumulative count of insts written-back +system.cpu.iew.wb_producers 153087171 # num instructions producing a value +system.cpu.iew.wb_consumers 267302196 # num instructions consuming a value +system.cpu.iew.wb_rate 1.351545 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.572712 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 14157457 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 850692 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 243036852 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.348817 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.044097 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 243149020 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.348195 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.043585 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 113296519 46.62% 46.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 65998128 27.16% 73.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 21346559 8.78% 82.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13163754 5.42% 87.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8182652 3.37% 91.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4361649 1.79% 93.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2983865 1.23% 94.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2442147 1.00% 95.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11261579 4.63% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 113393055 46.64% 46.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 66012492 27.15% 73.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 21342156 8.78% 82.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13170021 5.42% 87.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8181798 3.36% 91.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4369731 1.80% 93.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2981979 1.23% 94.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2444680 1.01% 95.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11253108 4.63% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 243036852 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 243149020 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037830 # Number of instructions committed system.cpu.commit.committedOps 327812212 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -686,35 +686,35 @@ system.cpu.commit.op_class_0::FloatMemWrite 27367218 8.35% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 327812212 # Class of committed instruction -system.cpu.commit.bw_lim_events 11261579 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 573745483 # The number of ROB reads -system.cpu.rob.rob_writes 686139464 # The number of ROB writes -system.cpu.timesIdled 39266 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3353460 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 11253108 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 573863058 # The number of ROB reads +system.cpu.rob.rob_writes 686133284 # The number of ROB writes +system.cpu.timesIdled 39270 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3356791 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273037218 # Number of Instructions Simulated system.cpu.committedOps 327811600 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.910432 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.910432 # CPI: Total CPI of All Threads -system.cpu.ipc 1.098379 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.098379 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 325197340 # number of integer regfile reads -system.cpu.int_regfile_writes 134110925 # number of integer regfile writes -system.cpu.fp_regfile_reads 186451715 # number of floating regfile reads -system.cpu.fp_regfile_writes 131763174 # number of floating regfile writes -system.cpu.cc_regfile_reads 1279529156 # number of cc regfile reads -system.cpu.cc_regfile_writes 79965327 # number of cc regfile writes -system.cpu.misc_regfile_reads 1056169060 # number of misc regfile reads +system.cpu.cpi 0.910855 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.910855 # CPI: Total CPI of All Threads +system.cpu.ipc 1.097869 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.097869 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 325196483 # number of integer regfile reads +system.cpu.int_regfile_writes 134110146 # number of integer regfile writes +system.cpu.fp_regfile_reads 186451278 # number of floating regfile reads +system.cpu.fp_regfile_writes 131762607 # number of floating regfile writes +system.cpu.cc_regfile_reads 1279524952 # number of cc regfile reads +system.cpu.cc_regfile_writes 79965424 # number of cc regfile writes +system.cpu.misc_regfile_reads 1056166666 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1542798 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.843941 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 161960642 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1543310 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 104.943687 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 91635000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.843941 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999695 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999695 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1542800 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.844324 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 161972906 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1543312 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 104.951498 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 90889000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.844324 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999696 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999696 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id @@ -722,121 +722,121 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 89 system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 333233788 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 333233788 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 80947765 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 80947765 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 80921307 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 80921307 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 69703 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 69703 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 333232684 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 333232684 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 80960207 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 80960207 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 80921128 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 80921128 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 69704 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 69704 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10908 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10908 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 161869072 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 161869072 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 161938775 # number of overall hits -system.cpu.dcache.overall_hits::total 161938775 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2753247 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2753247 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1131392 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1131392 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 161881335 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 161881335 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 161951039 # number of overall hits +system.cpu.dcache.overall_hits::total 161951039 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2740251 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2740251 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1131571 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1131571 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3884639 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3884639 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3884657 # number of overall misses -system.cpu.dcache.overall_misses::total 3884657 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 47533202500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 47533202500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9194702918 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9194702918 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 3871822 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3871822 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3871840 # number of overall misses +system.cpu.dcache.overall_misses::total 3871840 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 47426688500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 47426688500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9189520410 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9189520410 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 194000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 194000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 56727905418 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 56727905418 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 56727905418 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 56727905418 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 83701012 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 83701012 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 56616208910 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 56616208910 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 56616208910 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 56616208910 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 83700458 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 83700458 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 69721 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 69721 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 69722 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 69722 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10912 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10912 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 165753711 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 165753711 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 165823432 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 165823432 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032894 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.032894 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013789 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013789 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 165753157 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 165753157 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 165822879 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 165822879 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032739 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.032739 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013791 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013791 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000258 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.000258 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000367 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000367 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023436 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023436 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023426 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023426 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17264.416342 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17264.416342 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8126.894054 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 8126.894054 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.023359 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023359 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023349 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023349 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17307.424940 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17307.424940 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8121.028561 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8121.028561 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 48500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 48500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14603.134401 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14603.134401 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14603.066736 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14603.066736 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14622.626998 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14622.626998 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14622.559018 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14622.559018 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1098365 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1097340 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 136254 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 136170 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 8.061158 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 1542798 # number of writebacks -system.cpu.dcache.writebacks::total 1542798 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1430654 # 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number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1845527195 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1845527195 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1269000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1269000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28953821695 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28953821695 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28955090695 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28955090695 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015801 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015801 # 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number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28913598193 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28914868193 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28914868193 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015802 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015802 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002690 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002690 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000158 # mshr miss rate for SoftPFReq accesses @@ -845,397 +845,396 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009311 system.cpu.dcache.demand_mshr_miss_rate::total 0.009311 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009307 # 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Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 157 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 100 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 160 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 97 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 70 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 165181558 # Number of tag accesses -system.cpu.icache.tags.data_accesses 165181558 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 81493663 # 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number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 8421387941 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 8421387941 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 8421387941 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 8421387941 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 82227443 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 82227443 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 82227443 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 82227443 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 82227443 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 82227443 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008924 # 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average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 139290 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 165175152 # Number of tag accesses +system.cpu.icache.tags.data_accesses 165175152 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 81490807 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 81490807 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 81490807 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 81490807 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 81490807 # number of overall hits +system.cpu.icache.overall_hits::total 81490807 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 733549 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 733549 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 733549 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 733549 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 733549 # number of overall misses +system.cpu.icache.overall_misses::total 733549 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 8424023442 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 8424023442 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 8424023442 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 8424023442 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 8424023442 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 8424023442 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 82224356 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 82224356 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 82224356 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 82224356 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 82224356 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 82224356 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008921 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008921 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.008921 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.008921 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.008921 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.008921 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11483.927375 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 11483.927375 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 11483.927375 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 11483.927375 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 11483.927375 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 11483.927375 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 138949 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 124 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 4412 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4383 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 31.570716 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 31.701802 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 41.333333 # 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Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 79.842232 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.314595 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004873 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.319468 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 172 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 6120 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 12 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::2 48 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 101 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 90 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 163 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 542 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 737 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 554 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4127 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.011536 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.373718 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 70566797 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 70566797 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 968251 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61837.344070 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4538943 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2268977 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254452 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 51443 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 51442 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.137720 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3749.890977 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3749.890977 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15588.235294 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15588.235294 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86997.953615 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86997.953615 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 83114.990847 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 83114.990847 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72598.448060 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72598.448060 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 83114.990847 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72644.559391 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73839.839472 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 83114.990847 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72644.559391 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3749.890977 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61690.732691 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4538483 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2268732 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254880 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 51558 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 51557 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 2049252 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 968251 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1300691 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 55450 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 2049022 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 968252 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1300460 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 55547 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 18 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 18 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 220730 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 220730 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 726673 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322580 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2179407 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4629454 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6808861 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92974976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197510912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 290485888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 55532 # Total snoops (count) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 726441 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322582 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2178711 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4629460 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6808171 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92945280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197511168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 290456448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 55629 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 5248 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2325451 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.131557 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.338010 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 2325318 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.131791 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.338265 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2019523 86.84% 86.84% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 305927 13.16% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2018862 86.82% 86.82% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 306455 13.18% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2325451 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4538413500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 3.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1090077361 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2325318 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4537953500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 3.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1089727365 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2314996455 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2314999455 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 261057 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 261037 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 253739 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 260300 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 260286 # Transaction distribution system.membus.trans_dist::UpgradeReq 17 # Transaction distribution -system.membus.trans_dist::ReadExReq 739 # Transaction distribution -system.membus.trans_dist::ReadExResp 739 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 260301 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 522096 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 522096 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16706496 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 16706496 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 733 # Transaction distribution +system.membus.trans_dist::ReadExResp 733 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 260287 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 522056 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 522056 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16705216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 16705216 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 261057 # Request fanout histogram +system.membus.snoop_fanout::samples 261037 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 261057 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 261037 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 261057 # Request fanout histogram -system.membus.reqLayer0.occupancy 317283410 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 261037 # Request fanout histogram +system.membus.reqLayer0.occupancy 316168930 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1389540628 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1389509080 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 8f8bc9d4d..bcc6de449 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.339013 # Number of seconds simulated -sim_ticks 339012932000 # Number of ticks simulated -final_tick 339012932000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.338999 # Number of seconds simulated +sim_ticks 338998876000 # Number of ticks simulated +final_tick 338998876000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 218277 # Simulator instruction rate (inst/s) -host_op_rate 268728 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 115505586 # Simulator tick rate (ticks/s) -host_mem_usage 277356 # Number of bytes of host memory used -host_seconds 2935.04 # Real time elapsed on the host +host_inst_rate 210128 # Simulator instruction rate (inst/s) +host_op_rate 258696 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 111189218 # Simulator tick rate (ticks/s) +host_mem_usage 277020 # Number of bytes of host memory used +host_seconds 3048.85 # Real time elapsed on the host sim_insts 640649299 # Number of instructions simulated sim_ops 788724958 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 269632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 48043328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 12965504 # Number of bytes read from this memory -system.physmem.bytes_read::total 61278464 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 269632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 269632 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4245696 # Number of bytes written to this memory -system.physmem.bytes_written::total 4245696 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4213 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 750677 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 202586 # Number of read requests responded to by this memory -system.physmem.num_reads::total 957476 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66339 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66339 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 795344 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 141715325 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 38244866 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 180755535 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 795344 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 795344 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 12523699 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 12523699 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 12523699 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 795344 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 141715325 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 38244866 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 193279235 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 957477 # Number of read requests accepted -system.physmem.writeReqs 66339 # Number of write requests accepted -system.physmem.readBursts 957477 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66339 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 61258752 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19776 # Total number of bytes read from write queue -system.physmem.bytesWritten 4240576 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 61278528 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4245696 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 309 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 54 # Number of DRAM write bursts merged with an existing one +system.physmem.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 268928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 48012032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 12961152 # Number of bytes read from this memory +system.physmem.bytes_read::total 61242112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 268928 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 268928 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4244288 # Number of bytes written to this memory +system.physmem.bytes_written::total 4244288 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4202 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 750188 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 202518 # Number of read requests responded to by this memory +system.physmem.num_reads::total 956908 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66317 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66317 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 793301 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 141628883 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 38233613 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 180655797 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 793301 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 793301 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 12520065 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 12520065 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 12520065 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 793301 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 141628883 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 38233613 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 193175862 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 956909 # Number of read requests accepted +system.physmem.writeReqs 66317 # Number of write requests accepted +system.physmem.readBursts 956909 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66317 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 61223936 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 18240 # Total number of bytes read from write queue +system.physmem.bytesWritten 4238080 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 61242176 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4244288 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 285 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 65 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 19910 # Per bank write bursts -system.physmem.perBankRdBursts::1 19533 # Per bank write bursts -system.physmem.perBankRdBursts::2 657271 # Per bank write bursts -system.physmem.perBankRdBursts::3 20982 # Per bank write bursts -system.physmem.perBankRdBursts::4 19710 # Per bank write bursts -system.physmem.perBankRdBursts::5 21143 # Per bank write bursts -system.physmem.perBankRdBursts::6 19634 # Per bank write bursts -system.physmem.perBankRdBursts::7 20055 # Per bank write bursts -system.physmem.perBankRdBursts::8 19495 # Per bank write bursts -system.physmem.perBankRdBursts::9 20079 # Per bank write bursts -system.physmem.perBankRdBursts::10 19428 # Per bank write bursts -system.physmem.perBankRdBursts::11 19728 # Per bank write bursts -system.physmem.perBankRdBursts::12 19649 # Per bank write bursts -system.physmem.perBankRdBursts::13 21208 # Per bank write bursts -system.physmem.perBankRdBursts::14 19490 # Per bank write bursts -system.physmem.perBankRdBursts::15 19853 # Per bank write bursts -system.physmem.perBankWrBursts::0 4286 # Per bank write bursts +system.physmem.perBankRdBursts::0 19928 # Per bank write bursts +system.physmem.perBankRdBursts::1 19580 # Per bank write bursts +system.physmem.perBankRdBursts::2 657267 # Per bank write bursts +system.physmem.perBankRdBursts::3 20958 # Per bank write bursts +system.physmem.perBankRdBursts::4 19729 # Per bank write bursts +system.physmem.perBankRdBursts::5 20737 # Per bank write bursts +system.physmem.perBankRdBursts::6 19560 # Per bank write bursts +system.physmem.perBankRdBursts::7 19988 # Per bank write bursts +system.physmem.perBankRdBursts::8 19522 # Per bank write bursts +system.physmem.perBankRdBursts::9 20089 # Per bank write bursts +system.physmem.perBankRdBursts::10 19525 # Per bank write bursts +system.physmem.perBankRdBursts::11 19708 # Per bank write bursts +system.physmem.perBankRdBursts::12 19661 # Per bank write bursts +system.physmem.perBankRdBursts::13 21032 # Per bank write bursts +system.physmem.perBankRdBursts::14 19553 # Per bank write bursts +system.physmem.perBankRdBursts::15 19787 # Per bank write bursts +system.physmem.perBankWrBursts::0 4255 # Per bank write bursts system.physmem.perBankWrBursts::1 4105 # Per bank write bursts -system.physmem.perBankWrBursts::2 4145 # Per bank write bursts -system.physmem.perBankWrBursts::3 4153 # Per bank write bursts -system.physmem.perBankWrBursts::4 4249 # Per bank write bursts -system.physmem.perBankWrBursts::5 4230 # Per bank write bursts -system.physmem.perBankWrBursts::6 4173 # Per bank write bursts +system.physmem.perBankWrBursts::2 4143 # Per bank write bursts +system.physmem.perBankWrBursts::3 4152 # Per bank write bursts +system.physmem.perBankWrBursts::4 4244 # Per bank write bursts +system.physmem.perBankWrBursts::5 4226 # Per bank write bursts +system.physmem.perBankWrBursts::6 4174 # Per bank write bursts system.physmem.perBankWrBursts::7 4096 # Per bank write bursts system.physmem.perBankWrBursts::8 4096 # Per bank write bursts system.physmem.perBankWrBursts::9 4096 # Per bank write bursts -system.physmem.perBankWrBursts::10 4094 # Per bank write bursts +system.physmem.perBankWrBursts::10 4096 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts -system.physmem.perBankWrBursts::12 4098 # Per bank write bursts -system.physmem.perBankWrBursts::13 4096 # Per bank write bursts +system.physmem.perBankWrBursts::12 4097 # Per bank write bursts +system.physmem.perBankWrBursts::13 4095 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4149 # Per bank write bursts +system.physmem.perBankWrBursts::15 4152 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 339012921500 # Total gap between requests +system.physmem.totGap 338998865500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 957477 # Read request sizes (log2) +system.physmem.readPktSize::6 956909 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66339 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 764538 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 120546 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 15621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6697 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6433 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7720 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 9109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 10145 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 6841 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3643 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2525 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1571 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 672 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66317 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 764114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 120431 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 15489 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6701 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6466 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7783 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 9162 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 10166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 6863 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 3709 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2433 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1574 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1088 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 644 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see @@ -149,187 +149,183 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 537 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2089 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3068 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3545 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4065 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 553 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 931 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2610 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5885 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4080 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 195212 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 335.517735 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 192.597798 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 355.506182 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 64341 32.96% 32.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 60661 31.07% 64.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 15753 8.07% 72.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3211 1.64% 73.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3578 1.83% 75.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2458 1.26% 76.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2478 1.27% 78.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 34211 17.53% 95.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8521 4.36% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 195212 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3994 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 204.692539 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 35.349556 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2360.542955 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 3971 99.42% 99.42% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-8191 10 0.25% 99.67% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-12287 5 0.13% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-16383 1 0.03% 99.82% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::16384-20479 1 0.03% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::24576-28671 1 0.03% 99.87% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::28672-32767 1 0.03% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::36864-40959 1 0.03% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::45056-49151 1 0.03% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::69632-73727 1 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::98304-102399 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3994 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3994 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.589634 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.506417 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.926291 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3368 84.33% 84.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 17 0.43% 84.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 396 9.91% 94.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 46 1.15% 95.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 24 0.60% 96.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 17 0.43% 96.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 21 0.53% 97.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 18 0.45% 97.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 15 0.38% 98.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 17 0.43% 98.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 13 0.33% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 10 0.25% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 7 0.18% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 8 0.20% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 8 0.20% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 4 0.10% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 1 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 1 0.03% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 1 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 1 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 1 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3994 # Writes before turning the bus around for reads -system.physmem.totQLat 27473404757 # Total ticks spent queuing -system.physmem.totMemAccLat 45420304757 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4785840000 # Total ticks spent in databus transfers -system.physmem.avgQLat 28702.80 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 195260 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 335.246789 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 192.210032 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 355.737014 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 64653 33.11% 33.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 60691 31.08% 64.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 15519 7.95% 72.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3195 1.64% 73.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3493 1.79% 75.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2388 1.22% 76.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2513 1.29% 78.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 34304 17.57% 95.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8504 4.36% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 195260 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3991 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 173.742922 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 35.179059 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 1709.732000 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 3971 99.50% 99.50% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-8191 9 0.23% 99.72% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-12287 3 0.08% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-16383 3 0.08% 99.87% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16384-20479 1 0.03% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::24576-28671 1 0.03% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::36864-40959 1 0.03% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-49151 1 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::73728-77823 1 0.03% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 3991 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3991 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.592333 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.512127 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.873555 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3350 83.94% 83.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 21 0.53% 84.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 395 9.90% 94.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 55 1.38% 95.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 24 0.60% 96.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 19 0.48% 96.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 17 0.43% 97.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 26 0.65% 97.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 20 0.50% 98.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 16 0.40% 98.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 9 0.23% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 11 0.28% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 7 0.18% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 5 0.13% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 4 0.10% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 6 0.15% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 1 0.03% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 3 0.08% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 2 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3991 # Writes before turning the bus around for reads +system.physmem.totQLat 27417238749 # Total ticks spent queuing +system.physmem.totMemAccLat 45353938749 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4783120000 # Total ticks spent in databus transfers +system.physmem.avgQLat 28660.41 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47452.80 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 180.70 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 12.51 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 180.76 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 47410.41 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 180.60 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 12.50 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 180.66 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 12.52 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.51 # Data bus utilization in percentage system.physmem.busUtilRead 1.41 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.10 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.53 # Average write queue length when enqueuing -system.physmem.readRowHits 805066 # Number of row buffer hits during reads -system.physmem.writeRowHits 23137 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.11 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 34.91 # Row buffer hit rate for writes -system.physmem.avgGap 331126.81 # Average gap between requests -system.physmem.pageHitRate 80.92 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 894020820 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 475164360 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 5699412180 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 174541140 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 27331811520.000008 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 14462317590 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 674820000 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 138340924320 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 704060640 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 673701120.000000 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 189477322380 # Total energy per rank (pJ) -system.physmem_0.averagePower 558.908824 # Core power per rank (mW) -system.physmem_0.totalIdleTime 305437641889 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 528629764 # Time in different power states -system.physmem_0.memoryStateTime::REF 11569144000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 223118500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 1833570381 # Time in different power states -system.physmem_0.memoryStateTime::ACT 21477516347 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 303380953008 # Time in different power states -system.physmem_1.actEnergy 499878540 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 265665180 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1134760200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 171330840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 25420895760.000004 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 7011060990 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1362065280 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 70491607590 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 31027049280 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 25487678070 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 162872491950 # Total energy per rank (pJ) -system.physmem_1.averagePower 480.431501 # Core power per rank (mW) -system.physmem_1.totalIdleTime 320089357075 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 2604072271 # Time in different power states -system.physmem_1.memoryStateTime::REF 10809446000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 84703185250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 80799625521 # Time in different power states -system.physmem_1.memoryStateTime::ACT 5510033904 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 154586569054 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 174656775 # Number of BP lookups -system.cpu.branchPred.condPredicted 119110803 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 4015685 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 96721345 # Number of BTB lookups -system.cpu.branchPred.BTBHits 67754534 # Number of BTB hits +system.physmem.avgWrQLen 25.35 # Average write queue length when enqueuing +system.physmem.readRowHits 804753 # Number of row buffer hits during reads +system.physmem.writeRowHits 22823 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.12 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 34.45 # Row buffer hit rate for writes +system.physmem.avgGap 331304.00 # Average gap between requests +system.physmem.pageHitRate 80.91 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 893206860 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 474750705 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 5695906440 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 174321900 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 27330582240.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 14459296590 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 677245920 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 138340780680 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 698740320 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 673162065.000000 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 189465949500 # Total energy per rank (pJ) +system.physmem_0.averagePower 558.898453 # Core power per rank (mW) +system.physmem_0.totalIdleTime 305423895331 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 532417778 # Time in different power states +system.physmem_0.memoryStateTime::REF 11568510000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 220427000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 1819753036 # Time in different power states +system.physmem_0.memoryStateTime::ACT 21474052891 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 303383715295 # Time in different power states +system.physmem_1.actEnergy 500999520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 266260995 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1134381780 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 171346500 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 25447939920.000004 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 7069016310 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1362680640 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 70550856240 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 31070458080 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 25392894210 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 162967325295 # Total energy per rank (pJ) +system.physmem_1.averagePower 480.731167 # Core power per rank (mW) +system.physmem_1.totalIdleTime 319946801176 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 2603762514 # Time in different power states +system.physmem_1.memoryStateTime::REF 10820898000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 84317463250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 80912710040 # Time in different power states +system.physmem_1.memoryStateTime::ACT 5627391560 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 154716650636 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 174659469 # Number of BP lookups +system.cpu.branchPred.condPredicted 119114964 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4015677 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 96720579 # Number of BTB lookups +system.cpu.branchPred.BTBHits 67753891 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.051274 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18785121 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1299599 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 16716580 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 16702336 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 14244 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 1279516 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 70.051164 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18782444 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1299597 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 16716760 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 16702354 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 14406 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 1279517 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -359,7 +355,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -389,7 +385,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -419,7 +415,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -450,96 +446,96 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 339012932000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 678025865 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 338998876000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 677997753 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 34354212 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 824273790 # Number of instructions fetch has processed -system.cpu.fetch.Branches 174656775 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 103241991 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 639159762 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8068079 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 2457 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 35007390 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 824275552 # Number of instructions fetch has processed +system.cpu.fetch.Branches 174659469 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 103238689 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 638483488 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 8068049 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 3174 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3206 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 247740942 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 12520 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 677553693 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.500365 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.263651 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3169 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 247736654 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 13165 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 677531262 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.500399 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.263726 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 215486043 31.80% 31.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 148340760 21.89% 53.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72943473 10.77% 64.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 240783417 35.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 215511441 31.81% 31.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 148279019 21.89% 53.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72933920 10.76% 64.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 240806882 35.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 677553693 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.257596 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.215697 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 75112537 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 258679606 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 277758053 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 61982472 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4021025 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 20810112 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13117 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 924576668 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 11804380 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4021025 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 118056358 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 157938220 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 213059 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 294555904 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 102769127 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 906541450 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 6890856 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 27990855 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2220094 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 49338949 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 500517 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 980921468 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4318014727 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1001837715 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 677531262 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.257611 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.215750 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 75755548 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 258011846 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 277771746 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 61971111 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4021011 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 20808683 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13107 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 924572936 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 11806711 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4021011 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 118697379 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 157348847 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 212785 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 295131252 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 102119988 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 906539563 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 6891328 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 27972681 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2218640 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 49279009 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 483149 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 980928941 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4318000809 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1001835244 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 34457090 # Number of floating rename lookups system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 106143238 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6855 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6838 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 138815476 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 271882151 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 160587217 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 6164479 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 12153288 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 899827421 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 12582 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 860030622 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 9216880 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 111115045 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 244388609 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 428 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 677553693 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.269317 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.101593 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 106150711 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6852 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6840 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 138234074 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 271880895 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 160585540 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 6163609 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 12157039 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 899825913 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 12585 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 860027802 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 9216351 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 111113540 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 244391790 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 431 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 677531262 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.269355 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.103879 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 214894884 31.72% 31.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 182407403 26.92% 58.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 175555467 25.91% 84.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 92273782 13.62% 98.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12419846 1.83% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2311 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 215443123 31.80% 31.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 182412778 26.92% 58.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 173833847 25.66% 84.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 93421038 13.79% 98.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12418164 1.83% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2312 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 677553693 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 677531262 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 66603323 23.99% 23.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 18142 0.01% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 66604023 24.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 18144 0.01% 24.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 24.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 24.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 24.00% # attempts to use FU when none available @@ -569,15 +565,15 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 24.23% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 24.23% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.23% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 24.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 133475448 48.09% 72.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 66440411 23.94% 96.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 5100435 1.84% 98.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 5300037 1.91% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 132902314 47.88% 72.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 66436214 23.93% 96.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 5673709 2.04% 98.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 5298999 1.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 413090046 48.03% 48.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5187659 0.60% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 413088657 48.03% 48.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5187663 0.60% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 48.64% # Type of FU issued @@ -601,90 +597,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 48.64% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.07% 48.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 3187674 0.37% 49.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 2550149 0.30% 49.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 2550152 0.30% 49.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 11478193 1.33% 50.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 11478195 1.33% 50.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 259646740 30.19% 80.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 153401509 17.84% 98.74% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 7019167 0.82% 99.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 259646328 30.19% 80.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 153400482 17.84% 98.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 7019166 0.82% 99.55% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 3831957 0.45% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 860030622 # Type of FU issued -system.cpu.iq.rate 1.268433 # Inst issue rate -system.cpu.iq.fu_busy_cnt 277574685 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.322750 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2622330507 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 980332291 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 820083655 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 62075995 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 30641581 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 24878671 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1101050958 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 36554349 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 13986301 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 860027802 # Type of FU issued +system.cpu.iq.rate 1.268482 # Inst issue rate +system.cpu.iq.fu_busy_cnt 277570292 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.322746 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2621725269 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 980329256 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 820080739 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 62648240 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 30641595 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 24878674 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1100471505 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 37126589 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 13986954 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 19641213 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 120 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18827 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 31606721 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 19639957 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 122 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18816 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 31605044 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1918912 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 17820 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1918903 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 17949 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4021025 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 10591534 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6199 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 899849877 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 4021011 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 10591594 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 7946 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 899848641 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 271882151 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 160587217 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6842 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 967 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3331 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18827 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3295145 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3289956 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6585101 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 850175089 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 263374398 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9855533 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 271880895 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 160585540 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6845 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 969 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5082 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18816 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3295133 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3290188 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6585321 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 850172394 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 263373871 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9855408 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9874 # number of nop insts executed -system.cpu.iew.exec_refs 416064413 # number of memory reference insts executed -system.cpu.iew.exec_branches 143381564 # Number of branches executed -system.cpu.iew.exec_stores 152690015 # Number of stores executed -system.cpu.iew.exec_rate 1.253898 # Inst execution rate -system.cpu.iew.wb_sent 846298256 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 844962326 # cumulative count of insts written-back -system.cpu.iew.wb_producers 487342605 # num instructions producing a value -system.cpu.iew.wb_consumers 808106527 # num instructions consuming a value -system.cpu.iew.wb_rate 1.246210 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.603067 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 103169288 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 10143 # number of nop insts executed +system.cpu.iew.exec_refs 416062863 # number of memory reference insts executed +system.cpu.iew.exec_branches 143380865 # Number of branches executed +system.cpu.iew.exec_stores 152688992 # Number of stores executed +system.cpu.iew.exec_rate 1.253946 # Inst execution rate +system.cpu.iew.wb_sent 846295545 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 844959413 # cumulative count of insts written-back +system.cpu.iew.wb_producers 486195731 # num instructions producing a value +system.cpu.iew.wb_consumers 804663900 # num instructions consuming a value +system.cpu.iew.wb_rate 1.246257 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.604222 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 103166103 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 4002671 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 662973012 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.189687 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.047483 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 4002664 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 662950558 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.189727 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.047510 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 372633677 56.21% 56.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 137240232 20.70% 76.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 51341106 7.74% 84.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 28220443 4.26% 88.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 14381462 2.17% 91.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14774618 2.23% 93.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7871678 1.19% 94.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 6561077 0.99% 95.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29948719 4.52% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 372609039 56.20% 56.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 137243840 20.70% 76.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 51342182 7.74% 84.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 28218977 4.26% 88.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 14379686 2.17% 91.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14774384 2.23% 93.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7871744 1.19% 94.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6561841 0.99% 95.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29948865 4.52% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 662973012 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 662950558 # Number of insts commited each cycle system.cpu.commit.committedInsts 640654411 # Number of instructions committed system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -734,82 +730,82 @@ system.cpu.commit.op_class_0::FloatMemWrite 3830674 0.49% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction -system.cpu.commit.bw_lim_events 29948719 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1524914900 # The number of ROB reads -system.cpu.rob.rob_writes 1798382781 # The number of ROB writes -system.cpu.timesIdled 10519 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 472172 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 29948865 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1524889115 # The number of ROB reads +system.cpu.rob.rob_writes 1798376442 # The number of ROB writes +system.cpu.timesIdled 10544 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 466491 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 640649299 # Number of Instructions Simulated system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.058342 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.058342 # CPI: Total CPI of All Threads -system.cpu.ipc 0.944874 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.944874 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 868463326 # number of integer regfile reads -system.cpu.int_regfile_writes 500698648 # number of integer regfile writes -system.cpu.fp_regfile_reads 30616063 # number of floating regfile reads -system.cpu.fp_regfile_writes 22959490 # number of floating regfile writes -system.cpu.cc_regfile_reads 3322389826 # number of cc regfile reads -system.cpu.cc_regfile_writes 369207773 # number of cc regfile writes -system.cpu.misc_regfile_reads 606833337 # number of misc regfile reads +system.cpu.cpi 1.058298 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.058298 # CPI: Total CPI of All Threads +system.cpu.ipc 0.944914 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.944914 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 868460616 # number of integer regfile reads +system.cpu.int_regfile_writes 500698081 # number of integer regfile writes +system.cpu.fp_regfile_reads 30616065 # number of floating regfile reads +system.cpu.fp_regfile_writes 22959495 # number of floating regfile writes +system.cpu.cc_regfile_reads 3322380162 # number of cc regfile reads +system.cpu.cc_regfile_writes 369206587 # number of cc regfile writes +system.cpu.misc_regfile_reads 606831817 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2756453 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.911144 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 371050846 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2756965 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 134.586709 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 285699000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.911144 # Average occupied blocks per requestor +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2756456 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.910987 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 371049565 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2756968 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 134.586098 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 285993000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.910987 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999826 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999826 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 173 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 175 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 751747893 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 751747893 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 243127355 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 243127355 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 127907428 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 127907428 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 751745414 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 751745414 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 243126159 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 243126159 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 127907378 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 127907378 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 371034783 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 371034783 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 371037940 # number of overall hits -system.cpu.dcache.overall_hits::total 371037940 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2401348 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2401348 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1044049 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1044049 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 371033537 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 371033537 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 371036694 # number of overall hits +system.cpu.dcache.overall_hits::total 371036694 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2401303 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2401303 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1044099 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1044099 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3445397 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3445397 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3446044 # number of overall misses -system.cpu.dcache.overall_misses::total 3446044 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 80462385500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 80462385500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10017236850 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10017236850 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 3445402 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3445402 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3446049 # number of overall misses +system.cpu.dcache.overall_misses::total 3446049 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 80431299000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 80431299000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9946595850 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9946595850 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 140000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 140000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 90479622350 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 90479622350 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 90479622350 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 90479622350 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 245528703 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 245528703 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 90377894850 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 90377894850 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 90377894850 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 90377894850 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 245527462 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 245527462 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3804 # number of SoftPFReq accesses(hits+misses) @@ -818,470 +814,469 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5741 system.cpu.dcache.LoadLockedReq_accesses::total 5741 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 374480180 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 374480180 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 374483984 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 374483984 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 374478939 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 374478939 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 374482743 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 374482743 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009780 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.009780 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008096 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.008096 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008097 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.008097 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.170084 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.170084 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000348 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000348 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009200 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009200 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009201 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009201 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.009202 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.009202 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33507.174096 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33507.174096 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9594.604133 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9594.604133 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33494.856334 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33494.856334 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9526.487287 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9526.487287 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26261.015015 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26261.015015 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26256.084470 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26256.084470 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 71 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 355259 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4691 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 71 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 75.732040 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2756453 # number of writebacks -system.cpu.dcache.writebacks::total 2756453 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 365871 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 365871 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323013 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 323013 # number of WriteReq MSHR hits +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26231.451323 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26231.451323 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26226.526335 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26226.526335 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 336970 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4742 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 71.060734 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2756456 # number of writebacks +system.cpu.dcache.writebacks::total 2756456 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 365826 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 365826 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323069 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 323069 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 688884 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 688884 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 688884 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 688884 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 688895 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 688895 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 688895 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 688895 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035477 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 2035477 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721036 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 721036 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721030 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 721030 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 642 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 642 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2756513 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2756513 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2757155 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2757155 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75218139500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75218139500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5959023850 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5959023850 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5957500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5957500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 81177163350 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 81177163350 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 81183120850 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 81183120850 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2756507 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2756507 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2757149 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2757149 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75180323500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75180323500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5949856850 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5949856850 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5764000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5764000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 81130180350 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 81130180350 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 81135944350 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 81135944350 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.008290 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.008290 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005592 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005592 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005591 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005591 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168770 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168770 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007361 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.007361 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007363 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.007363 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36953.568869 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36953.568869 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8264.530273 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8264.530273 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 9279.595016 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 9279.595016 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29449.222024 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29449.222024 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29444.525553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29444.525553 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1979522 # number of replacements -system.cpu.icache.tags.tagsinuse 510.550232 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 245757624 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1980032 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 124.118006 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 275112500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.550232 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997168 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997168 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36934.990422 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36934.990422 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8251.885289 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8251.885289 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8978.193146 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8978.193146 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29432.241728 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29432.241728 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29427.479019 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29427.479019 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 1980154 # number of replacements +system.cpu.icache.tags.tagsinuse 511.083769 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 245752724 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1980664 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 124.075928 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 275035500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.083769 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998210 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998210 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 113 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 112 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 332 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 334 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 497462038 # Number of tag accesses -system.cpu.icache.tags.data_accesses 497462038 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 245757684 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 245757684 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 245757684 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 245757684 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 245757684 # number of overall hits -system.cpu.icache.overall_hits::total 245757684 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1983224 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1983224 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1983224 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1983224 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1983224 # number of overall misses -system.cpu.icache.overall_misses::total 1983224 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16215368926 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16215368926 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16215368926 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16215368926 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16215368926 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16215368926 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 247740908 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 247740908 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 247740908 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 247740908 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 247740908 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 247740908 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008005 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.008005 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.008005 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.008005 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.008005 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.008005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8176.266991 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8176.266991 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8176.266991 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8176.266991 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8176.266991 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8176.266991 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 83168 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 761 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2904 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 497454087 # Number of tag accesses +system.cpu.icache.tags.data_accesses 497454087 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 245752746 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 245752746 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 245752746 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 245752746 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 245752746 # number of overall hits +system.cpu.icache.overall_hits::total 245752746 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1983875 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1983875 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1983875 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1983875 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1983875 # number of overall misses +system.cpu.icache.overall_misses::total 1983875 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16221042426 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16221042426 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16221042426 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16221042426 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16221042426 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16221042426 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 247736621 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 247736621 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 247736621 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 247736621 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 247736621 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 247736621 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008008 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008008 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.008008 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.008008 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.008008 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.008008 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8176.443791 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8176.443791 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8176.443791 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8176.443791 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8176.443791 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8176.443791 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 85075 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 747 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2929 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.639118 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 108.714286 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1979522 # number of writebacks -system.cpu.icache.writebacks::total 1979522 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3000 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3000 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3000 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3000 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3000 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3000 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1980224 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1980224 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1980224 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1980224 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1980224 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1980224 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15180539440 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15180539440 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15180539440 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15180539440 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15180539440 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15180539440 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007993 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007993 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007993 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.007993 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007993 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.007993 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7666.071838 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7666.071838 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7666.071838 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 7666.071838 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7666.071838 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 7666.071838 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 1350153 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 1355017 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 4256 # number of redundant prefetches already in prefetch queue +system.cpu.icache.avg_blocked_cycles::no_mshrs 29.045749 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 106.714286 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 1980154 # number of writebacks +system.cpu.icache.writebacks::total 1980154 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3028 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3028 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3028 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3028 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3028 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3028 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1980847 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1980847 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1980847 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1980847 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1980847 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1980847 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15183658439 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15183658439 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15183658439 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15183658439 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15183658439 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15183658439 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007996 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007996 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007996 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.007996 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007996 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.007996 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7665.235346 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7665.235346 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7665.235346 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 7665.235346 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7665.235346 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 7665.235346 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 1350785 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 1355219 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 3879 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 4789879 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 297323 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16097.800949 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3937547 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 313525 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.558957 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 4789973 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 297120 # number of replacements +system.cpu.l2cache.tags.tagsinuse 16096.917401 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3841839 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 313315 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 12.261906 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15677.943381 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 419.857568 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.956906 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.025626 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.982532 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 424 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15778 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 15676.222250 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 420.695151 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.956801 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.025677 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.982478 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 430 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15765 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 63 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 273 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 82 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 61 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 263 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 100 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 408 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1549 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3670 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10056 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.025879 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.963013 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 145579085 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 145579085 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 735952 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 735952 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 3357075 # 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number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 957004 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 20275662144 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 20275662144 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2881000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2881000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 136635500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 136635500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 324486000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 324486000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59198284500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59198284500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 324486000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59334920000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 59659406000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 324486000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59334920000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 20275662144 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 79935068144 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001924 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001924 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.002128 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.002128 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367999 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367999 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.002128 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.272284 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.159361 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.002128 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.272284 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001907 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001907 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.002122 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.002122 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367765 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367765 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.002122 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.272106 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.159234 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.002122 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.272106 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.202146 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100211.116092 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 100211.116092 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15110.526316 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15110.526316 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 105569.574621 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 105569.574621 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 77395.467489 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 77395.467489 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79062.546544 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79062.546544 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77395.467489 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79111.522666 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79101.943194 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77395.467489 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79111.522666 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100211.116092 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83569.835347 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 9473354 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736191 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 643138 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 89 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 88 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.202000 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100070.884613 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 100070.884613 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15917.127072 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15917.127072 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 99371.272727 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 99371.272727 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 77203.426124 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 77203.426124 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79056.165558 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79056.165558 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77203.426124 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79093.400588 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79082.870819 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77203.426124 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79093.400588 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100070.884613 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83526.367856 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 9474606 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736642 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 643287 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 98 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 97 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 4016341 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 802291 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4000023 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 230984 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 255300 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 190 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 190 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 720846 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 720846 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1980224 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 4016964 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 802115 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4000812 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 230803 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 255056 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 181 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 181 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 720849 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 720849 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1980847 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 2036119 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5939779 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8270763 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 14210542 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253411520 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352858752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 606270272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 552812 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4257792 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 5290002 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.121634 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.326863 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5941666 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8270754 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 14212420 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253492416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352859136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 606351552 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 552356 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 4255808 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 5290172 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.121625 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.326853 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 4646559 87.84% 87.84% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 643442 12.16% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 4646755 87.84% 87.84% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 643416 12.16% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5290002 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 9472652000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 5290172 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 9473913000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2970335495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2971268997 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4135554975 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4135554476 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 1254990 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 940467 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 1254210 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 939897 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 956088 # Transaction distribution -system.membus.trans_dist::WritebackDirty 66339 # Transaction distribution -system.membus.trans_dist::CleanEvict 230984 # Transaction distribution -system.membus.trans_dist::UpgradeReq 190 # Transaction distribution -system.membus.trans_dist::ReadExReq 1387 # Transaction distribution -system.membus.trans_dist::ReadExResp 1387 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 956090 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2212465 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2212465 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65524096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 65524096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 955532 # Transaction distribution +system.membus.trans_dist::WritebackDirty 66317 # Transaction distribution +system.membus.trans_dist::CleanEvict 230803 # Transaction distribution +system.membus.trans_dist::UpgradeReq 181 # Transaction distribution +system.membus.trans_dist::ReadExReq 1375 # Transaction distribution +system.membus.trans_dist::ReadExResp 1375 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 955534 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2211117 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2211117 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65486336 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 65486336 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 957667 # Request fanout histogram +system.membus.snoop_fanout::samples 957090 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 957667 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 957090 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 957667 # Request fanout histogram -system.membus.reqLayer0.occupancy 1758860478 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 957090 # Request fanout histogram +system.membus.reqLayer0.occupancy 1757256327 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 5031633569 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5028523066 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index d9533629f..35c099c69 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.060131 # Number of seconds simulated -sim_ticks 60130734500 # Number of ticks simulated -final_tick 60130734500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.060132 # Number of seconds simulated +sim_ticks 60131512500 # Number of ticks simulated +final_tick 60131512500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 310652 # Simulator instruction rate (inst/s) -host_op_rate 397278 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 263409545 # Simulator tick rate (ticks/s) -host_mem_usage 281384 # Number of bytes of host memory used -host_seconds 228.28 # Real time elapsed on the host +host_inst_rate 320494 # Simulator instruction rate (inst/s) +host_op_rate 409865 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 271758284 # Simulator tick rate (ticks/s) +host_mem_usage 281048 # Number of bytes of host memory used +host_seconds 221.27 # Real time elapsed on the host sim_insts 70915150 # Number of instructions simulated sim_ops 90690106 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 286336 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7938624 # Number of bytes read from this memory system.physmem.bytes_read::total 8224960 # Number of bytes read from this memory @@ -26,17 +26,17 @@ system.physmem.num_reads::cpu.data 124041 # Nu system.physmem.num_reads::total 128515 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 86552 # Number of write requests responded to by this memory system.physmem.num_writes::total 86552 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 4761891 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 132022735 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 136784626 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4761891 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4761891 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 92121409 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 92121409 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 92121409 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4761891 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 132022735 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 228906035 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 4761829 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 132021026 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 136782856 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4761829 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4761829 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 92120217 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 92120217 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 92120217 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4761829 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 132021026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 228903073 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 128515 # Number of read requests accepted system.physmem.writeReqs 86552 # Number of write requests accepted system.physmem.readBursts 128515 # Number of DRAM read bursts, including those serviced by the write queue @@ -83,7 +83,7 @@ system.physmem.perBankWrBursts::14 5706 # Pe system.physmem.perBankWrBursts::15 5441 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 60130703000 # Total gap between requests +system.physmem.totGap 60131481000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -196,16 +196,16 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 32872 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 418.606960 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 258.790126 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 361.910519 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 8567 26.06% 26.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 6423 19.54% 45.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3392 10.32% 55.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2472 7.52% 63.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 258.799568 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 361.901911 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 8565 26.06% 26.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 6426 19.55% 45.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3391 10.32% 55.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2471 7.52% 63.44% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 2230 6.78% 70.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1616 4.92% 75.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1339 4.07% 79.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1211 3.68% 82.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1617 4.92% 75.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1341 4.08% 79.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1209 3.68% 82.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 5622 17.10% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 32872 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 5350 # Reads before turning the bus around for writes @@ -227,12 +227,12 @@ system.physmem.wrPerTurnAround::19 22 0.41% 99.93% # Wr system.physmem.wrPerTurnAround::20 3 0.06% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5350 # Writes before turning the bus around for reads -system.physmem.totQLat 3048956750 # Total ticks spent queuing -system.physmem.totMemAccLat 5458519250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3049168000 # Total ticks spent queuing +system.physmem.totMemAccLat 5458730500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 642550000 # Total ticks spent in databus transfers -system.physmem.avgQLat 23725.44 # Average queueing delay per DRAM burst +system.physmem.avgQLat 23727.09 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 42475.44 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 42477.09 # Average memory access latency per DRAM burst system.physmem.avgRdBW 136.78 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 92.09 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 136.78 # Average system read bandwidth in MiByte/s @@ -247,62 +247,62 @@ system.physmem.readRowHits 112228 # Nu system.physmem.writeRowHits 69923 # Number of row buffer hits during writes system.physmem.readRowHitRate 87.33 # Row buffer hit rate for reads system.physmem.writeRowHitRate 80.79 # Row buffer hit rate for writes -system.physmem.avgGap 279590.56 # Average gap between requests +system.physmem.avgGap 279594.18 # Average gap between requests system.physmem.pageHitRate 84.70 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 123522000 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 65634525 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 467912760 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 226187820 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2501584800.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2202428130 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 166870080 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 5871636120 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 2984284320 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 8652824730 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 23263603845 # Total energy per rank (pJ) -system.physmem_0.averagePower 386.883743 # Core power per rank (mW) -system.physmem_0.totalIdleTime 54864406750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 285894000 # Time in different power states -system.physmem_0.memoryStateTime::REF 1063168000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 34216733000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 7771569500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 3916970000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 12876400000 # Time in different power states +system.physmem_0.refreshEnergy 2502199440.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2202561510 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 166933440 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 5874746040 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 2984525760 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 8651084625 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 23265974460 # Total energy per rank (pJ) +system.physmem_0.averagePower 386.918165 # Core power per rank (mW) +system.physmem_0.totalIdleTime 54864943500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 285874500 # Time in different power states +system.physmem_0.memoryStateTime::REF 1063428000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 34209724750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 7772192000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 3916970750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 12883322500 # Time in different power states system.physmem_1.actEnergy 111255480 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 59114715 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 449648640 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 225462240 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 2476999200.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2186718930 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 154089120 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 5325084780 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 3204564480 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 8848391460 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 23042110905 # Total energy per rank (pJ) -system.physmem_1.averagePower 383.200220 # Core power per rank (mW) -system.physmem_1.totalIdleTime 54932244750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 256290500 # Time in different power states +system.physmem_1.actBackEnergy 2186669910 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 154102560 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 5325095040 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 3204580800 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 8848579860 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 23042291445 # Total energy per rank (pJ) +system.physmem_1.averagePower 383.198268 # Core power per rank (mW) +system.physmem_1.totalIdleTime 54933017000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 256278500 # Time in different power states system.physmem_1.memoryStateTime::REF 1053008000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 34909248000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 8345212750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 3889130500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 11677844750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.physmem_1.memoryStateTime::SREF 34910026000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 8345277500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 3889148250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 11677774250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 14827796 # Number of BP lookups system.cpu.branchPred.condPredicted 9922694 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 342031 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9662876 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 9662877 # Number of BTB lookups system.cpu.branchPred.BTBHits 6571901 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 68.011853 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1720083 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 68.011846 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1720082 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 175657 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 158615 # Number of indirect target hits. system.cpu.branchPred.indirectMisses 17042 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 24764 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -332,7 +332,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -362,7 +362,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -392,7 +392,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -423,16 +423,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 60130734500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 120261469 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 60131512500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 120263025 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915150 # Number of instructions committed system.cpu.committedOps 90690106 # Number of ops (including micro ops) committed system.cpu.discardedOps 1179235 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.695850 # CPI: cycles per instruction -system.cpu.ipc 0.589675 # IPC: instructions per cycle +system.cpu.cpi 1.695872 # CPI: cycles per instruction +system.cpu.ipc 0.589667 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 47187979 52.03% 52.03% # Class of committed instruction system.cpu.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction @@ -472,16 +472,16 @@ system.cpu.op_class_0::FloatMemWrite 32 0.00% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 90690106 # Class of committed instruction -system.cpu.tickCycles 98354903 # Number of cycles that the object actually ticked -system.cpu.idleCycles 21906566 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 98355658 # Number of cycles that the object actually ticked +system.cpu.idleCycles 21907367 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 156451 # number of replacements -system.cpu.dcache.tags.tagsinuse 4067.127252 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42637295 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4067.127626 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42637298 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 160547 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 265.575159 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 265.575177 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 880684500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4067.127252 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.127626 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.992951 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.992951 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -489,11 +489,11 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 system.cpu.dcache.tags.age_task_id_blocks_1024::1 1009 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 3044 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 86034713 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 86034713 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 22880152 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22880152 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 86034719 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86034719 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 22880155 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22880155 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19642142 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 19642142 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 83163 # number of SoftPFReq hits @@ -502,10 +502,10 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42522294 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42522294 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42605457 # number of overall hits -system.cpu.dcache.overall_hits::total 42605457 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 42522297 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42522297 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42605460 # number of overall hits +system.cpu.dcache.overall_hits::total 42605460 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 47246 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 47246 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 207759 # number of WriteReq misses @@ -516,16 +516,16 @@ system.cpu.dcache.demand_misses::cpu.data 255005 # n system.cpu.dcache.demand_misses::total 255005 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 299788 # number of overall misses system.cpu.dcache.overall_misses::total 299788 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1839858000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1839858000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18545282000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18545282000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20385140000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20385140000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20385140000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20385140000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22927398 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22927398 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1839905000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1839905000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18545313000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18545313000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20385218000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20385218000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20385218000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20385218000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22927401 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22927401 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 127946 # number of SoftPFReq accesses(hits+misses) @@ -534,10 +534,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42777299 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42777299 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42905245 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42905245 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 42777302 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42777302 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42905248 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42905248 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002061 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002061 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010467 # miss rate for WriteReq accesses @@ -548,14 +548,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005961 system.cpu.dcache.demand_miss_rate::total 0.005961 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.006987 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.006987 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38942.090336 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 38942.090336 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89263.435038 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 89263.435038 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 79940.158036 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 79940.158036 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67998.518953 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67998.518953 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38943.085129 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 38943.085129 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89263.584249 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 89263.584249 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 79940.463912 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 79940.463912 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67998.779137 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67998.779137 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 185 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -582,16 +582,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 136566 system.cpu.dcache.demand_mshr_misses::total 136566 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 160547 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 160547 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 773644500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 773644500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9479497500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9479497500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1896776500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1896776500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10253142000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10253142000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12149918500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12149918500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 773861500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 773861500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9479489000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9479489000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1896776000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1896776000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10253350500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10253350500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12150126500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12150126500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses @@ -602,26 +602,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003192 system.cpu.dcache.demand_mshr_miss_rate::total 0.003192 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26199.481865 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26199.481865 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 88562.810056 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 88562.810056 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79094.971019 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79094.971019 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75078.291815 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75078.291815 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75678.265555 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75678.265555 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26206.830573 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26206.830573 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 88562.730645 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 88562.730645 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79094.950169 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79094.950169 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75079.818549 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75079.818549 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75679.561125 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75679.561125 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 43545 # number of replacements -system.cpu.icache.tags.tagsinuse 1852.001681 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1851.999823 # Cycle average of tags in use system.cpu.icache.tags.total_refs 25048343 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 45587 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 549.462413 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1852.001681 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.904298 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.904298 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1851.999823 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.904297 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.904297 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id @@ -631,7 +631,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1021 system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 50233449 # Number of tag accesses system.cpu.icache.tags.data_accesses 50233449 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 25048343 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 25048343 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 25048343 # number of demand (read+write) hits @@ -644,12 +644,12 @@ system.cpu.icache.demand_misses::cpu.inst 45588 # n system.cpu.icache.demand_misses::total 45588 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 45588 # number of overall misses system.cpu.icache.overall_misses::total 45588 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1042270000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1042270000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1042270000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1042270000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1042270000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1042270000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1042263500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1042263500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1042263500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1042263500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1042263500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1042263500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 25093931 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 25093931 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 25093931 # number of demand (read+write) accesses @@ -662,12 +662,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001817 system.cpu.icache.demand_miss_rate::total 0.001817 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001817 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001817 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22862.814776 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22862.814776 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22862.814776 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22862.814776 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22862.814776 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22862.814776 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22862.672194 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22862.672194 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22862.672194 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22862.672194 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22862.672194 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22862.672194 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -682,34 +682,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 45588 system.cpu.icache.demand_mshr_misses::total 45588 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 45588 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 45588 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 996683000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 996683000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 996683000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 996683000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 996683000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 996683000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 996676500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 996676500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 996676500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 996676500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 996676500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 996676500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001817 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.001817 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.001817 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21862.836711 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21862.836711 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21862.836711 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21862.836711 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21862.836711 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21862.836711 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21862.694130 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21862.694130 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21862.694130 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21862.694130 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21862.694130 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21862.694130 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 97176 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31292.334990 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 31292.341702 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 268174 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 129944 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 2.063766 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 10980034000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 476.637646 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1378.081673 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29437.615671 # Average occupied blocks per requestor +system.cpu.l2cache.tags.warmup_cycle 10980599000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 476.632754 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1378.083150 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29437.625798 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.014546 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.042056 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.898365 # Average percentage of cache occupancy @@ -723,7 +723,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 782 system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3316240 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3316240 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 128145 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 128145 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 39944 # number of WritebackClean hits @@ -752,18 +752,18 @@ system.cpu.l2cache.demand_misses::total 128588 # nu system.cpu.l2cache.overall_misses::cpu.inst 4487 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 124101 # number of overall misses system.cpu.l2cache.overall_misses::total 128588 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9269336000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9269336000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 492869500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 492869500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2252818000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 2252818000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 492869500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11522154000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 12015023500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 492869500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11522154000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 12015023500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9269327500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9269327500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 492863000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 492863000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2253034500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 2253034500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 492863000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11522362000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 12015225000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 492863000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11522362000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 12015225000 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 128145 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 128145 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 39944 # number of WritebackClean accesses(hits+misses) @@ -792,18 +792,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.623805 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.098425 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.772989 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.623805 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90594.290294 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90594.290294 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 109843.882327 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 109843.882327 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103416.177011 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 103416.177011 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 109843.882327 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92844.973046 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 93438.139640 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 109843.882327 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92844.973046 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 93438.139640 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90594.207219 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90594.207219 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 109842.433697 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 109842.433697 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103426.115498 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 103426.115498 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 109842.433697 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92846.649100 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 93439.706660 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 109842.433697 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92846.649100 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 93439.706660 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -836,18 +836,18 @@ system.cpu.l2cache.demand_mshr_misses::total 128516 system.cpu.l2cache.overall_mshr_misses::cpu.inst 4475 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 124041 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 128516 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8246166000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8246166000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 446702000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 446702000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2029430500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2029430500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 446702000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10275596500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 10722298500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 446702000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10275596500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 10722298500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8246157500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8246157500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 446695500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 446695500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2029647000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2029647000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 446695500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10275804500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10722500000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 446695500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10275804500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10722500000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955903 # mshr miss rate for ReadExReq accesses @@ -862,25 +862,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.623456 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.772615 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.623456 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80594.290294 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80594.290294 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 99821.675978 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 99821.675978 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 93418.822500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 93418.822500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 99821.675978 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82840.322958 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83431.623300 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 99821.675978 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82840.322958 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83431.623300 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80594.207219 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80594.207219 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 99820.223464 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 99820.223464 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 93428.788437 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 93428.788437 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 99820.223464 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82841.999823 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83433.191198 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 99820.223464 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82841.999823 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83433.191198 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 406131 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 200034 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7844 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 3482 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3452 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 99097 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 214697 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 43545 # Transaction distribution @@ -920,7 +920,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 26198 # Transaction distribution system.membus.trans_dist::WritebackDirty 86552 # Transaction distribution system.membus.trans_dist::CleanEvict 7237 # Transaction distribution @@ -943,9 +943,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 128515 # Request fanout histogram -system.membus.reqLayer0.occupancy 588253000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 588249500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 677385750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 677382500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index da2276c3c..ad340b529 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.037982 # Number of seconds simulated -sim_ticks 37982056000 # Number of ticks simulated -final_tick 37982056000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.038007 # Number of seconds simulated +sim_ticks 38007342000 # Number of ticks simulated +final_tick 38007342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 220867 # Simulator instruction rate (inst/s) -host_op_rate 282464 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 118308818 # Simulator tick rate (ticks/s) -host_mem_usage 284316 # Number of bytes of host memory used -host_seconds 321.04 # Real time elapsed on the host +host_inst_rate 224949 # Simulator instruction rate (inst/s) +host_op_rate 287684 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 120575368 # Simulator tick rate (ticks/s) +host_mem_usage 283980 # Number of bytes of host memory used +host_seconds 315.22 # Real time elapsed on the host sim_insts 70907652 # Number of instructions simulated sim_ops 90682607 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 2372544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5696640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 6178368 # Number of bytes read from this memory -system.physmem.bytes_read::total 14247552 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 2372544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 2372544 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6227072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6227072 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 37071 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 89010 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 96537 # Number of read requests responded to by this memory -system.physmem.num_reads::total 222618 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97298 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97298 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 62464865 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 149982402 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 162665444 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 375112711 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 62464865 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 62464865 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 163947734 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 163947734 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 163947734 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 62464865 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 149982402 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 162665444 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 539060445 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 222619 # Number of read requests accepted -system.physmem.writeReqs 97298 # Number of write requests accepted -system.physmem.readBursts 222619 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97298 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 14237568 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 10048 # Total number of bytes read from write queue -system.physmem.bytesWritten 6225984 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 14247616 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6227072 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 157 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 2373952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5705216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 6169536 # Number of bytes read from this memory +system.physmem.bytes_read::total 14248704 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 2373952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 2373952 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6224192 # Number of bytes written to this memory +system.physmem.bytes_written::total 6224192 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 37093 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 89144 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 96399 # Number of read requests responded to by this memory +system.physmem.num_reads::total 222636 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97253 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97253 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 62460353 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 150108261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 162324848 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 374893461 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 62460353 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 62460353 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 163762886 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 163762886 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 163762886 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 62460353 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 150108261 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 162324848 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 538656347 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 222637 # Number of read requests accepted +system.physmem.writeReqs 97253 # Number of write requests accepted +system.physmem.readBursts 222637 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97253 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 14240000 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8704 # Total number of bytes read from write queue +system.physmem.bytesWritten 6222848 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 14248768 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6224192 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 136 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9655 # Per bank write bursts -system.physmem.perBankRdBursts::1 9974 # Per bank write bursts -system.physmem.perBankRdBursts::2 12579 # Per bank write bursts -system.physmem.perBankRdBursts::3 25363 # Per bank write bursts -system.physmem.perBankRdBursts::4 17343 # Per bank write bursts -system.physmem.perBankRdBursts::5 22132 # Per bank write bursts -system.physmem.perBankRdBursts::6 11760 # Per bank write bursts -system.physmem.perBankRdBursts::7 14137 # Per bank write bursts -system.physmem.perBankRdBursts::8 11660 # Per bank write bursts -system.physmem.perBankRdBursts::9 15453 # Per bank write bursts -system.physmem.perBankRdBursts::10 11698 # Per bank write bursts -system.physmem.perBankRdBursts::11 11338 # Per bank write bursts -system.physmem.perBankRdBursts::12 9437 # Per bank write bursts -system.physmem.perBankRdBursts::13 9564 # Per bank write bursts -system.physmem.perBankRdBursts::14 9858 # Per bank write bursts -system.physmem.perBankRdBursts::15 20511 # Per bank write bursts -system.physmem.perBankWrBursts::0 5992 # Per bank write bursts -system.physmem.perBankWrBursts::1 6239 # Per bank write bursts -system.physmem.perBankWrBursts::2 6121 # Per bank write bursts -system.physmem.perBankWrBursts::3 6129 # Per bank write bursts -system.physmem.perBankWrBursts::4 6098 # Per bank write bursts -system.physmem.perBankWrBursts::5 6229 # Per bank write bursts -system.physmem.perBankWrBursts::6 6018 # Per bank write bursts -system.physmem.perBankWrBursts::7 5980 # Per bank write bursts -system.physmem.perBankWrBursts::8 5938 # Per bank write bursts -system.physmem.perBankWrBursts::9 6095 # Per bank write bursts -system.physmem.perBankWrBursts::10 6202 # Per bank write bursts -system.physmem.perBankWrBursts::11 5916 # Per bank write bursts -system.physmem.perBankWrBursts::12 6046 # Per bank write bursts -system.physmem.perBankWrBursts::13 6090 # Per bank write bursts -system.physmem.perBankWrBursts::14 6173 # Per bank write bursts -system.physmem.perBankWrBursts::15 6015 # Per bank write bursts +system.physmem.perBankRdBursts::0 9656 # Per bank write bursts +system.physmem.perBankRdBursts::1 9952 # Per bank write bursts +system.physmem.perBankRdBursts::2 12608 # Per bank write bursts +system.physmem.perBankRdBursts::3 25349 # Per bank write bursts +system.physmem.perBankRdBursts::4 17405 # Per bank write bursts +system.physmem.perBankRdBursts::5 22083 # Per bank write bursts +system.physmem.perBankRdBursts::6 11752 # Per bank write bursts +system.physmem.perBankRdBursts::7 14068 # Per bank write bursts +system.physmem.perBankRdBursts::8 11731 # Per bank write bursts +system.physmem.perBankRdBursts::9 15466 # Per bank write bursts +system.physmem.perBankRdBursts::10 11740 # Per bank write bursts +system.physmem.perBankRdBursts::11 11331 # Per bank write bursts +system.physmem.perBankRdBursts::12 9464 # Per bank write bursts +system.physmem.perBankRdBursts::13 9568 # Per bank write bursts +system.physmem.perBankRdBursts::14 9844 # Per bank write bursts +system.physmem.perBankRdBursts::15 20483 # Per bank write bursts +system.physmem.perBankWrBursts::0 5965 # Per bank write bursts +system.physmem.perBankWrBursts::1 6210 # Per bank write bursts +system.physmem.perBankWrBursts::2 6157 # Per bank write bursts +system.physmem.perBankWrBursts::3 6128 # Per bank write bursts +system.physmem.perBankWrBursts::4 6115 # Per bank write bursts +system.physmem.perBankWrBursts::5 6243 # Per bank write bursts +system.physmem.perBankWrBursts::6 6020 # Per bank write bursts +system.physmem.perBankWrBursts::7 5952 # Per bank write bursts +system.physmem.perBankWrBursts::8 5952 # Per bank write bursts +system.physmem.perBankWrBursts::9 6130 # Per bank write bursts +system.physmem.perBankWrBursts::10 6213 # Per bank write bursts +system.physmem.perBankWrBursts::11 5918 # Per bank write bursts +system.physmem.perBankWrBursts::12 6006 # Per bank write bursts +system.physmem.perBankWrBursts::13 6051 # Per bank write bursts +system.physmem.perBankWrBursts::14 6145 # Per bank write bursts +system.physmem.perBankWrBursts::15 6027 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 37982044500 # Total gap between requests +system.physmem.totGap 38007330500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 222619 # Read request sizes (log2) +system.physmem.readPktSize::6 222637 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97298 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 111989 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 59707 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 15764 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10925 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6262 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5252 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97253 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 112108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 59931 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 15573 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10934 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6190 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5238 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 4622 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4266 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3549 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 76 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4261 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3516 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 73 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 42 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see @@ -149,36 +149,36 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1089 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4935 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7813 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6745 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1086 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1871 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2521 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5989 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6446 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7735 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8436 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7923 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see @@ -198,120 +198,119 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 132891 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 153.980270 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 102.520664 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 209.589027 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 82855 62.35% 62.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 32511 24.46% 86.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6209 4.67% 91.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2728 2.05% 93.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1195 0.90% 94.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 994 0.75% 95.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 885 0.67% 95.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 776 0.58% 96.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4738 3.57% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 132891 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 132899 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 153.968593 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 102.497917 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 209.528989 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 82983 62.44% 62.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 32243 24.26% 86.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6367 4.79% 91.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2726 2.05% 93.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1184 0.89% 94.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1005 0.76% 95.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 875 0.66% 95.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 807 0.61% 96.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4709 3.54% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 132899 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 5883 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 37.813870 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 211.295819 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 5876 99.88% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 6 0.10% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 37.820840 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 210.672420 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 5878 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 4 0.07% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-15871 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 5883 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5883 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.535951 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.496117 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.216118 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4707 80.01% 80.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 47 0.80% 80.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 703 11.95% 92.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 205 3.48% 96.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 109 1.85% 98.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 61 1.04% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 33 0.56% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 11 0.19% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 4 0.07% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5883 # Writes before turning the bus around for reads -system.physmem.totQLat 8417974819 # Total ticks spent queuing -system.physmem.totMemAccLat 12589137319 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1112310000 # Total ticks spent in databus transfers -system.physmem.avgQLat 37840.06 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 56590.06 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 374.85 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 163.92 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 375.11 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 163.95 # Average system write bandwidth in MiByte/s +system.physmem.wrPerTurnAround::samples 5882 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.528392 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.490234 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.186972 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4697 79.85% 79.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 46 0.78% 80.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 744 12.65% 93.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 191 3.25% 96.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 91 1.55% 98.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 73 1.24% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 20 0.34% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 15 0.26% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 2 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5882 # Writes before turning the bus around for reads +system.physmem.totQLat 8329547257 # Total ticks spent queuing +system.physmem.totMemAccLat 12501422257 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1112500000 # Total ticks spent in databus transfers +system.physmem.avgQLat 37436.00 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 4999.98 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 56185.91 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 374.66 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 163.73 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 374.90 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 163.76 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 4.21 # Data bus utilization in percentage system.physmem.busUtilRead 2.93 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.28 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.38 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.49 # Average write queue length when enqueuing -system.physmem.readRowHits 157076 # Number of row buffer hits during reads -system.physmem.writeRowHits 29766 # Number of row buffer hits during writes -system.physmem.readRowHitRate 70.61 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 30.59 # Row buffer hit rate for writes -system.physmem.avgGap 118724.68 # Average gap between requests +system.physmem.avgRdQLen 1.37 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.63 # Average write queue length when enqueuing +system.physmem.readRowHits 157173 # Number of row buffer hits during reads +system.physmem.writeRowHits 29653 # Number of row buffer hits during writes +system.physmem.readRowHitRate 70.64 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 30.49 # Row buffer hit rate for writes +system.physmem.avgGap 118813.75 # Average gap between requests system.physmem.pageHitRate 58.43 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 508332300 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 270162255 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 877813020 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 254767320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3007433520.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2937544590 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 74566560 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 13007568150 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 1007588640 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 71626485 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 22017862440 # Total energy per rank (pJ) -system.physmem_0.averagePower 579.691165 # Core power per rank (mW) -system.physmem_0.totalIdleTime 31344656336 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 41004063 # Time in different power states -system.physmem_0.memoryStateTime::REF 1272480000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 195565250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 2624595348 # Time in different power states -system.physmem_0.memoryStateTime::ACT 5323818601 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 28524592738 # Time in different power states -system.physmem_1.actEnergy 440580840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 234159090 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 710558520 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 253039500 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2889422640.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2771748120 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 73304160 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 11932439280 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 1384694400 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 508589940 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 21198847170 # Total energy per rank (pJ) -system.physmem_1.averagePower 558.127949 # Core power per rank (mW) -system.physmem_1.totalIdleTime 31712588164 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 50452548 # Time in different power states -system.physmem_1.memoryStateTime::REF 1222746000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1938473750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 3605935527 # Time in different power states -system.physmem_1.memoryStateTime::ACT 4996269288 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 26168178887 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 17071043 # Number of BP lookups -system.cpu.branchPred.condPredicted 11458506 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 598065 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9277652 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7374059 # Number of BTB hits +system.physmem_0.actEnergy 507596880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 269771370 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 877313220 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 254683800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3009892080.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2962459860 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 75632160 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 13054365150 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 948417120 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 77983215 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 22038660255 # Total energy per rank (pJ) +system.physmem_0.averagePower 579.852702 # Core power per rank (mW) +system.physmem_0.totalIdleTime 31313307761 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 43781047 # Time in different power states +system.physmem_0.memoryStateTime::REF 1273526000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 214718250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 2469720434 # Time in different power states +system.physmem_0.memoryStateTime::ACT 5376727192 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 28628869077 # Time in different power states +system.physmem_1.actEnergy 441337680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 234557565 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 711336780 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 252841140 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2899256880.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2760551040 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 73978560 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 11934955830 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 1428119040 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 493845795 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 21231004530 # Total energy per rank (pJ) +system.physmem_1.averagePower 558.602674 # Core power per rank (mW) +system.physmem_1.totalIdleTime 31760586804 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 51273339 # Time in different power states +system.physmem_1.memoryStateTime::REF 1226918000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1868150750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 3718457459 # Time in different power states +system.physmem_1.memoryStateTime::ACT 4968563857 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 26173978595 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 17074531 # Number of BP lookups +system.cpu.branchPred.condPredicted 11460402 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 598628 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9274722 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7374340 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 79.481953 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1854771 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 101571 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 233347 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 194967 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 38380 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 22266 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 79.510092 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1855435 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 101567 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 233050 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 195925 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 37125 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 22231 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -341,7 +340,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -371,7 +370,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -401,7 +400,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -432,134 +431,134 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 37982056000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 75964113 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 38007342000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 76014685 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5537723 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 87105546 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17071043 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9423797 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 66074321 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1222765 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 12043 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 60 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 33616 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22433583 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 69302 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 72269145 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.523281 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.330897 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 5565404 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 87125388 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17074531 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9425700 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 66120510 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1223729 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 11256 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 48 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 32224 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22440736 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 69274 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 72341306 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.522198 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.331033 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 27092588 37.49% 37.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8164913 11.30% 48.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9113637 12.61% 61.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 27898007 38.60% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 27150688 37.53% 37.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8169627 11.29% 48.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9114831 12.60% 61.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 27906160 38.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 72269145 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.224725 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.146667 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8914938 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 26268747 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 30971085 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5669704 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 444671 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3134143 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 168562 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 100303161 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2799230 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 444671 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13550474 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 11467047 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 876029 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 31784130 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14146794 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 98330583 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 860090 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 4210253 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 70388 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4670257 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5435231 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 103259286 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 453553071 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 114279094 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 706 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 72341306 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.224621 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.146165 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8942287 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 26299816 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 30976482 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5677371 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 445350 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3133946 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 168438 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 100318297 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2804928 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 445350 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13582767 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11480611 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 882043 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 31792045 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14158490 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 98346425 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 855389 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 4229008 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 68182 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4663621 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5443965 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 103273055 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 453619684 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 114297516 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 686 # Number of floating rename lookups system.cpu.rename.CommittedMaps 93629369 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9629917 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18998 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 19022 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12803731 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 24155645 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21760500 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1435489 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2293932 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97400499 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34856 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 94484787 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 595355 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6752748 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 17957034 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1070 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 72269145 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.307401 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.171287 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9643686 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18991 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 19021 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12815345 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 24159121 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21761593 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1442839 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2330212 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97411129 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34857 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 94489103 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 595557 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6763379 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 17995254 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1071 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 72341306 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.306157 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.170975 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24146655 33.41% 33.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17449315 24.14% 57.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17027031 23.56% 81.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 11604628 16.06% 97.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2040054 2.82% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1462 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24199109 33.45% 33.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17470195 24.15% 57.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17034708 23.55% 81.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 11601119 16.04% 97.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2034740 2.81% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1435 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 72269145 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 72341306 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6736684 22.63% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 37 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11088448 37.25% 59.89% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 11940306 40.11% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 30 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6739464 22.68% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 40 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11065982 37.24% 59.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 11909373 40.08% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 33 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemWrite 21 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49305598 52.18% 52.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 86530 0.09% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49308872 52.18% 52.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 86547 0.09% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.28% # Type of FU issued @@ -582,91 +581,91 @@ system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.28% # Ty system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 11 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 13 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 18 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23958815 25.36% 77.63% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21133689 22.37% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23960981 25.36% 77.63% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21132544 22.37% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 62 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 32 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 94484787 # Type of FU issued -system.cpu.iq.rate 1.243808 # Inst issue rate -system.cpu.iq.fu_busy_cnt 29765526 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.315030 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 291599265 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 104199326 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93203450 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 335 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 598 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 92 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 124250121 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 192 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1368397 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 94489103 # Type of FU issued +system.cpu.iq.rate 1.243037 # Inst issue rate +system.cpu.iq.fu_busy_cnt 29714913 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.314480 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 291629642 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 104220574 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 93205627 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 340 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 544 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 99 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 124203819 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 197 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1369166 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1289383 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2091 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11973 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1204762 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1292859 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2033 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11913 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1205855 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 147075 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 188044 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 148706 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 187344 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 444671 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 622988 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1195662 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97449431 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 445350 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 625818 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1199933 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97461708 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 24155645 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21760500 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18936 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1589 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1191442 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11973 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 249986 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 222081 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 472067 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93691189 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23695668 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 793598 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 24159121 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21761593 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18937 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1609 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1195657 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11913 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 250763 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 222991 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 473754 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93695211 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23697676 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 793892 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 14076 # number of nop insts executed -system.cpu.iew.exec_refs 44621004 # number of memory reference insts executed -system.cpu.iew.exec_branches 14207535 # Number of branches executed -system.cpu.iew.exec_stores 20925336 # Number of stores executed -system.cpu.iew.exec_rate 1.233361 # Inst execution rate -system.cpu.iew.wb_sent 93310594 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 93203542 # cumulative count of insts written-back -system.cpu.iew.wb_producers 44951761 # num instructions producing a value -system.cpu.iew.wb_consumers 76639550 # num instructions consuming a value -system.cpu.iew.wb_rate 1.226942 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.586535 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 5895620 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 15722 # number of nop insts executed +system.cpu.iew.exec_refs 44622526 # number of memory reference insts executed +system.cpu.iew.exec_branches 14207940 # Number of branches executed +system.cpu.iew.exec_stores 20924850 # Number of stores executed +system.cpu.iew.exec_rate 1.232594 # Inst execution rate +system.cpu.iew.wb_sent 93313259 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 93205726 # cumulative count of insts written-back +system.cpu.iew.wb_producers 44957522 # num instructions producing a value +system.cpu.iew.wb_consumers 76634731 # num instructions consuming a value +system.cpu.iew.wb_rate 1.226154 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.586647 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 5905401 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 431354 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 71312758 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.271696 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.107515 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 432114 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 71383083 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.270443 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.106463 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 37859507 53.09% 53.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16683603 23.39% 76.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4297164 6.03% 82.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4156384 5.83% 88.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1956005 2.74% 91.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1240140 1.74% 92.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 732437 1.03% 93.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 578410 0.81% 94.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3809108 5.34% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 37916370 53.12% 53.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16693361 23.39% 76.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4299601 6.02% 82.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4172974 5.85% 88.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1943479 2.72% 91.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1233650 1.73% 92.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 737671 1.03% 93.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 579334 0.81% 94.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3806643 5.33% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 71312758 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 71383083 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913204 # Number of instructions committed system.cpu.commit.committedOps 90688159 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -716,552 +715,552 @@ system.cpu.commit.op_class_0::FloatMemWrite 32 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 90688159 # Class of committed instruction -system.cpu.commit.bw_lim_events 3809108 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 164062130 # The number of ROB reads -system.cpu.rob.rob_writes 194125448 # The number of ROB writes -system.cpu.timesIdled 54252 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3694968 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3806643 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 164144701 # The number of ROB reads +system.cpu.rob.rob_writes 194146843 # The number of ROB writes +system.cpu.timesIdled 54077 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3673379 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907652 # Number of Instructions Simulated system.cpu.committedOps 90682607 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.071311 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.071311 # CPI: Total CPI of All Threads -system.cpu.ipc 0.933436 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.933436 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 101982930 # number of integer regfile reads -system.cpu.int_regfile_writes 56612163 # number of integer regfile writes -system.cpu.fp_regfile_reads 58 # number of floating regfile reads -system.cpu.fp_regfile_writes 45 # number of floating regfile writes -system.cpu.cc_regfile_reads 345107562 # number of cc regfile reads -system.cpu.cc_regfile_writes 38759661 # number of cc regfile writes -system.cpu.misc_regfile_reads 44102170 # number of misc regfile reads +system.cpu.cpi 1.072024 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.072024 # CPI: Total CPI of All Threads +system.cpu.ipc 0.932815 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.932815 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 101986551 # number of integer regfile reads +system.cpu.int_regfile_writes 56614441 # number of integer regfile writes +system.cpu.fp_regfile_reads 62 # number of floating regfile reads +system.cpu.fp_regfile_writes 51 # number of floating regfile writes +system.cpu.cc_regfile_reads 345121100 # number of cc regfile reads +system.cpu.cc_regfile_writes 38758964 # number of cc regfile writes +system.cpu.misc_regfile_reads 44102244 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 484814 # number of replacements -system.cpu.dcache.tags.tagsinuse 510.868965 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40339815 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 485326 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 83.119007 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 154595500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 510.868965 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997791 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997791 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 484796 # number of replacements +system.cpu.dcache.tags.tagsinuse 510.868688 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40338903 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 485308 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 83.120210 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 154723500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 510.868688 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997790 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997790 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 456 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84466838 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84466838 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 21417711 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21417711 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18830642 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18830642 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 60188 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 60188 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15309 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15309 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 84466908 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 84466908 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 21416602 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21416602 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18830761 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18830761 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 60264 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 60264 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15306 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15306 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40248353 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40248353 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40308541 # number of overall hits -system.cpu.dcache.overall_hits::total 40308541 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 562442 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 562442 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1019259 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1019259 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 68672 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 68672 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 614 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 614 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1581701 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1581701 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1650373 # number of overall misses -system.cpu.dcache.overall_misses::total 1650373 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14412910000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14412910000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14258561428 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14258561428 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5705500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 5705500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28671471428 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28671471428 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28671471428 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28671471428 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21980153 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21980153 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 40247363 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40247363 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40307627 # number of overall hits +system.cpu.dcache.overall_hits::total 40307627 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 563583 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 563583 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1019140 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1019140 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 68608 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 68608 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 617 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 617 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1582723 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1582723 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1651331 # number of overall misses +system.cpu.dcache.overall_misses::total 1651331 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14467064000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14467064000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14294982430 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14294982430 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6393500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 6393500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28762046430 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28762046430 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28762046430 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28762046430 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21980185 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21980185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128860 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128860 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128872 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128872 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15923 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15923 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41830054 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41830054 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41958914 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41958914 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025589 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.025589 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051348 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.051348 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532919 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.532919 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038561 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038561 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037813 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037813 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039333 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039333 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25625.593395 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25625.593395 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13989.144494 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 13989.144494 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9292.345277 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9292.345277 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18126.985712 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18126.985712 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17372.722062 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17372.722062 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 115 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2956958 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 15 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 131265 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.666667 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 22.526629 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 484814 # number of writebacks -system.cpu.dcache.writebacks::total 484814 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 263368 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 263368 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870698 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 870698 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 614 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 614 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1134066 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1134066 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1134066 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1134066 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299074 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 299074 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148561 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 148561 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37704 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 37704 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 447635 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 447635 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 485339 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 485339 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7124794500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7124794500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2343478471 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2343478471 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1981400500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1981400500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9468272971 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9468272971 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11449673471 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11449673471 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013607 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013607 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 41830086 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41830086 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41958958 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41958958 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025641 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.025641 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051342 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.051342 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532373 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.532373 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038749 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038749 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037837 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037837 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039356 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039356 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25669.801964 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25669.801964 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14026.514934 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 14026.514934 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10362.236629 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 10362.236629 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18172.508032 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18172.508032 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17417.493180 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17417.493180 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 29 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2976739 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 131356 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.800000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 22.661614 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 484796 # number of writebacks +system.cpu.dcache.writebacks::total 484796 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 264511 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 264511 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870576 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 870576 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 617 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 617 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1135087 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1135087 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1135087 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1135087 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299072 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 299072 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148564 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 148564 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37686 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 37686 # 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number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9463416971 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11464849471 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11464849471 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013606 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013606 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007484 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007484 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.292597 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.292597 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.292430 # 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average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52551.466688 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21151.770909 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21151.770909 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23591.084728 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23591.084728 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 325639 # number of replacements -system.cpu.icache.tags.tagsinuse 510.373274 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22095836 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 326151 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 67.747258 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 1176670500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.373274 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996823 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996823 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23783.583886 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23783.583886 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15820.878349 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15820.878349 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53108.117073 # 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Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 1174665500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.336563 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996751 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996751 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 328 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45192862 # 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average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17237.437832 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17237.437832 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17237.437832 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 562602 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 332 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 8 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 45207041 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45207041 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 22103280 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22103280 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22103280 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22103280 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22103280 # number of overall hits +system.cpu.icache.overall_hits::total 22103280 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 337250 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 337250 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 337250 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 337250 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 337250 # number of overall misses +system.cpu.icache.overall_misses::total 337250 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 5803062852 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 5803062852 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 5803062852 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 5803062852 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 5803062852 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 5803062852 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22440530 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22440530 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22440530 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22440530 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22440530 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22440530 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015029 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.015029 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.015029 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.015029 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.015029 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.015029 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17207.006233 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17207.006233 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17207.006233 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17207.006233 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17207.006233 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17207.006233 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 559762 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 94 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 26054 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 25894 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 21.593690 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 21.617440 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 47 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 325639 # number of writebacks -system.cpu.icache.writebacks::total 325639 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 11348 # 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average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84725.221585 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88283.519946 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 87263.333514 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84725.221585 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88283.519946 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 87263.333514 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # 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number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6427576500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6427576500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2920395500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7161099500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10081495000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2920395500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7161099500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10227090401 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20308585401 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056125 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056125 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.113665 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.113665 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.239570 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.239570 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113665 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.183402 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.155373 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113665 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.183402 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056940 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056940 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.113797 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.113797 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.239620 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.239620 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113797 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.183685 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.155604 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113797 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.183685 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.297472 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 89513.458694 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 89513.458694 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15500 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15500 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86665.467626 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86665.467626 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79075.285930 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79075.285930 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79569.145903 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79569.145903 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79075.285930 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80234.052354 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79893.339255 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79075.285930 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80234.052354 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 89513.458694 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84488.752411 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1621957 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 810494 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79908 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 18773 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 18772 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 662893 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 354931 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 552820 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 28222 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 146565 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 13 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 13 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 148597 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 148597 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 326165 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 336729 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 977954 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1455492 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2433446 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41714496 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62088960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 103803456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 272099 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6227968 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1083589 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.091107 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.287765 # Request fanout histogram +system.cpu.l2cache.overall_mshr_miss_rate::total 0.297350 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 88935.087621 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 88935.087621 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15571.428571 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15571.428571 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86694.598747 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86694.598747 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 78729.592387 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 78729.592387 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79664.569984 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79664.569984 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 78729.592387 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80331.817060 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79861.016493 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 78729.592387 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80331.817060 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 88935.087621 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84186.597194 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1621556 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 810285 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 80433 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 18616 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 18570 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 46 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 662693 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 357682 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 549823 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 28326 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 146207 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 14 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 14 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 148596 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 148596 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 325982 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 336712 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 977404 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1455440 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2432844 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41691008 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62086656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 103777664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 271801 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 6225152 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1083090 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.091523 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.288499 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 984867 90.89% 90.89% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 98721 9.11% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 984008 90.85% 90.85% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 99036 9.14% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 46 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1083589 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1621431500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1083090 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1621030000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 4.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 489373744 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 489099244 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 728066857 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 728047842 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 348152 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 205320 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 348230 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 205331 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 214278 # Transaction distribution -system.membus.trans_dist::WritebackDirty 97298 # Transaction distribution -system.membus.trans_dist::CleanEvict 28222 # Transaction distribution -system.membus.trans_dist::UpgradeReq 13 # Transaction distribution -system.membus.trans_dist::ReadExReq 8340 # Transaction distribution -system.membus.trans_dist::ReadExResp 8340 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 214279 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 570770 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 570770 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 20474624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20474624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 214175 # Transaction distribution +system.membus.trans_dist::WritebackDirty 97253 # Transaction distribution +system.membus.trans_dist::CleanEvict 28326 # Transaction distribution +system.membus.trans_dist::UpgradeReq 14 # Transaction distribution +system.membus.trans_dist::ReadExReq 8461 # Transaction distribution +system.membus.trans_dist::ReadExResp 8461 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 214176 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 570866 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 570866 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 20472896 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20472896 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 222632 # Request fanout histogram +system.membus.snoop_fanout::samples 222651 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 222632 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 222651 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 222632 # Request fanout histogram -system.membus.reqLayer0.occupancy 835899979 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 222651 # Request fanout histogram +system.membus.reqLayer0.occupancy 835869990 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1175524166 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1175713686 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index 20e951f6a..c13f099b6 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.150226 # Number of seconds simulated -sim_ticks 1150225722500 # Number of ticks simulated -final_tick 1150225722500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.150228 # Number of seconds simulated +sim_ticks 1150227786500 # Number of ticks simulated +final_tick 1150227786500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 386915 # Simulator instruction rate (inst/s) -host_op_rate 416843 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 288133243 # Simulator tick rate (ticks/s) -host_mem_usage 273608 # Number of bytes of host memory used -host_seconds 3991.99 # Real time elapsed on the host +host_inst_rate 394229 # Simulator instruction rate (inst/s) +host_op_rate 424722 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 293579950 # Simulator tick rate (ticks/s) +host_mem_usage 273524 # Number of bytes of host memory used +host_seconds 3917.94 # Real time elapsed on the host sim_insts 1544563088 # Number of instructions simulated sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 50240 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 132094848 # Number of bytes read from this memory system.physmem.bytes_read::total 132145088 # Number of bytes read from this memory @@ -27,16 +27,16 @@ system.physmem.num_reads::total 2064767 # Nu system.physmem.num_writes::writebacks 1060156 # Number of write requests responded to by this memory system.physmem.num_writes::total 1060156 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 43678 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 114842544 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 114886222 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 114842338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 114886016 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 43678 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 43678 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 58988408 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 58988408 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 58988408 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 58988302 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 58988302 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 58988302 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 43678 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 114842544 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 173874630 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 114842338 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 173874318 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 2064767 # Number of read requests accepted system.physmem.writeReqs 1060156 # Number of write requests accepted system.physmem.readBursts 2064767 # Number of DRAM read bursts, including those serviced by the write queue @@ -61,10 +61,10 @@ system.physmem.perBankRdBursts::8 132488 # Pe system.physmem.perBankRdBursts::9 134781 # Per bank write bursts system.physmem.perBankRdBursts::10 133246 # Per bank write bursts system.physmem.perBankRdBursts::11 134508 # Per bank write bursts -system.physmem.perBankRdBursts::12 134524 # Per bank write bursts +system.physmem.perBankRdBursts::12 134523 # Per bank write bursts system.physmem.perBankRdBursts::13 134597 # Per bank write bursts system.physmem.perBankRdBursts::14 130537 # Per bank write bursts -system.physmem.perBankRdBursts::15 130646 # Per bank write bursts +system.physmem.perBankRdBursts::15 130647 # Per bank write bursts system.physmem.perBankWrBursts::0 66781 # Per bank write bursts system.physmem.perBankWrBursts::1 64940 # Per bank write bursts system.physmem.perBankWrBursts::2 63173 # Per bank write bursts @@ -83,7 +83,7 @@ system.physmem.perBankWrBursts::14 67159 # Pe system.physmem.perBankWrBursts::15 66466 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1150225621500 # Total gap between requests +system.physmem.totGap 1150227685500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -98,8 +98,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 1060156 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1919491 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 143962 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1919511 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 143942 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -145,24 +145,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 31061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 32150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 57332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 62506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 62721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 62815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 62684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 62639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 62591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 62502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 62571 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 31051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 32142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 57333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 62501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 62728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 62816 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 62688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 62636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 62593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 62501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 62570 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 62618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62659 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 62645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 62805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 63052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 62414 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 62339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 62806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 63061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 62416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 62338 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 38 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -194,25 +194,25 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1927680 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.704050 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.827428 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 125.877785 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1497957 77.71% 77.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 310202 16.09% 93.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52219 2.71% 96.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20801 1.08% 97.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13076 0.68% 98.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7806 0.40% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5210 0.27% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5119 0.27% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 15290 0.79% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1927680 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 62182 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.137773 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 23.854622 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 150.738788 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 62143 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1927678 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.704158 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.827351 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 125.878363 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1497959 77.71% 77.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 310183 16.09% 93.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52221 2.71% 96.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20819 1.08% 97.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13074 0.68% 98.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7800 0.40% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5214 0.27% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5117 0.27% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 15291 0.79% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1927678 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 62183 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.137240 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 23.854238 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 150.737609 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 62144 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 18 0.03% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 7 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes @@ -222,24 +222,24 @@ system.physmem.rdPerTurnAround::10240-11263 1 0.00% 100.00% # system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::18432-19455 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 62182 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 62182 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.048808 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.017651 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.031288 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 29885 48.06% 48.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1078 1.73% 49.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 29552 47.53% 97.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1636 2.63% 99.95% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 62183 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 62183 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.048534 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.017369 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.031425 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 29894 48.07% 48.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1086 1.75% 49.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 29528 47.49% 97.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1644 2.64% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::20 28 0.05% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::21 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 62182 # Writes before turning the bus around for reads -system.physmem.totQLat 59945214750 # Total ticks spent queuing -system.physmem.totMemAccLat 98635221000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.wrPerTurnAround::total 62183 # Writes before turning the bus around for reads +system.physmem.totQLat 59946131250 # Total ticks spent queuing +system.physmem.totMemAccLat 98636137500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 10317335000 # Total ticks spent in databus transfers -system.physmem.avgQLat 29050.73 # Average queueing delay per DRAM burst +system.physmem.avgQLat 29051.17 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47800.73 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 47801.17 # Average memory access latency per DRAM burst system.physmem.avgRdBW 114.81 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 58.99 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 114.89 # Average system read bandwidth in MiByte/s @@ -250,58 +250,58 @@ system.physmem.busUtilRead 0.90 # Da system.physmem.busUtilWrite 0.46 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing system.physmem.avgWrQLen 24.88 # Average write queue length when enqueuing -system.physmem.readRowHits 775403 # Number of row buffer hits during reads -system.physmem.writeRowHits 420503 # Number of row buffer hits during writes +system.physmem.readRowHits 775435 # Number of row buffer hits during reads +system.physmem.writeRowHits 420473 # Number of row buffer hits during writes system.physmem.readRowHitRate 37.58 # Row buffer hit rate for reads system.physmem.writeRowHitRate 39.66 # Row buffer hit rate for writes -system.physmem.avgGap 368081.27 # Average gap between requests +system.physmem.avgGap 368081.93 # Average gap between requests system.physmem.pageHitRate 38.29 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6704024460 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3563246940 # Energy for precharge commands per rank (pJ) +system.physmem_0.actEnergy 6703938780 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3563201400 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 7126719600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 2697622920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 71584047600.000015 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 47598370410 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2598119520 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 242886973860 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 71929585440 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 82360762695 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 539073775965 # Total energy per rank (pJ) -system.physmem_0.averagePower 468.667814 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1039023905500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 3501879500 # Time in different power states -system.physmem_0.memoryStateTime::REF 30346756000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 319059811750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 187317352250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 77352878250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 532647044750 # Time in different power states -system.physmem_1.actEnergy 7059682140 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3752298660 # Energy for precharge commands per rank (pJ) +system.physmem_0.refreshEnergy 71587735440.000015 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 47610368340 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2598027360 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 242891748180 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 71936235360 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 82347779655 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 539087705175 # Total energy per rank (pJ) +system.physmem_0.averagePower 468.679083 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1039000185750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 3501543500 # Time in different power states +system.physmem_0.memoryStateTime::REF 30348316000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 319007908000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 187335147250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 77377438000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 532657433750 # Time in different power states +system.physmem_1.actEnergy 7059753540 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3752336610 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 7606434780 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 2836250460 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 71064062160.000015 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 47576528010 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2430223200 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 248601681570 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 68458810560 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 80907988260 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 540316908180 # Total energy per rank (pJ) -system.physmem_1.averagePower 469.748583 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1039511813000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 3059644000 # Time in different power states -system.physmem_1.memoryStateTime::REF 30118792000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 316054273750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 178278810500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 77535412750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 545178789500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 240019882 # Number of BP lookups -system.cpu.branchPred.condPredicted 186610383 # Number of conditional branches predicted +system.physmem_1.refreshEnergy 71062832880.000015 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 47583848520 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2430369600 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 248599905450 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 68453747040 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 80907358950 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 540315522360 # Total energy per rank (pJ) +system.physmem_1.averagePower 469.746535 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1039499383250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 3059154750 # Time in different power states +system.physmem_1.memoryStateTime::REF 30118266000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 316057409750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 178263690250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 77550921750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 545178344000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 240019900 # Number of BP lookups +system.cpu.branchPred.condPredicted 186610401 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 14528957 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 131646647 # Number of BTB lookups -system.cpu.branchPred.BTBHits 122324605 # Number of BTB hits +system.cpu.branchPred.BTBLookups 131646658 # Number of BTB lookups +system.cpu.branchPred.BTBHits 122324616 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.918891 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 92.918892 # BTB Hit Percentage system.cpu.branchPred.usedRAS 15657431 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 535 # Number of indirect predictor lookups. @@ -309,7 +309,7 @@ system.cpu.branchPred.indirectHits 232 # Nu system.cpu.branchPred.indirectMisses 303 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 162 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -339,7 +339,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -369,7 +369,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -399,7 +399,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -430,16 +430,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1150225722500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2300451445 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 1150227786500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2300455573 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563088 # Number of instructions committed system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed -system.cpu.discardedOps 41363683 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 41363694 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.489387 # CPI: cycles per instruction -system.cpu.ipc 0.671417 # IPC: instructions per cycle +system.cpu.cpi 1.489389 # CPI: cycles per instruction +system.cpu.ipc 0.671416 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 1030178776 61.91% 61.91% # Class of committed instruction system.cpu.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction @@ -479,16 +479,16 @@ system.cpu.op_class_0::FloatMemWrite 24 0.00% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 1664032481 # Class of committed instruction -system.cpu.tickCycles 1845014986 # Number of cycles that the object actually ticked -system.cpu.idleCycles 455436459 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 1845015660 # Number of cycles that the object actually ticked +system.cpu.idleCycles 455439913 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 9220107 # number of replacements -system.cpu.dcache.tags.tagsinuse 4085.805290 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 624493165 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4085.805308 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624493167 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9224203 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 67.701585 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 9872962500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4085.805290 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4085.805308 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997511 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997511 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -497,43 +497,43 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 1190 system.cpu.dcache.tags.age_task_id_blocks_1024::2 2640 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 65 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1277391151 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1277391151 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 454163885 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 454163885 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 170329157 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170329157 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1277391153 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1277391153 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 454163886 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 454163886 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170329158 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170329158 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 624493042 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 624493042 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 624493043 # number of overall hits -system.cpu.dcache.overall_hits::total 624493043 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 624493044 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624493044 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 624493045 # number of overall hits +system.cpu.dcache.overall_hits::total 624493045 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 7333417 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 7333417 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2256890 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2256890 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2256889 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2256889 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 9590307 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9590307 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9590309 # number of overall misses -system.cpu.dcache.overall_misses::total 9590309 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 208195707500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 208195707500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 119902321500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 119902321500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 328098029000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 328098029000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 328098029000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 328098029000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 461497302 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 461497302 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9590306 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9590306 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9590308 # number of overall misses +system.cpu.dcache.overall_misses::total 9590308 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 208196327000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 208196327000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 119903341000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 119903341000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 328099668000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 328099668000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 328099668000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 328099668000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 461497303 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 461497303 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) @@ -542,10 +542,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 634083349 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 634083349 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 634083352 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 634083352 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 634083350 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 634083350 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 634083353 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 634083353 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015890 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.015890 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013077 # miss rate for WriteReq accesses @@ -556,14 +556,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.015125 system.cpu.dcache.demand_miss_rate::total 0.015125 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015125 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015125 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28389.999846 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28389.999846 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53127.233272 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53127.233272 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34211.420865 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34211.420865 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34211.413730 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34211.413730 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28390.084322 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28390.084322 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53127.708540 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53127.708540 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34211.595334 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34211.595334 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34211.588199 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34211.588199 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -574,12 +574,12 @@ system.cpu.dcache.writebacks::writebacks 3670055 # nu system.cpu.dcache.writebacks::total 3670055 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 366056 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 366056 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 366105 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 366105 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 366105 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 366105 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 366055 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 366055 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 366104 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 366104 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 366104 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 366104 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333368 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7333368 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890834 # number of WriteReq MSHR misses @@ -590,16 +590,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9224202 system.cpu.dcache.demand_mshr_misses::total 9224202 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9224203 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9224203 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 200857919000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 200857919000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92466638500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 92466638500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 200858538000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 200858538000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92467008500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 92467008500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 81000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 81000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 293324557500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 293324557500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 293324638500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 293324638500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 293325546500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 293325546500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 293325627500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 293325627500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015890 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015890 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses @@ -610,24 +610,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014547 system.cpu.dcache.demand_mshr_miss_rate::total 0.014547 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014547 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014547 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27389.586749 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27389.586749 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48902.568126 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48902.568126 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27389.671158 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27389.671158 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48902.763807 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48902.763807 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 81000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 81000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31799.450782 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 31799.450782 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31799.456116 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 31799.456116 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31799.558000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 31799.558000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31799.563334 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 31799.563334 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 33 # number of replacements -system.cpu.icache.tags.tagsinuse 660.478132 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 466274661 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 660.477823 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 466274758 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 822 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 567244.113139 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 567244.231144 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 660.478132 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 660.477823 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.322499 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.322499 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 789 # Occupied blocks per task id @@ -635,15 +635,15 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 32 system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 751 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.385254 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 932551788 # Number of tag accesses -system.cpu.icache.tags.data_accesses 932551788 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 466274661 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 466274661 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 466274661 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 466274661 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 466274661 # number of overall hits -system.cpu.icache.overall_hits::total 466274661 # number of overall hits +system.cpu.icache.tags.tag_accesses 932551982 # Number of tag accesses +system.cpu.icache.tags.data_accesses 932551982 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 466274758 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 466274758 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 466274758 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 466274758 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 466274758 # number of overall hits +system.cpu.icache.overall_hits::total 466274758 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 822 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 822 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 822 # number of demand (read+write) misses @@ -656,12 +656,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 74803000 system.cpu.icache.demand_miss_latency::total 74803000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 74803000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 74803000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 466275483 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 466275483 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 466275483 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 466275483 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 466275483 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 466275483 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 466275580 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 466275580 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 466275580 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 466275580 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 466275580 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 466275580 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses @@ -706,16 +706,16 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 90001.216545 system.cpu.icache.demand_avg_mshr_miss_latency::total 90001.216545 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 90001.216545 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 90001.216545 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 2032334 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31895.835750 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 31895.837315 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 16378248 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2065102 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 7.930963 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 54709395000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 10.372188 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.535695 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31859.927867 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 10.372175 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.535649 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31859.929491 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000317 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000779 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.972288 # Average percentage of cache occupancy @@ -729,7 +729,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 21752 system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 149613670 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 149613670 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 3670055 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 3670055 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 33 # number of WritebackClean hits @@ -758,18 +758,18 @@ system.cpu.l2cache.demand_misses::total 2064773 # nu system.cpu.l2cache.overall_misses::cpu.inst 785 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2063988 # number of overall misses system.cpu.l2cache.overall_misses::total 2064773 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 78282559500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 78282559500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 78282928500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 78282928500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 72328000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::total 72328000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 125996723500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 125996723500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 125997338000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 125997338000 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 72328000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 204279283000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 204351611000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 204280266500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 204352594500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 72328000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 204279283000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 204351611000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 204280266500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 204352594500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 3670055 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 3670055 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 33 # number of WritebackClean accesses(hits+misses) @@ -798,18 +798,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.223823 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.954988 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.223758 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.223823 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96368.759102 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96368.759102 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96369.213355 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96369.213355 # average ReadExReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92137.579618 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92137.579618 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 100663.295291 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 100663.295291 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 100663.786237 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 100663.786237 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92137.579618 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 98973.096258 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 98970.497483 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 98973.572763 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 98970.973807 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92137.579618 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 98973.096258 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 98970.497483 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 98973.572763 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 98970.973807 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -838,18 +838,18 @@ system.cpu.l2cache.demand_mshr_misses::total 2064767 system.cpu.l2cache.overall_mshr_misses::cpu.inst 785 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2063982 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 2064767 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70159329500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70159329500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70159698500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70159698500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 64478000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 64478000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 113479586000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 113479586000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 113480200500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 113480200500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64478000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 183638915500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 183703393500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 183639899000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 183704377000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64478000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 183638915500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 183703393500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 183639899000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 183704377000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.429611 # mshr miss rate for ReadExReq accesses @@ -864,25 +864,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.223822 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223757 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.223822 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86368.759102 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86368.759102 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86369.213355 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86369.213355 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82137.579618 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82137.579618 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90663.340415 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90663.340415 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90663.831363 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90663.831363 # average ReadSharedReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82137.579618 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88973.118709 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88970.519918 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88973.595215 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88970.996243 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82137.579618 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88973.118709 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88970.519918 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88973.595215 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88970.996243 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 18445165 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 9220152 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 1444 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1438 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 7334191 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 4730211 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 33 # Transaction distribution @@ -922,7 +922,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1252444 # Transaction distribution system.membus.trans_dist::WritebackDirty 1060156 # Transaction distribution system.membus.trans_dist::CleanEvict 970949 # Transaction distribution @@ -945,9 +945,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 2064767 # Request fanout histogram -system.membus.reqLayer0.occupancy 8804910500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8804919500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 11285155750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 11285149250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 3e40b495b..413bb751f 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.787742 # Number of seconds simulated -sim_ticks 787742202500 # Number of ticks simulated -final_tick 787742202500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.787540 # Number of seconds simulated +sim_ticks 787540181500 # Number of ticks simulated +final_tick 787540181500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 267668 # Simulator instruction rate (inst/s) -host_op_rate 288372 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 136513298 # Simulator tick rate (ticks/s) -host_mem_usage 329792 # Number of bytes of host memory used -host_seconds 5770.44 # Real time elapsed on the host +host_inst_rate 265954 # Simulator instruction rate (inst/s) +host_op_rate 286525 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 135604104 # Simulator tick rate (ticks/s) +host_mem_usage 328428 # Number of bytes of host memory used +host_seconds 5807.64 # Real time elapsed on the host sim_insts 1544563024 # Number of instructions simulated sim_ops 1664032416 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 65664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 236035776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 63780672 # Number of bytes read from this memory -system.physmem.bytes_read::total 299882112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 65664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 65664 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 104579136 # Number of bytes written to this memory -system.physmem.bytes_written::total 104579136 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1026 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3688059 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 996573 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4685658 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1634049 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1634049 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 83357 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 299635814 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 80966428 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 380685599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 83357 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 83357 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 132758072 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 132758072 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 132758072 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 83357 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 299635814 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 80966428 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 513443671 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 4685658 # Number of read requests accepted -system.physmem.writeReqs 1634049 # Number of write requests accepted -system.physmem.readBursts 4685658 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1634049 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 299378880 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 503232 # Total number of bytes read from write queue -system.physmem.bytesWritten 104576512 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 299882112 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 104579136 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7863 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 17 # Number of DRAM write bursts merged with an existing one +system.physmem.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 65088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 236130432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 63765312 # Number of bytes read from this memory +system.physmem.bytes_read::total 299960832 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 65088 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 65088 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 104600704 # Number of bytes written to this memory +system.physmem.bytes_written::total 104600704 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1017 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3689538 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 996333 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4686888 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1634386 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1634386 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 82647 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 299832869 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 80967693 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 380883210 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 82647 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 82647 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 132819514 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 132819514 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 132819514 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 82647 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 299832869 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 80967693 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 513702723 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 4686888 # Number of read requests accepted +system.physmem.writeReqs 1634386 # Number of write requests accepted +system.physmem.readBursts 4686888 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1634386 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 299458048 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 502784 # Total number of bytes read from write queue +system.physmem.bytesWritten 104597376 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 299960832 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 104600704 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7856 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 26 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 301431 # Per bank write bursts -system.physmem.perBankRdBursts::1 301123 # Per bank write bursts -system.physmem.perBankRdBursts::2 285299 # Per bank write bursts -system.physmem.perBankRdBursts::3 287676 # Per bank write bursts -system.physmem.perBankRdBursts::4 288751 # Per bank write bursts -system.physmem.perBankRdBursts::5 286469 # Per bank write bursts -system.physmem.perBankRdBursts::6 281133 # Per bank write bursts -system.physmem.perBankRdBursts::7 278330 # Per bank write bursts -system.physmem.perBankRdBursts::8 294107 # Per bank write bursts -system.physmem.perBankRdBursts::9 299584 # Per bank write bursts -system.physmem.perBankRdBursts::10 292343 # Per bank write bursts -system.physmem.perBankRdBursts::11 297976 # Per bank write bursts -system.physmem.perBankRdBursts::12 299704 # Per bank write bursts -system.physmem.perBankRdBursts::13 299189 # Per bank write bursts -system.physmem.perBankRdBursts::14 294388 # Per bank write bursts -system.physmem.perBankRdBursts::15 290292 # Per bank write bursts -system.physmem.perBankWrBursts::0 103694 # Per bank write bursts -system.physmem.perBankWrBursts::1 101682 # Per bank write bursts -system.physmem.perBankWrBursts::2 99052 # Per bank write bursts -system.physmem.perBankWrBursts::3 99844 # Per bank write bursts -system.physmem.perBankWrBursts::4 99095 # Per bank write bursts -system.physmem.perBankWrBursts::5 98699 # Per bank write bursts -system.physmem.perBankWrBursts::6 102473 # Per bank write bursts -system.physmem.perBankWrBursts::7 104090 # Per bank write bursts -system.physmem.perBankWrBursts::8 105068 # Per bank write bursts -system.physmem.perBankWrBursts::9 104102 # Per bank write bursts -system.physmem.perBankWrBursts::10 101990 # Per bank write bursts -system.physmem.perBankWrBursts::11 102510 # Per bank write bursts -system.physmem.perBankWrBursts::12 102612 # Per bank write bursts -system.physmem.perBankWrBursts::13 102296 # Per bank write bursts -system.physmem.perBankWrBursts::14 104281 # Per bank write bursts -system.physmem.perBankWrBursts::15 102520 # Per bank write bursts +system.physmem.perBankRdBursts::0 302302 # Per bank write bursts +system.physmem.perBankRdBursts::1 301952 # Per bank write bursts +system.physmem.perBankRdBursts::2 285792 # Per bank write bursts +system.physmem.perBankRdBursts::3 288384 # Per bank write bursts +system.physmem.perBankRdBursts::4 288196 # Per bank write bursts +system.physmem.perBankRdBursts::5 285903 # Per bank write bursts +system.physmem.perBankRdBursts::6 281854 # Per bank write bursts +system.physmem.perBankRdBursts::7 277846 # Per bank write bursts +system.physmem.perBankRdBursts::8 294690 # Per bank write bursts +system.physmem.perBankRdBursts::9 300083 # Per bank write bursts +system.physmem.perBankRdBursts::10 291836 # Per bank write bursts +system.physmem.perBankRdBursts::11 298648 # Per bank write bursts +system.physmem.perBankRdBursts::12 299589 # Per bank write bursts +system.physmem.perBankRdBursts::13 298339 # Per bank write bursts +system.physmem.perBankRdBursts::14 293778 # Per bank write bursts +system.physmem.perBankRdBursts::15 289840 # Per bank write bursts +system.physmem.perBankWrBursts::0 103932 # Per bank write bursts +system.physmem.perBankWrBursts::1 101641 # Per bank write bursts +system.physmem.perBankWrBursts::2 99135 # Per bank write bursts +system.physmem.perBankWrBursts::3 99721 # Per bank write bursts +system.physmem.perBankWrBursts::4 98850 # Per bank write bursts +system.physmem.perBankWrBursts::5 98703 # Per bank write bursts +system.physmem.perBankWrBursts::6 102612 # Per bank write bursts +system.physmem.perBankWrBursts::7 104045 # Per bank write bursts +system.physmem.perBankWrBursts::8 105476 # Per bank write bursts +system.physmem.perBankWrBursts::9 104249 # Per bank write bursts +system.physmem.perBankWrBursts::10 101862 # Per bank write bursts +system.physmem.perBankWrBursts::11 102612 # Per bank write bursts +system.physmem.perBankWrBursts::12 102593 # Per bank write bursts +system.physmem.perBankWrBursts::13 102283 # Per bank write bursts +system.physmem.perBankWrBursts::14 104155 # Per bank write bursts +system.physmem.perBankWrBursts::15 102465 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 787742161500 # Total gap between requests +system.physmem.totGap 787540140500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 4685658 # Read request sizes (log2) +system.physmem.readPktSize::6 4686888 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1634049 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2727854 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1051064 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 327817 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 232993 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 158136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 89940 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 39970 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 24320 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 17966 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4404 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1761 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 825 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 484 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 11 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1634386 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 2728191 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1051856 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 328268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 233236 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 157524 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 89904 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 39917 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 24410 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 17981 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4434 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1760 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 828 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 462 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 250 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see @@ -149,42 +149,42 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 24393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 26784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 73104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 84746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 93459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 99625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 24307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 26803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 73031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 84525 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 93506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 99632 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 103284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 105129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 105804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 106233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 107403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 108454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 109545 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 110077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 108778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 102213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 101052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 4490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 898 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 105231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 105756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 106392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 107277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 108481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 109650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 110259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 109107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 102133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 101095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 4500 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 869 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 20 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see @@ -198,133 +198,132 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 4258602 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 94.856263 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 78.818587 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 102.740363 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3399214 79.82% 79.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 662534 15.56% 95.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 94110 2.21% 97.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 35203 0.83% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 22640 0.53% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12473 0.29% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7407 0.17% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5223 0.12% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19798 0.46% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 4258602 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 97968 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 47.747867 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 99.462080 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-255 95523 97.50% 97.50% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-511 1197 1.22% 98.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-767 705 0.72% 99.45% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::768-1023 407 0.42% 99.86% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1279 106 0.11% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1280-1535 17 0.02% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-1791 4 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1792-2047 4 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2303 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2304-2559 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3584-3839 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4352-4607 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 4260550 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 94.836056 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 78.812158 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 102.756680 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3400540 79.81% 79.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 663329 15.57% 95.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 94665 2.22% 97.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 34624 0.81% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 22478 0.53% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12365 0.29% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7339 0.17% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5272 0.12% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19938 0.47% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 4260550 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 97975 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 47.757050 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 99.440701 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 95549 97.52% 97.52% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 1198 1.22% 98.75% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-767 700 0.71% 99.46% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-1023 381 0.39% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1279 109 0.11% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1280-1535 28 0.03% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-1791 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1792-2047 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2303 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2304-2559 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2816-3071 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3328-3583 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4608-4863 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 97968 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 97968 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.678997 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.638691 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.208217 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 70313 71.77% 71.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1920 1.96% 73.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 17565 17.93% 91.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 5314 5.42% 97.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1711 1.75% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 637 0.65% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 262 0.27% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 130 0.13% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 63 0.06% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 33 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 13 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 97968 # Writes before turning the bus around for reads -system.physmem.totQLat 162666982970 # Total ticks spent queuing -system.physmem.totMemAccLat 250375639220 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 23388975000 # Total ticks spent in databus transfers -system.physmem.avgQLat 34774.29 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 97975 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 97975 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.681133 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.640632 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.211305 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 70258 71.71% 71.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1952 1.99% 73.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 17579 17.94% 91.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 5262 5.37% 97.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1746 1.78% 98.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 657 0.67% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 283 0.29% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 119 0.12% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 69 0.07% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 29 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 11 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 8 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 97975 # Writes before turning the bus around for reads +system.physmem.totQLat 162188930459 # Total ticks spent queuing +system.physmem.totMemAccLat 249920780459 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 23395160000 # Total ticks spent in databus transfers +system.physmem.avgQLat 34662.92 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 53524.29 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 380.05 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 132.75 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 380.69 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 132.76 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 53412.92 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 380.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 132.82 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 380.88 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 132.82 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 4.01 # Data bus utilization in percentage system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.04 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.91 # Average write queue length when enqueuing -system.physmem.readRowHits 1712898 # Number of row buffer hits during reads -system.physmem.writeRowHits 340301 # Number of row buffer hits during writes +system.physmem.avgWrQLen 24.99 # Average write queue length when enqueuing +system.physmem.readRowHits 1713351 # Number of row buffer hits during reads +system.physmem.writeRowHits 339452 # Number of row buffer hits during writes system.physmem.readRowHitRate 36.62 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 20.83 # Row buffer hit rate for writes -system.physmem.avgGap 124648.53 # Average gap between requests -system.physmem.pageHitRate 32.53 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 15106540680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8029309200 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 16494913680 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4221043380 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 59407414560.000015 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 64582002630 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1606944480 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 223006056720 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 35875852320 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 16122239730 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 444464207160 # Total energy per rank (pJ) -system.physmem_0.averagePower 564.225454 # Core power per rank (mW) -system.physmem_0.totalIdleTime 641904162368 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 1401750889 # Time in different power states -system.physmem_0.memoryStateTime::REF 25151370000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 59428702250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 93425472309 # Time in different power states -system.physmem_0.memoryStateTime::ACT 119284909993 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 489049997059 # Time in different power states -system.physmem_1.actEnergy 15299891880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 8132085390 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 16904542620 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4308478380 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 58934141760.000015 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 64765265610 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1612336320 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 219700492200 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 35552759520 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 18091245240 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 443312102310 # Total energy per rank (pJ) -system.physmem_1.averagePower 562.762917 # Core power per rank (mW) -system.physmem_1.totalIdleTime 641480248383 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 1450220904 # Time in different power states -system.physmem_1.memoryStateTime::REF 24952394000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 67105561000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 92583809905 # Time in different power states -system.physmem_1.memoryStateTime::ACT 119858377963 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 481791838728 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 286283098 # Number of BP lookups -system.cpu.branchPred.condPredicted 223408244 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14630421 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 158004936 # Number of BTB lookups -system.cpu.branchPred.BTBHits 150354998 # Number of BTB hits +system.physmem.writeRowHitRate 20.77 # Row buffer hit rate for writes +system.physmem.avgGap 124585.67 # Average gap between requests +system.physmem.pageHitRate 32.52 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 15118214580 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8035491255 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16509315060 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4221095580 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 59433229440.000015 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 64449448560 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1619596800 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 222781261830 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 36127794240 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 16128721335 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 444435904680 # Total energy per rank (pJ) +system.physmem_0.averagePower 564.334256 # Core power per rank (mW) +system.physmem_0.totalIdleTime 641954026654 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 1425644900 # Time in different power states +system.physmem_0.memoryStateTime::REF 25162536000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 59321643250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 94080310817 # Time in different power states +system.physmem_0.memoryStateTime::ACT 118997964696 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 488552081837 # Time in different power states +system.physmem_1.actEnergy 15302205240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 8133295995 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 16898973420 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4310127900 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 58889273040.000015 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 64896379290 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1612760640 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 219232237770 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 35640720960 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 18160779360 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 443087552175 # Total energy per rank (pJ) +system.physmem_1.averagePower 562.622143 # Core power per rank (mW) +system.physmem_1.totalIdleTime 640996653350 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 1453270191 # Time in different power states +system.physmem_1.memoryStateTime::REF 24933432000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 67412776000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 92813399032 # Time in different power states +system.physmem_1.memoryStateTime::ACT 120155386459 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 480771917818 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 286296319 # Number of BP lookups +system.cpu.branchPred.condPredicted 223413056 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14631953 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 158681776 # Number of BTB lookups +system.cpu.branchPred.BTBHits 150365310 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.158418 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 16643073 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 65 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 3065 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 1898 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1167 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 134 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 94.759029 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 16643535 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 63 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 3038 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 1928 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1110 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 135 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -354,7 +353,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -384,7 +383,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -414,7 +413,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -445,133 +444,133 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 787742202500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1575484406 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 787540181500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1575080364 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13928690 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2067537239 # Number of instructions fetch has processed -system.cpu.fetch.Branches 286283098 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 166999969 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1546809233 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29285745 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 303 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 986 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 656964714 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 942 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1575382084 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.406011 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.233492 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 13929690 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2067600144 # Number of instructions fetch has processed +system.cpu.fetch.Branches 286296319 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 167010773 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1546402654 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29288795 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 390 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 943 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 656982335 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 916 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1574978074 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.406414 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.233446 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 492942163 31.29% 31.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 465443083 29.54% 60.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101428647 6.44% 67.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 515568191 32.73% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 492512848 31.27% 31.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 465448024 29.55% 60.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 101428874 6.44% 67.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 515588328 32.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1575382084 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.181711 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.312318 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 74686824 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 577980395 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 849907031 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58165638 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14642196 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 42200734 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 724 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2037196735 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 52499519 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14642196 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 139768268 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 492678513 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 15538 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 837819054 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 90458515 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1976393108 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 26740093 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 45400307 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 126273 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1723349 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 29315109 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1985867653 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 9128208959 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2432891999 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 131 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1574978074 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.181766 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.312695 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 74681637 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 577546655 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 849949420 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58156641 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14643721 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 42204470 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 713 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2037236907 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 52506596 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14643721 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 139754890 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 492363005 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 15806 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 837855661 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 90344991 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1976429927 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 26743123 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 45374465 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 126519 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1703162 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 29238118 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1985901380 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 9128373257 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2432925820 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 137 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 310968708 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 177 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 176 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 111448171 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 542564068 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 199306440 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 26831952 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28868587 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1947979256 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 230 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1857513748 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13517148 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 283947070 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 647252748 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 60 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1575382084 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.179088 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.151868 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 311002435 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 176 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 174 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 111413296 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 542580071 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 199306810 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 26873371 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29046971 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1948011764 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 231 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1857503284 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13502415 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 283979579 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 647409512 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 61 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1574978074 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.179384 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.151840 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 622503864 39.51% 39.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 326012726 20.69% 60.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 378121823 24.00% 84.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 219723484 13.95% 98.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 29014011 1.84% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6176 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 622116780 39.50% 39.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 325952300 20.70% 60.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 378187133 24.01% 84.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 219716912 13.95% 98.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28998763 1.84% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6186 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1575382084 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1574978074 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 166098751 40.96% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2024 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191460455 47.22% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 47920650 11.82% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 166073423 40.98% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2008 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191445503 47.24% 88.22% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 47741848 11.78% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemRead 19 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 28 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 31 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1138250302 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 801028 0.04% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1138255860 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 800923 0.04% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -595,90 +594,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 29 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 30 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 532139508 28.65% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186322803 10.03% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 32 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 532128426 28.65% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186317966 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 33 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 24 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1857513748 # Type of FU issued -system.cpu.iq.rate 1.179011 # Inst issue rate -system.cpu.iq.fu_busy_cnt 405481927 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.218293 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5709408400 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2231939413 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1805717250 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 255 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 228 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 69 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2262995524 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 151 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17822173 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1857503284 # Type of FU issued +system.cpu.iq.rate 1.179307 # Inst issue rate +system.cpu.iq.fu_busy_cnt 405262832 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.218176 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5708749627 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2232004447 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1805721857 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 262 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 240 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 70 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2262765960 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 156 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 17817152 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 84257734 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 66715 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13309 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 24459395 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 84273737 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 66671 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13339 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 24459765 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4550351 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4849996 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4534666 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4848313 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14642196 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25436916 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1454941 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1947979633 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 14643721 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25440287 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1476217 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1948012141 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 542564068 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 199306440 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 168 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 159182 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1294449 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13309 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 7700831 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8703764 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 16404595 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1827842620 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 516961097 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29671128 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 542580071 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 199306810 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 169 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 159536 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1315183 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13339 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 7701795 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8704622 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 16406417 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1827836046 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 516947496 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29667238 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 147 # number of nop insts executed -system.cpu.iew.exec_refs 698716504 # number of memory reference insts executed -system.cpu.iew.exec_branches 229543654 # Number of branches executed -system.cpu.iew.exec_stores 181755407 # Number of stores executed -system.cpu.iew.exec_rate 1.160178 # Inst execution rate -system.cpu.iew.wb_sent 1808745333 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1805717319 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1169202335 # num instructions producing a value -system.cpu.iew.wb_consumers 1689603795 # num instructions consuming a value -system.cpu.iew.wb_rate 1.146135 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.691998 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 258049766 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 146 # number of nop insts executed +system.cpu.iew.exec_refs 698700973 # number of memory reference insts executed +system.cpu.iew.exec_branches 229547821 # Number of branches executed +system.cpu.iew.exec_stores 181753477 # Number of stores executed +system.cpu.iew.exec_rate 1.160472 # Inst execution rate +system.cpu.iew.wb_sent 1808752239 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1805721927 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1169243033 # num instructions producing a value +system.cpu.iew.wb_consumers 1689661119 # num instructions consuming a value +system.cpu.iew.wb_rate 1.146432 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.691999 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 258080144 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14629745 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1535892995 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.083430 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.009496 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14631277 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1535484809 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.083718 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.009601 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 955612705 62.22% 62.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 250634240 16.32% 78.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 110090472 7.17% 85.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 55300497 3.60% 89.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29246766 1.90% 91.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 34056030 2.22% 93.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 24731317 1.61% 95.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 18107101 1.18% 96.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 58113867 3.78% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 955186516 62.21% 62.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 250636789 16.32% 78.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 110101292 7.17% 85.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 55286350 3.60% 89.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29268667 1.91% 91.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 34069623 2.22% 93.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24728092 1.61% 95.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 18117164 1.18% 96.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 58090316 3.78% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1535892995 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1535484809 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563042 # Number of instructions committed system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -728,78 +727,78 @@ system.cpu.commit.op_class_0::FloatMemWrite 24 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction -system.cpu.commit.bw_lim_events 58113867 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3399860729 # The number of ROB reads -system.cpu.rob.rob_writes 3883658641 # The number of ROB writes -system.cpu.timesIdled 841 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 102322 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 58090316 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3399506472 # The number of ROB reads +system.cpu.rob.rob_writes 3883723576 # The number of ROB writes +system.cpu.timesIdled 829 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 102290 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563024 # Number of Instructions Simulated system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.020020 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.020020 # CPI: Total CPI of All Threads -system.cpu.ipc 0.980373 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.980373 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2175838440 # number of integer regfile reads -system.cpu.int_regfile_writes 1261579513 # number of integer regfile writes +system.cpu.cpi 1.019758 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.019758 # CPI: Total CPI of All Threads +system.cpu.ipc 0.980625 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.980625 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2175817673 # number of integer regfile reads +system.cpu.int_regfile_writes 1261583983 # number of integer regfile writes system.cpu.fp_regfile_reads 40 # number of floating regfile reads -system.cpu.fp_regfile_writes 51 # number of floating regfile writes -system.cpu.cc_regfile_reads 6965813253 # number of cc regfile reads -system.cpu.cc_regfile_writes 551861987 # number of cc regfile writes -system.cpu.misc_regfile_reads 675852638 # number of misc regfile reads +system.cpu.fp_regfile_writes 52 # number of floating regfile writes +system.cpu.cc_regfile_reads 6965793426 # number of cc regfile reads +system.cpu.cc_regfile_writes 551861251 # number of cc regfile writes +system.cpu.misc_regfile_reads 675850688 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 17003360 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.963277 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 638058665 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 17003872 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.524316 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 83293500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.963277 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999928 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999928 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 17003339 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.963435 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 638067140 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 17003851 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.524861 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 82999500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.963435 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999929 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999929 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 382 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 379 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1335696042 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1335696042 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 469342719 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 469342719 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 168715791 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 168715791 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1335713311 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1335713311 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 469350712 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 469350712 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 168716268 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 168716268 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 638058510 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 638058510 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 638058510 # number of overall hits -system.cpu.dcache.overall_hits::total 638058510 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 17417195 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 17417195 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3870256 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3870256 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 638066980 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 638066980 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 638066980 # number of overall hits +system.cpu.dcache.overall_hits::total 638066980 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 17417847 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 17417847 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3869779 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3869779 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 21287451 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21287451 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21287453 # number of overall misses -system.cpu.dcache.overall_misses::total 21287453 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 440618340000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 440618340000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 157333375444 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 157333375444 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 245500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 245500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 597951715444 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 597951715444 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 597951715444 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 597951715444 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 486759914 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 486759914 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 21287626 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21287626 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21287628 # number of overall misses +system.cpu.dcache.overall_misses::total 21287628 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 440481080000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 440481080000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 157197656848 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 157197656848 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 217500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 217500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 597678736848 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 597678736848 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 597678736848 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 597678736848 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 486768559 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 486768559 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) @@ -808,14 +807,14 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 659345961 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 659345961 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 659345963 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 659345963 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035782 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.035782 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022425 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.022425 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 659354606 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 659354606 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 659354608 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 659354608 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035783 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.035783 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022422 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.022422 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses @@ -824,56 +823,56 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.032286 system.cpu.dcache.demand_miss_rate::total 0.032286 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.032286 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.032286 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25297.893260 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25297.893260 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40651.929858 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 40651.929858 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 61375 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 61375 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28089.399499 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28089.399499 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28089.396859 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28089.396859 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21254267 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3791320 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 940376 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67438 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.601882 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 56.219342 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 17003360 # number of writebacks -system.cpu.dcache.writebacks::total 17003360 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3150878 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3150878 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1132695 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1132695 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25289.065864 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25289.065864 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40621.869323 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 40621.869323 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 54375 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 54375 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28076.345237 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28076.345237 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28076.342599 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28076.342599 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21218402 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3791861 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 939506 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67507 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.584637 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 56.169893 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 17003339 # number of writebacks +system.cpu.dcache.writebacks::total 17003339 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3151564 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3151564 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1132202 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1132202 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4283573 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4283573 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4283573 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4283573 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14266317 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 14266317 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737561 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2737561 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4283766 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4283766 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4283766 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4283766 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14266283 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 14266283 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737577 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2737577 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 17003878 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 17003878 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 17003879 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 17003879 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 354302060000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 354302060000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 121168074300 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 121168074300 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 17003860 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 17003860 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 17003861 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 17003861 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 354100253000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 354100253000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 121015069211 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 121015069211 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 75000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 75000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 475470134300 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 475470134300 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 475470209300 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 475470209300 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029309 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029309 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 475115322211 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 475115322211 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 475115397211 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 475115397211 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029308 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029308 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses @@ -882,401 +881,400 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025789 system.cpu.dcache.demand_mshr_miss_rate::total 0.025789 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.025789 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24834.865228 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24834.865228 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44261.323967 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44261.323967 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24820.778685 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24820.778685 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44205.174580 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44205.174580 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 75000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 75000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27962.452700 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27962.452700 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27962.455467 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27962.455467 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 589 # number of replacements -system.cpu.icache.tags.tagsinuse 445.623702 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 656963104 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1076 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 610560.505576 # Average number of references to valid blocks. +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27941.615740 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27941.615740 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27941.618507 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27941.618507 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 587 # number of replacements +system.cpu.icache.tags.tagsinuse 445.528749 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 656980742 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1074 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 611713.912477 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 445.623702 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.870359 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.870359 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 445.528749 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.870173 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.870173 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 487 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 442 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 443 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.951172 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1313930500 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1313930500 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 656963104 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 656963104 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 656963104 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 656963104 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 656963104 # number of overall hits -system.cpu.icache.overall_hits::total 656963104 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1608 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1608 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1608 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1608 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1608 # number of overall misses -system.cpu.icache.overall_misses::total 1608 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 127367486 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 127367486 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 127367486 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 127367486 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 127367486 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 127367486 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 656964712 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 656964712 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 656964712 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 656964712 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 656964712 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 656964712 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 1313965738 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1313965738 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 656980742 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 656980742 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 656980742 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 656980742 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 656980742 # number of overall hits +system.cpu.icache.overall_hits::total 656980742 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1590 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1590 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1590 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1590 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1590 # number of overall misses +system.cpu.icache.overall_misses::total 1590 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 127348986 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 127348986 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 127348986 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 127348986 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 127348986 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 127348986 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 656982332 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 656982332 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 656982332 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 656982332 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 656982332 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 656982332 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 79208.635572 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 79208.635572 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 79208.635572 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 79208.635572 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 79208.635572 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 79208.635572 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 21110 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 318 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 193 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80093.701887 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 80093.701887 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 80093.701887 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 80093.701887 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 80093.701887 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 80093.701887 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 20708 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 276 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 187 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 109.378238 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 35.333333 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 589 # number of writebacks -system.cpu.icache.writebacks::total 589 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 531 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 531 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 531 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 531 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 531 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 531 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1077 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1077 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1077 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1077 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1077 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1077 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 92273990 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 92273990 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 92273990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 92273990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 92273990 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 92273990 # number of overall MSHR miss cycles +system.cpu.icache.avg_blocked_cycles::no_mshrs 110.737968 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 30.666667 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 587 # number of writebacks +system.cpu.icache.writebacks::total 587 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 515 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 515 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 515 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 515 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 515 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 515 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1075 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1075 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1075 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1075 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1075 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1075 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 91881989 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 91881989 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 91881989 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 91881989 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 91881989 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 91881989 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 85676.870938 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 85676.870938 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 85676.870938 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 85676.870938 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 85676.870938 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 85676.870938 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 11610963 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 11639700 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 19388 # number of redundant prefetches already in prefetch queue +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 85471.617674 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 85471.617674 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 85471.617674 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 85471.617674 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 85471.617674 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 85471.617674 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 11608007 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 11635645 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 18478 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 4657940 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 4647528 # number of replacements -system.cpu.l2cache.tags.tagsinuse 15870.760193 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 13267468 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4663442 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.844995 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 4655443 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 4648753 # number of replacements +system.cpu.l2cache.tags.tagsinuse 15870.733376 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 13264824 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4664667 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.843681 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15649.753914 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 221.006278 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.955185 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.013489 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.968674 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 144 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15770 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 116 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 27 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 430 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4072 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 7121 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2569 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1578 # 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Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 221.297180 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.955166 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.013507 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.968673 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 130 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15784 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 6 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 105 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 19 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 423 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4048 # 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number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 237209473000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 84211500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 335344689000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 335428900500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 84211500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 335344689000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 84134366845 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 419563267345 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356978 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356978 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.952646 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.952646 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189920 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189920 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.952646 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216816 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.216863 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.952646 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216816 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356775 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356775 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.946047 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.946047 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.190062 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.190062 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.946047 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216903 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.216949 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.946047 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216903 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.287278 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70298.609693 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 70298.609693 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15214.285714 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15214.285714 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 100575.793669 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 100575.793669 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82436.647173 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82436.647173 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87633.448609 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87633.448609 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82436.647173 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 91064.167743 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 91061.767405 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82436.647173 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 91064.167743 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70298.609693 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85972.521147 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 34008905 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 17003965 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21224 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 200821 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 200820 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.287311 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70317.710271 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 70317.710271 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15200 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15200 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 100474.462434 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 100474.462434 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82803.834808 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82803.834808 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87483.716582 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87483.716582 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82803.834808 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 90923.968355 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90921.729885 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82803.834808 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 90923.968355 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70317.710271 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85875.879117 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 34008864 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 17003947 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21229 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 200156 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 200155 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 14267344 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 6459789 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 12178209 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 3013479 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 1493524 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFResp 11 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 7 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 7 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2737604 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2737604 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1077 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266268 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2742 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51011129 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 51013871 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106560 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176463552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2176570112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 6141063 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 104579840 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 23146008 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.009594 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.097477 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 14267297 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 6463501 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 12174811 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 3014367 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 1493474 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFResp 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 10 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 10 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2737628 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2737628 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1075 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266223 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2736 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51011077 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 51013813 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106304 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176461184 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2176567488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 6142243 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 104601728 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 23147163 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.009565 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.097331 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 22923954 99.04% 99.04% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 222053 0.96% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 22925769 99.04% 99.04% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 221393 0.96% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 23146008 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 34008401540 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 23147163 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 34008359033 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 4.3 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 16551 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 24049 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1614499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1612497 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 25505814993 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 25505785487 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 3.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 9333193 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 4668760 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 9335651 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 4669993 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 3708223 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1634049 # Transaction distribution -system.membus.trans_dist::CleanEvict 3013479 # Transaction distribution -system.membus.trans_dist::UpgradeReq 7 # Transaction distribution -system.membus.trans_dist::ReadExReq 977434 # Transaction distribution -system.membus.trans_dist::ReadExResp 977434 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3708224 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14018850 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14018850 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 404461184 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 404461184 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 3710005 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1634386 # Transaction distribution +system.membus.trans_dist::CleanEvict 3014367 # Transaction distribution +system.membus.trans_dist::UpgradeReq 10 # Transaction distribution +system.membus.trans_dist::ReadExReq 976882 # Transaction distribution +system.membus.trans_dist::ReadExResp 976882 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3710006 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14022538 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14022538 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 404561472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 404561472 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 4685665 # Request fanout histogram +system.membus.snoop_fanout::samples 4686898 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4685665 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 4686898 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 4685665 # Request fanout histogram -system.membus.reqLayer0.occupancy 17659262741 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 4686898 # Request fanout histogram +system.membus.reqLayer0.occupancy 17643111757 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 25448696800 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 25454576781 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 17a991711..5040af9e4 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.086155 # Number of seconds simulated -sim_ticks 86154694000 # Number of ticks simulated -final_tick 86154694000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.086149 # Number of seconds simulated +sim_ticks 86149358000 # Number of ticks simulated +final_tick 86149358000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 235949 # Simulator instruction rate (inst/s) -host_op_rate 248729 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 117978801 # Simulator tick rate (ticks/s) -host_mem_usage 272668 # Number of bytes of host memory used -host_seconds 730.26 # Real time elapsed on the host +host_inst_rate 240669 # Simulator instruction rate (inst/s) +host_op_rate 253706 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 120331720 # Simulator tick rate (ticks/s) +host_mem_usage 272336 # Number of bytes of host memory used +host_seconds 715.93 # Real time elapsed on the host sim_insts 172303022 # Number of instructions simulated sim_ops 181635954 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 652480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 193344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 71040 # Number of bytes read from this memory -system.physmem.bytes_read::total 916864 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 652480 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 652480 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 10195 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3021 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 1110 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14326 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 7573354 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2244149 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 824563 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10642067 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7573354 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7573354 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7573354 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2244149 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 824563 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10642067 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 14326 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 652096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 192896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 71744 # Number of bytes read from this memory +system.physmem.bytes_read::total 916736 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 652096 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 652096 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 10189 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3014 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 1121 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14324 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 7569366 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2239088 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 832786 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10641240 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7569366 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7569366 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7569366 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2239088 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 832786 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10641240 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 14324 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 14326 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 14324 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 916864 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 916736 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 916864 # Total read bytes from the system interface side +system.physmem.bytesReadSys 916736 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1380 # Per bank write bursts +system.physmem.perBankRdBursts::0 1375 # Per bank write bursts system.physmem.perBankRdBursts::1 498 # Per bank write bursts -system.physmem.perBankRdBursts::2 5094 # Per bank write bursts -system.physmem.perBankRdBursts::3 810 # Per bank write bursts +system.physmem.perBankRdBursts::2 5101 # Per bank write bursts +system.physmem.perBankRdBursts::3 808 # Per bank write bursts system.physmem.perBankRdBursts::4 2279 # Per bank write bursts system.physmem.perBankRdBursts::5 424 # Per bank write bursts system.physmem.perBankRdBursts::6 384 # Per bank write bursts system.physmem.perBankRdBursts::7 628 # Per bank write bursts system.physmem.perBankRdBursts::8 270 # Per bank write bursts system.physmem.perBankRdBursts::9 231 # Per bank write bursts -system.physmem.perBankRdBursts::10 355 # Per bank write bursts -system.physmem.perBankRdBursts::11 347 # Per bank write bursts -system.physmem.perBankRdBursts::12 322 # Per bank write bursts +system.physmem.perBankRdBursts::10 354 # Per bank write bursts +system.physmem.perBankRdBursts::11 348 # Per bank write bursts +system.physmem.perBankRdBursts::12 320 # Per bank write bursts system.physmem.perBankRdBursts::13 267 # Per bank write bursts system.physmem.perBankRdBursts::14 240 # Per bank write bursts system.physmem.perBankRdBursts::15 797 # Per bank write bursts @@ -80,14 +80,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 86154635500 # Total gap between requests +system.physmem.totGap 86149299500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 14326 # Read request sizes (log2) +system.physmem.readPktSize::6 14324 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -95,16 +95,16 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 12786 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1082 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 181 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 86 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 12783 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1071 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 85 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -191,26 +191,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 8486 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 107.983974 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 86.597492 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 122.302837 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 5884 69.34% 69.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 2105 24.81% 94.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 256 3.02% 97.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 62 0.73% 97.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 39 0.46% 98.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 37 0.44% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 16 0.19% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9 0.11% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 78 0.92% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 8486 # Bytes accessed per row activation -system.physmem.totQLat 1505073312 # Total ticks spent queuing -system.physmem.totMemAccLat 1773685812 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 71630000 # Total ticks spent in databus transfers -system.physmem.avgQLat 105058.87 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 8487 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 107.956168 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 86.535791 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 122.736079 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 5894 69.45% 69.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 2098 24.72% 94.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 256 3.02% 97.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 63 0.74% 97.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 36 0.42% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 32 0.38% 98.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 19 0.22% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 10 0.12% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 79 0.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 8487 # Bytes accessed per row activation +system.physmem.totQLat 1500750524 # Total ticks spent queuing +system.physmem.totMemAccLat 1769325524 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 71620000 # Total ticks spent in databus transfers +system.physmem.avgQLat 104771.75 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 123808.87 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 123521.75 # Average memory access latency per DRAM burst system.physmem.avgRdBW 10.64 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 10.64 # Average system read bandwidth in MiByte/s @@ -219,68 +219,68 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.08 # Data bus utilization in percentage system.physmem.busUtilRead 0.08 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 5836 # Number of row buffer hits during reads +system.physmem.readRowHits 5833 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.74 # Row buffer hit rate for reads +system.physmem.readRowHitRate 40.72 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 6013865.38 # Average gap between requests -system.physmem.pageHitRate 40.74 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 51536520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 27380925 # Energy for precharge commands per rank (pJ) +system.physmem.avgGap 6014332.55 # Average gap between requests +system.physmem.pageHitRate 40.72 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 51543660 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 27384720 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 82088580 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5189405520.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1121826120 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 276469440 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 12277996650 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 8345487360 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 9295531755 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 36669774810 # Total energy per rank (pJ) -system.physmem_0.averagePower 425.627121 # Core power per rank (mW) -system.physmem_0.totalIdleTime 82968376764 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 533443000 # Time in different power states -system.physmem_0.memoryStateTime::REF 2206916000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 34311542002 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 21733088112 # Time in different power states -system.physmem_0.memoryStateTime::ACT 444281236 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 26925423650 # Time in different power states +system.physmem_0.refreshEnergy 5186946960.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1121176890 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 276161760 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 12273342600 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 8346662400 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 9294814230 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 36662152740 # Total energy per rank (pJ) +system.physmem_0.averagePower 425.565010 # Core power per rank (mW) +system.physmem_0.totalIdleTime 82965211526 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 532687000 # Time in different power states +system.physmem_0.memoryStateTime::REF 2205840000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 34315599752 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 21736059604 # Time in different power states +system.physmem_0.memoryStateTime::ACT 443979474 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 26915192170 # Time in different power states system.physmem_1.actEnergy 9082080 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 4823445 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 20199060 # Energy for read commands per rank (pJ) +system.physmem_1.readEnergy 20184780 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 885081600.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 198834810 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 51009600 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 1986610170 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 1389476160 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 18829930140 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 23375329815 # Total energy per rank (pJ) -system.physmem_1.averagePower 271.318119 # Core power per rank (mW) -system.physmem_1.totalIdleTime 85585158757 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 101660000 # Time in different power states -system.physmem_1.memoryStateTime::REF 376638000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 77610163250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 3618418671 # Time in different power states -system.physmem_1.memoryStateTime::ACT 91210493 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 4356603586 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 85641138 # Number of BP lookups -system.cpu.branchPred.condPredicted 68185958 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5937589 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 39953535 # Number of BTB lookups -system.cpu.branchPred.BTBHits 38189781 # Number of BTB hits +system.physmem_1.refreshEnergy 883852320.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 198703710 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 50905920 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 1989700140 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 1383894720 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 18830063895 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 23371485780 # Total energy per rank (pJ) +system.physmem_1.averagePower 271.290305 # Core power per rank (mW) +system.physmem_1.totalIdleTime 85580460271 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 101384000 # Time in different power states +system.physmem_1.memoryStateTime::REF 376118000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 77613150500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 3603890386 # Time in different power states +system.physmem_1.memoryStateTime::ACT 91368979 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 4363446135 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 85639426 # Number of BP lookups +system.cpu.branchPred.condPredicted 68185953 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5937258 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 39949340 # Number of BTB lookups +system.cpu.branchPred.BTBHits 38185565 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.585487 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3685328 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 81910 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 681706 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 653811 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 27895 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 40302 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 95.584971 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3683095 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 81909 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 681696 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 653573 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 28123 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 40352 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -310,7 +310,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -340,7 +340,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -370,7 +370,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -401,97 +401,97 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 86154694000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 172309389 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 86149358000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 172298717 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5689865 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 347272234 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85641138 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42528920 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 158389740 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 11889123 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 4257 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 5689617 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 347266831 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85639426 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42522233 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 158380748 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11888463 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 4145 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingQuiesceStallCycles 80 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 4192 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 78352490 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 18126 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 170032695 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.137046 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.057606 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 4281 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 78346664 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 18062 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 170023102 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.137102 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.057569 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 18322538 10.78% 10.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30071394 17.69% 28.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31619936 18.60% 47.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 90018827 52.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 18318468 10.77% 10.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30068726 17.69% 28.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31619725 18.60% 47.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 90016183 52.94% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 170032695 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.497020 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.015399 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17554898 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 18106153 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 121828666 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6773205 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5769773 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11065170 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 189895 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 305047176 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27240886 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5769773 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37541623 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8963730 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 601187 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 108324902 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8831480 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 277455959 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13183896 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3097230 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 842604 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2610060 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 40707 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 26842 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 481461567 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1187957820 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 296507996 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3005110 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 170023102 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.497040 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.015493 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17554244 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 18101467 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 121824905 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6773054 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5769432 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11065775 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 189948 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 305038109 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27237354 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5769432 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37539679 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8956907 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 601126 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 108322423 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8833535 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 277447852 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13184486 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3097243 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 842563 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2612762 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 40533 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 26849 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 481448776 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1187920227 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 296497585 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3005089 # Number of floating rename lookups system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 188484638 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 188471847 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 23626 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23627 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13450862 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 33923289 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14424821 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2554501 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1823311 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 263831896 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 45982 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 214447255 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5189742 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 82241924 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 216953797 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 766 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 170032695 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.261212 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.018500 # Number of insts issued each cycle +system.cpu.rename.tempSerializingInsts 23625 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13449474 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 33921609 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14424624 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2552614 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1816807 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 263824183 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 45978 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 214443460 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5190288 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 82234207 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 216932052 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 762 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 170023102 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.261261 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.018489 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 53222567 31.30% 31.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 36044522 21.20% 52.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 65538005 38.54% 91.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 13630055 8.02% 99.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1551450 0.91% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 45818 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 278 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 53215331 31.30% 31.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 36043504 21.20% 52.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 65536118 38.55% 91.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13631246 8.02% 99.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1550810 0.91% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 45816 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 277 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 170032695 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 170023102 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35671912 66.13% 66.13% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 153261 0.28% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35671391 66.13% 66.13% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 153271 0.28% 66.41% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 66.41% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.41% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.41% # attempts to use FU when none available @@ -512,24 +512,24 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.41% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 66.41% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.41% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 1068 0.00% 66.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 1065 0.00% 66.42% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 35713 0.07% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 264 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 35712 0.07% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 263 0.00% 66.48% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 557 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 40113 0.07% 66.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 556 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 40135 0.07% 66.56% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.56% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 13911271 25.79% 92.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3849843 7.14% 99.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 142059 0.26% 99.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 136275 0.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 13909773 25.79% 92.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3850022 7.14% 99.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 142020 0.26% 99.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 136319 0.25% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 167013253 77.88% 77.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 919503 0.43% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 167011334 77.88% 77.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 919426 0.43% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.31% # Type of FU issued @@ -550,93 +550,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.31% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33015 0.02% 78.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 165181 0.08% 78.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 245720 0.11% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33015 0.02% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 165180 0.08% 78.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 245708 0.11% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 460387 0.21% 78.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 460349 0.21% 78.77% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 206623 0.10% 78.86% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.90% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 318 0.00% 78.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 31297547 14.59% 93.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13233764 6.17% 99.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 576685 0.27% 99.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 147618 0.07% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 31296412 14.59% 93.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13233182 6.17% 99.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 576648 0.27% 99.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 147624 0.07% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 214447255 # Type of FU issued -system.cpu.iq.rate 1.244548 # Inst issue rate -system.cpu.iq.fu_busy_cnt 53942541 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.251542 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 654066032 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 344116098 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 204293302 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3993456 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2010644 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1806352 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266215456 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2174340 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1590107 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 214443460 # Type of FU issued +system.cpu.iq.rate 1.244603 # Inst issue rate +system.cpu.iq.fu_busy_cnt 53940732 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.251538 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 654047721 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 344100630 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 204290427 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3993321 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2010682 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1806323 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266209914 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2174278 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1590245 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6027145 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7447 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7088 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1780187 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6025465 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7430 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7094 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1779990 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 25576 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 767 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 25605 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 790 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5769773 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5628686 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 175497 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 263897928 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 5769432 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5627104 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 174387 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 263890272 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 33923289 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14424821 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23574 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3848 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 168493 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7088 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3148569 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3247440 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6396009 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 207164807 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 30640004 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7282448 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 33921609 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14424624 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23570 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3854 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 167353 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 7094 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3148097 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3247402 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6395499 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 207161825 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 30639651 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7281635 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 20050 # number of nop insts executed -system.cpu.iew.exec_refs 43787631 # number of memory reference insts executed -system.cpu.iew.exec_branches 44861497 # Number of branches executed -system.cpu.iew.exec_stores 13147627 # Number of stores executed -system.cpu.iew.exec_rate 1.202284 # Inst execution rate -system.cpu.iew.wb_sent 206408899 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 206099654 # cumulative count of insts written-back -system.cpu.iew.wb_producers 129383753 # num instructions producing a value -system.cpu.iew.wb_consumers 221651913 # num instructions consuming a value -system.cpu.iew.wb_rate 1.196102 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.583725 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 68705367 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 20111 # number of nop insts executed +system.cpu.iew.exec_refs 43786600 # number of memory reference insts executed +system.cpu.iew.exec_branches 44861358 # Number of branches executed +system.cpu.iew.exec_stores 13146949 # Number of stores executed +system.cpu.iew.exec_rate 1.202341 # Inst execution rate +system.cpu.iew.wb_sent 206406222 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 206096750 # cumulative count of insts written-back +system.cpu.iew.wb_producers 129381204 # num instructions producing a value +system.cpu.iew.wb_consumers 221650091 # num instructions consuming a value +system.cpu.iew.wb_rate 1.196160 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.583718 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 68697467 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5762801 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158729167 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.144404 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.650562 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5762459 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158721175 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.144462 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.650716 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 74124112 46.70% 46.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 41154034 25.93% 72.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 22561648 14.21% 86.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9505511 5.99% 92.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3552884 2.24% 95.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2129952 1.34% 96.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1300201 0.82% 97.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1012623 0.64% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3388202 2.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 74120611 46.70% 46.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 41150811 25.93% 72.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 22560961 14.21% 86.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9504738 5.99% 92.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3552513 2.24% 95.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2129219 1.34% 96.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1299436 0.82% 97.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1012456 0.64% 97.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3390430 2.14% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158729167 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 158721175 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317410 # Number of instructions committed system.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -686,33 +686,33 @@ system.cpu.commit.op_class_0::FloatMemWrite 146246 0.08% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 181650342 # Class of committed instruction -system.cpu.commit.bw_lim_events 3388202 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 405691473 # The number of ROB reads -system.cpu.rob.rob_writes 512028923 # The number of ROB writes -system.cpu.timesIdled 10004 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 2276694 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3390430 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 405673353 # The number of ROB reads +system.cpu.rob.rob_writes 512011515 # The number of ROB writes +system.cpu.timesIdled 9971 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 2275615 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303022 # Number of Instructions Simulated system.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.000037 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.000037 # CPI: Total CPI of All Threads -system.cpu.ipc 0.999963 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.999963 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 218765999 # number of integer regfile reads -system.cpu.int_regfile_writes 114196362 # number of integer regfile writes -system.cpu.fp_regfile_reads 2903942 # number of floating regfile reads -system.cpu.fp_regfile_writes 2441736 # number of floating regfile writes -system.cpu.cc_regfile_reads 708332294 # number of cc regfile reads -system.cpu.cc_regfile_writes 229516818 # number of cc regfile writes -system.cpu.misc_regfile_reads 57457287 # number of misc regfile reads +system.cpu.cpi 0.999975 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.999975 # CPI: Total CPI of All Threads +system.cpu.ipc 1.000025 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.000025 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 218762027 # number of integer regfile reads +system.cpu.int_regfile_writes 114194444 # number of integer regfile writes +system.cpu.fp_regfile_reads 2903946 # number of floating regfile reads +system.cpu.fp_regfile_writes 2441681 # number of floating regfile writes +system.cpu.cc_regfile_reads 708323214 # number of cc regfile reads +system.cpu.cc_regfile_writes 229513810 # number of cc regfile writes +system.cpu.misc_regfile_reads 57456345 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 72598 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.401142 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 41046057 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 73110 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 561.428765 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 556160500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.401142 # Average occupied blocks per requestor +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 72586 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.401008 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 41045518 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 73098 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 561.513557 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 555248500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.401008 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.998830 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.998830 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -722,347 +722,347 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 230 system.cpu.dcache.tags.age_task_id_blocks_1024::3 44 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 82390572 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 82390572 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 28659846 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28659846 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12341293 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12341293 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 364 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 364 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 82389396 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 82389396 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 28659277 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28659277 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12341322 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12341322 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 365 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 365 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22147 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22147 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41001139 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41001139 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41001503 # number of overall hits -system.cpu.dcache.overall_hits::total 41001503 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89304 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89304 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 22994 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 22994 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 41000599 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41000599 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41000964 # number of overall hits +system.cpu.dcache.overall_hits::total 41000964 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89290 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89290 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 22965 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22965 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 116 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 116 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 260 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 260 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 112298 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 112298 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 112414 # number of overall misses -system.cpu.dcache.overall_misses::total 112414 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1992894500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1992894500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 247642499 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 247642499 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2317500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 2317500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 2240536999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 2240536999 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 2240536999 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 2240536999 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28749150 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28749150 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 112255 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 112255 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 112371 # number of overall misses +system.cpu.dcache.overall_misses::total 112371 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1989594500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1989594500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 244666499 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 244666499 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2316500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 2316500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 2234260999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 2234260999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 2234260999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 2234260999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28748567 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28748567 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 480 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 480 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 481 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 481 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41113437 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41113437 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41113917 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41113917 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 41112854 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41112854 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41113335 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41113335 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003106 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003106 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001860 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001860 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.241667 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.241667 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001857 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001857 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.241164 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.241164 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011604 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011604 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002731 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002731 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002734 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002734 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22315.848114 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22315.848114 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10769.874706 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10769.874706 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8913.461538 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8913.461538 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19951.708837 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19951.708837 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19931.120670 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19931.120670 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.002730 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002730 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002733 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002733 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22282.388845 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22282.388845 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10653.886305 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10653.886305 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8909.615385 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8909.615385 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19903.443045 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19903.443045 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19882.896824 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19882.896824 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 180 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 11146 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 11152 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 867 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 864 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 90 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 12.855825 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 72598 # number of writebacks -system.cpu.dcache.writebacks::total 72598 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24877 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 24877 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14424 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 14424 # number of WriteReq MSHR hits +system.cpu.dcache.avg_blocked_cycles::no_targets 12.907407 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 72586 # number of writebacks +system.cpu.dcache.writebacks::total 72586 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24872 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 24872 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14398 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 14398 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 260 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 260 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 39301 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 39301 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 39301 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 39301 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64427 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64427 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8570 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 8570 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 39270 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 39270 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 39270 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 39270 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64418 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 64418 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8567 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 8567 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 113 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 113 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 72997 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 72997 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 73110 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 73110 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1062486000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1062486000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 88387499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 88387499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 72985 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 72985 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 73098 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 73098 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1060539500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1060539500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 87795999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 87795999 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 969000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 969000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1150873499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 1150873499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1151842499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 1151842499 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1148335499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 1148335499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1149304499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 1149304499 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002241 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002241 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000693 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000693 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.235417 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.235417 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001776 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001776 # mshr miss rate for demand accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.234927 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.234927 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001775 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001775 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001778 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001778 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16491.315753 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16491.315753 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10313.593816 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10313.593816 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16463.403086 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16463.403086 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10248.161433 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10248.161433 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8575.221239 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8575.221239 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15766.038317 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15766.038317 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15754.924073 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15754.924073 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 53656 # number of replacements -system.cpu.icache.tags.tagsinuse 510.578461 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 78294727 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 54168 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1445.405535 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 85384212500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.578461 # Average occupied blocks per requestor +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15733.856258 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15733.856258 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15722.789940 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15722.789940 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 53582 # number of replacements +system.cpu.icache.tags.tagsinuse 510.578561 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78288973 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 54094 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1447.276463 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 85378568500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.578561 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.997224 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.997224 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 277 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 49 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 156759076 # Number of tag accesses -system.cpu.icache.tags.data_accesses 156759076 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 78294727 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78294727 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78294727 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78294727 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78294727 # number of overall hits -system.cpu.icache.overall_hits::total 78294727 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 57727 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 57727 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 57727 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 57727 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 57727 # number of overall misses -system.cpu.icache.overall_misses::total 57727 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2248583426 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2248583426 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2248583426 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2248583426 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2248583426 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2248583426 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78352454 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78352454 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78352454 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78352454 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78352454 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78352454 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000737 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000737 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000737 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000737 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000737 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000737 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38952.022901 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 38952.022901 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 38952.022901 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 38952.022901 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 38952.022901 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 38952.022901 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 93736 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 156747350 # Number of tag accesses +system.cpu.icache.tags.data_accesses 156747350 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 78288973 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 78288973 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 78288973 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 78288973 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 78288973 # number of overall hits +system.cpu.icache.overall_hits::total 78288973 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 57655 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 57655 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 57655 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 57655 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 57655 # number of overall misses +system.cpu.icache.overall_misses::total 57655 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2247853926 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2247853926 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2247853926 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2247853926 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2247853926 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2247853926 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 78346628 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 78346628 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 78346628 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 78346628 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 78346628 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 78346628 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000736 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000736 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000736 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000736 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000736 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000736 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38988.013633 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 38988.013633 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 38988.013633 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 38988.013633 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 38988.013633 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 38988.013633 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 94468 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 55 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3241 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3203 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.921938 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 29.493600 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 27.500000 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 53656 # number of writebacks -system.cpu.icache.writebacks::total 53656 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3558 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3558 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3558 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3558 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3558 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3558 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54169 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 54169 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 54169 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 54169 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 54169 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 54169 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2054126952 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2054126952 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2054126952 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2054126952 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2054126952 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2054126952 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000691 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000691 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000691 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37920.710222 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37920.710222 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37920.710222 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37920.710222 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37920.710222 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37920.710222 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 9281 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 9281 # number of prefetch candidates identified +system.cpu.icache.writebacks::writebacks 53582 # number of writebacks +system.cpu.icache.writebacks::total 53582 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3560 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3560 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3560 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3560 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3560 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3560 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54095 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 54095 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 54095 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 54095 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 54095 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 54095 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2052751452 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2052751452 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2052751452 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2052751452 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2052751452 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2052751452 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000690 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000690 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000690 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000690 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000690 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000690 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37947.156891 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37947.156891 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37947.156891 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 37947.156891 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37947.156891 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 37947.156891 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 9257 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 9257 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 1351 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.pfSpanPage 1327 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 1796.196657 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 99029 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2833 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 34.955524 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 1809.107747 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 98955 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2836 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 34.892454 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1727.103732 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 69.092925 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 1727.095683 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 82.012064 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.105414 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004217 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.109631 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 127 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 2706 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.005006 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.110419 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 131 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 2705 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 19 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 48 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 60 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 46 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 66 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 283 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1127 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 199 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 198 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 958 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.007751 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.165161 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4005715 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4005715 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 64715 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 64715 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 51058 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 51058 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 8400 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 8400 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 43969 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 43969 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 61680 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 61680 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 43969 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 70080 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 114049 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 43969 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 70080 # number of overall hits -system.cpu.l2cache.overall_hits::total 114049 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 236 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 236 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10200 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 10200 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2794 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 2794 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 10200 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3030 # 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mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043202 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.188354 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.041232 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.103803 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.188354 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.041232 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.119965 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 48423.580614 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 48423.580614 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82655.319149 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82655.319149 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 161793.673369 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 161793.673369 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 194081.658291 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 194081.658291 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 161793.673369 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185413.935783 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167192.947942 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 161793.673369 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185413.935783 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 48423.580614 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 151223.761281 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 253533 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 126274 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10481 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 943 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 942 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.119904 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 47911.933105 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 47911.933105 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81969.432314 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81969.432314 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 161810.236530 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 161810.236530 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 193500.179533 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 193500.179533 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 161810.236530 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185026.211015 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167110.012876 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 161810.236530 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185026.211015 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 47911.933105 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 151103.346600 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 253361 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 126188 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10476 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 927 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 926 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 118642 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 64715 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 61539 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 2391 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 8636 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 8636 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 54169 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 64474 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 161993 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218818 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 380811 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6900736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9325312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 16226048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2391 # Total snoops (count) +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 118558 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 64701 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 61467 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 2398 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 8634 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 8634 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 54095 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 64464 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 161771 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218782 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 380553 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6891264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9323776 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 16215040 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2398 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 129670 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.088263 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.283705 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 129591 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.088154 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.283547 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 118226 91.17% 91.17% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 11443 8.82% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 118168 91.19% 91.19% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 11422 8.81% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 129670 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 253020500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 129591 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 252848500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 81260982 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 81149483 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 109669990 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 109651491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 14326 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 10488 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 14324 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 10483 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 14090 # Transaction distribution -system.membus.trans_dist::ReadExReq 235 # Transaction distribution -system.membus.trans_dist::ReadExResp 235 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 14091 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 28651 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28651 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 916800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 916800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 14094 # Transaction distribution +system.membus.trans_dist::ReadExReq 229 # Transaction distribution +system.membus.trans_dist::ReadExResp 229 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 14095 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 28647 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28647 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 916672 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 916672 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 14326 # Request fanout histogram +system.membus.snoop_fanout::samples 14324 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 14326 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 14324 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 14326 # Request fanout histogram -system.membus.reqLayer0.occupancy 18054137 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 14324 # Request fanout histogram +system.membus.reqLayer0.occupancy 18004660 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 77252283 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 77243027 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index ed017dd04..4554501a1 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,63 +1,63 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.103189 # Number of seconds simulated -sim_ticks 103189362000 # Number of ticks simulated -final_tick 103189362000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.103324 # Number of seconds simulated +sim_ticks 103323995500 # Number of ticks simulated +final_tick 103323995500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 113263 # Simulator instruction rate (inst/s) -host_op_rate 189839 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 88494148 # Simulator tick rate (ticks/s) -host_mem_usage 308956 # Number of bytes of host memory used -host_seconds 1166.06 # Real time elapsed on the host +host_inst_rate 113414 # Simulator instruction rate (inst/s) +host_op_rate 190092 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 88727502 # Simulator tick rate (ticks/s) +host_mem_usage 308112 # Number of bytes of host memory used +host_seconds 1164.51 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 232704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 130112 # Number of bytes read from this memory -system.physmem.bytes_read::total 362816 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 232704 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 232704 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3636 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2033 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5669 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2255116 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1260905 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3516021 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2255116 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2255116 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2255116 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1260905 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3516021 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5669 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 232832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 130880 # Number of bytes read from this memory +system.physmem.bytes_read::total 363712 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 232832 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 232832 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3638 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2045 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5683 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2253417 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1266695 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3520112 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2253417 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2253417 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2253417 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1266695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3520112 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5683 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5669 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5683 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 362816 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 363712 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 362816 # Total read bytes from the system interface side +system.physmem.bytesReadSys 363712 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 309 # Per bank write bursts -system.physmem.perBankRdBursts::1 384 # Per bank write bursts -system.physmem.perBankRdBursts::2 476 # Per bank write bursts -system.physmem.perBankRdBursts::3 363 # Per bank write bursts -system.physmem.perBankRdBursts::4 357 # Per bank write bursts -system.physmem.perBankRdBursts::5 335 # Per bank write bursts -system.physmem.perBankRdBursts::6 419 # Per bank write bursts -system.physmem.perBankRdBursts::7 395 # Per bank write bursts -system.physmem.perBankRdBursts::8 387 # Per bank write bursts +system.physmem.perBankRdBursts::0 307 # Per bank write bursts +system.physmem.perBankRdBursts::1 383 # Per bank write bursts +system.physmem.perBankRdBursts::2 475 # Per bank write bursts +system.physmem.perBankRdBursts::3 366 # Per bank write bursts +system.physmem.perBankRdBursts::4 364 # Per bank write bursts +system.physmem.perBankRdBursts::5 336 # Per bank write bursts +system.physmem.perBankRdBursts::6 422 # Per bank write bursts +system.physmem.perBankRdBursts::7 392 # Per bank write bursts +system.physmem.perBankRdBursts::8 390 # Per bank write bursts system.physmem.perBankRdBursts::9 296 # Per bank write bursts -system.physmem.perBankRdBursts::10 260 # Per bank write bursts -system.physmem.perBankRdBursts::11 268 # Per bank write bursts -system.physmem.perBankRdBursts::12 228 # Per bank write bursts -system.physmem.perBankRdBursts::13 486 # Per bank write bursts -system.physmem.perBankRdBursts::14 420 # Per bank write bursts -system.physmem.perBankRdBursts::15 286 # Per bank write bursts +system.physmem.perBankRdBursts::10 255 # Per bank write bursts +system.physmem.perBankRdBursts::11 273 # Per bank write bursts +system.physmem.perBankRdBursts::12 229 # Per bank write bursts +system.physmem.perBankRdBursts::13 485 # Per bank write bursts +system.physmem.perBankRdBursts::14 425 # Per bank write bursts +system.physmem.perBankRdBursts::15 285 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 103189107000 # Total gap between requests +system.physmem.totGap 103323737000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5669 # Read request sizes (log2) +system.physmem.readPktSize::6 5683 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,10 +91,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4455 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 978 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 200 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4460 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 973 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 211 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 30 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1243 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 291.012068 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 164.006967 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 325.689818 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 565 45.45% 45.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 237 19.07% 64.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 95 7.64% 72.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 65 5.23% 77.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 45 3.62% 81.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 57 4.59% 85.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 29 2.33% 87.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 21 1.69% 89.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 129 10.38% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1243 # Bytes accessed per row activation -system.physmem.totQLat 180648250 # Total ticks spent queuing -system.physmem.totMemAccLat 286942000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 28345000 # Total ticks spent in databus transfers -system.physmem.avgQLat 31865.98 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1258 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 287.745628 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 162.611559 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 323.712964 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 571 45.39% 45.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 250 19.87% 65.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 94 7.47% 72.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 65 5.17% 77.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 43 3.42% 81.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 57 4.53% 85.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 29 2.31% 88.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 22 1.75% 89.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 127 10.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1258 # Bytes accessed per row activation +system.physmem.totQLat 187208250 # Total ticks spent queuing +system.physmem.totMemAccLat 293764500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 28415000 # Total ticks spent in databus transfers +system.physmem.avgQLat 32941.80 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 50615.98 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 51691.80 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.52 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s @@ -215,311 +215,311 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4421 # Number of row buffer hits during reads +system.physmem.readRowHits 4417 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.99 # Row buffer hit rate for reads +system.physmem.readRowHitRate 77.72 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 18202347.33 # Average gap between requests -system.physmem.pageHitRate 77.99 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5333580 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2823480 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 21691320 # Energy for read commands per rank (pJ) +system.physmem.avgGap 18181196.02 # Average gap between requests +system.physmem.pageHitRate 77.72 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5404980 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2853840 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 21741300 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 286422240.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 93806610 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 15765120 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 717579270 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 394813440 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 24141432120 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 25679671980 # Total energy per rank (pJ) -system.physmem_0.averagePower 248.859682 # Core power per rank (mW) -system.physmem_0.totalIdleTime 102941166250 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 30119500 # Time in different power states -system.physmem_0.memoryStateTime::REF 121808000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 100340787250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 1028168000 # Time in different power states -system.physmem_0.memoryStateTime::ACT 94814000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 1573665250 # Time in different power states -system.physmem_1.actEnergy 3577140 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1893705 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 18785340 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 298715040.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 95918460 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 16609440 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 744016440 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 410144160 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 24152474700 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 25747878360 # Total energy per rank (pJ) +system.physmem_0.averagePower 249.195533 # Core power per rank (mW) +system.physmem_0.totalIdleTime 103070096750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 32003500 # Time in different power states +system.physmem_0.memoryStateTime::REF 127050000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 100370697500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 1068078250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 94522250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 1631644000 # Time in different power states +system.physmem_1.actEnergy 3634260 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1920270 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 18835320 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 224343600.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 72770760 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 12467520 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 571365720 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 300199680 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 24277951200 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 25483354665 # Total energy per rank (pJ) -system.physmem_1.averagePower 246.957187 # Core power per rank (mW) -system.physmem_1.totalIdleTime 102997073250 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 23820000 # Time in different power states -system.physmem_1.memoryStateTime::REF 95422000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 100962546500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 781772000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 72828000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 1252973500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 40834752 # Number of BP lookups -system.cpu.branchPred.condPredicted 40834752 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6720926 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 35301077 # Number of BTB lookups +system.physmem_1.refreshEnergy 228031440.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 73672500 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 12688320 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 586536840 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 299079840 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 24303470280 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 25527869070 # Total energy per rank (pJ) +system.physmem_1.averagePower 247.066219 # Core power per rank (mW) +system.physmem_1.totalIdleTime 103129135750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 24348000 # Time in different power states +system.physmem_1.memoryStateTime::REF 96994000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 101064274500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 778849000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 73295500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 1286234500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 40855234 # Number of BP lookups +system.cpu.branchPred.condPredicted 40855234 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6727710 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 35293159 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3198104 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 606453 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 35301077 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 9875363 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 25425714 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 5011557 # Number of mispredicted indirect branches. +system.cpu.branchPred.usedRAS 3199678 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 605841 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 35293159 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 9878902 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 25414257 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 5019418 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 103189362000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 206378725 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 103323995500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 206647992 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 46270336 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 419359791 # Number of instructions fetch has processed -system.cpu.fetch.Branches 40834752 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13073467 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 152339601 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14895691 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 89 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 5905 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 73704 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 808 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 184 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 41191275 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1518616 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 206138472 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.415591 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.660484 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 46314104 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 419677545 # Number of instructions fetch has processed +system.cpu.fetch.Branches 40855234 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13078580 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 152558577 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14911731 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 146 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 6162 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 75545 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 535 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 173 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 41227932 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1521125 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 10 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 206411107 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.413574 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.660203 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 99063302 48.06% 48.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5137465 2.49% 50.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5366260 2.60% 53.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5330020 2.59% 55.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 6010905 2.92% 58.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5824389 2.83% 61.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5722044 2.78% 64.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4745811 2.30% 66.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 68938276 33.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 99253613 48.09% 48.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5140686 2.49% 50.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5371591 2.60% 53.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5329252 2.58% 55.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 6011005 2.91% 58.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5851603 2.83% 61.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5726027 2.77% 64.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4748810 2.30% 66.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 68978520 33.42% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 206138472 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.197863 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.031991 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32237214 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 86447407 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 62317142 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 17688864 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 7447845 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 590237823 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 7447845 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 42013779 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 46504501 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 31211 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 68811152 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 41329984 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 551593859 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1410 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 36393589 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4822156 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 169929 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 628796373 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1484193525 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 973498992 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 15084169 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 206411107 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.197704 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.030881 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32267820 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 86650194 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 62332865 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 17704363 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 7455865 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 590435256 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 7455865 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 42053837 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 46607662 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 29929 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 68827187 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 41436627 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 551754102 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1587 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 36503796 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4817365 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 169314 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 629088770 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1485013522 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 974082903 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 15054868 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 369366923 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2443 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2459 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 89351866 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 128676829 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 45848779 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 77202780 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 25186397 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 489944627 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 61663 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 338268196 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1105632 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 268642906 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 525336348 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 60418 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 206138472 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.640976 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.805234 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 369659320 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2323 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2340 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 89508181 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 128738720 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 45872059 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 77414851 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 25246681 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 490126112 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 61893 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 338153574 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1099180 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 268824621 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 526308720 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 60648 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 206411107 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.638253 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.802953 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 73134407 35.48% 35.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 46607709 22.61% 58.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 32815647 15.92% 74.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20883524 10.13% 84.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 15044203 7.30% 91.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8407546 4.08% 95.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5216740 2.53% 98.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2365929 1.15% 99.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1662767 0.81% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 73313522 35.52% 35.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 46679908 22.62% 58.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 32876430 15.93% 74.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20896006 10.12% 84.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 15048824 7.29% 91.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8392050 4.07% 95.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5201413 2.52% 98.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2354868 1.14% 99.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1648086 0.80% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 206138472 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 206411107 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 759085 19.25% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.25% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2706167 68.61% 87.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 429953 10.90% 98.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 45275 1.15% 99.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 3569 0.09% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 756912 19.27% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2690839 68.51% 87.78% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 431049 10.97% 98.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 45501 1.16% 99.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 3340 0.09% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1211760 0.36% 0.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 216459489 63.99% 64.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 800418 0.24% 64.59% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7047773 2.08% 66.67% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1809637 0.53% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 82580981 24.41% 91.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 26493050 7.83% 99.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 1734957 0.51% 99.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 130131 0.04% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1211791 0.36% 0.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 216412325 64.00% 64.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 800256 0.24% 64.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7047583 2.08% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1802667 0.53% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 82552665 24.41% 91.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 26471074 7.83% 99.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 1726255 0.51% 99.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 128958 0.04% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 338268196 # Type of FU issued -system.cpu.iq.rate 1.639065 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3944049 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011660 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 879529534 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 744046350 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 315909602 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 8195011 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 15431147 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 3556535 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 336881361 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 4119124 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18155877 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 338153574 # Type of FU issued +system.cpu.iq.rate 1.636375 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3927641 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011615 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 879585731 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 744431622 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 315835107 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 8159345 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 15410519 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 3544176 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 336768258 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 4101166 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18155454 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 72027242 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 72089133 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 55091 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 864575 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 25333062 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 866955 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 25356342 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 50542 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 27 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 50448 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 55 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 7447845 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 35704467 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 582987 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 490006290 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1248239 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 128676829 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 45848779 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 22549 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 539423 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 38394 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 864575 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1296720 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 6850218 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8146938 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 326347367 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 80684613 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 11920829 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 7455865 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 35715167 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 589866 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 490188005 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1248811 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 128738720 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 45872059 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 22561 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 546009 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 38338 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 866955 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1295323 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 6857589 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8152912 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 326241588 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 80652390 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 11911986 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 106316260 # number of memory reference insts executed -system.cpu.iew.exec_branches 18920718 # Number of branches executed -system.cpu.iew.exec_stores 25631647 # Number of stores executed -system.cpu.iew.exec_rate 1.581303 # Inst execution rate -system.cpu.iew.wb_sent 322480012 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 319466137 # cumulative count of insts written-back -system.cpu.iew.wb_producers 256417161 # num instructions producing a value -system.cpu.iew.wb_consumers 435540007 # num instructions consuming a value -system.cpu.iew.wb_rate 1.547961 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.588734 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 268667644 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 106269865 # number of memory reference insts executed +system.cpu.iew.exec_branches 18918443 # Number of branches executed +system.cpu.iew.exec_stores 25617475 # Number of stores executed +system.cpu.iew.exec_rate 1.578731 # Inst execution rate +system.cpu.iew.wb_sent 322387752 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 319379283 # cumulative count of insts written-back +system.cpu.iew.wb_producers 256328359 # num instructions producing a value +system.cpu.iew.wb_consumers 435429845 # num instructions consuming a value +system.cpu.iew.wb_rate 1.545523 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.588679 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 268850223 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6725958 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 163655626 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.352617 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.935975 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6732902 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 163914906 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.350477 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.932475 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 67077696 40.99% 40.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 54856110 33.52% 74.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13235317 8.09% 82.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 10672053 6.52% 89.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 5439540 3.32% 92.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 3134329 1.92% 94.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1088236 0.66% 95.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1157500 0.71% 95.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6994845 4.27% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 67189595 40.99% 40.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 54970007 33.54% 74.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13274329 8.10% 82.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 10696589 6.53% 89.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5450081 3.32% 92.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3128441 1.91% 94.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1086544 0.66% 95.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1161401 0.71% 95.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6957919 4.24% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 163655626 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 163914906 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -569,469 +569,469 @@ system.cpu.commit.op_class_0::FloatMemWrite 105487 0.05% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction -system.cpu.commit.bw_lim_events 6994845 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 646691809 # The number of ROB reads -system.cpu.rob.rob_writes 1022946396 # The number of ROB writes -system.cpu.timesIdled 2819 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 240253 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 6957919 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 647170594 # The number of ROB reads +system.cpu.rob.rob_writes 1023323556 # The number of ROB writes +system.cpu.timesIdled 2853 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 236885 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.562632 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.562632 # CPI: Total CPI of All Threads -system.cpu.ipc 0.639946 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.639946 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 524499390 # number of integer regfile reads -system.cpu.int_regfile_writes 288922915 # number of integer regfile writes -system.cpu.fp_regfile_reads 4524370 # number of floating regfile reads -system.cpu.fp_regfile_writes 3323309 # number of floating regfile writes -system.cpu.cc_regfile_reads 107020933 # number of cc regfile reads -system.cpu.cc_regfile_writes 65779043 # number of cc regfile writes -system.cpu.misc_regfile_reads 176790948 # number of misc regfile reads +system.cpu.cpi 1.564671 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.564671 # CPI: Total CPI of All Threads +system.cpu.ipc 0.639112 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.639112 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 524350393 # number of integer regfile reads +system.cpu.int_regfile_writes 288862618 # number of integer regfile writes +system.cpu.fp_regfile_reads 4510095 # number of floating regfile reads +system.cpu.fp_regfile_writes 3309705 # number of floating regfile writes +system.cpu.cc_regfile_reads 106995415 # number of cc regfile reads +system.cpu.cc_regfile_writes 65768687 # number of cc regfile writes +system.cpu.misc_regfile_reads 176729824 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 81 # number of replacements -system.cpu.dcache.tags.tagsinuse 1508.634180 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 82760913 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2105 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 39316.348219 # Average number of references to valid blocks. +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 82 # number of replacements +system.cpu.dcache.tags.tagsinuse 1514.501359 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 82730891 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2127 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 38895.576399 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1508.634180 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.368319 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.368319 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2024 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1514.501359 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.369751 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.369751 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2045 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 423 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1459 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.494141 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 165529197 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 165529197 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 62246604 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 62246604 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513664 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513664 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 82760268 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 82760268 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 82760268 # number of overall hits -system.cpu.dcache.overall_hits::total 82760268 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1211 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1211 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2067 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2067 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3278 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3278 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3278 # number of overall misses -system.cpu.dcache.overall_misses::total 3278 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 109883500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 109883500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 137432000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 137432000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 247315500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 247315500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 247315500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 247315500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 62247815 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 62247815 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.age_task_id_blocks_1024::2 111 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 418 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1470 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.499268 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 165469279 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 165469279 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 62216578 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 62216578 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513684 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513684 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 82730262 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 82730262 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 82730262 # number of overall hits +system.cpu.dcache.overall_hits::total 82730262 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1267 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1267 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2047 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2047 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3314 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3314 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3314 # number of overall misses +system.cpu.dcache.overall_misses::total 3314 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 112642500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 112642500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 136500000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 136500000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 249142500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 249142500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 249142500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 249142500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 62217845 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 62217845 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 82763546 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 82763546 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 82763546 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 82763546 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000101 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000101 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 82733576 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 82733576 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 82733576 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 82733576 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000100 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000100 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000040 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000040 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000040 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000040 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 90737.819983 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 90737.819983 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66488.630866 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66488.630866 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 75447.071385 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 75447.071385 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 75447.071385 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 75447.071385 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 307 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 88904.893449 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 88904.893449 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66682.950660 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66682.950660 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 75178.786964 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 75178.786964 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 75178.786964 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 75178.786964 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 331 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 143 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 76.750000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 82.750000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 71.500000 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 16 # number of writebacks -system.cpu.dcache.writebacks::total 16 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 626 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 626 # number of ReadReq MSHR hits +system.cpu.dcache.writebacks::writebacks 17 # number of writebacks +system.cpu.dcache.writebacks::total 17 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 658 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 658 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 6 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 632 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 632 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 632 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 632 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 585 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 585 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2061 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2061 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2646 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2646 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2646 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2646 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 67088500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 67088500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 134984000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 134984000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 202072500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 202072500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 202072500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 202072500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000100 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000100 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 664 # 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average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65689.367957 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65689.367957 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77249.433962 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77249.433962 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77249.433962 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77249.433962 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 6640 # number of replacements +system.cpu.icache.tags.tagsinuse 1671.571610 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 41214631 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8628 # 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Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 841 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 142 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 742 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 860 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 163 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 713 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.970703 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 82391597 # Number of tag accesses -system.cpu.icache.tags.data_accesses 82391597 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 41178058 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 41178058 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 41178058 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 41178058 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 41178058 # number of overall hits -system.cpu.icache.overall_hits::total 41178058 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13213 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 13213 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 13213 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13213 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13213 # number of overall misses -system.cpu.icache.overall_misses::total 13213 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 660957500 # 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number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 62.833333 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 842 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 6530 # number of writebacks -system.cpu.icache.writebacks::total 6530 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4157 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4157 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4157 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4157 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4157 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4157 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9056 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 9056 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 9056 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 9056 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 9056 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 9056 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 451350000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 451350000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 451350000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 451350000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 451350000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 451350000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000220 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000220 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000220 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000220 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000220 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000220 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49839.885159 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49839.885159 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49839.885159 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 49839.885159 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49839.885159 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 49839.885159 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states +system.cpu.icache.avg_blocked_cycles::no_mshrs 63.125000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 107 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 6640 # number of writebacks +system.cpu.icache.writebacks::total 6640 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4152 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4152 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4152 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4152 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4152 # 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number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1515 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1515 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3636 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3636 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 518 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 518 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3636 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2033 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5669 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 170728500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 519892000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 349163500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 170728500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 519892000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995401 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995401 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.427111 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.427111 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.888508 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.888508 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.427111 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.965796 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.533905 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.427111 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.965796 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.533905 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73004.950495 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73004.950495 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 96029.565457 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 96029.565457 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 116073.359073 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 116073.359073 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 96029.565457 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83978.603050 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 91707.884989 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 96029.565457 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83978.603050 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 91707.884989 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18313 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 7194 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 597 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1513 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1513 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3638 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3638 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 532 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 532 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3638 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2045 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5683 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3638 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2045 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5683 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 109950500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 109950500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 353832000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 353832000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 63372500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 63372500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 353832000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 173323000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 527155000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 353832000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 173323000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 527155000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995395 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995395 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.422042 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.422042 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.876442 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.876442 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.422042 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.961448 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.528799 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.422042 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.961448 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.528799 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72670.522141 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72670.522141 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97260.032985 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97260.032985 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 119121.240602 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 119121.240602 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97260.032985 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84754.523227 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 92759.985923 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97260.032985 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84754.523227 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 92759.985923 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 18517 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 6823 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1046 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 9638 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 6530 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 9751 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 6640 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 65 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 541 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 541 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1522 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1522 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 9056 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 583 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24098 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5373 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 29471 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 962688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 135744 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1098432 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 543 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 34752 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11702 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.100496 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.300673 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeReq 523 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 523 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1520 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1520 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 9145 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 607 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24404 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5382 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 29786 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 976576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 137216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1113792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 525 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 33600 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 11795 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.096651 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.295495 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 10526 89.95% 89.95% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1176 10.05% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 10655 90.33% 90.33% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1140 9.67% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11702 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 15702500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11795 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 15915500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 13582500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 13716000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3428499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3452000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 5669 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 5683 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 4154 # Transaction distribution -system.membus.trans_dist::ReadExReq 1515 # Transaction distribution -system.membus.trans_dist::ReadExResp 1515 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 4154 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11338 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11338 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11338 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 362816 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 362816 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 362816 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 4170 # Transaction distribution +system.membus.trans_dist::ReadExReq 1513 # Transaction distribution +system.membus.trans_dist::ReadExResp 1513 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 4170 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11366 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11366 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11366 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 363712 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 363712 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 363712 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 5669 # Request fanout histogram +system.membus.snoop_fanout::samples 5683 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5669 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5683 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5669 # Request fanout histogram -system.membus.reqLayer0.occupancy 7048500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5683 # Request fanout histogram +system.membus.reqLayer0.occupancy 6909500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 30047500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 30126750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |