diff options
Diffstat (limited to 'tests/long/se')
23 files changed, 7010 insertions, 7354 deletions
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index 7484e6ff9..c659f4312 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.269672 # Nu sim_ticks 269671683500 # Number of ticks simulated final_tick 269671683500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125294 # Simulator instruction rate (inst/s) -host_op_rate 125294 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56139844 # Simulator tick rate (ticks/s) -host_mem_usage 224468 # Number of bytes of host memory used -host_seconds 4803.57 # Real time elapsed on the host +host_inst_rate 149368 # Simulator instruction rate (inst/s) +host_op_rate 149368 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66926769 # Simulator tick rate (ticks/s) +host_mem_usage 224496 # Number of bytes of host memory used +host_seconds 4029.35 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory @@ -85,26 +85,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 26294 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1014 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 1014 # Categorize write packet sizes system.physmem.rdQLenPdf::0 16680 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 6777 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1890 # What read queue length does an incoming req see @@ -137,7 +124,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 37 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 44 # What write queue length does an incoming req see @@ -170,15 +156,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 384531397 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1096635147 # Sum of mem lat for all requests +system.physmem.totQLat 383646750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1095736750 # Sum of mem lat for all requests system.physmem.totBusLat 131400000 # Total cycles spent in databus access -system.physmem.totBankLat 580703750 # Total cycles spent in bank access -system.physmem.avgQLat 14632.09 # Average queueing delay per request -system.physmem.avgBankLat 22096.79 # Average bank access latency per request +system.physmem.totBankLat 580690000 # Total cycles spent in bank access +system.physmem.avgQLat 14598.43 # Average queueing delay per request +system.physmem.avgBankLat 22096.27 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 41728.89 # Average memory access latency +system.physmem.avgMemAccLat 41694.70 # Average memory access latency system.physmem.avgRdBW 6.24 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 6.24 # Average consumed read bandwidth in MB/s @@ -379,14 +364,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53901.754386 system.cpu.icache.overall_avg_mshr_miss_latency::total 53901.754386 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1042 # number of replacements -system.cpu.l2cache.tagsinuse 22879.116549 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 22879.116891 # Cycle average of tags in use system.cpu.l2cache.total_refs 531830 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23279 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 22.845913 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21684.482794 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 718.953898 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 475.679858 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 21684.482898 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 718.953897 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 475.680097 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.661758 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.021941 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.014517 # Average percentage of cache occupancy @@ -418,14 +403,14 @@ system.cpu.l2cache.overall_misses::total 26294 # nu system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45081000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 470660000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 515741000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1199043000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1199043000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1198171500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1198171500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 45081000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1669703000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1714784000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1668831500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1713912500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 45081000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1669703000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1714784000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1668831500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1713912500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 201207 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 202062 # number of ReadReq accesses(hits+misses) @@ -453,14 +438,14 @@ system.cpu.l2cache.overall_miss_rate::total 0.057631 # system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53604.042806 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 114099.393939 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 103854.409988 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56219.195424 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56219.195424 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56178.333646 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56178.333646 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53604.042806 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65599.457824 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 65215.790675 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65565.218245 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 65182.646231 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53604.042806 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65599.457824 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 65215.790675 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65565.218245 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 65182.646231 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -482,17 +467,17 @@ system.cpu.l2cache.demand_mshr_misses::total 26294 system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 25453 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 26294 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34645117 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 418280186 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 452925303 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 933604040 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 933604040 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34645117 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1351884226 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1386529343 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34645117 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1351884226 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1386529343 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34644438 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 418276481 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 452920919 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 932715801 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 932715801 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34644438 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1350992282 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1385636720 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34644438 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1350992282 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1385636720 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020501 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024577 # mshr miss rate for ReadReq accesses @@ -504,25 +489,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.057631 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055892 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.057631 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41195.145065 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 101401.257212 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 91205.256343 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43773.632783 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43773.632783 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41195.145065 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53112.962166 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52731.776945 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41195.145065 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53112.962166 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52731.776945 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41194.337693 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 101400.359030 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 91204.373540 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43731.986168 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43731.986168 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41194.337693 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53077.919381 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52697.829163 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41194.337693 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53077.919381 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52697.829163 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4093.423527 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4093.423689 # Cycle average of tags in use system.cpu.dcache.total_refs 151786159 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 333.306600 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 332210000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.423527 # Average occupied blocks per requestor +system.cpu.dcache.warmup_cycle 332192000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4093.423689 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999371 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999371 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 114120811 # number of ReadReq hits @@ -543,12 +528,12 @@ system.cpu.dcache.overall_misses::cpu.data 2179204 # system.cpu.dcache.overall_misses::total 2179204 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 5984681000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 5984681000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23175803000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23175803000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29160484000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29160484000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29160484000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29160484000 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23170641500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23170641500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29155322500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29155322500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29155322500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29155322500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) @@ -567,12 +552,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.014154 system.cpu.dcache.overall_miss_rate::total 0.014154 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15219.250263 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 15219.250263 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12976.569635 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 12976.569635 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13381.254807 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13381.254807 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13381.254807 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13381.254807 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12973.679613 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 12973.679613 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13378.886281 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13378.886281 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13378.886281 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13378.886281 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 191152 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 560 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 6083 # number of cycles access was blocked @@ -601,12 +586,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 455395 system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2643654000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 2643654000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3783295500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3783295500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6426949500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6426949500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6426949500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6426949500 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3782424000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3782424000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6426078000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6426078000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6426078000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6426078000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses @@ -617,12 +602,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13137.343961 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13137.343961 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14885.311788 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14885.311788 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14112.911868 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14112.911868 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14112.911868 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14112.911868 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14881.882886 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14881.882886 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14110.998144 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14110.998144 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14110.998144 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14110.998144 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index fd6611525..80e818735 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,65 +1,65 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.133806 # Number of seconds simulated -sim_ticks 133806308500 # Number of ticks simulated -final_tick 133806308500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.133774 # Number of seconds simulated +sim_ticks 133773851500 # Number of ticks simulated +final_tick 133773851500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 271409 # Simulator instruction rate (inst/s) -host_op_rate 271409 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64213833 # Simulator tick rate (ticks/s) -host_mem_usage 226532 # Number of bytes of host memory used -host_seconds 2083.76 # Real time elapsed on the host +host_inst_rate 262576 # Simulator instruction rate (inst/s) +host_op_rate 262576 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62108832 # Simulator tick rate (ticks/s) +host_mem_usage 226536 # Number of bytes of host memory used +host_seconds 2153.86 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated sim_ops 565552443 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1636352 # Number of bytes read from this memory -system.physmem.bytes_read::total 1697856 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61504 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67200 # Number of bytes written to this memory -system.physmem.bytes_written::total 67200 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 961 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 25568 # Number of read requests responded to by this memory -system.physmem.num_reads::total 26529 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1050 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1050 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 459649 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12229259 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12688908 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 459649 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 459649 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 502218 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 502218 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 502218 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 459649 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12229259 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13191127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 26529 # Total number of read requests seen -system.physmem.writeReqs 1050 # Total number of write requests seen -system.physmem.cpureqs 27579 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1697856 # Total number of bytes read from memory -system.physmem.bytesWritten 67200 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1697856 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 67200 # bytesWritten derated as per pkt->getSize() +system.physmem.bytes_read::cpu.inst 60992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1636544 # Number of bytes read from this memory +system.physmem.bytes_read::total 1697536 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 60992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 60992 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 67072 # Number of bytes written to this memory +system.physmem.bytes_written::total 67072 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 953 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 25571 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26524 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1048 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1048 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 455934 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12233661 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12689595 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 455934 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 455934 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 501383 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 501383 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 501383 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 455934 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12233661 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13190979 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 26524 # Total number of read requests seen +system.physmem.writeReqs 1048 # Total number of write requests seen +system.physmem.cpureqs 27572 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1697536 # Total number of bytes read from memory +system.physmem.bytesWritten 67072 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1697536 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 67072 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 15 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1632 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1631 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 1662 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1679 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1680 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 1686 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 1626 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 1603 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 1584 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 1608 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1668 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1666 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 1722 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1650 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1645 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1723 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1666 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1676 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1684 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 61 # Track writes on a per bank basis +system.physmem.perBankRdReqs::10 1648 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1647 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1724 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1665 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1675 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1682 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 60 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 60 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 68 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 65 # Track writes on a per bank basis @@ -72,44 +72,31 @@ system.physmem.perBankWrReqs::9 75 # Tr system.physmem.perBankWrReqs::10 63 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 61 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 83 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 74 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 73 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 72 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 81 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 133806263000 # Total gap between requests +system.physmem.totGap 133773818000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 26529 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1050 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 8850 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 11428 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1089 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see +system.physmem.readPktSize::6 26524 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 1048 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 8806 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 11451 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5143 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1096 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -137,8 +124,7 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 41 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 46 # What write queue length does an incoming req see @@ -151,8 +137,8 @@ system.physmem.wrQLenPdf::9 46 # Wh system.physmem.wrQLenPdf::10 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 45 # What write queue length does an incoming req see @@ -161,7 +147,7 @@ system.physmem.wrQLenPdf::19 45 # Wh system.physmem.wrQLenPdf::20 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -170,15 +156,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 648232398 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1339932398 # Sum of mem lat for all requests -system.physmem.totBusLat 132570000 # Total cycles spent in databus access -system.physmem.totBankLat 559130000 # Total cycles spent in bank access -system.physmem.avgQLat 24448.68 # Average queueing delay per request -system.physmem.avgBankLat 21088.10 # Average bank access latency per request +system.physmem.totQLat 654284750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1345973500 # Sum of mem lat for all requests +system.physmem.totBusLat 132545000 # Total cycles spent in databus access +system.physmem.totBankLat 559143750 # Total cycles spent in bank access +system.physmem.avgQLat 24681.61 # Average queueing delay per request +system.physmem.avgBankLat 21092.60 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 50536.79 # Average memory access latency +system.physmem.avgMemAccLat 50774.21 # Average memory access latency system.physmem.avgRdBW 12.69 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.50 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 12.69 # Average consumed read bandwidth in MB/s @@ -186,41 +171,41 @@ system.physmem.avgConsumedWrBW 0.50 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.10 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.03 # Average write queue length over time -system.physmem.readRowHits 16972 # Number of row buffer hits during reads -system.physmem.writeRowHits 273 # Number of row buffer hits during writes -system.physmem.readRowHitRate 64.01 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 26.00 # Row buffer hit rate for writes -system.physmem.avgGap 4851744.55 # Average gap between requests -system.cpu.branchPred.lookups 76500721 # Number of BP lookups -system.cpu.branchPred.condPredicted 70919742 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2718676 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 43116993 # Number of BTB lookups -system.cpu.branchPred.BTBHits 41952631 # Number of BTB hits +system.physmem.avgWrQLen 9.24 # Average write queue length over time +system.physmem.readRowHits 16966 # Number of row buffer hits during reads +system.physmem.writeRowHits 271 # Number of row buffer hits during writes +system.physmem.readRowHitRate 64.00 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 25.86 # Row buffer hit rate for writes +system.physmem.avgGap 4851799.58 # Average gap between requests +system.cpu.branchPred.lookups 76502410 # Number of BP lookups +system.cpu.branchPred.condPredicted 70922676 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2717282 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 43095322 # Number of BTB lookups +system.cpu.branchPred.BTBHits 41949760 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.299529 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1606312 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 238 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.341795 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1606512 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 241 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 122623794 # DTB read hits -system.cpu.dtb.read_misses 28860 # DTB read misses +system.cpu.dtb.read_hits 122629608 # DTB read hits +system.cpu.dtb.read_misses 28810 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 122652654 # DTB read accesses -system.cpu.dtb.write_hits 40761180 # DTB write hits -system.cpu.dtb.write_misses 25673 # DTB write misses +system.cpu.dtb.read_accesses 122658418 # DTB read accesses +system.cpu.dtb.write_hits 40760367 # DTB write hits +system.cpu.dtb.write_misses 25602 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 40786853 # DTB write accesses -system.cpu.dtb.data_hits 163384974 # DTB hits -system.cpu.dtb.data_misses 54533 # DTB misses +system.cpu.dtb.write_accesses 40785969 # DTB write accesses +system.cpu.dtb.data_hits 163389975 # DTB hits +system.cpu.dtb.data_misses 54412 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 163439507 # DTB accesses -system.cpu.itb.fetch_hits 65534932 # ITB hits +system.cpu.dtb.data_accesses 163444387 # DTB accesses +system.cpu.itb.fetch_hits 65529846 # ITB hits system.cpu.itb.fetch_misses 41 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 65534973 # ITB accesses +system.cpu.itb.fetch_accesses 65529887 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -234,133 +219,133 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 267612618 # number of cpu cycles simulated +system.cpu.numCycles 267547704 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 67186400 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 699453099 # Number of instructions fetch has processed -system.cpu.fetch.Branches 76500721 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 43558943 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 117852914 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 11666249 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 73358963 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 67181660 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 699454641 # Number of instructions fetch has processed +system.cpu.fetch.Branches 76502410 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 43556272 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 117851527 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11664601 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 73301689 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 1199 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 10 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 65534932 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 934826 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 267314333 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.616594 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.444810 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 21 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 65529846 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 933458 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 267250540 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.617224 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.444995 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 149461419 55.91% 55.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 10349982 3.87% 59.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 11850266 4.43% 64.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10577716 3.96% 68.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7012506 2.62% 70.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2870690 1.07% 71.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3579816 1.34% 73.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3108437 1.16% 74.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 68503501 25.63% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 149399013 55.90% 55.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 10348526 3.87% 59.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 11849388 4.43% 64.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10578020 3.96% 68.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7012807 2.62% 70.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2871984 1.07% 71.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3578789 1.34% 73.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3106707 1.16% 74.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 68505306 25.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 267314333 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.285864 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.613678 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 84322022 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 57655855 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 102751859 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 13670665 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 8913932 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3876852 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 942 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 691462372 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3197 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 8913932 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 92304341 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12773232 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1346 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 103106270 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 50215212 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 681285072 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 434 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 38522944 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5472741 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 520920645 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 897379043 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 897376453 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2590 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 267250540 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.285939 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.614317 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 84320129 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 57595253 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 102753479 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 13668133 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 8913546 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3876280 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 932 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 691464517 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3449 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 8913546 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 92299678 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12776720 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1189 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 103108433 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 50150974 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 681302234 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 431 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 38477727 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5455282 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 520934901 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 897390123 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 897387366 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2757 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 57065756 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 66 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 71 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 112077327 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 127005785 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 42387861 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14833107 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 10089887 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 621266103 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 59 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 604722021 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 299730 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 55073821 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 30009810 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 42 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 267314333 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.262213 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.825151 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 57080012 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 63 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 67 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 112027328 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 127008438 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 42384710 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14844783 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 10088023 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 621271293 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 55 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 604725807 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 299798 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 55080788 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 30005964 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 38 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 267250540 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.262767 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.823653 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52513972 19.65% 19.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55954300 20.93% 40.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 53424383 19.99% 60.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 36299246 13.58% 74.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31212895 11.68% 85.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 23807225 8.91% 94.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10138155 3.79% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3408674 1.28% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 555483 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52429829 19.62% 19.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 55852855 20.90% 40.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 53444845 20.00% 60.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 36460113 13.64% 74.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31255141 11.70% 85.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 23773948 8.90% 94.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10075913 3.77% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3406027 1.27% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 551869 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 267314333 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 267250540 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2798552 71.38% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 39 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 727516 18.56% 89.94% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 394572 10.06% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2756472 71.14% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 40 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 728591 18.80% 89.94% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 389871 10.06% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 439175234 72.62% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7035 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 439176954 72.62% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7066 0.00% 72.63% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.63% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.63% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.63% # Type of FU issued @@ -388,84 +373,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.63% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.63% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.63% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.63% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 124352577 20.56% 93.19% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 41187127 6.81% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 124356224 20.56% 93.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 41185515 6.81% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 604722021 # Type of FU issued -system.cpu.iq.rate 2.259692 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3920679 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006483 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1480975025 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 676343136 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 596595322 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3759 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2270 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1723 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 608640802 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1898 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 12279325 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 604725807 # Type of FU issued +system.cpu.iq.rate 2.260254 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3874974 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006408 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1480873086 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 676355161 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 596602519 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3840 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2402 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1730 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 608598846 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1935 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 12280408 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 12491743 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 36092 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 5478 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2936540 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 12494396 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 35705 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 5495 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2933389 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6432 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 54776 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6442 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 54892 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 8913932 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1438086 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 192048 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 664143136 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1694587 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 127005785 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 42387861 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 59 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 143884 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7497 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 5478 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1342912 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1811100 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3154012 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 599591446 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 122652830 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5130575 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 8913546 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1440408 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 191911 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 664145675 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1694595 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 127008438 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 42384710 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 55 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 143753 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7490 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 5495 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1342563 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1811283 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3153846 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 599598114 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 122658565 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5127693 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 42876974 # number of nop insts executed -system.cpu.iew.exec_refs 163458157 # number of memory reference insts executed -system.cpu.iew.exec_branches 66641389 # Number of branches executed -system.cpu.iew.exec_stores 40805327 # Number of stores executed -system.cpu.iew.exec_rate 2.240520 # Inst execution rate -system.cpu.iew.wb_sent 597536756 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 596597045 # cumulative count of insts written-back -system.cpu.iew.wb_producers 415962909 # num instructions producing a value -system.cpu.iew.wb_consumers 530370743 # num instructions consuming a value +system.cpu.iew.exec_nop 42874327 # number of nop insts executed +system.cpu.iew.exec_refs 163462793 # number of memory reference insts executed +system.cpu.iew.exec_branches 66641793 # Number of branches executed +system.cpu.iew.exec_stores 40804228 # Number of stores executed +system.cpu.iew.exec_rate 2.241089 # Inst execution rate +system.cpu.iew.wb_sent 597543507 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 596604249 # cumulative count of insts written-back +system.cpu.iew.wb_producers 415969736 # num instructions producing a value +system.cpu.iew.wb_consumers 530347418 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.229331 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.784287 # average fanout of values written-back +system.cpu.iew.wb_rate 2.229899 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.784334 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 62162261 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 62164646 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2717793 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 258400401 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.329164 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.692856 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2716416 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 258336994 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.329736 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.693311 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 79574518 30.80% 30.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 72566023 28.08% 58.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 25599330 9.91% 68.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9197400 3.56% 72.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10258446 3.97% 76.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 20921268 8.10% 84.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6836400 2.65% 87.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3734572 1.45% 88.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29712444 11.50% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 79521079 30.78% 30.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 72557315 28.09% 58.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 25650829 9.93% 68.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9136101 3.54% 72.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10241480 3.96% 76.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 20967757 8.12% 84.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6801640 2.63% 87.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3711202 1.44% 88.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29749591 11.52% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 258400401 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 258336994 # Number of insts commited each cycle system.cpu.commit.committedInsts 601856963 # Number of instructions committed system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -476,192 +461,192 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 29712444 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 29749591 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 892642792 # The number of ROB reads -system.cpu.rob.rob_writes 1336966756 # The number of ROB writes -system.cpu.timesIdled 34291 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 298285 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 892544623 # The number of ROB reads +system.cpu.rob.rob_writes 1336970755 # The number of ROB writes +system.cpu.timesIdled 34274 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 297164 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.473188 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.473188 # CPI: Total CPI of All Threads -system.cpu.ipc 2.113325 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.113325 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 845166386 # number of integer regfile reads -system.cpu.int_regfile_writes 490617161 # number of integer regfile writes -system.cpu.fp_regfile_reads 389 # number of floating regfile reads +system.cpu.cpi 0.473073 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.473073 # CPI: Total CPI of All Threads +system.cpu.ipc 2.113838 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.113838 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 845171662 # number of integer regfile reads +system.cpu.int_regfile_writes 490625638 # number of integer regfile writes +system.cpu.fp_regfile_reads 396 # number of floating regfile reads system.cpu.fp_regfile_writes 54 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 41 # number of replacements -system.cpu.icache.tagsinuse 825.582407 # Cycle average of tags in use -system.cpu.icache.total_refs 65533545 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 979 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 66939.269663 # Average number of references to valid blocks. +system.cpu.icache.replacements 39 # number of replacements +system.cpu.icache.tagsinuse 824.684718 # Cycle average of tags in use +system.cpu.icache.total_refs 65528462 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 971 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 67485.542739 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 825.582407 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.403116 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.403116 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 65533545 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 65533545 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 65533545 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 65533545 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 65533545 # number of overall hits -system.cpu.icache.overall_hits::total 65533545 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1386 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1386 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1386 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1386 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1386 # number of overall misses -system.cpu.icache.overall_misses::total 1386 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 74542000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 74542000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 74542000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 74542000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 74542000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 74542000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 65534931 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 65534931 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 65534931 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 65534931 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 65534931 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 65534931 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 824.684718 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.402678 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.402678 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 65528462 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 65528462 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 65528462 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 65528462 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 65528462 # number of overall hits +system.cpu.icache.overall_hits::total 65528462 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1383 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1383 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1383 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1383 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1383 # number of overall misses +system.cpu.icache.overall_misses::total 1383 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 72600500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 72600500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 72600500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 72600500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 72600500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 72600500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 65529845 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 65529845 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 65529845 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 65529845 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 65529845 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 65529845 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000021 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000021 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000021 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000021 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000021 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53782.106782 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53782.106782 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53782.106782 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53782.106782 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53782.106782 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53782.106782 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 93 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52494.938539 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52494.938539 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52494.938539 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52494.938539 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52494.938539 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52494.938539 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 18.600000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 25.400000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 407 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 407 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 407 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 407 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 407 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 407 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 979 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 979 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 979 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 979 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 979 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 979 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54570500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 54570500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54570500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 54570500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54570500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 54570500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 412 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 412 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 412 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 412 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 412 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 412 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 971 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 971 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 971 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 971 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 971 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 971 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54205000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 54205000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54205000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 54205000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54205000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 54205000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000015 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000015 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000015 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55741.062308 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55741.062308 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55741.062308 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 55741.062308 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55741.062308 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 55741.062308 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55823.892894 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55823.892894 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55823.892894 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 55823.892894 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55823.892894 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 55823.892894 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1082 # number of replacements -system.cpu.l2cache.tagsinuse 22917.401709 # Cycle average of tags in use -system.cpu.l2cache.total_refs 547365 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 23522 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 23.270343 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1081 # number of replacements +system.cpu.l2cache.tagsinuse 22920.644164 # Cycle average of tags in use +system.cpu.l2cache.total_refs 547028 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 23516 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 23.261949 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21471.188255 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 816.032339 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 630.181115 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.655249 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.024903 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019232 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.699384 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 21474.762913 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 815.139111 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 630.742140 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.655358 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.024876 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.019249 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.699483 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 18 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 206157 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 206175 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 445006 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 445006 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 233310 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 233310 # number of ReadExReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 206066 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 206084 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 444903 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 444903 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 233285 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 233285 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 439467 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 439485 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 439351 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 439369 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 18 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 439467 # number of overall hits -system.cpu.l2cache.overall_hits::total 439485 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 961 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 4311 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 5272 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 21257 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 21257 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 961 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 25568 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 26529 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 961 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 25568 # number of overall misses -system.cpu.l2cache.overall_misses::total 26529 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 53397000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 418986500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 472383500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1501574500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1501574500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 53397000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1920561000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1973958000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 53397000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1920561000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1973958000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 979 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 210468 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 211447 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 445006 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 445006 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 254567 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 254567 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 979 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 465035 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 466014 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 979 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 465035 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 466014 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.981614 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020483 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.024933 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083503 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.083503 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.981614 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.054981 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.056927 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.981614 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.054981 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.056927 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 55563.995838 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 97190.095106 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 89602.333080 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70639.060074 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70639.060074 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 55563.995838 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75115.808824 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74407.553998 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 55563.995838 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75115.808824 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74407.553998 # average overall miss latency +system.cpu.l2cache.overall_hits::cpu.data 439351 # number of overall hits +system.cpu.l2cache.overall_hits::total 439369 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 953 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 4305 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 5258 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 21266 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 21266 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 953 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 25571 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 26524 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 953 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 25571 # number of overall misses +system.cpu.l2cache.overall_misses::total 26524 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 53037500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 418895500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 471933000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1507958500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1507958500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 53037500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1926854000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1979891500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 53037500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1926854000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1979891500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 971 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 210371 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 211342 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 444903 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 444903 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 254551 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 254551 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 971 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 464922 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 465893 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 971 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 464922 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 465893 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.981462 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020464 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.024879 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083543 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.083543 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.981462 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.055001 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.056932 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.981462 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.055001 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.056932 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 55653.200420 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 97304.413473 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 89755.230126 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70909.362362 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70909.362362 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 55653.200420 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75353.095303 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74645.283517 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 55653.200420 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75353.095303 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74645.283517 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -670,174 +655,174 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1050 # number of writebacks -system.cpu.l2cache.writebacks::total 1050 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 961 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4311 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5272 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21257 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21257 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 961 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 25568 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 26529 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 961 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 25568 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 26529 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41447516 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 363900322 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 405347838 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1236862753 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1236862753 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41447516 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1600763075 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1642210591 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41447516 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1600763075 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1642210591 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.981614 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020483 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024933 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083503 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083503 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.981614 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.054981 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.056927 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.981614 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.054981 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.056927 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43129.569199 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 84412.044073 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76886.919196 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58186.138825 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58186.138825 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43129.569199 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62608.067702 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61902.468657 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43129.569199 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62608.067702 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61902.468657 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 1049 # number of writebacks +system.cpu.l2cache.writebacks::total 1049 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 953 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4305 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5258 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21266 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21266 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 953 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 25571 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 26524 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 953 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 25571 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 26524 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41181755 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 363891160 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 405072915 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1243149416 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1243149416 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41181755 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1607040576 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1648222331 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41181755 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1607040576 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1648222331 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.981462 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020464 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024879 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083543 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083543 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.981462 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055001 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.056932 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.981462 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055001 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.056932 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43212.754460 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 84527.563298 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77039.352415 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58457.134205 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58457.134205 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43212.754460 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62846.215478 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62140.790642 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43212.754460 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62846.215478 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62140.790642 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 460939 # number of replacements -system.cpu.dcache.tagsinuse 4090.899850 # Cycle average of tags in use -system.cpu.dcache.total_refs 146914514 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 465035 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 315.921412 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 301771000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4090.899850 # Average occupied blocks per requestor +system.cpu.dcache.replacements 460826 # number of replacements +system.cpu.dcache.tagsinuse 4090.898597 # Cycle average of tags in use +system.cpu.dcache.total_refs 146919615 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 464922 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 316.009169 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 301835000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4090.898597 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.998755 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.998755 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 109265934 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 109265934 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 37648563 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 37648563 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 17 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 17 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 146914497 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 146914497 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 146914497 # number of overall hits -system.cpu.dcache.overall_hits::total 146914497 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1025246 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1025246 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1802758 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1802758 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2828004 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2828004 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2828004 # number of overall misses -system.cpu.dcache.overall_misses::total 2828004 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 15342477500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 15342477500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26169777829 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 26169777829 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 37000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 37000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41512255329 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41512255329 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41512255329 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41512255329 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 110291180 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 110291180 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits::cpu.data 109271003 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 109271003 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 37648598 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 37648598 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 14 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 14 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 146919601 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 146919601 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 146919601 # number of overall hits +system.cpu.dcache.overall_hits::total 146919601 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1024794 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1024794 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1802723 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1802723 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2827517 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2827517 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2827517 # number of overall misses +system.cpu.dcache.overall_misses::total 2827517 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 15336763000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 15336763000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 26197701326 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 26197701326 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 20000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 20000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41534464326 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41534464326 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41534464326 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41534464326 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 110295797 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 110295797 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 21 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 21 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 149742501 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 149742501 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 149742501 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 149742501 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009296 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009296 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045696 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.045696 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.190476 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.190476 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.018886 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.018886 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.018886 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.018886 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14964.679209 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14964.679209 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14516.522922 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 14516.522922 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14678.994559 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14678.994559 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14678.994559 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14678.994559 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 301355 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2673 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 17784 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 16 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 149747118 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 149747118 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 149747118 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 149747118 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009291 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009291 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045695 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.045695 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.125000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.125000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.018882 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.018882 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.018882 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018882 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14965.703351 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14965.703351 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14532.294382 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 14532.294382 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 10000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14689.377403 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14689.377403 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14689.377403 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14689.377403 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 303569 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2051 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 17829 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.945288 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 243 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 17.026698 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 186.454545 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 445006 # number of writebacks -system.cpu.dcache.writebacks::total 445006 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 814778 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 814778 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1548191 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1548191 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2362969 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2362969 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2362969 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2362969 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210468 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 210468 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254567 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 254567 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 465035 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 465035 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 465035 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 465035 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2697344500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2697344500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4097543997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4097543997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6794888497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6794888497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6794888497 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6794888497 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001908 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001908 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006453 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006453 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003106 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003106 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003106 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003106 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12815.936389 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12815.936389 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16096.131851 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16096.131851 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14611.563639 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14611.563639 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14611.563639 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14611.563639 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 444903 # number of writebacks +system.cpu.dcache.writebacks::total 444903 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 814423 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 814423 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1548172 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1548172 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2362595 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2362595 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2362595 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2362595 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210371 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 210371 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254551 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 254551 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 464922 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 464922 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 464922 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 464922 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2696208000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2696208000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4103693497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4103693497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6799901497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6799901497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6799901497 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6799901497 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001907 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001907 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006452 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006452 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003105 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003105 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003105 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003105 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12816.443331 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12816.443331 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16121.301810 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16121.301810 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14625.897456 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14625.897456 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14625.897456 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14625.897456 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index e289c0e8e..aa7b7ad18 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.164572 # Nu sim_ticks 164572262000 # Number of ticks simulated final_tick 164572262000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 164809 # Simulator instruction rate (inst/s) -host_op_rate 174150 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47579904 # Simulator tick rate (ticks/s) -host_mem_usage 241928 # Number of bytes of host memory used -host_seconds 3458.86 # Real time elapsed on the host +host_inst_rate 185108 # Simulator instruction rate (inst/s) +host_op_rate 195599 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53440170 # Simulator tick rate (ticks/s) +host_mem_usage 241944 # Number of bytes of host memory used +host_seconds 3079.56 # Real time elapsed on the host sim_insts 570051585 # Number of instructions simulated sim_ops 602359791 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 47424 # Number of bytes read from this memory @@ -85,26 +85,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 27336 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 2538 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 2538 # Categorize write packet sizes system.physmem.rdQLenPdf::0 14742 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 3442 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 8340 # What read queue length does an incoming req see @@ -137,7 +124,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 71 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 96 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see @@ -170,15 +156,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 921366434 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1672075184 # Sum of mem lat for all requests +system.physmem.totQLat 921339250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1672034250 # Sum of mem lat for all requests system.physmem.totBusLat 136675000 # Total cycles spent in databus access -system.physmem.totBankLat 614033750 # Total cycles spent in bank access -system.physmem.avgQLat 33705.24 # Average queueing delay per request -system.physmem.avgBankLat 22462.46 # Average bank access latency per request +system.physmem.totBankLat 614020000 # Total cycles spent in bank access +system.physmem.avgQLat 33704.25 # Average queueing delay per request +system.physmem.avgBankLat 22461.95 # Average bank access latency per request system.physmem.avgBusLat 4999.82 # Average bus latency per request -system.physmem.avgMemAccLat 61167.51 # Average memory access latency +system.physmem.avgMemAccLat 61166.02 # Average memory access latency system.physmem.avgRdBW 10.63 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.99 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 10.63 # Average consumed read bandwidth in MB/s @@ -323,11 +308,11 @@ system.cpu.iq.issued_per_cycle::mean 1.967168 # Nu system.cpu.iq.issued_per_cycle::stdev 1.722204 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 68107234 20.75% 20.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 85141417 25.94% 46.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 76162034 23.21% 69.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 40819071 12.44% 82.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 85141419 25.94% 46.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 76162032 23.21% 69.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 40819070 12.44% 82.34% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 28853170 8.79% 91.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 14914630 4.54% 95.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 14914631 4.54% 95.68% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 5559324 1.69% 97.37% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 6732498 2.05% 99.42% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 1901914 0.58% 100.00% # Number of insts issued each cycle @@ -629,16 +614,16 @@ system.cpu.l2cache.overall_misses::cpu.inst 743 # system.cpu.l2cache.overall_misses::cpu.data 26602 # number of overall misses system.cpu.l2cache.overall_misses::total 27345 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 40442500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 687360500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 727803000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 687347500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 727790000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1581776500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 1581776500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 40442500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 2269137000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 2309579500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 2269124000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 2309566500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 40442500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 2269137000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 2309579500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2269124000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 2309566500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 831 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 197598 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 198429 # number of ReadReq accesses(hits+misses) @@ -666,16 +651,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.894103 system.cpu.l2cache.overall_miss_rate::cpu.data 0.059811 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.061367 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54431.359354 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 142872.687591 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 131041.231545 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 142869.985450 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 131038.890889 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72588.522785 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72588.522785 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54431.359354 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85299.488760 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 84460.760651 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85299.000075 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 84460.285244 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54431.359354 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85299.488760 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 84460.760651 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85299.000075 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 84460.285244 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -706,17 +691,17 @@ system.cpu.l2cache.demand_mshr_misses::total 27336 system.cpu.l2cache.overall_mshr_misses::cpu.inst 741 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 26595 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 27336 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31149679 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 627911476 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 659061155 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1310031171 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1310031171 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31149679 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1937942647 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1969092326 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31149679 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1937942647 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1969092326 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31149092 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 627893373 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 659042465 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1310013362 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1310013362 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31149092 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1937906735 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1969055827 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31149092 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1937906735 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1969055827 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.891697 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024312 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027945 # mshr miss rate for ReadReq accesses @@ -728,17 +713,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.061347 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.891697 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059795 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.061347 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42037.353576 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 130705.969192 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 118856.835888 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60117.992336 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60117.992336 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42037.353576 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72868.683850 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72032.935543 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42037.353576 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72868.683850 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72032.935543 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42036.561404 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 130702.200874 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 118853.465284 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60117.175072 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60117.175072 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42036.561404 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72867.333521 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72031.600344 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42036.561404 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72867.333521 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72031.600344 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 440669 # number of replacements system.cpu.dcache.tagsinuse 4091.484070 # Cycle average of tags in use @@ -771,16 +756,16 @@ system.cpu.dcache.demand_misses::cpu.data 3718210 # n system.cpu.dcache.demand_misses::total 3718210 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 3718210 # number of overall misses system.cpu.dcache.overall_misses::total 3718210 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5073572500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5073572500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5073533500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5073533500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 40705228766 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 40705228766 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 337500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 337500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45778801266 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45778801266 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45778801266 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45778801266 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 45778762266 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45778762266 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45778762266 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45778762266 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 131865640 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 131865640 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) @@ -803,16 +788,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.018473 system.cpu.dcache.demand_miss_rate::total 0.018473 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.018473 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.018473 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14838.521697 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14838.521697 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14838.407635 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14838.407635 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12056.196805 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 12056.196805 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15340.909091 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15340.909091 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12312.053721 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12312.053721 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12312.053721 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12312.053721 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12312.043232 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12312.043232 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12312.043232 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12312.043232 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 148065 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 30 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 4947 # number of cycles access was blocked @@ -841,14 +826,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 444768 system.cpu.dcache.demand_mshr_misses::total 444768 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 444768 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 444768 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2836417500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2836417500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2836404500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2836404500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4096422821 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 4096422821 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6932840321 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6932840321 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6932840321 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6932840321 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6932827321 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6932827321 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6932827321 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6932827321 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001498 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001498 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003561 # mshr miss rate for WriteReq accesses @@ -857,14 +842,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002210 system.cpu.dcache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14354.412219 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14354.412219 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14354.346429 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14354.346429 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16573.368104 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16573.368104 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15587.542991 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15587.542991 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15587.542991 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15587.542991 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15587.513762 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15587.513762 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15587.513762 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15587.513762 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index dd62eb55a..4f3b9b27a 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,63 +1,63 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.387316 # Number of seconds simulated -sim_ticks 387315507500 # Number of ticks simulated -final_tick 387315507500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.387321 # Number of seconds simulated +sim_ticks 387320726500 # Number of ticks simulated +final_tick 387320726500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 183094 # Simulator instruction rate (inst/s) -host_op_rate 183671 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50610731 # Simulator tick rate (ticks/s) -host_mem_usage 233664 # Number of bytes of host memory used -host_seconds 7652.83 # Real time elapsed on the host +host_inst_rate 176162 # Simulator instruction rate (inst/s) +host_op_rate 176717 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48695201 # Simulator tick rate (ticks/s) +host_mem_usage 235496 # Number of bytes of host memory used +host_seconds 7953.98 # Real time elapsed on the host sim_insts 1401188945 # Number of instructions simulated sim_ops 1405604139 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 76544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1678528 # Number of bytes read from this memory -system.physmem.bytes_read::total 1755072 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 76544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 76544 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 76480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1678784 # Number of bytes read from this memory +system.physmem.bytes_read::total 1755264 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 76480 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 76480 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 162112 # Number of bytes written to this memory system.physmem.bytes_written::total 162112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1196 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26227 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27423 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1195 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26231 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27426 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 2533 # Number of write requests responded to by this memory system.physmem.num_writes::total 2533 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 197627 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4333749 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4531375 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 197627 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 197627 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 418553 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 418553 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 418553 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 197627 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4333749 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4949928 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27424 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 197459 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4334351 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4531810 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 197459 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 197459 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 418547 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 418547 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 418547 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 197459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4334351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4950357 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27427 # Total number of read requests seen system.physmem.writeReqs 2533 # Total number of write requests seen -system.physmem.cpureqs 29957 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1755072 # Total number of bytes read from memory +system.physmem.cpureqs 29960 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1755264 # Total number of bytes read from memory system.physmem.bytesWritten 162112 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1755072 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 1755264 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 162112 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 1660 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 1716 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 1723 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1744 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1743 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 1702 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 1707 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 1721 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 1697 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1767 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1768 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 1765 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1769 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1770 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 1755 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 1736 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1673 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1661 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1676 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1660 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 1628 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 157 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 155 # Track writes on a per bank basis @@ -77,37 +77,24 @@ system.physmem.perBankWrReqs::14 154 # Tr system.physmem.perBankWrReqs::15 153 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 387315479500 # Total gap between requests +system.physmem.totGap 387320698500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27424 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 2533 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 7981 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 13392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5076 # What read queue length does an incoming req see +system.physmem.readPktSize::6 27427 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 2533 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 7983 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 13387 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5082 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 974 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -137,7 +124,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 88 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 107 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see @@ -170,15 +156,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 713274952 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1439334952 # Sum of mem lat for all requests -system.physmem.totBusLat 137120000 # Total cycles spent in databus access -system.physmem.totBankLat 588940000 # Total cycles spent in bank access -system.physmem.avgQLat 26009.15 # Average queueing delay per request -system.physmem.avgBankLat 21475.35 # Average bank access latency per request +system.physmem.totQLat 712904000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1439226500 # Sum of mem lat for all requests +system.physmem.totBusLat 137135000 # Total cycles spent in databus access +system.physmem.totBankLat 589187500 # Total cycles spent in bank access +system.physmem.avgQLat 25992.78 # Average queueing delay per request +system.physmem.avgBankLat 21482.03 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 52484.50 # Average memory access latency +system.physmem.avgMemAccLat 52474.81 # Average memory access latency system.physmem.avgRdBW 4.53 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.42 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 4.53 # Average consumed read bandwidth in MB/s @@ -186,252 +171,252 @@ system.physmem.avgConsumedWrBW 0.42 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 16.51 # Average write queue length over time -system.physmem.readRowHits 17585 # Number of row buffer hits during reads +system.physmem.avgWrQLen 16.63 # Average write queue length over time +system.physmem.readRowHits 17586 # Number of row buffer hits during reads system.physmem.writeRowHits 1048 # Number of row buffer hits during writes system.physmem.readRowHitRate 64.12 # Row buffer hit rate for reads system.physmem.writeRowHitRate 41.37 # Row buffer hit rate for writes -system.physmem.avgGap 12929047.62 # Average gap between requests -system.cpu.branchPred.lookups 97759655 # Number of BP lookups -system.cpu.branchPred.condPredicted 88050231 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 3614520 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 65786552 # Number of BTB lookups -system.cpu.branchPred.BTBHits 65492883 # Number of BTB hits +system.physmem.avgGap 12927927.19 # Average gap between requests +system.cpu.branchPred.lookups 97754812 # Number of BP lookups +system.cpu.branchPred.condPredicted 88045070 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 3614513 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 65790839 # Number of BTB lookups +system.cpu.branchPred.BTBHits 65487235 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.553603 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1341 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 221 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.538531 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1327 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 219 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 774631016 # number of cpu cycles simulated +system.cpu.numCycles 774641454 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 164855721 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1642251558 # Number of instructions fetch has processed -system.cpu.fetch.Branches 97759655 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 65494224 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 329204399 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 20834739 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 263342259 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 64 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2502 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 164855086 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1642226882 # Number of instructions fetch has processed +system.cpu.fetch.Branches 97754812 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 65488562 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 329193327 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 20835132 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 263364086 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 66 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2508 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 12 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 161937023 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 736247 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 774398184 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.126696 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.146676 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 161933823 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 733897 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 774407665 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.126639 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.146663 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 445193785 57.49% 57.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 74062525 9.56% 67.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 37899229 4.89% 71.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 9077552 1.17% 73.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28106227 3.63% 76.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18772117 2.42% 79.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 11485912 1.48% 80.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3791430 0.49% 81.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 146009407 18.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 445214338 57.49% 57.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 74055584 9.56% 67.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 37896707 4.89% 71.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 9077649 1.17% 73.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28106182 3.63% 76.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18772378 2.42% 79.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 11485240 1.48% 80.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3791473 0.49% 81.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 146008114 18.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 774398184 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126202 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.120044 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 215922553 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 214452390 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 284209898 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 42820116 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 16993227 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 1636550752 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 16993227 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 239771948 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36701097 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52424917 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 302039391 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 126467604 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1625687860 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 146 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 30927407 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 73464560 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 3152152 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1356365192 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2746429093 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2712307786 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 34121307 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 774407665 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126194 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.119983 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 215996576 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 214396476 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 284196048 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 42825985 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 16992580 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 1636523781 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 16992580 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 239852916 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36748965 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52423247 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 302028125 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 126361832 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1625670094 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 144 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 30926636 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 73309992 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3198488 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1356344294 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2746400105 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2712277962 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 34122143 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1244770439 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 111594753 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2643851 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2663506 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 271777312 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 436941235 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 179754378 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 254555015 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 82904621 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1512542697 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2609193 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1459339312 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 53583 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 109245499 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 130204517 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 365522 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 774398184 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.884482 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.431065 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 111573855 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2642593 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2663144 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 271720784 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 436941817 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 179749373 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 254480906 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 83188791 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1512511277 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2608080 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1459319933 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 52996 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 109213691 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 130186216 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 364409 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 774407665 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.884434 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.431122 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 145558409 18.80% 18.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 184658706 23.85% 42.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 209828049 27.10% 69.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131187469 16.94% 86.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 70686123 9.13% 95.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 20416273 2.64% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7987184 1.03% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3894628 0.50% 99.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 181343 0.02% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 145648239 18.81% 18.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 184522685 23.83% 42.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 209864984 27.10% 69.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131209019 16.94% 86.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 70693972 9.13% 95.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20392101 2.63% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8014841 1.03% 99.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3879808 0.50% 99.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 182016 0.02% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 774398184 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 774407665 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 118946 7.04% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 95273 5.64% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1158517 68.57% 81.24% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 316903 18.76% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 140362 8.20% 8.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 95230 5.57% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1159729 67.79% 81.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 315506 18.44% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 866474644 59.37% 59.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 866449380 59.37% 59.37% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.37% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2644797 0.18% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 419098125 28.72% 88.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 171121746 11.73% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2644870 0.18% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 419102646 28.72% 88.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 171123037 11.73% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1459339312 # Type of FU issued -system.cpu.iq.rate 1.883915 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1689639 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001158 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3676979008 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1615425319 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1443226704 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 17841022 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9210458 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 8545776 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1451900530 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 9128421 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 215265115 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1459319933 # Type of FU issued +system.cpu.iq.rate 1.883865 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1710827 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001172 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3676966203 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1615362108 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1443197913 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 17845151 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9210352 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 8546882 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1451899562 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 9131198 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 215327027 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 34428392 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 58884 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 245184 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12906236 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 34428974 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 58580 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 245871 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12901231 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3305 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 101102 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3337 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 100836 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 16993227 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3018866 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 247688 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1608835504 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4126277 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 436941235 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 179754378 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2526244 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 149012 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1899 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 245184 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2269311 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1473063 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3742374 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1454021381 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 416550474 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5317931 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 16992580 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3019126 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 247748 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1608802731 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4125538 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 436941817 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 179749373 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2524925 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 149083 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1915 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 245871 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2268919 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1473448 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3742367 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1454001167 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 416555573 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5318766 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 93683614 # number of nop insts executed -system.cpu.iew.exec_refs 586997386 # number of memory reference insts executed -system.cpu.iew.exec_branches 89036634 # Number of branches executed -system.cpu.iew.exec_stores 170446912 # Number of stores executed -system.cpu.iew.exec_rate 1.877050 # Inst execution rate -system.cpu.iew.wb_sent 1452648479 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1451772480 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1153427719 # num instructions producing a value -system.cpu.iew.wb_consumers 1204682131 # num instructions consuming a value +system.cpu.iew.exec_nop 93683374 # number of nop insts executed +system.cpu.iew.exec_refs 587003910 # number of memory reference insts executed +system.cpu.iew.exec_branches 89035290 # Number of branches executed +system.cpu.iew.exec_stores 170448337 # Number of stores executed +system.cpu.iew.exec_rate 1.876999 # Inst execution rate +system.cpu.iew.wb_sent 1452626666 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1451744795 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1153395564 # num instructions producing a value +system.cpu.iew.wb_consumers 1204642088 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.874147 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.957454 # average fanout of values written-back +system.cpu.iew.wb_rate 1.874086 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.957459 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 119216890 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 119183948 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3614520 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 757404957 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.966614 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.509691 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3614513 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 757415085 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.966588 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.509597 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 239974569 31.68% 31.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 275852046 36.42% 68.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 42571811 5.62% 73.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 54691782 7.22% 80.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19624283 2.59% 83.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13282059 1.75% 85.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 30580381 4.04% 89.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10561653 1.39% 90.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 70266373 9.28% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 240000251 31.69% 31.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 275796766 36.41% 68.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 42566622 5.62% 73.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 54725654 7.23% 80.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19677570 2.60% 83.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13283245 1.75% 85.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 30556171 4.03% 89.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10517669 1.39% 90.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 70291137 9.28% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 757404957 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 757415085 # Number of insts commited each cycle system.cpu.commit.committedInsts 1485108088 # Number of instructions committed system.cpu.commit.committedOps 1489523282 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -442,70 +427,70 @@ system.cpu.commit.branches 86248928 # Nu system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. system.cpu.commit.int_insts 1319476376 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 70266373 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 70291137 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2295813886 # The number of ROB reads -system.cpu.rob.rob_writes 3234496299 # The number of ROB writes -system.cpu.timesIdled 25967 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 232832 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2295766308 # The number of ROB reads +system.cpu.rob.rob_writes 3234429823 # The number of ROB writes +system.cpu.timesIdled 26016 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 233789 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1401188945 # Number of Instructions Simulated system.cpu.committedOps 1405604139 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1401188945 # Number of Instructions Simulated -system.cpu.cpi 0.552838 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.552838 # CPI: Total CPI of All Threads -system.cpu.ipc 1.808847 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.808847 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1979103244 # number of integer regfile reads -system.cpu.int_regfile_writes 1275174788 # number of integer regfile writes -system.cpu.fp_regfile_reads 16962430 # number of floating regfile reads -system.cpu.fp_regfile_writes 10491706 # number of floating regfile writes -system.cpu.misc_regfile_reads 592650972 # number of misc regfile reads +system.cpu.cpi 0.552846 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.552846 # CPI: Total CPI of All Threads +system.cpu.ipc 1.808823 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.808823 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1979081340 # number of integer regfile reads +system.cpu.int_regfile_writes 1275150411 # number of integer regfile writes +system.cpu.fp_regfile_reads 16965180 # number of floating regfile reads +system.cpu.fp_regfile_writes 10491866 # number of floating regfile writes +system.cpu.misc_regfile_reads 592655969 # number of misc regfile reads system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes -system.cpu.icache.replacements 197 # number of replacements -system.cpu.icache.tagsinuse 1035.237714 # Cycle average of tags in use -system.cpu.icache.total_refs 161935084 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1336 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 121208.895210 # Average number of references to valid blocks. +system.cpu.icache.replacements 200 # number of replacements +system.cpu.icache.tagsinuse 1035.615179 # Cycle average of tags in use +system.cpu.icache.total_refs 161931886 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1338 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 121025.325859 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1035.237714 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.505487 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.505487 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 161935084 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 161935084 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 161935084 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 161935084 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 161935084 # number of overall hits -system.cpu.icache.overall_hits::total 161935084 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1939 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1939 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1939 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1939 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1939 # number of overall misses -system.cpu.icache.overall_misses::total 1939 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 84566500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 84566500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 84566500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 84566500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 84566500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 84566500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 161937023 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 161937023 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 161937023 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 161937023 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 161937023 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 161937023 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1035.615179 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.505671 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.505671 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 161931886 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 161931886 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 161931886 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 161931886 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 161931886 # number of overall hits +system.cpu.icache.overall_hits::total 161931886 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1937 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1937 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1937 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1937 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1937 # number of overall misses +system.cpu.icache.overall_misses::total 1937 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 85579500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 85579500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 85579500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 85579500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 85579500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 85579500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 161933823 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 161933823 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 161933823 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 161933823 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 161933823 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 161933823 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000012 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000012 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000012 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43613.460547 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 43613.460547 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 43613.460547 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 43613.460547 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 43613.460547 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 43613.460547 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44181.466185 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 44181.466185 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 44181.466185 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 44181.466185 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 44181.466185 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 44181.466185 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -514,120 +499,120 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 31.750000 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 602 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 602 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 602 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 602 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 602 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 602 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1337 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1337 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1337 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1337 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1337 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1337 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 62189000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 62189000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 62189000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 62189000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 62189000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 62189000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 598 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 598 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 598 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 598 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 598 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 598 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1339 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1339 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1339 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1339 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1339 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1339 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 62434000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 62434000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 62434000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 62434000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 62434000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 62434000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000008 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000008 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 46513.836948 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 46513.836948 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 46513.836948 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 46513.836948 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 46513.836948 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 46513.836948 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 46627.333831 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 46627.333831 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 46627.333831 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 46627.333831 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 46627.333831 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 46627.333831 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2556 # number of replacements -system.cpu.l2cache.tagsinuse 22451.693912 # Cycle average of tags in use -system.cpu.l2cache.total_refs 550222 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 24270 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.670869 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 22454.455372 # Cycle average of tags in use +system.cpu.l2cache.total_refs 550476 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 24273 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 22.678532 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20743.567402 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1060.766368 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 647.360142 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.633043 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.032372 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019756 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.685171 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 140 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 196406 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 196546 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 443933 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 443933 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 240653 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 240653 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 140 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 437059 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 437199 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 140 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 437059 # number of overall hits -system.cpu.l2cache.overall_hits::total 437199 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1197 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 4444 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 5641 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 21783 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 21783 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1197 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 26227 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 27424 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1197 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 26227 # number of overall misses -system.cpu.l2cache.overall_misses::total 27424 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 59434000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 444973500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 504407500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1588740500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1588740500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 59434000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 2033714000 # number of demand (read+write) miss cycles +system.cpu.l2cache.occ_blocks::writebacks 20744.724619 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1061.167682 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 648.563071 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.633079 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.032384 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.019793 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.685256 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 143 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 196431 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 196574 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 443982 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 443982 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 240656 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 240656 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 143 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 437087 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 437230 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 143 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 437087 # number of overall hits +system.cpu.l2cache.overall_hits::total 437230 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1196 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 4446 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 5642 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 21785 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 21785 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1196 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 26231 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 27427 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1196 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 26231 # number of overall misses +system.cpu.l2cache.overall_misses::total 27427 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 59648000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 445587500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 505235500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1587912500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1587912500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 59648000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 2033500000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 2093148000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 59434000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 2033714000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 59648000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2033500000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 2093148000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1337 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 200850 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 202187 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 443933 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 443933 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 262436 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 262436 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1337 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 463286 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 464623 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1337 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 463286 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 464623 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.895288 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022126 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.027900 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083003 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.083003 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.895288 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.056611 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.059024 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.895288 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.056611 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.059024 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49652.464495 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 100129.050405 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 89418.099628 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72934.880411 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72934.880411 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49652.464495 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77542.761277 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76325.408401 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49652.464495 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77542.761277 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76325.408401 # average overall miss latency +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1339 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 200877 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 202216 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 443982 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 443982 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 262441 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 262441 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1339 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 463318 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 464657 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1339 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 463318 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 464657 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.893204 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022133 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.027901 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083009 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.083009 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.893204 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.056616 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.059026 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.893204 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.056616 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.059026 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49872.909699 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 100222.109762 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 89549.007444 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72890.176727 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72890.176727 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49872.909699 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77522.778392 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76317.059832 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49872.909699 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77522.778392 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76317.059832 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -638,160 +623,160 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 2533 # number of writebacks system.cpu.l2cache.writebacks::total 2533 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1197 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4444 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5641 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21783 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21783 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1197 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 26227 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 27424 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1197 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 26227 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 27424 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 44575992 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 389548209 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 434124201 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1319276658 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1319276658 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44575992 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1708824867 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1753400859 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44575992 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1708824867 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1753400859 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.895288 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022126 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027900 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083003 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083003 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.895288 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056611 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.059024 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.895288 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056611 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.059024 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37239.759398 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 87657.112736 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76958.730899 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60564.507093 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60564.507093 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37239.759398 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65155.178518 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63936.729106 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37239.759398 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65155.178518 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63936.729106 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1196 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4446 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5642 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21785 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21785 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1196 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26231 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27427 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1196 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 26231 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 27427 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 44803245 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 390135886 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 434939131 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1318424366 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1318424366 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44803245 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1708560252 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1753363497 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44803245 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1708560252 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1753363497 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.893204 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022133 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027901 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083009 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083009 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.893204 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056616 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.059026 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.893204 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056616 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.059026 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37460.907191 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 87749.861898 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77089.530486 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60519.824007 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60519.824007 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37460.907191 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65135.155046 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63928.373391 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37460.907191 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65135.155046 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63928.373391 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 459190 # number of replacements -system.cpu.dcache.tagsinuse 4093.797590 # Cycle average of tags in use -system.cpu.dcache.total_refs 365198263 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 463286 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 788.278219 # Average number of references to valid blocks. +system.cpu.dcache.replacements 459222 # number of replacements +system.cpu.dcache.tagsinuse 4093.797620 # Cycle average of tags in use +system.cpu.dcache.total_refs 365142346 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 463318 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 788.103087 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 340173000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.797590 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4093.797620 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999462 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999462 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 200241495 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 200241495 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 164955449 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 164955449 # number of WriteReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 200185442 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 200185442 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 164955585 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 164955585 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 365196944 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 365196944 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 365196944 # number of overall hits -system.cpu.dcache.overall_hits::total 365196944 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 923055 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 923055 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1891367 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1891367 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 365141027 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 365141027 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 365141027 # number of overall hits +system.cpu.dcache.overall_hits::total 365141027 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 923072 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 923072 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1891231 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1891231 # number of WriteReq misses system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 2814422 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2814422 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2814422 # number of overall misses -system.cpu.dcache.overall_misses::total 2814422 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14739603500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14739603500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 31907348686 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 31907348686 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 2814303 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2814303 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2814303 # number of overall misses +system.cpu.dcache.overall_misses::total 2814303 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14740246000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14740246000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31916028682 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 31916028682 # number of WriteReq miss cycles system.cpu.dcache.SwapReq_miss_latency::cpu.data 150000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_latency::total 150000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 46646952186 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 46646952186 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 46646952186 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 46646952186 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 201164550 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 201164550 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 46656274682 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 46656274682 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 46656274682 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 46656274682 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 201108514 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 201108514 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 368011366 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 368011366 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 368011366 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 368011366 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004589 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004589 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011336 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.011336 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 367955330 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 367955330 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 367955330 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 367955330 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004590 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004590 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011335 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.011335 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.007648 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.007648 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.007648 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.007648 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15968.283038 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15968.283038 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16869.993336 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16869.993336 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15968.685000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15968.685000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16875.796073 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16875.796073 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 21428.571429 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::total 21428.571429 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16574.256521 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16574.256521 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16574.256521 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16574.256521 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 590116 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 5 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 35661 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16578.269888 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16578.269888 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16578.269888 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16578.269888 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 588860 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 17 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 35662 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.547938 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 5 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.512254 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 17 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 443933 # number of writebacks -system.cpu.dcache.writebacks::total 443933 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 722205 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 722205 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1628938 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1628938 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2351143 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2351143 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2351143 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2351143 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200850 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 200850 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262429 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 262429 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 443982 # number of writebacks +system.cpu.dcache.writebacks::total 443982 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 722195 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 722195 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1628797 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1628797 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2350992 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2350992 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2350992 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2350992 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200877 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 200877 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262434 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 262434 # number of WriteReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 463279 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 463279 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 463279 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 463279 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2612152000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2612152000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4357934500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4357934500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 463311 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 463311 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 463311 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 463311 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2613052500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2613052500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4357141500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4357141500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 136000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::total 136000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6970086500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6970086500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6970086500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6970086500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000998 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000998 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6970194000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6970194000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6970194000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6970194000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000999 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000999 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001573 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001573 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses @@ -800,16 +785,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001259 system.cpu.dcache.demand_mshr_miss_rate::total 0.001259 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001259 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001259 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13005.486682 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13005.486682 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16606.146805 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16606.146805 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13008.221449 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13008.221449 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16602.808706 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16602.808706 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 19428.571429 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 19428.571429 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15045.116442 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15045.116442 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15045.116442 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15045.116442 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15044.309330 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15044.309330 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15044.309330 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15044.309330 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index dc034cfd1..6ca2fc4f2 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.607292 # Nu sim_ticks 607292111000 # Number of ticks simulated final_tick 607292111000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91190 # Simulator instruction rate (inst/s) -host_op_rate 168022 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62928697 # Simulator tick rate (ticks/s) -host_mem_usage 248736 # Number of bytes of host memory used -host_seconds 9650.48 # Real time elapsed on the host +host_inst_rate 88731 # Simulator instruction rate (inst/s) +host_op_rate 163492 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61232046 # Simulator tick rate (ticks/s) +host_mem_usage 248756 # Number of bytes of host memory used +host_seconds 9917.88 # Real time elapsed on the host sim_insts 880025277 # Number of instructions simulated sim_ops 1621493926 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 57664 # Number of bytes read from this memory @@ -85,26 +85,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 27359 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 2534 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 2534 # Categorize write packet sizes system.physmem.rdQLenPdf::0 26892 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 344 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 100 # What read queue length does an incoming req see @@ -137,7 +124,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see @@ -170,15 +156,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 90448613 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 895548613 # Sum of mem lat for all requests +system.physmem.totQLat 90421500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 895535250 # Sum of mem lat for all requests system.physmem.totBusLat 136795000 # Total cycles spent in databus access -system.physmem.totBankLat 668305000 # Total cycles spent in bank access -system.physmem.avgQLat 3305.99 # Average queueing delay per request -system.physmem.avgBankLat 24427.25 # Average bank access latency per request +system.physmem.totBankLat 668318750 # Total cycles spent in bank access +system.physmem.avgQLat 3305.00 # Average queueing delay per request +system.physmem.avgBankLat 24427.75 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32733.24 # Average memory access latency +system.physmem.avgMemAccLat 32732.75 # Average memory access latency system.physmem.avgRdBW 2.88 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.27 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.88 # Average consumed read bandwidth in MB/s @@ -235,22 +220,22 @@ system.cpu.fetch.rateDist::max_value 8 # Nu system.cpu.fetch.rateDist::total 1214221440 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.130483 # Number of branch fetches per cycle system.cpu.fetch.rate 1.200203 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 288175293 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 497913619 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 274106217 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 92482436 # Number of cycles decode is unblocking +system.cpu.decode.IdleCycles 288175297 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 497913615 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 274106209 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 92482444 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 61543875 # Number of cycles decode is squashing system.cpu.decode.DecodedInsts 2343534245 # Number of instructions handled by decode system.cpu.rename.SquashCycles 61543875 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 336850045 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 336850046 # Number of cycles rename is idle system.cpu.rename.BlockCycles 124204658 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 2567 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 303948664 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 387671631 # Number of cycles rename is unblocking +system.cpu.rename.RunCycles 303948666 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 387671628 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 2247678746 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 360 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 242705543 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 120202916 # Number of times rename has blocked due to LSQ full +system.cpu.rename.IQFullEvents 242705531 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 120202926 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 2618040036 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 5722358621 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 5722353197 # Number of integer rename lookups @@ -259,11 +244,11 @@ system.cpu.rename.CommittedMaps 1886895258 # Nu system.cpu.rename.UndoneMaps 731144778 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 87 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 87 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 731406447 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 731406444 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 531670409 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 219217246 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 342048419 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 144614488 # Number of conflicting stores. +system.cpu.memDep0.conflictingStores 144614487 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 1993488562 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 286 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 1783952231 # Number of instructions issued @@ -275,12 +260,12 @@ system.cpu.iq.issued_per_cycle::samples 1214221440 # Nu system.cpu.iq.issued_per_cycle::mean 1.469215 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.421905 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 360233763 29.67% 29.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 364161192 29.99% 59.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 234288879 19.30% 78.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 141409866 11.65% 90.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 60623194 4.99% 95.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 39782569 3.28% 98.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 360233765 29.67% 29.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 364161190 29.99% 59.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 234288875 19.30% 78.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 141409873 11.65% 90.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 60623190 4.99% 95.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 39782570 3.28% 98.87% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 11078669 0.91% 99.78% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 2040416 0.17% 99.95% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 602892 0.05% 100.00% # Number of insts issued each cycle @@ -368,7 +353,7 @@ system.cpu.iq.fp_inst_queue_writes 1776 # Nu system.cpu.iq.fp_inst_queue_wakeup_accesses 123 # Number of floating instruction queue wakeup accesses system.cpu.iq.int_alu_accesses 1740037802 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 245 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 210029942 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 210029946 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 112628288 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 39424 # Number of memory responses ignored because the instruction is squashed @@ -404,8 +389,8 @@ system.cpu.iew.exec_stores 191706202 # Nu system.cpu.iew.exec_rate 1.454114 # Inst execution rate system.cpu.iew.wb_sent 1725748007 # cumulative count of insts sent to commit system.cpu.iew.wb_count 1724635217 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1267063012 # num instructions producing a value -system.cpu.iew.wb_consumers 1828799696 # num instructions consuming a value +system.cpu.iew.wb_producers 1267063011 # num instructions producing a value +system.cpu.iew.wb_consumers 1828799692 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 1.419939 # insts written-back per cycle system.cpu.iew.wb_fanout 0.692839 # average fanout of values written-back @@ -583,14 +568,14 @@ system.cpu.l2cache.overall_misses::total 27359 # nu system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46268500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 330234500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 376503000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1134971000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1134971000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1134984000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1134984000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 46268500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1465205500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1511474000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1465218500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1511487000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 46268500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1465205500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1511474000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1465218500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1511487000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 918 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 203811 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 204729 # number of ReadReq accesses(hits+misses) @@ -620,14 +605,14 @@ system.cpu.l2cache.overall_miss_rate::total 0.060649 # system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51352.386238 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72403.968428 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 68931.343830 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51832.260127 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51832.260127 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51832.853816 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51832.853816 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51352.386238 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55378.543352 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 55245.951972 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55379.034697 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 55246.427135 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51352.386238 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55378.543352 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 55245.951972 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55379.034697 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 55246.427135 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -649,17 +634,17 @@ system.cpu.l2cache.demand_mshr_misses::total 27359 system.cpu.l2cache.overall_mshr_misses::cpu.inst 901 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 26458 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 27359 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35083215 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 273211469 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 308294684 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 862598556 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 862598556 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35083215 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1135810025 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1170893240 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35083215 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1135810025 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1170893240 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35082483 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 273207016 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 308289499 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 862590617 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 862590617 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35082483 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1135797633 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1170880116 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35082483 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1135797633 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1170880116 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022379 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.026679 # mshr miss rate for ReadReq accesses @@ -671,35 +656,35 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.060649 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.981481 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058772 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.060649 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38938.085461 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59901.659504 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56443.552545 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39393.458282 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39393.458282 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38938.085461 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42928.793749 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42797.369787 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38938.085461 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42928.793749 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42797.369787 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38937.273030 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59900.683184 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56442.603259 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39393.095721 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39393.095721 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38937.273030 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42928.325384 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42796.890091 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38937.273030 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42928.325384 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42796.890091 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 446086 # number of replacements system.cpu.dcache.tagsinuse 4092.713768 # Cycle average of tags in use -system.cpu.dcache.total_refs 452307982 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 452307978 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 450182 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 1004.722494 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 1004.722486 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 861652000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 4092.713768 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999198 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999198 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 264368372 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 264368372 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 264368368 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 264368368 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 187939603 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 187939603 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 452307975 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 452307975 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 452307975 # number of overall hits -system.cpu.dcache.overall_hits::total 452307975 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 452307971 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 452307971 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 452307971 # number of overall hits +system.cpu.dcache.overall_hits::total 452307971 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 211281 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 211281 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 246455 # number of WriteReq misses @@ -710,20 +695,20 @@ system.cpu.dcache.overall_misses::cpu.data 457736 # system.cpu.dcache.overall_misses::total 457736 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 3022618500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 3022618500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4119755500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4119755500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7142374000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7142374000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7142374000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7142374000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 264579653 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 264579653 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4119768500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4119768500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7142387000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7142387000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7142387000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7142387000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 264579649 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 264579649 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 188186058 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 188186058 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 452765711 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 452765711 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 452765711 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 452765711 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 452765707 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 452765707 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 452765707 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 452765707 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000799 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000799 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001310 # miss rate for WriteReq accesses @@ -734,12 +719,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.001011 system.cpu.dcache.overall_miss_rate::total 0.001011 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14306.153890 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 14306.153890 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16716.055669 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16716.055669 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15603.697328 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15603.697328 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15603.697328 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15603.697328 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16716.108417 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16716.108417 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15603.725728 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15603.725728 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15603.725728 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15603.725728 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 365 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 40 # number of cycles access was blocked @@ -768,12 +753,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 450191 system.cpu.dcache.overall_mshr_misses::total 450191 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2528414500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 2528414500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3626209000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3626209000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6154623500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6154623500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6154623500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6154623500 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3626222000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3626222000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6154636500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6154636500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6154636500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6154636500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000770 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000770 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001309 # mshr miss rate for WriteReq accesses @@ -784,12 +769,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000994 system.cpu.dcache.overall_mshr_miss_rate::total 0.000994 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12405.317025 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12405.317025 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14718.310374 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14718.310374 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13671.138472 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13671.138472 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13671.138472 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13671.138472 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14718.363139 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14718.363139 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13671.167349 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13671.167349 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13671.167349 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13671.167349 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index b0849c006..e47377a85 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026779 # Number of seconds simulated -sim_ticks 26779468500 # Number of ticks simulated -final_tick 26779468500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026786 # Number of seconds simulated +sim_ticks 26785824500 # Number of ticks simulated +final_tick 26785824500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 196675 # Simulator instruction rate (inst/s) -host_op_rate 198087 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58139571 # Simulator tick rate (ticks/s) -host_mem_usage 373976 # Number of bytes of host memory used -host_seconds 460.61 # Real time elapsed on the host +host_inst_rate 121944 # Simulator instruction rate (inst/s) +host_op_rate 122819 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36056613 # Simulator tick rate (ticks/s) +host_mem_usage 374016 # Number of bytes of host memory used +host_seconds 742.88 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated sim_ops 91240351 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 45248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 44992 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 947840 # Number of bytes read from this memory -system.physmem.bytes_read::total 993088 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 45248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 45248 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 707 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 992832 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44992 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 703 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14810 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15517 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1689653 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 35394280 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 37083932 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1689653 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1689653 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1689653 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 35394280 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 37083932 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15517 # Total number of read requests seen +system.physmem.num_reads::total 15513 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1679694 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 35385881 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 37065575 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1679694 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1679694 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1679694 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 35385881 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 37065575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15513 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 15520 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 993088 # Total number of bytes read from memory +system.physmem.cpureqs 15516 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 992832 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 993088 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 992832 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 3 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 997 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 996 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 960 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 997 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 1012 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 996 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 1013 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 926 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 925 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 882 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 885 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 951 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 993 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 992 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 1001 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 966 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 968 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 968 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1002 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1001 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,37 +70,24 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 26779289500 # Total gap between requests +system.physmem.totGap 26785652500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 15517 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 3 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 10168 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 5067 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 252 # What read queue length does an incoming req see +system.physmem.readPktSize::6 15513 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 10163 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 5065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 255 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,37 +149,36 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 52084984 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 311719984 # Sum of mem lat for all requests -system.physmem.totBusLat 77585000 # Total cycles spent in databus access -system.physmem.totBankLat 182050000 # Total cycles spent in bank access -system.physmem.avgQLat 3356.64 # Average queueing delay per request -system.physmem.avgBankLat 11732.29 # Average bank access latency per request +system.physmem.totQLat 55611750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 315006750 # Sum of mem lat for all requests +system.physmem.totBusLat 77565000 # Total cycles spent in databus access +system.physmem.totBankLat 181830000 # Total cycles spent in bank access +system.physmem.avgQLat 3584.85 # Average queueing delay per request +system.physmem.avgBankLat 11721.14 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 20088.93 # Average memory access latency -system.physmem.avgRdBW 37.08 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 20305.99 # Average memory access latency +system.physmem.avgRdBW 37.07 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 37.08 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 37.07 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.29 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 14783 # Number of row buffer hits during reads +system.physmem.readRowHits 14781 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.27 # Row buffer hit rate for reads +system.physmem.readRowHitRate 95.28 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 1725803.28 # Average gap between requests -system.cpu.branchPred.lookups 26678818 # Number of BP lookups -system.cpu.branchPred.condPredicted 21998913 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 842318 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11366409 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11281153 # Number of BTB hits +system.physmem.avgGap 1726658.45 # Average gap between requests +system.cpu.branchPred.lookups 26682480 # Number of BP lookups +system.cpu.branchPred.condPredicted 22002618 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 841998 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11368270 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11282813 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.249930 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 69723 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 201 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.248285 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 69658 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 194 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -237,239 +222,239 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 53558938 # number of cpu cycles simulated +system.cpu.numCycles 53571650 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 14172731 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 127871641 # Number of instructions fetch has processed -system.cpu.fetch.Branches 26678818 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11350876 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24033181 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4760167 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 11226793 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 14170612 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 127882618 # Number of instructions fetch has processed +system.cpu.fetch.Branches 26682480 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11352471 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24034762 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4762849 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 11235788 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 94 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13844867 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 331224 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 53334396 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.414044 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.215935 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 13843090 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 329835 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 53345786 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.413719 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.215837 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 29339451 55.01% 55.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3389540 6.36% 61.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2028066 3.80% 65.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1555662 2.92% 68.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1667100 3.13% 71.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2918330 5.47% 76.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1510510 2.83% 79.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1090066 2.04% 81.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9835671 18.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 29349323 55.02% 55.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3389433 6.35% 61.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2028287 3.80% 65.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1555177 2.92% 68.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1667492 3.13% 71.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2918592 5.47% 76.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1510888 2.83% 79.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1090794 2.04% 81.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9835800 18.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 53334396 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.498121 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.387494 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16935376 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9075535 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22432463 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 998016 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3893006 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4442432 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 8659 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 126044255 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 42607 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3893006 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18714710 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3545279 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 156066 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21549370 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5475965 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 123134352 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 422701 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4592939 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1259 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 143588919 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 536358187 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 536353466 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4721 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 53345786 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.498071 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.387132 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16933018 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9083258 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 22434897 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 998703 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3895910 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4442085 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 8696 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 126062223 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42630 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3895910 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18712984 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3548131 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 156179 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21551652 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5480930 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 123149853 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 23 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 423091 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4597179 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1286 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 143608098 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 536423645 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 536418417 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 5228 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36174733 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4601 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4599 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12509318 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29470006 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5522308 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2104178 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1264650 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 118149095 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 8470 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105144375 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 78107 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26722736 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65554797 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 252 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 53334396 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.971418 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.910922 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 36193912 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4607 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4605 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12518412 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29475899 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5522776 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2125822 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1253238 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 118167784 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8472 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105151160 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 77497 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26739027 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65605268 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 254 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 53345786 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.971124 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.910487 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15312252 28.71% 28.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11634281 21.81% 50.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8274633 15.51% 66.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6753758 12.66% 78.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4949297 9.28% 87.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2972831 5.57% 93.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2466224 4.62% 98.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 528093 0.99% 99.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 443027 0.83% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15316861 28.71% 28.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11639595 21.82% 50.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8263506 15.49% 66.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6760248 12.67% 78.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4974624 9.33% 88.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2955128 5.54% 93.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2464546 4.62% 98.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 527827 0.99% 99.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 443451 0.83% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 53334396 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 53345786 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 44474 6.73% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 340155 51.46% 58.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 276363 41.81% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 44563 6.73% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 340033 51.38% 58.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 277229 41.89% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74414194 70.77% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10982 0.01% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 3 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 143 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 186 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25601639 24.35% 95.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5117225 4.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74420309 70.77% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10977 0.01% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 155 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 201 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25602989 24.35% 95.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5116524 4.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105144375 # Type of FU issued -system.cpu.iq.rate 1.963153 # Inst issue rate -system.cpu.iq.fu_busy_cnt 661019 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006287 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 264361545 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 144884747 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102673470 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 727 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1011 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 322 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 105805031 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 363 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 444404 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 105151160 # Type of FU issued +system.cpu.iq.rate 1.962814 # Inst issue rate +system.cpu.iq.fu_busy_cnt 661852 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006294 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 264386671 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 144919691 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102682625 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 784 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1077 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 339 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 105812622 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 390 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 443741 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6896040 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6651 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6197 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 777464 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6901933 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6293 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6180 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 777932 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 31327 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 31373 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3893006 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 929576 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 127351 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 118170277 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 309597 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29470006 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5522308 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4582 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 66448 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6858 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6197 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 446675 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 445546 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 892221 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104166430 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25281924 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 977945 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3895910 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 928973 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 127070 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 118188976 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 309212 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29475899 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5522776 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4584 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 66075 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6911 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6180 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 446439 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 445443 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 891882 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104175676 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25284542 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 975484 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12712 # number of nop insts executed -system.cpu.iew.exec_refs 30342174 # number of memory reference insts executed -system.cpu.iew.exec_branches 21323986 # Number of branches executed -system.cpu.iew.exec_stores 5060250 # Number of stores executed -system.cpu.iew.exec_rate 1.944893 # Inst execution rate -system.cpu.iew.wb_sent 102951824 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102673792 # cumulative count of insts written-back -system.cpu.iew.wb_producers 62219945 # num instructions producing a value -system.cpu.iew.wb_consumers 104261628 # num instructions consuming a value +system.cpu.iew.exec_nop 12720 # number of nop insts executed +system.cpu.iew.exec_refs 30343976 # number of memory reference insts executed +system.cpu.iew.exec_branches 21325145 # Number of branches executed +system.cpu.iew.exec_stores 5059434 # Number of stores executed +system.cpu.iew.exec_rate 1.944605 # Inst execution rate +system.cpu.iew.wb_sent 102960011 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102682964 # cumulative count of insts written-back +system.cpu.iew.wb_producers 62233069 # num instructions producing a value +system.cpu.iew.wb_consumers 104282875 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.917024 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.596767 # average fanout of values written-back +system.cpu.iew.wb_rate 1.916741 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.596772 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 26920302 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 26939053 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 833747 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 49441390 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.845680 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.541256 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 833398 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 49449876 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.845363 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.541608 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19945415 40.34% 40.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13149428 26.60% 66.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4162611 8.42% 75.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3435070 6.95% 82.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1540295 3.12% 85.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 748484 1.51% 86.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 932633 1.89% 88.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 245930 0.50% 89.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5281524 10.68% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 19967148 40.38% 40.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13135707 26.56% 66.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4163389 8.42% 75.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3434332 6.95% 82.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1535763 3.11% 85.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 744463 1.51% 86.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 942034 1.91% 88.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 246412 0.50% 89.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5280628 10.68% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 49441390 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 49449876 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602407 # Number of instructions committed system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -480,70 +465,70 @@ system.cpu.commit.branches 18732304 # Nu system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. system.cpu.commit.int_insts 72525674 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5281524 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5280628 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 162327394 # The number of ROB reads -system.cpu.rob.rob_writes 240259263 # The number of ROB writes -system.cpu.timesIdled 43763 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 224542 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 162355527 # The number of ROB reads +system.cpu.rob.rob_writes 240299704 # The number of ROB writes +system.cpu.timesIdled 43654 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 225864 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589798 # Number of Instructions Simulated system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated -system.cpu.cpi 0.591225 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.591225 # CPI: Total CPI of All Threads -system.cpu.ipc 1.691404 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.691404 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 495495273 # number of integer regfile reads -system.cpu.int_regfile_writes 120530797 # number of integer regfile writes -system.cpu.fp_regfile_reads 175 # number of floating regfile reads -system.cpu.fp_regfile_writes 405 # number of floating regfile writes -system.cpu.misc_regfile_reads 29088840 # number of misc regfile reads +system.cpu.cpi 0.591365 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.591365 # CPI: Total CPI of All Threads +system.cpu.ipc 1.691003 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.691003 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 495535708 # number of integer regfile reads +system.cpu.int_regfile_writes 120542575 # number of integer regfile writes +system.cpu.fp_regfile_reads 173 # number of floating regfile reads +system.cpu.fp_regfile_writes 431 # number of floating regfile writes +system.cpu.misc_regfile_reads 29089632 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes system.cpu.icache.replacements 3 # number of replacements -system.cpu.icache.tagsinuse 630.551988 # Cycle average of tags in use -system.cpu.icache.total_refs 13843878 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 733 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 18886.600273 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 630.397373 # Cycle average of tags in use +system.cpu.icache.total_refs 13842106 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 728 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 19013.881868 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 630.551988 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.307887 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.307887 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13843878 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13843878 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13843878 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13843878 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13843878 # number of overall hits -system.cpu.icache.overall_hits::total 13843878 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 988 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 988 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 988 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 988 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 988 # number of overall misses -system.cpu.icache.overall_misses::total 988 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 49634499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 49634499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 49634499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 49634499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 49634499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 49634499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13844866 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13844866 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13844866 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13844866 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13844866 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13844866 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 630.397373 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.307811 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.307811 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13842106 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13842106 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13842106 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13842106 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13842106 # number of overall hits +system.cpu.icache.overall_hits::total 13842106 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 983 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 983 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 983 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 983 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 983 # number of overall misses +system.cpu.icache.overall_misses::total 983 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 49432499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 49432499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 49432499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 49432499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 49432499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 49432499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13843089 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13843089 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13843089 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13843089 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13843089 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13843089 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50237.347166 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 50237.347166 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 50237.347166 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 50237.347166 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 50237.347166 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 50237.347166 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50287.384537 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 50287.384537 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 50287.384537 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 50287.384537 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 50287.384537 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 50287.384537 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 502 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked @@ -552,128 +537,128 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 55.777778 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 251 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 251 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 251 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 251 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 251 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 251 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 737 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 737 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 737 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 737 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 737 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 737 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38036999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 38036999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38036999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 38036999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38036999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 38036999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 250 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 250 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 250 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 250 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 250 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 250 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 733 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 733 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 733 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 733 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 733 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 733 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37907999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 37907999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37907999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 37907999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37907999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 37907999 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51610.582090 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51610.582090 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51610.582090 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51610.582090 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51610.582090 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51610.582090 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51716.233288 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51716.233288 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51716.233288 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51716.233288 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51716.233288 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51716.233288 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 10759.564287 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1831570 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 15500 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 118.165806 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 10760.479556 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1831525 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 15496 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 118.193405 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 9910.782646 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 616.871655 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 231.909986 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.302453 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.018825 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 9911.805562 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 616.761334 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 231.912660 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.302484 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.018822 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.007077 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.328356 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 25 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 903763 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 903788 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 942924 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 942924 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 29047 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 29047 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 25 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 932810 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 932835 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 25 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 932810 # number of overall hits -system.cpu.l2cache.overall_hits::total 932835 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 708 # number of ReadReq misses +system.cpu.l2cache.occ_percent::total 0.328384 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 24 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 903743 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 903767 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 942900 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 942900 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 2 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 2 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 29045 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 29045 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 932788 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 932812 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 24 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 932788 # number of overall hits +system.cpu.l2cache.overall_hits::total 932812 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 704 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 281 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 989 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 985 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 3 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 3 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 14539 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 14539 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 708 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 704 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 14820 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 15528 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 708 # number of overall misses +system.cpu.l2cache.demand_misses::total 15524 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 704 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14820 # number of overall misses -system.cpu.l2cache.overall_misses::total 15528 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37036500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 15642500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 52679000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 625286000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 625286000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 37036500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 640928500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 677965000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 37036500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 640928500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 677965000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 733 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 904044 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 904777 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 942924 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 942924 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 4 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 43586 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 43586 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 733 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 947630 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 948363 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 733 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 947630 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 948363 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965894 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_misses::total 15524 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 36918500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 15609500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 52528000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 628655000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 628655000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 36918500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 644264500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 681183000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 36918500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 644264500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 681183000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 728 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 904024 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 904752 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 942900 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 942900 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 5 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 43584 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 43584 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 728 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 947608 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 948336 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 728 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 947608 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 948336 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967033 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000311 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.001093 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.333570 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.333570 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965894 # miss rate for demand accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.001089 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.600000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.600000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.333586 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.333586 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967033 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.015639 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.016373 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965894 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.016370 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967033 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015639 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.016373 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52311.440678 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55667.259786 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 53264.914055 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43007.497077 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43007.497077 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52311.440678 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 43247.537112 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 43660.806285 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52311.440678 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 43247.537112 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 43660.806285 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.016370 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52441.051136 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55549.822064 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 53327.918782 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43239.218653 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43239.218653 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52441.051136 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 43472.638327 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 43879.348106 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52441.051136 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 43472.638327 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 43879.348106 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -691,184 +676,184 @@ system.cpu.l2cache.demand_mshr_hits::total 11 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 707 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 703 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 978 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 974 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14539 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 14539 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 707 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 703 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 14810 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 15517 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 707 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15513 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 703 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14810 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15517 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 28010860 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 11866667 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 39877527 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 15513 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27943554 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 11832709 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 39776263 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 30003 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 30003 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 445060185 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 445060185 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28010860 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 456926852 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 484937712 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28010860 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 456926852 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 484937712 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964529 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 448424221 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 448424221 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27943554 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 460256930 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 488200484 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27943554 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 460256930 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 488200484 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965659 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000300 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001081 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.750000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.750000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.333570 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.333570 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964529 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015628 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016362 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964529 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015628 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016362 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39619.321075 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43788.439114 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40774.567485 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001077 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.333586 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.333586 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965659 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015629 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016358 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965659 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015629 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016358 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39749.009957 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43663.132841 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40838.052361 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 30611.471559 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 30611.471559 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39619.321075 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 30852.589602 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31252.027583 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39619.321075 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 30852.589602 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31252.027583 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 30842.851709 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 30842.851709 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39749.009957 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31077.442944 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31470.410881 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39749.009957 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31077.442944 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31470.410881 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 943534 # number of replacements -system.cpu.dcache.tagsinuse 3674.806480 # Cycle average of tags in use -system.cpu.dcache.total_refs 28135871 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 947630 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 29.690777 # Average number of references to valid blocks. +system.cpu.dcache.replacements 943512 # number of replacements +system.cpu.dcache.tagsinuse 3674.906425 # Cycle average of tags in use +system.cpu.dcache.total_refs 28139228 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 947608 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 29.695009 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 7938358000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3674.806480 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.897170 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.897170 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 23591287 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23591287 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4536767 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4536767 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3920 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3920 # number of LoadLockedReq hits +system.cpu.dcache.occ_blocks::cpu.data 3674.906425 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.897194 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.897194 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 23594668 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23594668 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4536751 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4536751 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3908 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3908 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28128054 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28128054 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28128054 # number of overall hits -system.cpu.dcache.overall_hits::total 28128054 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1173096 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1173096 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 198214 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 198214 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 28131419 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28131419 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28131419 # number of overall hits +system.cpu.dcache.overall_hits::total 28131419 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1172935 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1172935 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 198230 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 198230 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1371310 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1371310 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1371310 # number of overall misses -system.cpu.dcache.overall_misses::total 1371310 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13884435000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13884435000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5574763392 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5574763392 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 1371165 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1371165 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1371165 # number of overall misses +system.cpu.dcache.overall_misses::total 1371165 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13884681000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13884681000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5602018407 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5602018407 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 247000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 247000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19459198392 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19459198392 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19459198392 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19459198392 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24764383 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24764383 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 19486699407 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19486699407 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19486699407 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19486699407 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24767603 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24767603 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3926 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3926 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3914 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3914 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29499364 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29499364 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29499364 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29499364 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047370 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.047370 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041862 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.041862 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001528 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001528 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.046486 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.046486 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.046486 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.046486 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11835.719327 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11835.719327 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28124.972969 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28124.972969 # average WriteReq miss latency +system.cpu.dcache.demand_accesses::cpu.data 29502584 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29502584 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29502584 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29502584 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047358 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.047358 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041865 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.041865 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001533 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001533 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.046476 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.046476 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.046476 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.046476 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11837.553658 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11837.553658 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28260.194759 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28260.194759 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 41166.666667 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 41166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14190.225691 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14190.225691 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14190.225691 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14190.225691 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 152485 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14211.782978 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14211.782978 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14211.782978 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14211.782978 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 152466 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 23871 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 23833 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.387877 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.397264 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942924 # number of writebacks -system.cpu.dcache.writebacks::total 942924 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269038 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 269038 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154638 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 154638 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 942900 # number of writebacks +system.cpu.dcache.writebacks::total 942900 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 268897 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 268897 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154655 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 154655 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 423676 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 423676 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 423676 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 423676 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904058 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 904058 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43576 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43576 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947634 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947634 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947634 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947634 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9990434000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9990434000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 980693945 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 980693945 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10971127945 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10971127945 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10971127945 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10971127945 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036506 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036506 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 423552 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 423552 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 423552 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 423552 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904038 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 904038 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43575 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43575 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947613 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947613 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947613 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947613 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9990153500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9990153500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 984037459 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 984037459 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10974190959 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10974190959 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10974190959 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10974190959 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036501 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036501 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009203 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009203 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032124 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.032124 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032124 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032124 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11050.656042 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11050.656042 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22505.368666 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22505.368666 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11577.389525 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11577.389525 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11577.389525 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11577.389525 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032120 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032120 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032120 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032120 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11050.590241 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11050.590241 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22582.615238 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22582.615238 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11580.878438 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11580.878438 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11580.878438 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11580.878438 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 8e442dc5d..c14a5bb89 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,114 +1,101 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.066005 # Number of seconds simulated -sim_ticks 66004575000 # Number of ticks simulated -final_tick 66004575000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.066022 # Number of seconds simulated +sim_ticks 66021796500 # Number of ticks simulated +final_tick 66021796500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 124260 # Simulator instruction rate (inst/s) -host_op_rate 218802 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51913433 # Simulator tick rate (ticks/s) -host_mem_usage 384868 # Number of bytes of host memory used -host_seconds 1271.44 # Real time elapsed on the host +host_inst_rate 92381 # Simulator instruction rate (inst/s) +host_op_rate 162668 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38604948 # Simulator tick rate (ticks/s) +host_mem_usage 384888 # Number of bytes of host memory used +host_seconds 1710.19 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192463 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 65088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1882560 # Number of bytes read from this memory -system.physmem.bytes_read::total 1947648 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 65088 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 65088 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10816 # Number of bytes written to this memory -system.physmem.bytes_written::total 10816 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1017 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29415 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30432 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 169 # Number of write requests responded to by this memory -system.physmem.num_writes::total 169 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 986113 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 28521659 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 29507773 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 986113 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 986113 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 163867 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 163867 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 163867 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 986113 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 28521659 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 29671640 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30434 # Total number of read requests seen -system.physmem.writeReqs 169 # Total number of write requests seen -system.physmem.cpureqs 30604 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1947648 # Total number of bytes read from memory -system.physmem.bytesWritten 10816 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1947648 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 10816 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 60 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 64832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1881664 # Number of bytes read from this memory +system.physmem.bytes_read::total 1946496 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 64832 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 64832 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9856 # Number of bytes written to this memory +system.physmem.bytes_written::total 9856 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1013 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29401 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30414 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 154 # Number of write requests responded to by this memory +system.physmem.num_writes::total 154 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 981979 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28500648 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29482627 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 981979 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 981979 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 149284 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 149284 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 149284 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 981979 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 28500648 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 29631911 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30416 # Total number of read requests seen +system.physmem.writeReqs 154 # Total number of write requests seen +system.physmem.cpureqs 30571 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1946496 # Total number of bytes read from memory +system.physmem.bytesWritten 9856 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1946496 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 9856 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 46 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 1 # Reqs where no action is needed system.physmem.perBankRdReqs::0 1928 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1909 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1972 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1959 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1883 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1865 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1906 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1973 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1961 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1879 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1864 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 1928 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 1952 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1932 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1937 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1870 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1874 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1846 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1891 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1931 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1939 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1872 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1873 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1845 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1890 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 1830 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1798 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1799 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 61 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 46 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 14 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 39 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 2 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 7 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 3 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 1 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 5 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 9 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 9 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 8 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 6 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 5 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 3 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 13 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 66004558000 # Total gap between requests +system.physmem.totGap 66021783500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 30434 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 169 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 1 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 29835 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 405 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 98 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 29 # What read queue length does an incoming req see +system.physmem.readPktSize::6 30416 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 154 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 29836 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 402 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 97 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -137,15 +124,14 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 7 # What write queue length does an incoming req see @@ -154,13 +140,13 @@ system.physmem.wrQLenPdf::12 7 # Wh system.physmem.wrQLenPdf::13 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see @@ -170,164 +156,163 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 12335337 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 610214087 # Sum of mem lat for all requests -system.physmem.totBusLat 151870000 # Total cycles spent in databus access -system.physmem.totBankLat 446008750 # Total cycles spent in bank access -system.physmem.avgQLat 406.11 # Average queueing delay per request -system.physmem.avgBankLat 14683.90 # Average bank access latency per request +system.physmem.totQLat 12785750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 610218250 # Sum of mem lat for all requests +system.physmem.totBusLat 151850000 # Total cycles spent in databus access +system.physmem.totBankLat 445582500 # Total cycles spent in bank access +system.physmem.avgQLat 421.00 # Average queueing delay per request +system.physmem.avgBankLat 14671.80 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 20090.01 # Average memory access latency -system.physmem.avgRdBW 29.51 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.16 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 29.51 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.16 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 20092.80 # Average memory access latency +system.physmem.avgRdBW 29.48 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 29.48 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.15 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.23 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 1.18 # Average write queue length over time -system.physmem.readRowHits 29113 # Number of row buffer hits during reads -system.physmem.writeRowHits 87 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.85 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 51.48 # Row buffer hit rate for writes -system.physmem.avgGap 2156800.25 # Average gap between requests -system.cpu.branchPred.lookups 34551755 # Number of BP lookups -system.cpu.branchPred.condPredicted 34551755 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 910403 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24766802 # Number of BTB lookups -system.cpu.branchPred.BTBHits 24665055 # Number of BTB hits +system.physmem.avgWrQLen 1.30 # Average write queue length over time +system.physmem.readRowHits 29116 # Number of row buffer hits during reads +system.physmem.writeRowHits 69 # Number of row buffer hits during writes +system.physmem.readRowHitRate 95.87 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 44.81 # Row buffer hit rate for writes +system.physmem.avgGap 2159691.97 # Average gap between requests +system.cpu.branchPred.lookups 34555739 # Number of BP lookups +system.cpu.branchPred.condPredicted 34555739 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 911751 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 24769004 # Number of BTB lookups +system.cpu.branchPred.BTBHits 24665056 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.589180 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 99.580330 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 132009151 # number of cpu cycles simulated +system.cpu.numCycles 132043594 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 26590977 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 185543024 # Number of instructions fetch has processed -system.cpu.fetch.Branches 34551755 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24665055 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 56499392 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6118358 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 43667810 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 138 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 25944504 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 189453 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 131930197 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.484743 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.326414 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 26598616 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 185589305 # Number of instructions fetch has processed +system.cpu.fetch.Branches 34555739 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24665056 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 56508781 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6124933 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 43680261 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 26 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 134 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 25951098 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 190273 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 131964855 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.484572 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.326415 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 77978275 59.11% 59.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1995894 1.51% 60.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2955143 2.24% 62.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3921314 2.97% 65.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7795304 5.91% 71.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4757842 3.61% 75.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2730359 2.07% 77.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1578596 1.20% 78.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 28217470 21.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 78003722 59.11% 59.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1996961 1.51% 60.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2955104 2.24% 62.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3922098 2.97% 65.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7793741 5.91% 71.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4759235 3.61% 75.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2730671 2.07% 77.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1579089 1.20% 78.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 28224234 21.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 131930197 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.261738 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.405532 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 37427999 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 35920173 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 44744893 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8665277 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5171855 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 324565548 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 5171855 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 42969195 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8593654 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9092 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 47590664 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 27595737 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 320190802 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 211 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 56984 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 25724332 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 365 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 322194206 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 849198017 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 849196232 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1785 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 131964855 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.261699 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.405515 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 37438024 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 35931161 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 44761152 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8657481 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5177037 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 324625052 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 5177037 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 42998776 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8560534 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9611 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 47593573 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 27625324 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 320243292 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 235 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 57194 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 25761475 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 370 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 322250586 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 849328812 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 849326947 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1865 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212745 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 42981461 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 43037841 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 469 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 463 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 62356862 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 102568377 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 35231338 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 39589479 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6005074 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 315870239 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1674 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 302163622 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 115310 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 37046058 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 54286160 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1229 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 131930197 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.290329 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.700150 # Number of insts issued each cycle +system.cpu.rename.skidInsts 62395647 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 102574673 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 35240496 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 39587079 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6070451 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 315904307 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1659 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 302190238 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 114769 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 37077809 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 54333314 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1214 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 131964855 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.289930 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.700500 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24515615 18.58% 18.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23292289 17.66% 36.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25896464 19.63% 55.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 25797972 19.55% 75.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 18916380 14.34% 89.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8292938 6.29% 96.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4139203 3.14% 99.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 915627 0.69% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 163709 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24574614 18.62% 18.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23238985 17.61% 36.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25913680 19.64% 55.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 25803819 19.55% 75.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 18917522 14.34% 89.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8297062 6.29% 96.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4140134 3.14% 99.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 916078 0.69% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 162961 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 131930197 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 131964855 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 38493 1.98% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1820587 93.51% 95.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 87813 4.51% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 38351 1.96% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1834339 93.53% 95.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 88449 4.51% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 31282 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 171146899 56.64% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 171161474 56.64% 56.65% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.65% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 35 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 29 0.00% 56.65% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.65% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.65% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.65% # Type of FU issued @@ -353,84 +338,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.65% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.65% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.65% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 97755630 32.35% 89.00% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 33229776 11.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 97761295 32.35% 89.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 33236158 11.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 302163622 # Type of FU issued -system.cpu.iq.rate 2.288960 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1946893 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006443 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 738319072 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 352950108 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 299522625 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 572 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 867 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 162 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 304078975 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 258 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 53992768 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 302190238 # Type of FU issued +system.cpu.iq.rate 2.288564 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1961139 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006490 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 738420696 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 353016005 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 299545946 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 543 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 861 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 154 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 304119846 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 249 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 53994204 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 11788993 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 26852 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 33996 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3791586 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 11795289 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 26124 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34117 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3800744 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3239 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8506 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3243 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 8488 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5171855 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1763635 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 159728 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 315871913 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 195728 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 102568377 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 35231338 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 5177037 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1758271 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 159446 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 315905966 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 197291 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 102574673 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 35240496 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 464 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3188 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 73556 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 33996 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 522451 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 444817 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 967268 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 300543939 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 97286160 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1619683 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 3186 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 73305 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 34117 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 522582 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 446237 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 968819 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 300569422 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 97293064 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1620816 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 130298049 # number of memory reference insts executed -system.cpu.iew.exec_branches 30887567 # Number of branches executed -system.cpu.iew.exec_stores 33011889 # Number of stores executed -system.cpu.iew.exec_rate 2.276690 # Inst execution rate -system.cpu.iew.wb_sent 299950982 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 299522787 # cumulative count of insts written-back -system.cpu.iew.wb_producers 219513248 # num instructions producing a value -system.cpu.iew.wb_consumers 298024509 # num instructions consuming a value +system.cpu.iew.exec_refs 130310023 # number of memory reference insts executed +system.cpu.iew.exec_branches 30888402 # Number of branches executed +system.cpu.iew.exec_stores 33016959 # Number of stores executed +system.cpu.iew.exec_rate 2.276289 # Inst execution rate +system.cpu.iew.wb_sent 299975987 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 299546100 # cumulative count of insts written-back +system.cpu.iew.wb_producers 219510783 # num instructions producing a value +system.cpu.iew.wb_consumers 298009836 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.268955 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.736561 # average fanout of values written-back +system.cpu.iew.wb_rate 2.268539 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.736589 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 37692291 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 37726716 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 910422 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 126758342 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.194668 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.965617 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 911770 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 126787818 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.194158 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.965410 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58200495 45.91% 45.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 19281721 15.21% 61.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11800672 9.31% 70.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9590531 7.57% 78.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1751465 1.38% 79.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2073903 1.64% 81.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1296843 1.02% 82.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 720324 0.57% 82.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22042388 17.39% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58221604 45.92% 45.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 19287083 15.21% 61.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11808302 9.31% 70.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9592177 7.57% 78.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1746716 1.38% 79.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2074829 1.64% 81.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1294024 1.02% 82.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 717572 0.57% 82.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22045511 17.39% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 126758342 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 126787818 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192463 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -441,69 +426,69 @@ system.cpu.commit.branches 29309705 # Nu system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.int_insts 278186172 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22042388 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22045511 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 420600708 # The number of ROB reads -system.cpu.rob.rob_writes 636946432 # The number of ROB writes -system.cpu.timesIdled 13762 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 78954 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 420661486 # The number of ROB reads +system.cpu.rob.rob_writes 637020452 # The number of ROB writes +system.cpu.timesIdled 13945 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 78739 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192463 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated -system.cpu.cpi 0.835562 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.835562 # CPI: Total CPI of All Threads -system.cpu.ipc 1.196800 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.196800 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 592847791 # number of integer regfile reads -system.cpu.int_regfile_writes 300194164 # number of integer regfile writes -system.cpu.fp_regfile_reads 150 # number of floating regfile reads -system.cpu.fp_regfile_writes 76 # number of floating regfile writes -system.cpu.misc_regfile_reads 192689354 # number of misc regfile reads -system.cpu.icache.replacements 61 # number of replacements -system.cpu.icache.tagsinuse 835.847711 # Cycle average of tags in use -system.cpu.icache.total_refs 25943160 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1033 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 25114.385286 # Average number of references to valid blocks. +system.cpu.cpi 0.835780 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.835780 # CPI: Total CPI of All Threads +system.cpu.ipc 1.196488 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.196488 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 592874208 # number of integer regfile reads +system.cpu.int_regfile_writes 300213863 # number of integer regfile writes +system.cpu.fp_regfile_reads 139 # number of floating regfile reads +system.cpu.fp_regfile_writes 70 # number of floating regfile writes +system.cpu.misc_regfile_reads 192707426 # number of misc regfile reads +system.cpu.icache.replacements 62 # number of replacements +system.cpu.icache.tagsinuse 835.762840 # Cycle average of tags in use +system.cpu.icache.total_refs 25949757 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1029 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 25218.422741 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 835.847711 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.408129 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.408129 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25943160 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25943160 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25943160 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25943160 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25943160 # number of overall hits -system.cpu.icache.overall_hits::total 25943160 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1344 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1344 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1344 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1344 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1344 # number of overall misses -system.cpu.icache.overall_misses::total 1344 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 65684000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 65684000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 65684000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 65684000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 65684000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 65684000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25944504 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25944504 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25944504 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25944504 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25944504 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25944504 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 835.762840 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.408087 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.408087 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25949757 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25949757 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25949757 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25949757 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25949757 # number of overall hits +system.cpu.icache.overall_hits::total 25949757 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1341 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1341 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1341 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1341 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1341 # number of overall misses +system.cpu.icache.overall_misses::total 1341 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 65663000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 65663000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 65663000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 65663000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 65663000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 65663000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25951098 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25951098 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25951098 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25951098 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25951098 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25951098 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48872.023810 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 48872.023810 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 48872.023810 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 48872.023810 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 48872.023810 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 48872.023810 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48965.697241 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 48965.697241 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 48965.697241 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 48965.697241 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 48965.697241 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 48965.697241 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 133 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -512,126 +497,126 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 26.600000 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 310 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 310 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 310 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 310 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 310 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 310 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1034 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1034 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1034 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1034 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1034 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1034 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51833500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 51833500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51833500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 51833500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51833500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 51833500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 311 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 311 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 311 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 311 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 311 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 311 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1030 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1030 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1030 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1030 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1030 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1030 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51831000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 51831000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51831000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 51831000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51831000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 51831000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50129.110251 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50129.110251 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50129.110251 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50129.110251 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50129.110251 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50129.110251 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50321.359223 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50321.359223 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50321.359223 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50321.359223 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50321.359223 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50321.359223 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 480 # number of replacements -system.cpu.l2cache.tagsinuse 20802.892196 # Cycle average of tags in use -system.cpu.l2cache.total_refs 4028440 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 30411 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 132.466542 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 462 # number of replacements +system.cpu.l2cache.tagsinuse 20805.290602 # Cycle average of tags in use +system.cpu.l2cache.total_refs 4028325 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 30393 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 132.541210 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 19867.143947 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 689.298857 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 246.449393 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.606297 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.021036 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.007521 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.634854 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 19869.756423 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 689.265972 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 246.268207 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.606377 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.021035 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.007516 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.634927 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1993529 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1993545 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2066104 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2066104 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 53248 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 53248 # number of ReadExReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1993469 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1993485 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2066038 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2066038 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 53254 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 53254 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2046777 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2046793 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2046723 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2046739 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2046777 # number of overall hits -system.cpu.l2cache.overall_hits::total 2046793 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1017 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 417 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1434 # number of ReadReq misses +system.cpu.l2cache.overall_hits::cpu.data 2046723 # number of overall hits +system.cpu.l2cache.overall_hits::total 2046739 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1013 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 404 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1417 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 29000 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 29000 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1017 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 29417 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 30434 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1017 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 29417 # number of overall misses -system.cpu.l2cache.overall_misses::total 30434 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50633000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21040000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 71673000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1219810500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1219810500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 50633000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1240850500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1291483500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 50633000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1240850500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1291483500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1033 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1993946 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1994979 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2066104 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2066104 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 28999 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 28999 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1013 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 29403 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 30416 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1013 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 29403 # number of overall misses +system.cpu.l2cache.overall_misses::total 30416 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50632500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 20596000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 71228500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1219887500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1219887500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 50632500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1240483500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1291116000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 50632500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1240483500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1291116000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1029 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1993873 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1994902 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2066038 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2066038 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 82248 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 82248 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1033 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2076194 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2077227 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1033 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2076194 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2077227 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.984511 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000209 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000719 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 82253 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 82253 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1029 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2076126 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2077155 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1029 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2076126 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2077155 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.984451 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000203 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000710 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352592 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.352592 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.984511 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.014169 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.014651 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984511 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.014169 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.014651 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49786.627335 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 50455.635492 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 49981.171548 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42062.431034 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42062.431034 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49786.627335 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 42181.408709 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 42435.549057 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49786.627335 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 42181.408709 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 42435.549057 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352559 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.352559 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.984451 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014162 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014643 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984451 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014162 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014643 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49982.724580 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 50980.198020 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 50267.113620 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42066.536777 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42066.536777 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49982.724580 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 42189.011325 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 42448.579695 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49982.724580 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 42189.011325 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 42448.579695 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -640,168 +625,168 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 169 # number of writebacks -system.cpu.l2cache.writebacks::total 169 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1017 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 417 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1434 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 154 # number of writebacks +system.cpu.l2cache.writebacks::total 154 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1013 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 404 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1417 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29000 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 29000 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1017 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 29417 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 30434 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1017 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 29417 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 30434 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38011868 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15869892 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53881760 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28999 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 28999 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1013 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29403 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30416 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1013 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 29403 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30416 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38064309 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15602084 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53666393 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 10001 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 10001 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 862092136 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 862092136 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38011868 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 877962028 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 915973896 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38011868 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 877962028 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 915973896 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.984511 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000209 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000719 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 862137460 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 862137460 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38064309 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 877739544 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 915803853 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38064309 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 877739544 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 915803853 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.984451 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000203 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000710 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352592 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352592 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984511 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014169 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014651 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984511 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014169 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014651 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37376.468043 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38057.294964 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37574.449093 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352559 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352559 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984451 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014162 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014643 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984451 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014162 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014643 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37575.823297 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38619.019802 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37873.248412 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 29727.315034 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 29727.315034 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37376.468043 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 29845.396471 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 30097.059079 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37376.468043 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29845.396471 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 30097.059079 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 29729.903100 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 29729.903100 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37575.823297 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 29852.040404 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 30109.279754 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37575.823297 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29852.040404 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 30109.279754 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2072095 # number of replacements -system.cpu.dcache.tagsinuse 4072.471954 # Cycle average of tags in use -system.cpu.dcache.total_refs 71964033 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2076191 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34.661567 # Average number of references to valid blocks. +system.cpu.dcache.replacements 2072027 # number of replacements +system.cpu.dcache.tagsinuse 4072.478091 # Cycle average of tags in use +system.cpu.dcache.total_refs 71969321 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2076123 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34.665249 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 21154875000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4072.471954 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994256 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994256 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 40622570 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 40622570 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31341456 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31341456 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 71964026 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 71964026 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 71964026 # number of overall hits -system.cpu.dcache.overall_hits::total 71964026 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2625435 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2625435 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 98296 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 98296 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2723731 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2723731 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2723731 # number of overall misses -system.cpu.dcache.overall_misses::total 2723731 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31317831000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31317831000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2109058498 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2109058498 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33426889498 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33426889498 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33426889498 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33426889498 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 43248005 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 43248005 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 4072.478091 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994257 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994257 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 40627855 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 40627855 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31341459 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31341459 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 71969314 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 71969314 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 71969314 # number of overall hits +system.cpu.dcache.overall_hits::total 71969314 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2625363 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2625363 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 98293 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 98293 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2723656 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2723656 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2723656 # number of overall misses +system.cpu.dcache.overall_misses::total 2723656 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31317935000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31317935000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2109133999 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2109133999 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33427068999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33427068999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33427068999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33427068999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 43253218 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 43253218 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 74687757 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 74687757 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 74687757 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 74687757 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060706 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.060706 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 74692970 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 74692970 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 74692970 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 74692970 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060698 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.060698 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003126 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.003126 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036468 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036468 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036468 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036468 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11928.625542 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11928.625542 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21456.198604 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 21456.198604 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12272.463580 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12272.463580 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12272.463580 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12272.463580 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32211 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.036465 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036465 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036465 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036465 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11928.992296 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11928.992296 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21457.621591 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 21457.621591 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12272.867425 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12272.867425 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12272.867425 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12272.867425 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 31969 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 9475 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 9433 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.399578 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.389060 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2066104 # number of writebacks -system.cpu.dcache.writebacks::total 2066104 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631384 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 631384 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16152 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16152 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 647536 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 647536 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 647536 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 647536 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994051 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994051 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82144 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82144 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076195 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076195 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076195 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076195 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21987856500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21987856500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1833812998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1833812998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23821669498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23821669498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23821669498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23821669498 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046107 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046107 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 2066038 # number of writebacks +system.cpu.dcache.writebacks::total 2066038 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631383 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 631383 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16146 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16146 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 647529 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 647529 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 647529 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 647529 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1993980 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1993980 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82147 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82147 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076127 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076127 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076127 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076127 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21982224500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21982224500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1833925499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1833925499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23816149999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23816149999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23816149999 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23816149999 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046100 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046100 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002613 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002613 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027798 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.027798 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027798 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027798 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11026.727250 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11026.727250 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22324.369376 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22324.369376 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11473.714896 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11473.714896 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11473.714896 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11473.714896 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027795 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.027795 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027795 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027795 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11024.295379 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.295379 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22324.923600 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22324.923600 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11471.432142 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11471.432142 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11471.432142 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11471.432142 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index f32034add..1e537017c 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,117 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.434532 # Number of seconds simulated -sim_ticks 434531908500 # Number of ticks simulated -final_tick 434531908500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.434431 # Number of seconds simulated +sim_ticks 434430920500 # Number of ticks simulated +final_tick 434430920500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91853 # Simulator instruction rate (inst/s) -host_op_rate 169847 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48269802 # Simulator tick rate (ticks/s) -host_mem_usage 425632 # Number of bytes of host memory used -host_seconds 9002.15 # Real time elapsed on the host +host_inst_rate 103951 # Simulator instruction rate (inst/s) +host_op_rate 192218 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54614710 # Simulator tick rate (ticks/s) +host_mem_usage 421552 # Number of bytes of host memory used +host_seconds 7954.47 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988700 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 206656 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24475072 # Number of bytes read from this memory -system.physmem.bytes_read::total 24681728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24473856 # Number of bytes read from this memory +system.physmem.bytes_read::total 24680512 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 206656 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 206656 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18793472 # Number of bytes written to this memory -system.physmem.bytes_written::total 18793472 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 18792192 # Number of bytes written to this memory +system.physmem.bytes_written::total 18792192 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 3229 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382423 # Number of read requests responded to by this memory -system.physmem.num_reads::total 385652 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293648 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293648 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 475583 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 56325143 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 56800726 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 475583 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 475583 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 43249924 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 43249924 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 43249924 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 475583 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 56325143 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 100050650 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 385654 # Total number of read requests seen -system.physmem.writeReqs 293648 # Total number of write requests seen -system.physmem.cpureqs 897087 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 24681728 # Total number of bytes read from memory -system.physmem.bytesWritten 18793472 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 24681728 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 18793472 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 151 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 214401 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 23129 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 24463 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 23958 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 22626 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 23437 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 24746 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 24520 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 24217 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 24346 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 24649 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 24306 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 24351 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 24467 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 23427 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 24871 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 23990 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 17780 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 18806 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 18330 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 17563 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 18009 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 18654 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 18318 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 18307 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 18738 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 18746 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 18443 # Track writes on a per bank basis +system.physmem.num_reads::cpu.data 382404 # Number of read requests responded to by this memory +system.physmem.num_reads::total 385633 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293628 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293628 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 475694 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 56335438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 56811131 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 475694 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 475694 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 43257031 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 43257031 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 43257031 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 475694 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 56335438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 100068163 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 385635 # Total number of read requests seen +system.physmem.writeReqs 293628 # Total number of write requests seen +system.physmem.cpureqs 897306 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 24680512 # Total number of bytes read from memory +system.physmem.bytesWritten 18792192 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 24680512 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 18792192 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 135 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 215167 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 23200 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 24440 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 23926 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 22603 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 23455 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 24726 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 24470 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 24228 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 24367 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 24672 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 24294 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 24362 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 24487 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 23459 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 24852 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 23959 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 17796 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 18805 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 18324 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 17566 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 18019 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 18653 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 18315 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 18311 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 18728 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 18743 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 18429 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 18564 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 18554 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 17877 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 18850 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 18109 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 18552 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 17863 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 18856 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 18104 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 3384 # Number of times wr buffer was full causing retry -system.physmem.totGap 434531891500 # Total gap between requests +system.physmem.numWrRetry 2876 # Number of times wr buffer was full causing retry +system.physmem.totGap 434430903500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 385654 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 297032 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 214401 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 380704 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4364 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 366 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.readPktSize::6 385635 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 293628 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 380797 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4262 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -137,195 +124,194 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 12706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 12717 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 12721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 12709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 12719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 12720 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 12722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 12726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 12730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 12725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 12729 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 12733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 12733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 12737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 12739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 12741 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 48 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 42 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3414434563 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12002683313 # Sum of mem lat for all requests -system.physmem.totBusLat 1927515000 # Total cycles spent in databus access -system.physmem.totBankLat 6660733750 # Total cycles spent in bank access -system.physmem.avgQLat 8857.09 # Average queueing delay per request -system.physmem.avgBankLat 17278.03 # Average bank access latency per request +system.physmem.wrQLenPdf::29 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 26 # What write queue length does an incoming req see +system.physmem.totQLat 3409479750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11997177250 # Sum of mem lat for all requests +system.physmem.totBusLat 1927500000 # Total cycles spent in databus access +system.physmem.totBankLat 6660197500 # Total cycles spent in bank access +system.physmem.avgQLat 8844.31 # Average queueing delay per request +system.physmem.avgBankLat 17276.78 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31135.12 # Average memory access latency -system.physmem.avgRdBW 56.80 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 43.25 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 56.80 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 43.25 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 31121.08 # Average memory access latency +system.physmem.avgRdBW 56.81 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 43.26 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 56.81 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 43.26 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.78 # Data bus utilization in percentage system.physmem.avgRdQLen 0.03 # Average read queue length over time -system.physmem.avgWrQLen 9.81 # Average write queue length over time -system.physmem.readRowHits 331850 # Number of row buffer hits during reads -system.physmem.writeRowHits 191739 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.08 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 65.30 # Row buffer hit rate for writes -system.physmem.avgGap 639674.09 # Average gap between requests -system.cpu.branchPred.lookups 214985170 # Number of BP lookups -system.cpu.branchPred.condPredicted 214985170 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 13134974 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 150557498 # Number of BTB lookups -system.cpu.branchPred.BTBHits 147831953 # Number of BTB hits +system.physmem.avgWrQLen 9.17 # Average write queue length over time +system.physmem.readRowHits 331860 # Number of row buffer hits during reads +system.physmem.writeRowHits 191798 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.09 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 65.32 # Row buffer hit rate for writes +system.physmem.avgGap 639562.15 # Average gap between requests +system.cpu.branchPred.lookups 214905339 # Number of BP lookups +system.cpu.branchPred.condPredicted 214905339 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 13127433 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 150477516 # Number of BTB lookups +system.cpu.branchPred.BTBHits 147823689 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.189698 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 98.236396 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 869063818 # number of cpu cycles simulated +system.cpu.numCycles 868861842 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 180571756 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1193203975 # Number of instructions fetch has processed -system.cpu.fetch.Branches 214985170 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 147831953 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 371215101 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 83387755 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 231673075 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33185 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 322843 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 68 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 173439567 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 3823649 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 853812868 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.595051 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.389323 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 180577504 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1192973241 # Number of instructions fetch has processed +system.cpu.fetch.Branches 214905339 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 147823689 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 371150852 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 83341611 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 231393952 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33171 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 324598 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 87 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 173446874 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 3818726 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 853436670 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.595518 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.389389 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 486992667 57.04% 57.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 24704335 2.89% 59.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 27327411 3.20% 63.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 28832283 3.38% 66.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 18475468 2.16% 68.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 24603692 2.88% 71.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 30623589 3.59% 75.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28857730 3.38% 78.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 183395693 21.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 486691437 57.03% 57.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 24707790 2.90% 59.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 27346098 3.20% 63.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 28808795 3.38% 66.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 18459850 2.16% 68.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 24598509 2.88% 71.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 30642263 3.59% 75.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28856964 3.38% 78.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 183324964 21.48% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 853812868 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.247376 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.372976 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 237064473 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 188186572 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 313399146 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 45165837 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 69996840 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2166788008 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 69996840 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 270473923 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 53975472 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 17892 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 322682449 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 136666292 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2119871980 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 32012 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 21236600 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 101165935 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 102 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2216234467 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5355317387 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5355179179 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 138208 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 853436670 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.247341 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.373030 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 237036597 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 187932241 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 313348177 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 45163149 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 69956506 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2166370172 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 6 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 69956506 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 270406129 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 53950609 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 16000 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 322641702 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 136465724 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2119600897 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 32452 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 20939189 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 101244294 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 109 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2216054849 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5354933162 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5354796739 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 136423 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040852 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 602193615 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1385 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1348 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 330022122 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 512693840 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 204894369 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 196280742 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 55580246 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2033860002 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 23240 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1808188122 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 845695 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 499369913 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 817987835 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 22688 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 853812868 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.117780 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.887735 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 602013997 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1381 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1341 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 329887917 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 512569621 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 204871608 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 196009794 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 55366102 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2033547368 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 23672 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1807958991 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 824800 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 499056334 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 817700270 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 23120 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 853436670 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.118445 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.887633 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 233534658 27.35% 27.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 145245329 17.01% 44.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 138299025 16.20% 60.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 133036648 15.58% 76.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 95993641 11.24% 87.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 58825628 6.89% 94.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 34908775 4.09% 98.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12073867 1.41% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1895297 0.22% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 233342895 27.34% 27.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 145008680 16.99% 44.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 138353825 16.21% 60.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 133057886 15.59% 76.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 96025914 11.25% 87.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 58740201 6.88% 94.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34984970 4.10% 98.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12023870 1.41% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1898429 0.22% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 853812868 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 853436670 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4968961 32.44% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7761394 50.67% 83.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2587769 16.89% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4945296 32.31% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7774785 50.79% 83.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2587375 16.90% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2719358 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1190817504 65.86% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2719757 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1190688442 65.86% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.01% # Type of FU issued @@ -354,84 +340,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.01% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 438925166 24.27% 90.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 175726094 9.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 438864121 24.27% 90.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 175686671 9.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1808188122 # Type of FU issued -system.cpu.iq.rate 2.080616 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15318124 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008472 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4486330411 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2533466617 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1768665835 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 22520 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 43644 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 4990 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1820776414 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 10474 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 170620885 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1807958991 # Type of FU issued +system.cpu.iq.rate 2.080836 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15307456 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008467 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4485463564 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2532842226 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1768511816 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23344 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 44056 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 5298 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1820535825 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 10865 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 170531860 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 128591684 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 469733 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 268884 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 55734548 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 128467465 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 477996 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 270600 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 55711763 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12443 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 683 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12158 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 637 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 69996840 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 16364844 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2884009 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2033883242 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2403682 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 512693840 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 204894734 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6182 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1820537 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 77063 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 268884 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 9113160 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4488782 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 13601942 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1780436006 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 431388742 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 27752116 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 69956506 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 16270481 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2882420 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2033571040 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2388116 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 512569621 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 204871949 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6204 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1819124 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 76761 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 270600 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 9107192 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4485988 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 13593180 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1780284053 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 431339374 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 27674938 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 602101798 # number of memory reference insts executed -system.cpu.iew.exec_branches 169273677 # Number of branches executed -system.cpu.iew.exec_stores 170713056 # Number of stores executed -system.cpu.iew.exec_rate 2.048683 # Inst execution rate -system.cpu.iew.wb_sent 1775376016 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1768670825 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1341566013 # num instructions producing a value -system.cpu.iew.wb_consumers 1964312147 # num instructions consuming a value +system.cpu.iew.exec_refs 602039294 # number of memory reference insts executed +system.cpu.iew.exec_branches 169246967 # Number of branches executed +system.cpu.iew.exec_stores 170699920 # Number of stores executed +system.cpu.iew.exec_rate 2.048984 # Inst execution rate +system.cpu.iew.wb_sent 1775206038 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1768517114 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1341481369 # num instructions producing a value +system.cpu.iew.wb_consumers 1964281102 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.035145 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.682970 # average fanout of values written-back +system.cpu.iew.wb_rate 2.035441 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.682938 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 504930562 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 504616245 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 13167809 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 783816028 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.950698 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.458733 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 13160386 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 783480164 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.951535 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.459630 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 290605318 37.08% 37.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 195507197 24.94% 62.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 61957017 7.90% 69.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92299201 11.78% 81.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25131164 3.21% 84.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 28287004 3.61% 88.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9364104 1.19% 89.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10794618 1.38% 91.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 69870405 8.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 290390176 37.06% 37.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 195527314 24.96% 62.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 61904118 7.90% 69.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92200524 11.77% 81.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25009746 3.19% 84.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 28276907 3.61% 88.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9452853 1.21% 89.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10837267 1.38% 91.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69881259 8.92% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 783816028 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 783480164 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988700 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -442,203 +428,203 @@ system.cpu.commit.branches 149758583 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317559 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 69870405 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69881259 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2747864885 # The number of ROB reads -system.cpu.rob.rob_writes 4138016116 # The number of ROB writes -system.cpu.timesIdled 327647 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 15250950 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2747203850 # The number of ROB reads +system.cpu.rob.rob_writes 4137345189 # The number of ROB writes +system.cpu.timesIdled 333192 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 15425172 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988700 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated -system.cpu.cpi 1.051019 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.051019 # CPI: Total CPI of All Threads -system.cpu.ipc 0.951457 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.951457 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3357381544 # number of integer regfile reads -system.cpu.int_regfile_writes 1848396157 # number of integer regfile writes -system.cpu.fp_regfile_reads 4985 # number of floating regfile reads -system.cpu.fp_regfile_writes 5 # number of floating regfile writes -system.cpu.misc_regfile_reads 980232069 # number of misc regfile reads -system.cpu.icache.replacements 5428 # number of replacements -system.cpu.icache.tagsinuse 1035.426880 # Cycle average of tags in use -system.cpu.icache.total_refs 173198733 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 7017 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 24682.732364 # Average number of references to valid blocks. +system.cpu.cpi 1.050775 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.050775 # CPI: Total CPI of All Threads +system.cpu.ipc 0.951678 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.951678 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3357185623 # number of integer regfile reads +system.cpu.int_regfile_writes 1848288300 # number of integer regfile writes +system.cpu.fp_regfile_reads 5295 # number of floating regfile reads +system.cpu.fp_regfile_writes 3 # number of floating regfile writes +system.cpu.misc_regfile_reads 980095444 # number of misc regfile reads +system.cpu.icache.replacements 5498 # number of replacements +system.cpu.icache.tagsinuse 1034.775539 # Cycle average of tags in use +system.cpu.icache.total_refs 173205275 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7087 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 24439.858191 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1035.426880 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.505580 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.505580 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 173214256 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 173214256 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 173214256 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 173214256 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 173214256 # number of overall hits -system.cpu.icache.overall_hits::total 173214256 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 225311 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 225311 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 225311 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 225311 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 225311 # number of overall misses -system.cpu.icache.overall_misses::total 225311 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1422825499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1422825499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1422825499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1422825499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1422825499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1422825499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 173439567 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 173439567 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 173439567 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 173439567 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 173439567 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 173439567 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001299 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001299 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001299 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001299 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001299 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001299 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6314.940234 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6314.940234 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6314.940234 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6314.940234 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6314.940234 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6314.940234 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 893 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1034.775539 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.505261 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.505261 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 173220667 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 173220667 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 173220667 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 173220667 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 173220667 # number of overall hits +system.cpu.icache.overall_hits::total 173220667 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 226207 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 226207 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 226207 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 226207 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 226207 # number of overall misses +system.cpu.icache.overall_misses::total 226207 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1445018998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1445018998 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1445018998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1445018998 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1445018998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1445018998 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 173446874 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 173446874 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 173446874 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 173446874 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 173446874 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 173446874 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001304 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001304 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001304 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001304 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001304 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001304 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6388.038381 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6388.038381 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6388.038381 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6388.038381 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6388.038381 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6388.038381 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 531 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 14 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 63.785714 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 33.187500 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2350 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2350 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2350 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2350 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2350 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2350 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 222961 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 222961 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 222961 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 222961 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 222961 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 222961 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 908771999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 908771999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 908771999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 908771999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 908771999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 908771999 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001286 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001286 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001286 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001286 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001286 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001286 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4075.923588 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4075.923588 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4075.923588 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 4075.923588 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4075.923588 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 4075.923588 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2416 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2416 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2416 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2416 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2416 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2416 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 223791 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 223791 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 223791 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 223791 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 223791 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 223791 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 922806998 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 922806998 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 922806998 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 922806998 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 922806998 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 922806998 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001290 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001290 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001290 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001290 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001290 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001290 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4123.521491 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4123.521491 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4123.521491 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 4123.521491 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4123.521491 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 4123.521491 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 352967 # number of replacements -system.cpu.l2cache.tagsinuse 29623.610985 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3697581 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 385328 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 9.595931 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 202031394500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21046.511292 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 232.202938 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 8344.896755 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.642289 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.007086 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.254666 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.904041 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 3753 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1586557 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1590310 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2331178 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2331178 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1519 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1519 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 564630 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 564630 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3753 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2151187 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2154940 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3753 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2151187 # number of overall hits -system.cpu.l2cache.overall_hits::total 2154940 # number of overall hits +system.cpu.l2cache.replacements 352952 # number of replacements +system.cpu.l2cache.tagsinuse 29623.817782 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3697849 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 385320 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 9.596826 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 201967197500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 21048.763248 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 234.229259 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 8340.825274 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.642357 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.007148 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.254542 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.904047 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 3812 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1586582 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1590394 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2331083 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2331083 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1524 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 1524 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 564588 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 564588 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 3812 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2151170 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2154982 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 3812 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2151170 # number of overall hits +system.cpu.l2cache.overall_hits::total 2154982 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 3230 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 175686 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 178916 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 214369 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 214369 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 206771 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206771 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 175670 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 178900 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 215135 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 215135 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 206768 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 206768 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 3230 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 382457 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 385687 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 382438 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 385668 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 3230 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 382457 # number of overall misses -system.cpu.l2cache.overall_misses::total 385687 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 196335000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10103953956 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 10300288956 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 7210000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 7210000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10386868500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10386868500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 196335000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 20490822456 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20687157456 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 196335000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 20490822456 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20687157456 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 6983 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1762243 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1769226 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2331178 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2331178 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 215888 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 215888 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 771401 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 771401 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 6983 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2533644 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2540627 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 6983 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2533644 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2540627 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.462552 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099695 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.101127 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.992964 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.992964 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268046 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.268046 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.462552 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.150951 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.151808 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.462552 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.150951 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.151808 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60784.829721 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57511.434924 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 57570.530059 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 33.633594 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 33.633594 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50233.681222 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50233.681222 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60784.829721 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53576.800676 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 53637.165515 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60784.829721 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53576.800676 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 53637.165515 # average overall miss latency +system.cpu.l2cache.overall_misses::cpu.data 382438 # number of overall misses +system.cpu.l2cache.overall_misses::total 385668 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 200745500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10125783456 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 10326528956 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 7277000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 7277000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10354954000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10354954000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 200745500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 20480737456 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20681482956 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 200745500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 20480737456 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20681482956 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 7042 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1762252 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1769294 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2331083 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2331083 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 216659 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 216659 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 771356 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 771356 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 7042 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2533608 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2540650 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 7042 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2533608 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2540650 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.458677 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099685 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.101114 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.992966 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.992966 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268058 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.268058 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.458677 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.150946 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.151799 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.458677 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.150946 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.151799 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 62150.309598 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57640.937303 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 57722.353024 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 33.825273 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 33.825273 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50080.060744 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50080.060744 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 62150.309598 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53553.092151 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 53625.094527 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 62150.309598 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53553.092151 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 53625.094527 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -647,168 +633,168 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 293648 # number of writebacks -system.cpu.l2cache.writebacks::total 293648 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 293628 # number of writebacks +system.cpu.l2cache.writebacks::total 293628 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3230 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175686 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 178916 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 214369 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 214369 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206771 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206771 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175670 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 178900 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 215135 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 215135 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206768 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206768 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 3230 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 382457 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 385687 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 382438 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 385668 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 3230 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 382457 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 385687 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 156219180 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7929842195 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8086061375 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2149350076 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2149350076 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7799617575 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7799617575 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 156219180 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15729459770 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15885678950 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 156219180 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15729459770 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15885678950 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.462552 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099695 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101127 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.992964 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.992964 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268046 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268046 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.462552 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150951 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151808 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.462552 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150951 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151808 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48365.071207 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45136.449091 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45194.735938 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10026.403426 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10026.403426 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37721.041998 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37721.041998 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48365.071207 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41127.394112 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41188.007244 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48365.071207 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41127.394112 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41188.007244 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.data 382438 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 385668 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 160592502 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7951741535 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8112334037 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2156878107 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2156878107 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7767550023 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7767550023 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 160592502 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15719291558 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15879884060 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 160592502 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15719291558 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15879884060 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.458677 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099685 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101114 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.992966 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.992966 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268058 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268058 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.458677 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150946 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151799 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.458677 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150946 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151799 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 49719.040867 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45265.221922 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45345.634639 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10025.695991 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10025.695991 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37566.499763 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37566.499763 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49719.040867 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41102.849502 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41175.010786 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49719.040867 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41102.849502 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41175.010786 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2529546 # number of replacements -system.cpu.dcache.tagsinuse 4087.815974 # Cycle average of tags in use -system.cpu.dcache.total_refs 405263721 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2533642 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 159.953032 # Average number of references to valid blocks. +system.cpu.dcache.replacements 2529510 # number of replacements +system.cpu.dcache.tagsinuse 4087.814071 # Cycle average of tags in use +system.cpu.dcache.total_refs 405300363 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2533606 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 159.969768 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 1790563000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.815974 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998002 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998002 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 256525921 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 256525921 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148156323 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148156323 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 404682244 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 404682244 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 404682244 # number of overall hits -system.cpu.dcache.overall_hits::total 404682244 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2897766 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2897766 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1003879 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1003879 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3901645 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3901645 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3901645 # number of overall misses -system.cpu.dcache.overall_misses::total 3901645 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 51407808000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 51407808000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23879895000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23879895000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 75287703000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 75287703000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 75287703000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 75287703000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 259423687 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 259423687 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 4087.814071 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998001 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998001 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 256561451 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 256561451 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148155645 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148155645 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 404717096 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 404717096 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 404717096 # number of overall hits +system.cpu.dcache.overall_hits::total 404717096 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2903042 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2903042 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1004557 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1004557 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3907599 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3907599 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3907599 # number of overall misses +system.cpu.dcache.overall_misses::total 3907599 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 51581963000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 51581963000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23867126500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23867126500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 75449089500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 75449089500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 75449089500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 75449089500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 259464493 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 259464493 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 408583889 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 408583889 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 408583889 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 408583889 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011170 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011170 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006730 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006730 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009549 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009549 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009549 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009549 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17740.496645 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17740.496645 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23787.622811 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 23787.622811 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19296.400108 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19296.400108 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19296.400108 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19296.400108 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6861 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 408624695 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 408624695 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 408624695 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 408624695 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011189 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011189 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006735 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006735 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009563 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009563 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009563 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009563 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17768.245516 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17768.245516 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23758.857387 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 23758.857387 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19308.298907 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19308.298907 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19308.298907 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19308.298907 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6217 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 663 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 681 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.348416 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.129222 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2331178 # number of writebacks -system.cpu.dcache.writebacks::total 2331178 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1135254 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1135254 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16862 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16862 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1152116 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1152116 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1152116 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1152116 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762512 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1762512 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 987017 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 987017 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2749529 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2749529 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2749529 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2749529 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27769073500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27769073500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 21705384500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 21705384500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49474458000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 49474458000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49474458000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 49474458000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006794 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006794 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006617 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006617 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006729 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006729 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006729 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006729 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15755.395424 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15755.395424 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21990.892254 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21990.892254 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17993.793846 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17993.793846 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17993.793846 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17993.793846 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2331083 # number of writebacks +system.cpu.dcache.writebacks::total 2331083 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1140525 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1140525 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16809 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16809 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1157334 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1157334 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1157334 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1157334 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762517 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1762517 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 987748 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 987748 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2750265 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2750265 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2750265 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2750265 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27791691500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27791691500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 21690054500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 21690054500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49481746000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 49481746000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49481746000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 49481746000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006793 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006793 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006622 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006622 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006731 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006731 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006731 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006731 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15768.183513 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15768.183513 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21959.097361 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21959.097361 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17991.628443 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17991.628443 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17991.628443 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17991.628443 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index 6c858f4a6..188ee6566 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.139855 # Nu sim_ticks 139855372500 # Number of ticks simulated final_tick 139855372500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 164436 # Simulator instruction rate (inst/s) -host_op_rate 164436 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57685897 # Simulator tick rate (ticks/s) -host_mem_usage 230388 # Number of bytes of host memory used -host_seconds 2424.43 # Real time elapsed on the host +host_inst_rate 118034 # Simulator instruction rate (inst/s) +host_op_rate 118034 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41407532 # Simulator tick rate (ticks/s) +host_mem_usage 230404 # Number of bytes of host memory used +host_seconds 3377.53 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 7328 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 4560 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 1887 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 585 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 47661305 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 197340055 # Sum of mem lat for all requests +system.physmem.totQLat 47654000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 197332750 # Sum of mem lat for all requests system.physmem.totBusLat 36640000 # Total cycles spent in databus access system.physmem.totBankLat 113038750 # Total cycles spent in bank access -system.physmem.avgQLat 6504.00 # Average queueing delay per request +system.physmem.avgQLat 6503.00 # Average queueing delay per request system.physmem.avgBankLat 15425.59 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26929.59 # Average memory access latency +system.physmem.avgMemAccLat 26928.60 # Average memory access latency system.physmem.avgRdBW 3.35 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 3.35 # Average consumed read bandwidth in MB/s @@ -473,17 +458,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7328 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3359 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 128897344 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 35549956 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 164447300 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 120759327 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 120759327 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 128897344 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156309283 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 285206627 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 128897344 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156309283 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 285206627 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 128894552 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 35549355 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 164443907 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 120757665 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 120757665 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 128894552 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156307020 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 285201572 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 128894552 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156307020 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 285201572 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862474 # mshr miss rate for ReadReq accesses @@ -495,17 +480,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.909745 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.909745 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38373.725514 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43143.150485 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39313.244083 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38397.242289 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38397.242289 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38373.725514 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39382.535399 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38920.118313 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38373.725514 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39382.535399 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38920.118313 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38372.894314 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43142.421117 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39312.432943 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38396.713831 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38396.713831 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38372.894314 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39381.965231 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38919.428493 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38372.894314 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39381.965231 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38919.428493 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 764 # number of replacements system.cpu.dcache.tagsinuse 3285.521075 # Cycle average of tags in use diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index f63466b63..8274182ca 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.077334 # Nu sim_ticks 77333663500 # Number of ticks simulated final_tick 77333663500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 196388 # Simulator instruction rate (inst/s) -host_op_rate 196388 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40437661 # Simulator tick rate (ticks/s) -host_mem_usage 232448 # Number of bytes of host memory used -host_seconds 1912.42 # Real time elapsed on the host +host_inst_rate 154881 # Simulator instruction rate (inst/s) +host_op_rate 154881 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 31891174 # Simulator tick rate (ticks/s) +host_mem_usage 232452 # Number of bytes of host memory used +host_seconds 2424.92 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 221120 # Number of bytes read from this memory @@ -78,30 +78,17 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 7448 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 4136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2085 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 804 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 307 # What read queue length does an incoming req see +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 4137 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2083 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 806 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 306 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 111 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 53873160 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 207011910 # Sum of mem lat for all requests +system.physmem.totQLat 53845750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 206984500 # Sum of mem lat for all requests system.physmem.totBusLat 37240000 # Total cycles spent in databus access system.physmem.totBankLat 115898750 # Total cycles spent in bank access -system.physmem.avgQLat 7233.24 # Average queueing delay per request +system.physmem.avgQLat 7229.56 # Average queueing delay per request system.physmem.avgBankLat 15561.06 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27794.30 # Average memory access latency +system.physmem.avgMemAccLat 27790.61 # Average memory access latency system.physmem.avgRdBW 6.16 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 6.16 # Average consumed read bandwidth in MB/s @@ -198,18 +183,18 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 101791406 # DTB read hits +system.cpu.dtb.read_hits 101791407 # DTB read hits system.cpu.dtb.read_misses 78057 # DTB read misses system.cpu.dtb.read_acv 48605 # DTB read access violations -system.cpu.dtb.read_accesses 101869463 # DTB read accesses +system.cpu.dtb.read_accesses 101869464 # DTB read accesses system.cpu.dtb.write_hits 78427886 # DTB write hits system.cpu.dtb.write_misses 1487 # DTB write misses system.cpu.dtb.write_acv 4 # DTB write access violations system.cpu.dtb.write_accesses 78429373 # DTB write accesses -system.cpu.dtb.data_hits 180219292 # DTB hits +system.cpu.dtb.data_hits 180219293 # DTB hits system.cpu.dtb.data_misses 79544 # DTB misses system.cpu.dtb.data_acv 48609 # DTB access violations -system.cpu.dtb.data_accesses 180298836 # DTB accesses +system.cpu.dtb.data_accesses 180298837 # DTB accesses system.cpu.itb.fetch_hits 50219857 # ITB hits system.cpu.itb.fetch_misses 371 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv @@ -230,23 +215,23 @@ system.cpu.workload.num_syscalls 215 # Nu system.cpu.numCycles 154667329 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 51106120 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 51106123 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 448669005 # Number of instructions fetch has processed system.cpu.fetch.Branches 50250166 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 32239639 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 78764977 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 6110488 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 19721587 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 19721562 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 9420 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 31 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 50219857 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 408750 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 154473509 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 154473487 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.904505 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.325354 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 75708532 49.01% 49.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 75708510 49.01% 49.01% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 4277779 2.77% 51.78% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 6877340 4.45% 56.23% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 5358744 3.47% 59.70% # Number of instructions fetched each cycle (Total) @@ -258,11 +243,11 @@ system.cpu.fetch.rateDist::8 35257809 22.82% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 154473509 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 154473487 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.324892 # Number of branch fetches per cycle system.cpu.fetch.rate 2.900865 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 56459553 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 15066363 # Number of cycles decode is blocked +system.cpu.decode.IdleCycles 56459555 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 15066339 # Number of cycles decode is blocked system.cpu.decode.RunCycles 74129391 # Number of cycles decode is running system.cpu.decode.UnblockCycles 3951215 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 4866987 # Number of cycles decode is squashing @@ -271,15 +256,15 @@ system.cpu.decode.BranchMispred 4302 # Nu system.cpu.decode.DecodedInsts 444763327 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 12199 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 4866987 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 59590768 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4877628 # Number of cycles rename is blocking +system.cpu.rename.IdleCycles 59590769 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4877606 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 403370 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 75043534 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 9691222 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 440325296 # Number of instructions processed by rename +system.cpu.rename.UnblockCycles 9691221 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 440325297 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 81 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 19775 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8008636 # Number of times rename has blocked due to LSQ full +system.cpu.rename.LSQFullEvents 8008634 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 287258509 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 578891151 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 306269628 # Number of integer rename lookups @@ -288,35 +273,35 @@ system.cpu.rename.CommittedMaps 259532329 # Nu system.cpu.rename.UndoneMaps 27726180 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 36829 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 293 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 27858963 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 27858970 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 104659356 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 80576509 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 8905764 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 6378561 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 408090088 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 408090089 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 285 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 401700569 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 966818 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 32383170 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 966819 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 32383171 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 15203599 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 70 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 154473509 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 154473487 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.600450 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.995226 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 28241568 18.28% 18.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 25850506 16.73% 35.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25557985 16.55% 51.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 24263587 15.71% 67.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21289313 13.78% 81.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15479662 10.02% 91.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8473783 5.49% 96.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 28241547 18.28% 18.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 25850500 16.73% 35.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25557992 16.55% 51.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 24263583 15.71% 67.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21289316 13.78% 81.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15479664 10.02% 91.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8473780 5.49% 96.56% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 3991768 2.58% 99.14% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 1325337 0.86% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 154473509 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 154473487 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 34109 0.29% 0.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 0.29% # attempts to use FU when none available @@ -347,12 +332,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.08% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.08% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5072339 42.83% 74.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5072338 42.83% 74.92% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 2970257 25.08% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 155713729 38.76% 38.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 155713730 38.76% 38.77% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 2126194 0.53% 39.30% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 32798014 8.16% 47.47% # Type of FU issued @@ -381,21 +366,21 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.54% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 103367731 25.73% 80.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 103367730 25.73% 80.27% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 79244441 19.73% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 401700569 # Type of FU issued system.cpu.iq.rate 2.597191 # Inst issue rate -system.cpu.iq.fu_busy_cnt 11841746 # FU busy when requested +system.cpu.iq.fu_busy_cnt 11841745 # FU busy when requested system.cpu.iq.fu_busy_rate 0.029479 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 633918884 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 260111127 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 234694704 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_reads 633918862 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 260111129 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 234694703 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 336764327 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 180411325 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 161341889 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 241419354 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 241419353 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 172089380 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 15066516 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -409,10 +394,10 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 260879 # system.cpu.iew.lsq.thread0.cacheBlocked 2892 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 4866987 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2513908 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 367539 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 432875837 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 130046 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewBlockCycles 2513893 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 367538 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 432875839 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 130047 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 104659356 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 80576509 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 285 # Number of dispatched non-speculative instructions @@ -423,42 +408,42 @@ system.cpu.iew.predictedTakenIncorrect 945508 # Nu system.cpu.iew.predictedNotTakenIncorrect 405299 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 1350807 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 398189954 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 101918110 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts 101918111 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 3510615 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 24785464 # number of nop insts executed -system.cpu.iew.exec_refs 180347520 # number of memory reference insts executed +system.cpu.iew.exec_nop 24785465 # number of nop insts executed +system.cpu.iew.exec_refs 180347521 # number of memory reference insts executed system.cpu.iew.exec_branches 46544583 # Number of branches executed system.cpu.iew.exec_stores 78429410 # Number of stores executed system.cpu.iew.exec_rate 2.574493 # Inst execution rate -system.cpu.iew.wb_sent 396666494 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 396036593 # cumulative count of insts written-back -system.cpu.iew.wb_producers 193534236 # num instructions producing a value +system.cpu.iew.wb_sent 396666493 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 396036592 # cumulative count of insts written-back +system.cpu.iew.wb_producers 193534237 # num instructions producing a value system.cpu.iew.wb_consumers 271064264 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 2.560570 # insts written-back per cycle system.cpu.iew.wb_fanout 0.713979 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 34241397 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 34241399 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1196652 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149606522 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 149606500 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 2.664754 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.996488 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 55299818 36.96% 36.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 55299795 36.96% 36.96% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 22506360 15.04% 52.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13038976 8.72% 60.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11456394 7.66% 68.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8182427 5.47% 73.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 5460458 3.65% 77.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13038980 8.72% 60.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11456393 7.66% 68.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8182424 5.47% 73.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5460459 3.65% 77.50% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 5170598 3.46% 80.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3276425 2.19% 83.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 25215066 16.85% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3276423 2.19% 83.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 25215068 16.85% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149606522 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 149606500 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -469,12 +454,12 @@ system.cpu.commit.branches 44587533 # Nu system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. system.cpu.commit.int_insts 316365839 # Number of committed integer instructions. system.cpu.commit.function_calls 8007752 # Number of function calls committed. -system.cpu.commit.bw_lim_events 25215066 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 25215068 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 557294459 # The number of ROB reads -system.cpu.rob.rob_writes 870687579 # The number of ROB writes -system.cpu.timesIdled 3435 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 193820 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 557294437 # The number of ROB reads +system.cpu.rob.rob_writes 870687583 # The number of ROB writes +system.cpu.timesIdled 3434 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 193842 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated @@ -483,18 +468,18 @@ system.cpu.cpi_total 0.411815 # CP system.cpu.ipc 2.428275 # IPC: Instructions Per Cycle system.cpu.ipc_total 2.428275 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 398027050 # number of integer regfile reads -system.cpu.int_regfile_writes 170092718 # number of integer regfile writes +system.cpu.int_regfile_writes 170092717 # number of integer regfile writes system.cpu.fp_regfile_reads 156507210 # number of floating regfile reads system.cpu.fp_regfile_writes 104024348 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 2144 # number of replacements -system.cpu.icache.tagsinuse 1832.992748 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1832.992783 # Cycle average of tags in use system.cpu.icache.total_refs 50214380 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 4071 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 12334.654876 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1832.992748 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1832.992783 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.895016 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.895016 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 50214380 # number of ReadReq hits @@ -509,12 +494,12 @@ system.cpu.icache.demand_misses::cpu.inst 5477 # n system.cpu.icache.demand_misses::total 5477 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 5477 # number of overall misses system.cpu.icache.overall_misses::total 5477 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 242175000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 242175000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 242175000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 242175000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 242175000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 242175000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 242151500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 242151500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 242151500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 242151500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 242151500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 242151500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 50219857 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 50219857 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 50219857 # number of demand (read+write) accesses @@ -527,12 +512,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000109 system.cpu.icache.demand_miss_rate::total 0.000109 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000109 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000109 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44216.724484 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 44216.724484 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 44216.724484 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 44216.724484 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 44216.724484 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 44216.724484 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44212.433814 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 44212.433814 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 44212.433814 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 44212.433814 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 44212.433814 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 44212.433814 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 692 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -553,34 +538,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4071 system.cpu.icache.demand_mshr_misses::total 4071 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4071 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4071 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 185126500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 185126500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 185126500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 185126500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 185126500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 185126500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 185116500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 185116500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 185116500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 185116500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 185116500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 185116500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000081 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000081 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000081 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45474.453451 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 45474.453451 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45474.453451 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 45474.453451 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45474.453451 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 45474.453451 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45471.997052 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 45471.997052 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45471.997052 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 45471.997052 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45471.997052 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 45471.997052 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 4012.712180 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 4012.712247 # Cycle average of tags in use system.cpu.l2cache.total_refs 831 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 4852 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.171270 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 372.528713 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2978.555345 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 661.628123 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 372.528715 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2978.555395 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 661.628136 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.011369 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.090898 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.020191 # Average percentage of cache occupancy @@ -609,17 +594,17 @@ system.cpu.l2cache.demand_misses::total 7448 # nu system.cpu.l2cache.overall_misses::cpu.inst 3455 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3993 # number of overall misses system.cpu.l2cache.overall_misses::total 7448 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 174877500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51530000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 226407500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 163360500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 163360500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 174877500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 214890500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 389768000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 174877500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 214890500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 389768000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 174867500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51533000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 226400500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 163361000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 163361000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 174867500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 214894000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 389761500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 174867500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 214894000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 389761500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 4071 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 990 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 5061 # number of ReadReq accesses(hits+misses) @@ -644,17 +629,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.902460 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.848686 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.954806 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.902460 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50615.774240 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59849.012776 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52457.715477 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52158.524904 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52158.524904 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50615.774240 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53816.804408 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52331.901182 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50615.774240 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53816.804408 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52331.901182 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50612.879884 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59852.497096 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52456.093605 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52158.684547 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52158.684547 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50612.879884 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53817.680942 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52331.028464 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50612.879884 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53817.680942 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52331.028464 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -674,17 +659,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7448 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3455 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3993 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7448 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 131818904 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 40942458 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 172761362 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 125001233 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 125001233 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 131818904 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 165943691 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 297762595 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 131818904 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 165943691 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 297762595 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 131805705 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 40944982 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 172750687 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 124998745 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 124998745 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 131805705 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 165943727 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 297749432 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 131805705 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 165943727 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 297749432 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.848686 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869697 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.852796 # mshr miss rate for ReadReq accesses @@ -696,37 +681,37 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.902460 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.848686 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.954806 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.902460 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38153.083647 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47552.216028 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40028.119092 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39910.993934 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39910.993934 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38153.083647 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41558.650388 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39978.866139 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38153.083647 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41558.650388 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39978.866139 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38149.263386 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47555.147503 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40025.645737 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39910.199553 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39910.199553 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38149.263386 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41558.659404 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39977.098818 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38149.263386 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41558.659404 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39977.098818 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 780 # number of replacements -system.cpu.dcache.tagsinuse 3297.047040 # Cycle average of tags in use -system.cpu.dcache.total_refs 159960718 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3297.047136 # Cycle average of tags in use +system.cpu.dcache.total_refs 159960719 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 4182 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 38249.813008 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 38249.813247 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3297.047040 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 3297.047136 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.804943 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.804943 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 86459752 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86459752 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 86459753 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86459753 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 73500960 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 73500960 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 6 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 6 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 159960712 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 159960712 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 159960712 # number of overall hits -system.cpu.dcache.overall_hits::total 159960712 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 159960713 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 159960713 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 159960713 # number of overall hits +system.cpu.dcache.overall_hits::total 159960713 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1811 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1811 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 19769 # number of WriteReq misses @@ -735,24 +720,24 @@ system.cpu.dcache.demand_misses::cpu.data 21580 # n system.cpu.dcache.demand_misses::total 21580 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 21580 # number of overall misses system.cpu.dcache.overall_misses::total 21580 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 89987500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 89987500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 779488110 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 779488110 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 869475610 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 869475610 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 869475610 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 869475610 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86461563 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86461563 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 89990500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 89990500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 779566610 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 779566610 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 869557110 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 869557110 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 869557110 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 869557110 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86461564 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86461564 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 159982292 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 159982292 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 159982292 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 159982292 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 159982293 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 159982293 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 159982293 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 159982293 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses @@ -761,19 +746,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000135 system.cpu.dcache.demand_miss_rate::total 0.000135 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000135 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000135 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49689.398123 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 49689.398123 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39429.819920 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39429.819920 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40290.806766 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40290.806766 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40290.806766 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40290.806766 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 28165 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49691.054666 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49691.054666 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39433.790784 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39433.790784 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40294.583411 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40294.583411 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40294.583411 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40294.583411 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 28158 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 631 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.635499 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.624406 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -795,14 +780,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4182 system.cpu.dcache.demand_mshr_misses::total 4182 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4182 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4182 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53863000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 53863000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167256500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 167256500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 221119500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 221119500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 221119500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 221119500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53866000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 53866000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167257000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 167257000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 221123000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 221123000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 221123000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 221123000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses @@ -811,14 +796,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54407.070707 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54407.070707 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52398.652882 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52398.652882 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52874.103300 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52874.103300 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52874.103300 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52874.103300 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54410.101010 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54410.101010 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52398.809524 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52398.809524 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52874.940220 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52874.940220 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52874.940220 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52874.940220 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index c2e0aed87..3aa47fab4 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.068358 # Nu sim_ticks 68358106500 # Number of ticks simulated final_tick 68358106500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 148173 # Simulator instruction rate (inst/s) -host_op_rate 189432 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37097000 # Simulator tick rate (ticks/s) -host_mem_usage 250340 # Number of bytes of host memory used -host_seconds 1842.69 # Real time elapsed on the host +host_inst_rate 161957 # Simulator instruction rate (inst/s) +host_op_rate 207054 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40547923 # Simulator tick rate (ticks/s) +host_mem_usage 250356 # Number of bytes of host memory used +host_seconds 1685.86 # Real time elapsed on the host sim_insts 273036725 # Number of instructions simulated sim_ops 349064449 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 193152 # Number of bytes read from this memory @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 7278 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 2 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 4253 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 2167 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 597 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 46727256 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 192182256 # Sum of mem lat for all requests +system.physmem.totQLat 46720000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 192175000 # Sum of mem lat for all requests system.physmem.totBusLat 36390000 # Total cycles spent in databus access system.physmem.totBankLat 109065000 # Total cycles spent in bank access -system.physmem.avgQLat 6420.34 # Average queueing delay per request +system.physmem.avgQLat 6419.35 # Average queueing delay per request system.physmem.avgBankLat 14985.57 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26405.92 # Average memory access latency +system.physmem.avgMemAccLat 26404.92 # Average memory access latency system.physmem.avgRdBW 6.81 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 6.81 # Average consumed read bandwidth in MB/s @@ -584,7 +569,7 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18773.979853 system.cpu.icache.overall_avg_mshr_miss_latency::total 18773.979853 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 3956.608159 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 3956.608160 # Cycle average of tags in use system.cpu.l2cache.total_refs 13151 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 5398 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.436273 # Average number of references to valid blocks. @@ -702,19 +687,19 @@ system.cpu.l2cache.demand_mshr_misses::total 7278 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3019 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4259 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7278 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115050359 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 62984754 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 178035113 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115047807 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 62983881 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 178031688 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 100922692 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 100922692 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115050359 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 163907446 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 278957805 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115050359 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 163907446 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 278957805 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 100921221 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 100921221 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115047807 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 163905102 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 278952909 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115047807 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 163905102 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 278952909 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191318 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.815000 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255176 # mshr miss rate for ReadReq accesses @@ -728,19 +713,19 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.356940 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191318 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.923861 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.356940 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38108.764160 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42934.392638 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39686.828578 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38107.918847 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42933.797546 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39686.065091 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36147.095989 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36147.095989 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38108.764160 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38484.960319 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38328.909728 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38108.764160 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38484.960319 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38328.909728 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36146.569126 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36146.569126 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38107.918847 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38484.409955 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38328.237016 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38107.918847 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38484.409955 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38328.237016 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1413 # number of replacements system.cpu.dcache.tagsinuse 3109.949983 # Cycle average of tags in use diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 5cf480155..c87b3b35f 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.629815 # Number of seconds simulated -sim_ticks 629814900000 # Number of ticks simulated -final_tick 629814900000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.629620 # Number of seconds simulated +sim_ticks 629619966000 # Number of ticks simulated +final_tick 629619966000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 180734 # Simulator instruction rate (inst/s) -host_op_rate 180734 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62438874 # Simulator tick rate (ticks/s) -host_mem_usage 248904 # Number of bytes of host memory used -host_seconds 10086.90 # Real time elapsed on the host +host_inst_rate 178339 # Simulator instruction rate (inst/s) +host_op_rate 178339 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61592425 # Simulator tick rate (ticks/s) +host_mem_usage 247872 # Number of bytes of host memory used +host_seconds 10222.36 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 176256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30295232 # Number of bytes read from this memory -system.physmem.bytes_read::total 30471488 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 176256 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 176256 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 176384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30295936 # Number of bytes read from this memory +system.physmem.bytes_read::total 30472320 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 176384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 176384 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2754 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 473363 # Number of read requests responded to by this memory -system.physmem.num_reads::total 476117 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2756 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 473374 # Number of read requests responded to by this memory +system.physmem.num_reads::total 476130 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 279854 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 48101803 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 48381656 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 279854 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 279854 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6799001 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6799001 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6799001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 279854 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 48101803 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 55180657 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 476117 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 280144 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 48117813 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 48397957 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 280144 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 280144 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6801106 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6801106 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6801106 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 280144 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 48117813 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 55199063 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 476130 # Total number of read requests seen system.physmem.writeReqs 66908 # Total number of write requests seen -system.physmem.cpureqs 543025 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 30471488 # Total number of bytes read from memory +system.physmem.cpureqs 543038 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30472320 # Total number of bytes read from memory system.physmem.bytesWritten 4282112 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30471488 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 30472320 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 4282112 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 84 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 29663 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 29736 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 29645 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 29664 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 29737 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 29644 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 29657 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 29698 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 29699 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 29716 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 29817 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 29814 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 29793 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 29817 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 29794 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 29811 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 29701 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 29703 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 29776 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 29780 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 29752 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 29783 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 29754 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 29855 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 29819 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 4150 # Track writes on a per bank basis @@ -77,38 +77,25 @@ system.physmem.perBankWrReqs::14 4205 # Tr system.physmem.perBankWrReqs::15 4210 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 629814837500 # Total gap between requests +system.physmem.totGap 629619903500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 476117 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 66908 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 406568 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66991 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 165 # What read queue length does an incoming req see +system.physmem.readPktSize::6 476130 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 66908 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 406575 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66997 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2280 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 167 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 25 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -137,7 +124,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 2899 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 2909 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 2909 # What write queue length does an incoming req see @@ -170,57 +156,56 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2509077325 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 20518523575 # Sum of mem lat for all requests -system.physmem.totBusLat 2380165000 # Total cycles spent in databus access -system.physmem.totBankLat 15629281250 # Total cycles spent in bank access -system.physmem.avgQLat 5270.81 # Average queueing delay per request -system.physmem.avgBankLat 32832.35 # Average bank access latency per request +system.physmem.totQLat 2394780250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 20405886500 # Sum of mem lat for all requests +system.physmem.totBusLat 2380230000 # Total cycles spent in databus access +system.physmem.totBankLat 15630876250 # Total cycles spent in bank access +system.physmem.avgQLat 5030.56 # Average queueing delay per request +system.physmem.avgBankLat 32834.80 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 43103.15 # Average memory access latency -system.physmem.avgRdBW 48.38 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 42865.37 # Average memory access latency +system.physmem.avgRdBW 48.40 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 6.80 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 48.38 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 48.40 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 6.80 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.43 # Data bus utilization in percentage system.physmem.avgRdQLen 0.03 # Average read queue length over time system.physmem.avgWrQLen 11.00 # Average write queue length over time -system.physmem.readRowHits 143855 # Number of row buffer hits during reads +system.physmem.readRowHits 143857 # Number of row buffer hits during reads system.physmem.writeRowHits 46184 # Number of row buffer hits during writes system.physmem.readRowHitRate 30.22 # Row buffer hit rate for reads system.physmem.writeRowHitRate 69.03 # Row buffer hit rate for writes -system.physmem.avgGap 1159826.60 # Average gap between requests -system.cpu.branchPred.lookups 389306486 # Number of BP lookups -system.cpu.branchPred.condPredicted 255918117 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 25837227 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 318716729 # Number of BTB lookups -system.cpu.branchPred.BTBHits 258426851 # Number of BTB hits +system.physmem.avgGap 1159439.86 # Average gap between requests +system.cpu.branchPred.lookups 389447649 # Number of BP lookups +system.cpu.branchPred.condPredicted 255913711 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 25827412 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 318653162 # Number of BTB lookups +system.cpu.branchPred.BTBHits 258406685 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.083554 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 57314223 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 6830 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.093401 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 57304748 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 7060 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 523161150 # DTB read hits -system.cpu.dtb.read_misses 589917 # DTB read misses +system.cpu.dtb.read_hits 523436365 # DTB read hits +system.cpu.dtb.read_misses 589877 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 523751067 # DTB read accesses -system.cpu.dtb.write_hits 283054328 # DTB write hits -system.cpu.dtb.write_misses 50219 # DTB write misses +system.cpu.dtb.read_accesses 524026242 # DTB read accesses +system.cpu.dtb.write_hits 283043527 # DTB write hits +system.cpu.dtb.write_misses 50254 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 283104547 # DTB write accesses -system.cpu.dtb.data_hits 806215478 # DTB hits -system.cpu.dtb.data_misses 640136 # DTB misses +system.cpu.dtb.write_accesses 283093781 # DTB write accesses +system.cpu.dtb.data_hits 806479892 # DTB hits +system.cpu.dtb.data_misses 640131 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 806855614 # DTB accesses -system.cpu.itb.fetch_hits 394785394 # ITB hits -system.cpu.itb.fetch_misses 699 # ITB misses +system.cpu.dtb.data_accesses 807120023 # DTB accesses +system.cpu.itb.fetch_hits 394546295 # ITB hits +system.cpu.itb.fetch_misses 717 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 394786093 # ITB accesses +system.cpu.itb.fetch_accesses 394547012 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -234,98 +219,98 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 1259629801 # number of cpu cycles simulated +system.cpu.numCycles 1259239933 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 410360591 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3276218906 # Number of instructions fetch has processed -system.cpu.fetch.Branches 389306486 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 315741074 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 630494032 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 158021665 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 72839727 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 148 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 7225 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 64 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 394785394 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 10887979 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1245397368 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.630661 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.141486 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 410282333 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3275811622 # Number of instructions fetch has processed +system.cpu.fetch.Branches 389447649 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 315711433 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 630410102 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 157985911 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 72865288 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 149 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 7390 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 394546295 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10716533 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1245235231 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.630677 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.141977 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 614903336 49.37% 49.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 57906135 4.65% 54.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 43369742 3.48% 57.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 71861713 5.77% 63.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 128784934 10.34% 73.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 45918421 3.69% 77.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 41219044 3.31% 80.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7530301 0.60% 81.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 233903742 18.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 614825129 49.37% 49.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 58056687 4.66% 54.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 43354375 3.48% 57.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 71856761 5.77% 63.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 128610709 10.33% 73.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 45745044 3.67% 77.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 41218746 3.31% 80.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7546870 0.61% 81.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 234020910 18.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1245397368 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.309064 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.600938 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 438252598 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 59249665 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 607151892 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9059684 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 131683529 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 32106155 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12464 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3195982000 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 46456 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 131683529 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 467489876 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 24458626 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 27637 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 586624719 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 35112981 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3097789893 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 99 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 15390 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 28842141 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2055592035 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3582007579 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3461235411 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 120772168 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1245235231 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.309272 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.601420 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 438008414 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 59262942 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 607236165 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9069872 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 131657838 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 32266957 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12470 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3196223031 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 46480 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 131657838 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 467254081 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 24463646 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 27494 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 586711565 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 35120607 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3098173488 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 98 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 15446 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 28849573 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2055567023 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3582389843 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3461627532 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 120762311 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 670622965 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4249 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 110 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 109569448 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 744863024 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 351426191 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 68774306 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8838853 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2625568629 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 106 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2161657606 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 17941272 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 802459111 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 727402983 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 67 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1245397368 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.735717 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.803838 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 670597953 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4242 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 103 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 109579430 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 745093938 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 351398329 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 68579657 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8864385 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2626006003 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 100 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2162044617 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 17925122 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 802898808 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 727596475 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 61 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1245235231 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.736254 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.804060 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 448194916 35.99% 35.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 197399515 15.85% 51.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 251498314 20.19% 72.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 120129049 9.65% 81.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 104781180 8.41% 90.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 79785428 6.41% 96.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 24208472 1.94% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 17632328 1.42% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1768166 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 447917303 35.97% 35.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 197535103 15.86% 51.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 251432136 20.19% 72.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 120080138 9.64% 81.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 104735346 8.41% 90.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 79904704 6.42% 96.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 24241740 1.95% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17620604 1.42% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1768157 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1245397368 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1245235231 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1146254 3.12% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1146296 3.12% 3.12% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available @@ -354,15 +339,15 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.12% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.12% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.12% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 25630359 69.68% 72.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 10007683 27.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 25620524 69.67% 72.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 10007560 27.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1235285403 57.15% 57.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1235570303 57.15% 57.15% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 17096 0.00% 57.15% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 27851426 1.29% 58.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 27851417 1.29% 58.44% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 8254694 0.38% 58.82% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 7204648 0.33% 59.15% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.15% # Type of FU issued @@ -388,84 +373,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.15% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.15% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.15% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 589902835 27.29% 86.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 293138748 13.56% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 590015596 27.29% 86.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 293128107 13.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2161657606 # Type of FU issued -system.cpu.iq.rate 1.716105 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36784296 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.017017 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5472336078 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3339899399 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1991115322 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 151102070 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 88201964 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 73610146 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2120988960 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 77450190 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62844771 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2162044617 # Type of FU issued +system.cpu.iq.rate 1.716944 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36774380 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.017009 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5472922147 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3340796044 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1991352678 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 151101820 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 88182161 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 73610057 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2121366202 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 77450043 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 63177927 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 233792998 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 726346 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 76067 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 140631295 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 234023912 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1058362 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 75850 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 140603433 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 4418 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2432 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 2424 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 131683529 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 10419712 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 524131 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2988971416 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 730880 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 744863024 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 351426191 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 106 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 195253 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 131657838 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 10420983 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 524239 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2989422700 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 731121 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 745093938 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 351398329 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 100 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 195339 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 1467 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 76067 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 25831488 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 28075 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 25859563 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2067932709 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 523751206 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 93724897 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 75850 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 25820235 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 27779 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 25848014 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2068492319 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 524026374 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 93552298 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 363402681 # number of nop insts executed -system.cpu.iew.exec_refs 806856273 # number of memory reference insts executed -system.cpu.iew.exec_branches 278042301 # Number of branches executed -system.cpu.iew.exec_stores 283105067 # Number of stores executed -system.cpu.iew.exec_rate 1.641699 # Inst execution rate -system.cpu.iew.wb_sent 2067106315 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2064725468 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1181149065 # num instructions producing a value -system.cpu.iew.wb_consumers 1753530061 # num instructions consuming a value +system.cpu.iew.exec_nop 363416597 # number of nop insts executed +system.cpu.iew.exec_refs 807120680 # number of memory reference insts executed +system.cpu.iew.exec_branches 278196977 # Number of branches executed +system.cpu.iew.exec_stores 283094306 # Number of stores executed +system.cpu.iew.exec_rate 1.642651 # Inst execution rate +system.cpu.iew.wb_sent 2067333908 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2064962735 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1181126750 # num instructions producing a value +system.cpu.iew.wb_consumers 1753498514 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.639153 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.673584 # average fanout of values written-back +system.cpu.iew.wb_rate 1.639849 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.673583 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 963038308 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 963484022 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 25825176 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1113713839 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.803863 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.507965 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 25815357 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1113577393 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.804084 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.508160 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 494406511 44.39% 44.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 228855545 20.55% 64.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 119827890 10.76% 75.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 58850017 5.28% 80.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 50714183 4.55% 85.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24146625 2.17% 87.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19124586 1.72% 89.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 16719001 1.50% 90.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 101069481 9.07% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 494309525 44.39% 44.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 228815920 20.55% 64.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 119838693 10.76% 75.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 58859369 5.29% 80.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 50684004 4.55% 85.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24146580 2.17% 87.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19115188 1.72% 89.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 16708765 1.50% 90.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 101099349 9.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1113713839 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1113577393 # Number of insts commited each cycle system.cpu.commit.committedInsts 2008987604 # Number of instructions committed system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -476,192 +461,192 @@ system.cpu.commit.branches 266706457 # Nu system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. system.cpu.commit.function_calls 39955347 # Number of function calls committed. -system.cpu.commit.bw_lim_events 101069481 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 101099349 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3979033860 # The number of ROB reads -system.cpu.rob.rob_writes 6075737407 # The number of ROB writes -system.cpu.timesIdled 331555 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 14232433 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3979313260 # The number of ROB reads +system.cpu.rob.rob_writes 6076602940 # The number of ROB writes +system.cpu.timesIdled 331541 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 14004702 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated -system.cpu.cpi 0.690949 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.690949 # CPI: Total CPI of All Threads -system.cpu.ipc 1.447285 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.447285 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2629419671 # number of integer regfile reads -system.cpu.int_regfile_writes 1497304474 # number of integer regfile writes -system.cpu.fp_regfile_reads 78811610 # number of floating regfile reads -system.cpu.fp_regfile_writes 52661263 # number of floating regfile writes +system.cpu.cpi 0.690735 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.690735 # CPI: Total CPI of All Threads +system.cpu.ipc 1.447733 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.447733 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2629807592 # number of integer regfile reads +system.cpu.int_regfile_writes 1497388428 # number of integer regfile writes +system.cpu.fp_regfile_reads 78811502 # number of floating regfile reads +system.cpu.fp_regfile_writes 52661191 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 8336 # number of replacements -system.cpu.icache.tagsinuse 1655.843165 # Cycle average of tags in use -system.cpu.icache.total_refs 394772509 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 10048 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 39288.665307 # Average number of references to valid blocks. +system.cpu.icache.replacements 8338 # number of replacements +system.cpu.icache.tagsinuse 1655.801182 # Cycle average of tags in use +system.cpu.icache.total_refs 394533427 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 10050 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 39257.057413 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1655.843165 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.808517 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.808517 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 394772509 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 394772509 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 394772509 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 394772509 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 394772509 # number of overall hits -system.cpu.icache.overall_hits::total 394772509 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12885 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12885 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12885 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12885 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12885 # number of overall misses -system.cpu.icache.overall_misses::total 12885 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 310466999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 310466999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 310466999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 310466999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 310466999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 310466999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 394785394 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 394785394 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 394785394 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 394785394 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 394785394 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 394785394 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1655.801182 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.808497 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.808497 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 394533427 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 394533427 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 394533427 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 394533427 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 394533427 # number of overall hits +system.cpu.icache.overall_hits::total 394533427 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12868 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12868 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12868 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12868 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12868 # number of overall misses +system.cpu.icache.overall_misses::total 12868 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 310260499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 310260499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 310260499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 310260499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 310260499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 310260499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 394546295 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 394546295 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 394546295 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 394546295 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 394546295 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 394546295 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000033 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000033 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000033 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000033 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000033 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000033 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24095.226931 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 24095.226931 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 24095.226931 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 24095.226931 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 24095.226931 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 24095.226931 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1110 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24111.011735 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 24111.011735 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 24111.011735 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 24111.011735 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 24111.011735 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 24111.011735 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1217 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 69.375000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 71.588235 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2836 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2836 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2836 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2836 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2836 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2836 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10049 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 10049 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 10049 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 10049 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 10049 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 10049 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 233497999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 233497999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 233497999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 233497999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 233497999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 233497999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2817 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2817 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2817 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2817 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2817 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2817 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10051 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 10051 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 10051 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 10051 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 10051 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 10051 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 233282499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 233282499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 233282499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 233282499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 233282499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 233282499 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23235.943776 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23235.943776 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23235.943776 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 23235.943776 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23235.943776 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 23235.943776 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23209.879514 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23209.879514 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23209.879514 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 23209.879514 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23209.879514 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 23209.879514 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 443339 # number of replacements -system.cpu.l2cache.tagsinuse 32702.171158 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1090083 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 476075 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.289730 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 443352 # number of replacements +system.cpu.l2cache.tagsinuse 32702.161581 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1090053 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 476088 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.289604 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 1306.977523 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 33.798931 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31361.394703 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.039886 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001031 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.957074 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 1307.378151 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 33.870078 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31360.913353 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.039898 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001034 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.957059 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.997991 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 7294 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1053750 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1061044 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1053720 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1061014 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 95989 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 95989 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4788 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4788 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 4789 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4789 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 7294 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1058538 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1065832 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1058509 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1065803 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 7294 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1058538 # number of overall hits -system.cpu.l2cache.overall_hits::total 1065832 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2755 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 406509 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 409264 # number of ReadReq misses +system.cpu.l2cache.overall_hits::cpu.data 1058509 # number of overall hits +system.cpu.l2cache.overall_hits::total 1065803 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2757 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 406520 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 409277 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 66854 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 66854 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2755 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 473363 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 476118 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2755 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 473363 # number of overall misses -system.cpu.l2cache.overall_misses::total 476118 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 150496500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 27603201000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 27753697500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3778888000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3778888000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 150496500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 31382089000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31532585500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 150496500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 31382089000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31532585500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 10049 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1460259 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1470308 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 2757 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 473374 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 476131 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2757 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 473374 # number of overall misses +system.cpu.l2cache.overall_misses::total 476131 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 150279500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 27491647500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 27641927000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3779391500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3779391500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 150279500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 31271039000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 31421318500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 150279500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 31271039000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31421318500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 10051 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1460240 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1470291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 95989 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 95989 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 71642 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 71642 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 10049 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1531901 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1541950 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 10049 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1531901 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1541950 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.274157 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.278381 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.278353 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.933168 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.933168 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.274157 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.309004 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.308777 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.274157 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.309004 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.308777 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54626.678766 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67903.050117 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67813.678946 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56524.486194 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56524.486194 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54626.678766 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66296.032854 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66228.509529 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54626.678766 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66296.032854 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66228.509529 # average overall miss latency +system.cpu.l2cache.ReadExReq_accesses::cpu.data 71643 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 71643 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 10051 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1531883 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1541934 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 10051 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1531883 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1541934 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.274301 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.278393 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.278365 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.933155 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.933155 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.274301 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.309014 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.308788 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.274301 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.309014 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.308788 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54508.342401 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67626.801879 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67538.432406 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56532.017531 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56532.017531 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54508.342401 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66059.899783 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 65993.011377 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54508.342401 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66059.899783 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 65993.011377 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -672,178 +657,178 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66908 # number of writebacks system.cpu.l2cache.writebacks::total 66908 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2755 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406509 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 409264 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2757 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406520 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 409277 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66854 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66854 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2755 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 473363 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 476118 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2755 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 473363 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 476118 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 116276173 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 22528768631 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22645044804 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2972753104 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2972753104 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116276173 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25501521735 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25617797908 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116276173 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25501521735 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25617797908 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.274157 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278381 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278353 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933168 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933168 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.274157 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.309004 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.308777 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.274157 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.309004 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.308777 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42205.507441 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55420.098032 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55331.142744 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 44466.346127 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 44466.346127 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42205.507441 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53873.077818 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53805.564814 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42205.507441 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53873.077818 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53805.564814 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2757 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 473374 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 476131 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2757 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 473374 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 476131 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 116032718 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 22416103108 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22532135826 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2973259427 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2973259427 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116032718 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25389362535 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25505395253 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116032718 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25389362535 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25505395253 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.274301 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278393 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278365 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933155 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933155 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.274301 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.309014 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.308788 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.274301 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.309014 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.308788 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42086.586144 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55141.452101 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55053.511011 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 44473.919691 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 44473.919691 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42086.586144 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53634.890245 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53568.020677 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42086.586144 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53634.890245 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53568.020677 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1527805 # number of replacements -system.cpu.dcache.tagsinuse 4094.859699 # Cycle average of tags in use -system.cpu.dcache.total_refs 668117069 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1531901 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 436.135931 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 314208000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.859699 # Average occupied blocks per requestor +system.cpu.dcache.replacements 1527787 # number of replacements +system.cpu.dcache.tagsinuse 4094.859370 # Cycle average of tags in use +system.cpu.dcache.total_refs 668059061 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1531883 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 436.103189 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 314057000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.859370 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999722 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999722 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 458383895 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 458383895 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 209733146 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 209733146 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 28 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 28 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 668117041 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 668117041 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 668117041 # number of overall hits -system.cpu.dcache.overall_hits::total 668117041 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1925777 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1925777 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1061750 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1061750 # number of WriteReq misses +system.cpu.dcache.ReadReq_hits::cpu.data 458325911 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 458325911 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 209733124 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 209733124 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 26 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 26 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 668059035 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 668059035 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 668059035 # number of overall hits +system.cpu.dcache.overall_hits::total 668059035 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1925830 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1925830 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1061772 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1061772 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2987527 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2987527 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2987527 # number of overall misses -system.cpu.dcache.overall_misses::total 2987527 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 64904546500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 64904546500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 35420882879 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 35420882879 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 44000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 44000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 100325429379 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 100325429379 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 100325429379 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 100325429379 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 460309672 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 460309672 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2987602 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2987602 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2987602 # number of overall misses +system.cpu.dcache.overall_misses::total 2987602 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 64791591000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 64791591000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 35422596379 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 35422596379 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 44500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 44500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 100214187379 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 100214187379 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 100214187379 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 100214187379 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 460251741 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 460251741 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 29 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 671104568 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 671104568 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 671104568 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 671104568 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 27 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 27 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 671046637 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 671046637 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 671046637 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 671046637 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004184 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.004184 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005037 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.005037 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.034483 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.034483 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.037037 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.037037 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.004452 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.004452 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.004452 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.004452 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33703.043758 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33703.043758 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33360.850369 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33360.850369 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 44000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 44000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33581.430186 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33581.430186 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 33581.430186 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 33581.430186 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 14466 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33643.463338 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33643.463338 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33361.772941 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33361.772941 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 44500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 44500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33543.352622 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33543.352622 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33543.352622 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 33543.352622 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 14428 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 113 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 388 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 387 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.283505 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.281654 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 113 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 95989 # number of writebacks system.cpu.dcache.writebacks::total 95989 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465519 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 465519 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 990108 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 990108 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1455627 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1455627 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1455627 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1455627 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460258 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1460258 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71642 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 71642 # number of WriteReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465591 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 465591 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 990129 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 990129 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1455720 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1455720 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1455720 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1455720 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460239 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1460239 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71643 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 71643 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1531900 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1531900 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1531900 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1531900 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39601531500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 39601531500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3899018500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3899018500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 42000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 42000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43500550000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 43500550000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43500550000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 43500550000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003172 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003172 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 1531882 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1531882 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1531882 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1531882 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39489667000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 39489667000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3899533000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3899533000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 42500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 42500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43389200000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 43389200000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43389200000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 43389200000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003173 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003173 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.034483 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.034483 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.037037 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.037037 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002283 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.002283 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002283 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002283 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27119.544286 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27119.544286 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54423.641160 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54423.641160 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 42000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 42000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28396.468438 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28396.468438 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28396.468438 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28396.468438 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27043.290174 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27043.290174 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54430.062951 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54430.062951 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 42500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 42500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28324.113737 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28324.113737 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28324.113737 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28324.113737 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 2843a5b3f..675c50cd2 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.627778 # Nu sim_ticks 627777658000 # Number of ticks simulated final_tick 627777658000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 102547 # Simulator instruction rate (inst/s) -host_op_rate 139655 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46502403 # Simulator tick rate (ticks/s) -host_mem_usage 263380 # Number of bytes of host memory used -host_seconds 13499.90 # Real time elapsed on the host +host_inst_rate 109787 # Simulator instruction rate (inst/s) +host_op_rate 149515 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49785649 # Simulator tick rate (ticks/s) +host_mem_usage 262368 # Number of bytes of host memory used +host_seconds 12609.61 # Real time elapsed on the host sim_insts 1384370590 # Number of instructions simulated sim_ops 1885325342 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 154944 # Number of bytes read from this memory @@ -36,13 +36,13 @@ system.physmem.bw_total::cpu.data 48174508 # To system.physmem.bw_total::total 55159809 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 474966 # Total number of read requests seen system.physmem.writeReqs 66098 # Total number of write requests seen -system.physmem.cpureqs 545370 # Reqs generatd by CPU via cache - shady +system.physmem.cpureqs 545372 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 30397824 # Total number of bytes read from memory system.physmem.bytesWritten 4230272 # Total number of bytes written to memory system.physmem.bytesConsumedRd 30397824 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 160 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4306 # Reqs where no action is needed +system.physmem.neitherReadNorWrite 4308 # Reqs where no action is needed system.physmem.perBankRdReqs::0 29710 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 29703 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 29690 # Track reads on a per bank basis @@ -85,26 +85,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 474966 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 66098 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4306 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 66098 # Categorize write packet sizes system.physmem.rdQLenPdf::0 405913 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 66670 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 2123 # What read queue length does an incoming req see @@ -137,7 +124,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 2873 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 2874 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 2874 # What write queue length does an incoming req see @@ -170,15 +156,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3183088396 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 21162955896 # Sum of mem lat for all requests +system.physmem.totQLat 3182824500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 21162788250 # Sum of mem lat for all requests system.physmem.totBusLat 2374030000 # Total cycles spent in databus access -system.physmem.totBankLat 15605837500 # Total cycles spent in bank access -system.physmem.avgQLat 6703.98 # Average queueing delay per request -system.physmem.avgBankLat 32867.82 # Average bank access latency per request +system.physmem.totBankLat 15605933750 # Total cycles spent in bank access +system.physmem.avgQLat 6703.42 # Average queueing delay per request +system.physmem.avgBankLat 32868.02 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 44571.80 # Average memory access latency +system.physmem.avgMemAccLat 44571.44 # Average memory access latency system.physmem.avgRdBW 48.42 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 6.74 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 48.42 # Average consumed read bandwidth in MB/s @@ -192,11 +177,11 @@ system.physmem.writeRowHits 45521 # Nu system.physmem.readRowHitRate 30.19 # Row buffer hit rate for reads system.physmem.writeRowHitRate 68.87 # Row buffer hit rate for writes system.physmem.avgGap 1160264.94 # Average gap between requests -system.cpu.branchPred.lookups 438315949 # Number of BP lookups -system.cpu.branchPred.condPredicted 349727895 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 30635218 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 247833729 # Number of BTB lookups -system.cpu.branchPred.BTBHits 226959272 # Number of BTB hits +system.cpu.branchPred.lookups 438315942 # Number of BP lookups +system.cpu.branchPred.condPredicted 349727890 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 30635219 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 247833723 # Number of BTB lookups +system.cpu.branchPred.BTBHits 226959266 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 91.577233 # BTB Hit Percentage system.cpu.branchPred.usedRAS 52304914 # Number of times the RAS was used to get a target. @@ -247,94 +232,94 @@ system.cpu.workload.num_syscalls 1411 # Nu system.cpu.numCycles 1255555317 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 353470069 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2285596028 # Number of instructions fetch has processed -system.cpu.fetch.Branches 438315949 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 279264186 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 600835407 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 353470076 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2285596018 # Number of instructions fetch has processed +system.cpu.fetch.Branches 438315942 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 279264180 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 600835401 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 157814267 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 132516295 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 132517239 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 565 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 11276 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 79 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 333121638 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 10719820 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1213960668 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.592464 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 333121635 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10719821 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1213961612 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.592462 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.190927 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 613169619 50.51% 50.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42771995 3.52% 54.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 613170569 50.51% 50.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42771992 3.52% 54.03% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 95714848 7.88% 61.92% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 55497081 4.57% 66.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 71974347 5.93% 72.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 42167025 3.47% 75.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 30997749 2.55% 78.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 71974346 5.93% 72.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 42167023 3.47% 75.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 30997748 2.55% 78.45% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 31607119 2.60% 81.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 230060885 18.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 230060886 18.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1213960668 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 1213961612 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.349101 # Number of branch fetches per cycle system.cpu.fetch.rate 1.820387 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 402973564 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 105163486 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 561876522 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 16833920 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 127113176 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 44705456 # Number of times decode resolved a branch +system.cpu.decode.IdleCycles 402973570 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 105164432 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 561876513 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 16833922 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 127113175 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 44705454 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 15362 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3047243338 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 3047243320 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 28333 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 127113176 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 438520822 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 34436909 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 439020 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 541081767 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 72368974 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2975054938 # Number of instructions processed by rename +system.cpu.rename.SquashCycles 127113175 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 438520828 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 34437480 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 439400 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 541081761 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 72368968 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2975054899 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 69 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4810929 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 57090218 # Number of times rename has blocked due to LSQ full +system.cpu.rename.IQFullEvents 4810930 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 57090211 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2946030157 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14164065012 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13593632114 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 570432898 # Number of floating rename lookups +system.cpu.rename.RenamedOperands 2946030115 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14164064845 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13593631976 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 570432869 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 952890067 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25235 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 952890025 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 25236 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 22720 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 195466607 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 973207419 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 490834558 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 195466614 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 973207403 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 490834559 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 36203648 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 40613994 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2806590548 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.memDep0.conflictingStores 40613980 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2806590515 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 29404 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2437414927 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13391010 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 908731725 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2361150738 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 2437414876 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13391013 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 908731819 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2361150824 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 8020 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1213960668 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.007820 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.875088 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 1213961612 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.007819 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.875089 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 377941740 31.13% 31.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 183591562 15.12% 46.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 202672032 16.70% 62.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 169721528 13.98% 76.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 132842997 10.94% 87.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 93759242 7.72% 95.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 37926001 3.12% 98.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12454015 1.03% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 377942739 31.13% 31.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 183591536 15.12% 46.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 202672014 16.70% 62.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 169721523 13.98% 76.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 132842970 10.94% 87.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 93759245 7.72% 95.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 37926008 3.12% 98.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12454026 1.03% 99.75% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 3051551 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1213960668 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1213961612 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 716787 0.82% 0.82% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 24382 0.03% 0.85% # attempts to use FU when none available @@ -365,12 +350,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.85% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.85% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.85% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 55152383 62.89% 63.74% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 55152382 62.89% 63.74% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 31800755 36.26% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1108357182 45.47% 45.47% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1108357154 45.47% 45.47% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 11223525 0.46% 45.93% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.93% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 45.93% # Type of FU issued @@ -393,90 +378,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.93% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.99% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.99% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 6876477 0.28% 46.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5502589 0.23% 46.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5502588 0.23% 46.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23405387 0.96% 47.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23405386 0.96% 47.46% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.46% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.46% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 838249114 34.39% 81.85% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 442425362 18.15% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 838249094 34.39% 81.85% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 442425361 18.15% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2437414927 # Type of FU issued +system.cpu.iq.FU_type_0::total 2437414876 # Type of FU issued system.cpu.iq.rate 1.941304 # Inst issue rate -system.cpu.iq.fu_busy_cnt 87694307 # FU busy when requested +system.cpu.iq.fu_busy_cnt 87694306 # FU busy when requested system.cpu.iq.fu_busy_rate 0.035978 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6067361460 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3632711634 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2254358298 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 122514379 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 82707337 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 56439823 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2461788389 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 63320845 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 84306518 # Number of loads that had data forwarded from stores +system.cpu.iq.int_inst_queue_reads 6067362312 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3632711697 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2254358254 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 122514371 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 82707334 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 56439819 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2461788341 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 63320841 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 84306513 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 341820238 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 8584 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1429957 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 213839261 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 341820222 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 8583 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1429956 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 213839262 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 315 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 127113176 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 12638060 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1558330 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2806632420 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 127113175 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 12638633 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1558332 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2806632387 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 1396294 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 973207419 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 490834558 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 973207403 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 490834559 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 19418 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1554339 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 1554341 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 2519 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1429957 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 32461973 # Number of branches that were predicted taken incorrectly +system.cpu.iew.memOrderViolationEvents 1429956 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 32461974 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 1494406 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 33956379 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2363518803 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 792548176 # Number of load instructions executed +system.cpu.iew.branchMispredicts 33956380 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2363518752 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 792548156 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 73896124 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 12468 # number of nop insts executed -system.cpu.iew.exec_refs 1216269109 # number of memory reference insts executed -system.cpu.iew.exec_branches 322574295 # Number of branches executed -system.cpu.iew.exec_stores 423720933 # Number of stores executed +system.cpu.iew.exec_refs 1216269086 # number of memory reference insts executed +system.cpu.iew.exec_branches 322574286 # Number of branches executed +system.cpu.iew.exec_stores 423720930 # Number of stores executed system.cpu.iew.exec_rate 1.882449 # Inst execution rate -system.cpu.iew.wb_sent 2336489279 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2310798121 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1347631532 # num instructions producing a value -system.cpu.iew.wb_consumers 2523967593 # num instructions consuming a value +system.cpu.iew.wb_sent 2336489228 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2310798073 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1347631579 # num instructions producing a value +system.cpu.iew.wb_consumers 2523967689 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 1.840459 # insts written-back per cycle system.cpu.iew.wb_fanout 0.533934 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 921296208 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 921296175 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 30621417 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1086847492 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.734683 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.398806 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 30621418 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1086848437 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.734682 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.398805 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 446547765 41.09% 41.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 288590720 26.55% 67.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 95114963 8.75% 76.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 446548721 41.09% 41.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 288590719 26.55% 67.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 95114953 8.75% 76.39% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 70229595 6.46% 82.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 46461872 4.27% 87.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 22187807 2.04% 89.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15847038 1.46% 90.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10983680 1.01% 91.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 90884052 8.36% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 46461870 4.27% 87.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 22187798 2.04% 89.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15847039 1.46% 90.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10983692 1.01% 91.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 90884050 8.36% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1086847492 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1086848437 # Number of insts commited each cycle system.cpu.commit.committedInsts 1384381606 # Number of instructions committed system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -487,12 +472,12 @@ system.cpu.commit.branches 299634395 # Nu system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 90884052 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 90884050 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3802577661 # The number of ROB reads -system.cpu.rob.rob_writes 5740389540 # The number of ROB writes -system.cpu.timesIdled 353175 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 41594649 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3802578575 # The number of ROB reads +system.cpu.rob.rob_writes 5740389473 # The number of ROB writes +system.cpu.timesIdled 353174 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 41593705 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1384370590 # Number of Instructions Simulated system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated @@ -500,57 +485,57 @@ system.cpu.cpi 0.906950 # CP system.cpu.cpi_total 0.906950 # CPI: Total CPI of All Threads system.cpu.ipc 1.102596 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.102596 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11774707522 # number of integer regfile reads -system.cpu.int_regfile_writes 2226782313 # number of integer regfile writes -system.cpu.fp_regfile_reads 68797358 # number of floating regfile reads -system.cpu.fp_regfile_writes 49551948 # number of floating regfile writes -system.cpu.misc_regfile_reads 1364040381 # number of misc regfile reads +system.cpu.int_regfile_reads 11774707263 # number of integer regfile reads +system.cpu.int_regfile_writes 2226782267 # number of integer regfile writes +system.cpu.fp_regfile_reads 68797357 # number of floating regfile reads +system.cpu.fp_regfile_writes 49551943 # number of floating regfile writes +system.cpu.misc_regfile_reads 1364040345 # number of misc regfile reads system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes system.cpu.icache.replacements 22740 # number of replacements -system.cpu.icache.tagsinuse 1642.119595 # Cycle average of tags in use -system.cpu.icache.total_refs 333085984 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1642.119596 # Cycle average of tags in use +system.cpu.icache.total_refs 333085977 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 24420 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 13639.884685 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 13639.884398 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1642.119595 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1642.119596 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.801816 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.801816 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 333090009 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 333090009 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 333090009 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 333090009 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 333090009 # number of overall hits -system.cpu.icache.overall_hits::total 333090009 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 31628 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 31628 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 31628 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 31628 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 31628 # number of overall misses -system.cpu.icache.overall_misses::total 31628 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 481224999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 481224999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 481224999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 481224999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 481224999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 481224999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 333121637 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 333121637 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 333121637 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 333121637 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 333121637 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 333121637 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_hits::cpu.inst 333090004 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 333090004 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 333090004 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 333090004 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 333090004 # number of overall hits +system.cpu.icache.overall_hits::total 333090004 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 31630 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 31630 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 31630 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 31630 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 31630 # number of overall misses +system.cpu.icache.overall_misses::total 31630 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 481232999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 481232999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 481232999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 481232999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 481232999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 481232999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 333121634 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 333121634 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 333121634 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 333121634 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 333121634 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 333121634 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000095 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000095 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000095 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000095 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000095 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000095 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15215.157424 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15215.157424 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15215.157424 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15215.157424 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15215.157424 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15215.157424 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15214.448277 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15214.448277 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15214.448277 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15214.448277 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15214.448277 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15214.448277 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 850 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked @@ -565,40 +550,40 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 2899 system.cpu.icache.demand_mshr_hits::total 2899 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 2899 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 2899 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28729 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 28729 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 28729 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 28729 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 28729 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 28729 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 386560499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 386560499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 386560499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 386560499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 386560499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 386560499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28731 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 28731 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 28731 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 28731 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 28731 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 28731 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 386564499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 386564499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 386564499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 386564499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 386564499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 386564499 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000086 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000086 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13455.410874 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13455.410874 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13455.410874 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13455.410874 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13455.410874 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13455.410874 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13454.613449 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13454.613449 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13454.613449 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13454.613449 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13454.613449 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13454.613449 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 442184 # number of replacements -system.cpu.l2cache.tagsinuse 32692.569161 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 32692.574562 # Cycle average of tags in use system.cpu.l2cache.total_refs 1110053 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 474931 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.337293 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 1286.526974 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 50.225034 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31355.817153 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 1286.532429 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 50.222145 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31355.819987 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.039262 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.001533 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.956904 # Average percentage of cache occupancy @@ -621,8 +606,8 @@ system.cpu.l2cache.overall_hits::total 1086653 # nu system.cpu.l2cache.ReadReq_misses::cpu.inst 2425 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 406491 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 408916 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 4306 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 4306 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 4308 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 4308 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 66075 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 66075 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 2425 # number of demand (read+write) misses @@ -632,23 +617,23 @@ system.cpu.l2cache.overall_misses::cpu.inst 2425 # system.cpu.l2cache.overall_misses::cpu.data 472566 # number of overall misses system.cpu.l2cache.overall_misses::total 474991 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 133322500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 28783784000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 28917106500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3174044000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3174044000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 28783806000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 28917128500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3174251000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3174251000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 133322500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 31957828000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 32091150500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 31958057000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 32091379500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 133322500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 31957828000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 32091150500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 31958057000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 32091379500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 24421 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1464706 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1489127 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 96321 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 96321 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4309 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 4309 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4311 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 4311 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 72517 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 72517 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 24421 # number of demand (read+write) accesses @@ -671,16 +656,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.099300 system.cpu.l2cache.overall_miss_rate::cpu.data 0.307415 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.304161 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54978.350515 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70810.384486 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70716.495564 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48036.988271 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48036.988271 # average ReadExReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70810.438607 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70716.549365 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48040.121075 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48040.121075 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54978.350515 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67626.168620 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67561.596957 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67626.653208 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 67562.079071 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54978.350515 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67626.168620 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67561.596957 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67626.653208 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 67562.079071 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -703,8 +688,8 @@ system.cpu.l2cache.overall_mshr_hits::total 25 # system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2421 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406470 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 408891 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4306 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 4306 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4308 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 4308 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66075 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66075 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2421 # number of demand (read+write) MSHR misses @@ -713,19 +698,19 @@ system.cpu.l2cache.demand_mshr_misses::total 474966 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2421 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 472545 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 474966 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 103136612 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 23729331565 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23832468177 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43064306 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43064306 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2356932012 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2356932012 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 103136612 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26086263577 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26189400189 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 103136612 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26086263577 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26189400189 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 103134689 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 23729007693 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23832142382 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43084308 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43084308 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2357071286 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2357071286 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 103134689 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26086078979 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26189213668 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 103134689 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26086078979 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26189213668 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.099136 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277510 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274584 # mshr miss rate for ReadReq accesses @@ -739,73 +724,73 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.304145 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.099136 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307402 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.304145 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42600.831062 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58379.047814 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58285.626676 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42600.036762 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58378.251022 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58284.829898 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35670.556368 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35670.556368 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42600.831062 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55203.765942 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55139.526175 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42600.831062 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55203.765942 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55139.526175 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35672.664185 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35672.664185 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42600.036762 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55203.375295 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55139.133471 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42600.036762 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55203.375295 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55139.133471 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1533127 # number of replacements system.cpu.dcache.tagsinuse 4094.656080 # Cycle average of tags in use -system.cpu.dcache.total_refs 969988260 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 969988245 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1537223 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 631.000356 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 631.000346 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 319304000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 4094.656080 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999672 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999672 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 693861551 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 693861551 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276093814 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276093814 # number of WriteReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 693861536 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 693861536 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276093810 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276093810 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 9998 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9998 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 969955365 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 969955365 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 969955365 # number of overall hits -system.cpu.dcache.overall_hits::total 969955365 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 969955346 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 969955346 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 969955346 # number of overall hits +system.cpu.dcache.overall_hits::total 969955346 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1953541 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1953541 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 841864 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 841864 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 841868 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 841868 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2795405 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2795405 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2795405 # number of overall misses -system.cpu.dcache.overall_misses::total 2795405 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 66482799000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 66482799000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 39425610969 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 39425610969 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 2795409 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2795409 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2795409 # number of overall misses +system.cpu.dcache.overall_misses::total 2795409 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 66484216000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 66484216000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 39427025969 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 39427025969 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 215500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 215500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 105908409969 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 105908409969 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 105908409969 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 105908409969 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 695815092 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 695815092 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 105911241969 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 105911241969 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 105911241969 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 105911241969 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 695815077 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 695815077 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10001 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10001 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 972750770 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 972750770 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 972750770 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 972750770 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 972750755 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 972750755 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 972750755 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 972750755 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002808 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002808 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003040 # miss rate for WriteReq accesses @@ -816,16 +801,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002874 system.cpu.dcache.demand_miss_rate::total 0.002874 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002874 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002874 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34031.944556 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34031.944556 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46831.330202 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 46831.330202 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34032.669906 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34032.669906 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46832.788476 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 46832.788476 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71833.333333 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37886.606760 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37886.606760 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37886.606760 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37886.606760 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37887.565637 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37887.565637 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37887.565637 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37887.565637 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 1756 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 747 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 57 # number of cycles access was blocked @@ -838,30 +823,30 @@ system.cpu.dcache.writebacks::writebacks 96321 # nu system.cpu.dcache.writebacks::total 96321 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488834 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 488834 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765039 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 765039 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765041 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 765041 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1253873 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1253873 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1253873 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1253873 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1253875 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1253875 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1253875 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1253875 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464707 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1464707 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76825 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 76825 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1541532 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1541532 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1541532 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1541532 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40831551000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 40831551000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3409167500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3409167500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44240718500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 44240718500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44240718500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 44240718500 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76827 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 76827 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1541534 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1541534 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1541534 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1541534 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40831573000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 40831573000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3409419500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3409419500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44240992500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 44240992500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44240992500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 44240992500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses @@ -870,14 +855,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585 system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27876.941259 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27876.941259 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44375.756590 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44375.756590 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28699.189183 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28699.189183 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28699.189183 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28699.189183 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27876.956279 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27876.956279 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44377.881474 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44377.881474 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28699.329694 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28699.329694 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28699.329694 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28699.329694 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 2f98c15fc..a79a513d0 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.042726 # Nu sim_ticks 42726055500 # Number of ticks simulated final_tick 42726055500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 156388 # Simulator instruction rate (inst/s) -host_op_rate 156388 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 75637274 # Simulator tick rate (ticks/s) -host_mem_usage 259292 # Number of bytes of host memory used -host_seconds 564.88 # Real time elapsed on the host +host_inst_rate 89848 # Simulator instruction rate (inst/s) +host_op_rate 89848 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43455006 # Simulator tick rate (ticks/s) +host_mem_usage 257260 # Number of bytes of host memory used +host_seconds 983.23 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 454848 # Number of bytes read from this memory @@ -85,30 +85,17 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 165519 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 114011 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 62480 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 76428 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 18694 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7913 # What read queue length does an incoming req see +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 113997 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 62479 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 76432 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 18692 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7912 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -137,9 +124,8 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 2065 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3856 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 4866 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 4917 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 4945 # What write queue length does an incoming req see @@ -162,7 +148,7 @@ system.physmem.wrQLenPdf::20 4956 # Wh system.physmem.wrQLenPdf::21 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 2892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1101 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 91 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 40 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 12 # What write queue length does an incoming req see @@ -170,15 +156,14 @@ system.physmem.wrQLenPdf::28 1 # Wh system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 7053628221 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 9647149471 # Sum of mem lat for all requests +system.physmem.totQLat 7053839750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 9647402250 # Sum of mem lat for all requests system.physmem.totBusLat 827595000 # Total cycles spent in databus access -system.physmem.totBankLat 1765926250 # Total cycles spent in bank access -system.physmem.avgQLat 42615.22 # Average queueing delay per request -system.physmem.avgBankLat 10669.02 # Average bank access latency per request +system.physmem.totBankLat 1765967500 # Total cycles spent in bank access +system.physmem.avgQLat 42616.50 # Average queueing delay per request +system.physmem.avgBankLat 10669.27 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 58284.24 # Average memory access latency +system.physmem.avgMemAccLat 58285.77 # Average memory access latency system.physmem.avgRdBW 247.93 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 170.76 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 247.93 # Average consumed read bandwidth in MB/s @@ -188,7 +173,7 @@ system.physmem.busUtil 3.27 # Da system.physmem.avgRdQLen 0.23 # Average read queue length over time system.physmem.avgWrQLen 10.42 # Average write queue length over time system.physmem.readRowHits 148856 # Number of row buffer hits during reads -system.physmem.writeRowHits 71620 # Number of row buffer hits during writes +system.physmem.writeRowHits 71619 # Number of row buffer hits during writes system.physmem.readRowHitRate 89.93 # Row buffer hit rate for reads system.physmem.writeRowHitRate 62.83 # Row buffer hit rate for writes system.physmem.avgGap 152857.21 # Average gap between requests @@ -256,9 +241,9 @@ system.cpu.execution_unit.executions 44777871 # Nu system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 77185122 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 77185132 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 229327 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 229329 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 15874710 # Number of cycles cpu's stages were not processed system.cpu.runCycles 69577402 # Number of cycles cpu stages are processed. system.cpu.activity 81.422683 # Percentage of cycles cpu is active @@ -295,12 +280,12 @@ system.cpu.stage4.idleCycles 39402909 # Nu system.cpu.stage4.runCycles 46049203 # Number of cycles 1+ instructions are processed. system.cpu.stage4.utilization 53.888900 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 84308 # number of replacements -system.cpu.icache.tagsinuse 1908.296965 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1908.296945 # Cycle average of tags in use system.cpu.icache.total_refs 12251160 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 86354 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 141.871367 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1908.296965 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1908.296945 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.931786 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.931786 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 12251160 # number of ReadReq hits @@ -315,12 +300,12 @@ system.cpu.icache.demand_misses::cpu.inst 117106 # n system.cpu.icache.demand_misses::total 117106 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 117106 # number of overall misses system.cpu.icache.overall_misses::total 117106 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1888398500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1888398500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1888398500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1888398500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1888398500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1888398500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1889037500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1889037500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1889037500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1889037500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1889037500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1889037500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 12368266 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 12368266 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 12368266 # number of demand (read+write) accesses @@ -333,12 +318,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.009468 system.cpu.icache.demand_miss_rate::total 0.009468 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.009468 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.009468 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16125.548648 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16125.548648 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16125.548648 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16125.548648 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16125.548648 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16125.548648 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16131.005243 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16131.005243 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16131.005243 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16131.005243 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16131.005243 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16131.005243 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 271 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 28 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked @@ -359,34 +344,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 86354 system.cpu.icache.demand_mshr_misses::total 86354 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 86354 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 86354 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1336296000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1336296000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1336296000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1336296000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1336296000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1336296000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1336921000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1336921000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1336921000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1336921000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1336921000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1336921000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006982 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006982 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006982 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.006982 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006982 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.006982 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15474.627695 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15474.627695 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15474.627695 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15474.627695 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15474.627695 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15474.627695 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15481.865345 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15481.865345 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15481.865345 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15481.865345 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15481.865345 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15481.865345 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 131595 # number of replacements -system.cpu.l2cache.tagsinuse 30966.013927 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 30966.013370 # Cycle average of tags in use system.cpu.l2cache.total_refs 151363 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 163654 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.924896 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 27281.106507 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2018.513793 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1666.393626 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 27281.106918 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2018.513701 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1666.392751 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.832553 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.061600 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.050854 # Average percentage of cache occupancy @@ -415,17 +400,17 @@ system.cpu.l2cache.demand_misses::total 165519 # nu system.cpu.l2cache.overall_misses::cpu.inst 7107 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 158412 # number of overall misses system.cpu.l2cache.overall_misses::total 165519 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 454675000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1513576000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1968251000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11996247000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 11996247000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 454675000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13509823000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13964498000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 454675000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13509823000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13964498000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 455300000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1513155000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1968455000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11996427000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 11996427000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 455300000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 13509582000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13964882000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 455300000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 13509582000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13964882000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 86354 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 60575 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 146929 # number of ReadReq accesses(hits+misses) @@ -450,17 +435,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.569383 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082301 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.775218 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.569383 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 63975.657802 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54997.129465 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 56839.869470 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91650.663529 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91650.663529 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 63975.657802 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85282.825796 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 84367.945674 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 63975.657802 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85282.825796 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 84367.945674 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 64063.599268 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54981.832056 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 56845.760656 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91652.038719 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91652.038719 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 64063.599268 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85281.304447 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 84370.265649 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 64063.599268 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85281.304447 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 84370.265649 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -482,17 +467,17 @@ system.cpu.l2cache.demand_mshr_misses::total 165519 system.cpu.l2cache.overall_mshr_misses::cpu.inst 7107 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 158412 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 165519 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 366278633 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1171229430 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1537508063 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10407065579 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10407065579 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 366278633 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11578295009 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11944573642 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 366278633 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11578295009 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11944573642 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 366897656 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1170781845 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1537679501 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10407190958 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10407190958 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 366897656 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11577972803 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11944870459 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 366897656 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11577972803 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11944870459 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082301 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454329 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235678 # mshr miss rate for ReadReq accesses @@ -504,17 +489,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.569383 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082301 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775218 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.569383 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 51537.728015 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42557.662512 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 44400.718003 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79509.405375 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79509.405375 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 51537.728015 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73089.759671 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72164.365674 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 51537.728015 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73089.759671 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72164.365674 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 51624.828479 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42541.399113 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 44405.668852 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79510.363264 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79510.363264 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 51624.828479 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73087.725696 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72166.158924 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 51624.828479 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73087.725696 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72166.158924 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200249 # number of replacements system.cpu.dcache.tagsinuse 4078.188712 # Cycle average of tags in use @@ -541,14 +526,14 @@ system.cpu.dcache.demand_misses::cpu.data 1135133 # n system.cpu.dcache.demand_misses::total 1135133 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1135133 # number of overall misses system.cpu.dcache.overall_misses::total 1135133 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3868219500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3868219500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 76703201000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 76703201000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 80571420500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 80571420500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 80571420500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 80571420500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3867683500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3867683500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 76704328000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 76704328000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 80572011500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 80572011500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 80572011500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 80572011500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -565,19 +550,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.032535 system.cpu.dcache.demand_miss_rate::total 0.032535 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.032535 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.032535 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40139.666283 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40139.666283 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73840.834877 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73840.834877 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 70979.718236 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 70979.718236 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 70979.718236 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 70979.718236 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5030029 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40134.104328 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40134.104328 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73841.919820 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73841.919820 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70980.238879 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70980.238879 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 70980.238879 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 70980.238879 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5030125 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 519 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 116378 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.221477 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.222301 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 519 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -599,14 +584,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204345 system.cpu.dcache.demand_mshr_misses::total 204345 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204345 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204345 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1908697000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1908697000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12268407000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12268407000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14177104000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14177104000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14177104000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14177104000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1908276000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1908276000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12268587000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12268587000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14176863000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14176863000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14176863000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14176863000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -615,14 +600,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31411.124825 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31411.124825 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85446.489762 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85446.489762 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69378.276934 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 69378.276934 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69378.276934 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 69378.276934 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31404.196495 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31404.196495 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85447.743418 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85447.743418 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69377.097556 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 69377.097556 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69377.097556 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 69377.097556 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 2c49ec916..74c8f08b1 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,116 +1,103 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023883 # Number of seconds simulated -sim_ticks 23882696000 # Number of ticks simulated -final_tick 23882696000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023888 # Number of seconds simulated +sim_ticks 23888231000 # Number of ticks simulated +final_tick 23888231000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 224964 # Simulator instruction rate (inst/s) -host_op_rate 224964 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67503934 # Simulator tick rate (ticks/s) -host_mem_usage 262380 # Number of bytes of host memory used -host_seconds 353.80 # Real time elapsed on the host +host_inst_rate 143918 # Simulator instruction rate (inst/s) +host_op_rate 143918 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43194720 # Simulator tick rate (ticks/s) +host_mem_usage 260336 # Number of bytes of host memory used +host_seconds 553.04 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 490816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10154176 # Number of bytes read from this memory -system.physmem.bytes_read::total 10644992 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 490816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 490816 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7297024 # Number of bytes written to this memory -system.physmem.bytes_written::total 7297024 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7669 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158659 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166328 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114016 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114016 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 20551114 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 425168750 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 445719863 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 20551114 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 20551114 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 305536025 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 305536025 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 305536025 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 20551114 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 425168750 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 751255888 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166328 # Total number of read requests seen -system.physmem.writeReqs 114016 # Total number of write requests seen -system.physmem.cpureqs 280344 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 10644992 # Total number of bytes read from memory -system.physmem.bytesWritten 7297024 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 10644992 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7297024 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 1 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 490944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10154112 # Number of bytes read from this memory +system.physmem.bytes_read::total 10645056 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 490944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 490944 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7296832 # Number of bytes written to this memory +system.physmem.bytes_written::total 7296832 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7671 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158658 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166329 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114013 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114013 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 20551710 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 425067557 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 445619267 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 20551710 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 20551710 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 305457194 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 305457194 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 305457194 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 20551710 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 425067557 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 751076461 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166329 # Total number of read requests seen +system.physmem.writeReqs 114013 # Total number of write requests seen +system.physmem.cpureqs 280342 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 10645056 # Total number of bytes read from memory +system.physmem.bytesWritten 7296832 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 10645056 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7296832 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 4 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 10650 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10530 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10319 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10261 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 10573 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10797 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 10412 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10353 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 10494 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10479 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10254 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 10521 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 10326 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 10267 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 10582 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 10798 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 10408 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 10348 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 10490 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10474 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 10257 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 9973 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 10566 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 10395 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 10156 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 10115 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 10565 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 10397 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 10153 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 10116 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 7374 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7243 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7242 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 6949 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6836 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7243 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6837 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7244 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 7385 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7027 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7026 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 7008 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 7264 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7155 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 7041 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 6935 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7275 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7274 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 7250 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 7040 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 6989 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 23882663000 # Total gap between requests +system.physmem.totGap 23888198000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 166328 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 114016 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 67939 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 63061 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 27665 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7639 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.readPktSize::6 166329 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 114013 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 67947 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 63103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 27555 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7700 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -137,15 +124,14 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4933 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4949 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4946 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 4957 # What write queue length does an incoming req see @@ -161,66 +147,65 @@ system.physmem.wrQLenPdf::19 4957 # Wh system.physmem.wrQLenPdf::20 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 617 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 11 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 7244561154 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 9788827404 # Sum of mem lat for all requests -system.physmem.totBusLat 831635000 # Total cycles spent in databus access -system.physmem.totBankLat 1712631250 # Total cycles spent in bank access -system.physmem.avgQLat 43556.13 # Average queueing delay per request -system.physmem.avgBankLat 10296.77 # Average bank access latency per request +system.physmem.totQLat 7273642250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 9818352250 # Sum of mem lat for all requests +system.physmem.totBusLat 831625000 # Total cycles spent in databus access +system.physmem.totBankLat 1713085000 # Total cycles spent in bank access +system.physmem.avgQLat 43731.50 # Average queueing delay per request +system.physmem.avgBankLat 10299.62 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 58852.91 # Average memory access latency -system.physmem.avgRdBW 445.72 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 305.54 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 445.72 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 305.54 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 59031.13 # Average memory access latency +system.physmem.avgRdBW 445.62 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 305.46 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 445.62 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 305.46 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 5.87 # Data bus utilization in percentage system.physmem.avgRdQLen 0.41 # Average read queue length over time -system.physmem.avgWrQLen 10.04 # Average write queue length over time -system.physmem.readRowHits 149202 # Number of row buffer hits during reads -system.physmem.writeRowHits 70865 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.70 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 62.15 # Row buffer hit rate for writes -system.physmem.avgGap 85190.56 # Average gap between requests -system.cpu.branchPred.lookups 16542352 # Number of BP lookups -system.cpu.branchPred.condPredicted 10681130 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 417709 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11519084 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7344749 # Number of BTB hits +system.physmem.avgWrQLen 10.09 # Average write queue length over time +system.physmem.readRowHits 149212 # Number of row buffer hits during reads +system.physmem.writeRowHits 70966 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.71 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 62.24 # Row buffer hit rate for writes +system.physmem.avgGap 85210.91 # Average gap between requests +system.cpu.branchPred.lookups 16542734 # Number of BP lookups +system.cpu.branchPred.condPredicted 10685518 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 416834 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11542683 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7340422 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 63.761572 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1990053 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 40943 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 63.593724 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1986948 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 41598 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22396635 # DTB read hits -system.cpu.dtb.read_misses 219070 # DTB read misses -system.cpu.dtb.read_acv 53 # DTB read access violations -system.cpu.dtb.read_accesses 22615705 # DTB read accesses -system.cpu.dtb.write_hits 15704107 # DTB write hits -system.cpu.dtb.write_misses 40999 # DTB write misses -system.cpu.dtb.write_acv 6 # DTB write access violations -system.cpu.dtb.write_accesses 15745106 # DTB write accesses -system.cpu.dtb.data_hits 38100742 # DTB hits -system.cpu.dtb.data_misses 260069 # DTB misses -system.cpu.dtb.data_acv 59 # DTB access violations -system.cpu.dtb.data_accesses 38360811 # DTB accesses -system.cpu.itb.fetch_hits 13916224 # ITB hits -system.cpu.itb.fetch_misses 34938 # ITB misses +system.cpu.dtb.read_hits 22395624 # DTB read hits +system.cpu.dtb.read_misses 219289 # DTB read misses +system.cpu.dtb.read_acv 61 # DTB read access violations +system.cpu.dtb.read_accesses 22614913 # DTB read accesses +system.cpu.dtb.write_hits 15707380 # DTB write hits +system.cpu.dtb.write_misses 41224 # DTB write misses +system.cpu.dtb.write_acv 1 # DTB write access violations +system.cpu.dtb.write_accesses 15748604 # DTB write accesses +system.cpu.dtb.data_hits 38103004 # DTB hits +system.cpu.dtb.data_misses 260513 # DTB misses +system.cpu.dtb.data_acv 62 # DTB access violations +system.cpu.dtb.data_accesses 38363517 # DTB accesses +system.cpu.itb.fetch_hits 13912342 # ITB hits +system.cpu.itb.fetch_misses 34675 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13951162 # ITB accesses +system.cpu.itb.fetch_accesses 13947017 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -234,238 +219,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 47765395 # number of cpu cycles simulated +system.cpu.numCycles 47776465 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15792461 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105331722 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16542352 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9334802 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19546012 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2000871 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 6407929 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 7641 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 309888 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 68 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13916224 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 206477 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 43516697 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.420490 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.137268 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15792140 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 105356372 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16542734 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9327370 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19544101 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1999173 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 6408053 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 7580 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 309115 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13912342 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 209427 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 43512690 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.421279 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.137905 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 23970685 55.08% 55.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1532413 3.52% 58.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1373284 3.16% 61.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1510754 3.47% 65.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4137026 9.51% 74.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1849440 4.25% 78.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 675147 1.55% 80.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1069291 2.46% 83.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7398657 17.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 23968589 55.08% 55.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1529417 3.51% 58.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1370330 3.15% 61.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1513065 3.48% 65.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4135878 9.50% 74.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1846880 4.24% 78.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 674126 1.55% 80.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1070808 2.46% 82.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7403597 17.01% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43516697 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.346325 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.205189 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16865376 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5950414 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18541793 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 811002 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1348112 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3746218 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 106835 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103623462 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 302130 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1348112 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17322335 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3664232 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 84922 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18847631 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2249465 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102361026 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 441 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2593 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2123305 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 61634933 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123335826 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 122884489 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 451337 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 43512690 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.346253 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.205194 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16866618 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5950644 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18537765 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 810794 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1346869 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3745393 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 107096 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103623154 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 304519 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1346869 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17322284 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3660735 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 85948 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18844978 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2251876 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102372237 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 493 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2675 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2125269 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 61644392 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123362389 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 122911717 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 450672 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9088052 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5535 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5532 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4634659 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23233430 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16268738 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1206800 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 454955 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90740192 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5270 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88424187 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 96369 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10688335 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4670210 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 687 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43516697 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.031960 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.108941 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9097511 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5543 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5541 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4645908 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23234130 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16272775 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1204976 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 463178 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90743430 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5284 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88424765 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 96747 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10698511 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4674782 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 701 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43512690 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.032160 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.108847 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15243033 35.03% 35.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 6914940 15.89% 50.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5620995 12.92% 63.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4761900 10.94% 74.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4675938 10.75% 85.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2651856 6.09% 91.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1932644 4.44% 96.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1300467 2.99% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 414924 0.95% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15237669 35.02% 35.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6914925 15.89% 50.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5623850 12.92% 63.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4759728 10.94% 74.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4676300 10.75% 85.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2652660 6.10% 91.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1932814 4.44% 96.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1300380 2.99% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 414364 0.95% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43516697 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43512690 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 125783 6.76% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 785729 42.22% 48.97% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 949726 51.03% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 125555 6.75% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 785994 42.27% 49.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 947743 50.97% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49355625 55.82% 55.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43814 0.05% 55.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49355125 55.82% 55.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43912 0.05% 55.87% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121422 0.14% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 87 0.00% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 121345 0.14% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 53 0.00% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38953 0.04% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22849621 25.84% 82.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15893267 17.97% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121242 0.14% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 91 0.00% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 121107 0.14% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 56 0.00% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38943 0.04% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22848081 25.84% 82.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15896208 17.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88424187 # Type of FU issued -system.cpu.iq.rate 1.851219 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1861238 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021049 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 221719097 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101035757 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86539045 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 603581 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 415879 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 294278 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 89983556 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 301869 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1467344 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88424765 # Type of FU issued +system.cpu.iq.rate 1.850802 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1859292 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021027 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 221714954 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101050466 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86544122 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 603305 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 414877 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 294005 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 89982323 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 301734 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1469012 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2956792 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4757 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18083 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1655361 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2957492 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4689 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18546 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1659398 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2846 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 90923 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2825 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 92449 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1348112 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2689881 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 74163 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100228982 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 217751 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23233430 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16268738 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5270 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 60091 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 514 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18083 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 196583 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 160586 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 357169 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87578672 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22618883 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 845515 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1346869 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2686448 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 74137 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100230193 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 219543 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23234130 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16272775 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5284 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 60080 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 507 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18546 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 196235 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 160668 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 356903 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87583307 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22618160 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 841458 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9483520 # number of nop insts executed -system.cpu.iew.exec_refs 38364354 # number of memory reference insts executed -system.cpu.iew.exec_branches 15084185 # Number of branches executed -system.cpu.iew.exec_stores 15745471 # Number of stores executed -system.cpu.iew.exec_rate 1.833517 # Inst execution rate -system.cpu.iew.wb_sent 87223381 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86833323 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33358386 # num instructions producing a value -system.cpu.iew.wb_consumers 43765374 # num instructions consuming a value +system.cpu.iew.exec_nop 9481479 # number of nop insts executed +system.cpu.iew.exec_refs 38367101 # number of memory reference insts executed +system.cpu.iew.exec_branches 15084952 # Number of branches executed +system.cpu.iew.exec_stores 15748941 # Number of stores executed +system.cpu.iew.exec_rate 1.833189 # Inst execution rate +system.cpu.iew.wb_sent 87228229 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86838127 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33365194 # num instructions producing a value +system.cpu.iew.wb_consumers 43783216 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.817913 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.762210 # average fanout of values written-back +system.cpu.iew.wb_rate 1.817592 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.762054 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8889050 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8889017 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 313123 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 42168585 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.094940 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.806680 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 312044 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 42165821 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.095078 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.806430 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19301880 45.77% 45.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7026183 16.66% 62.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3423669 8.12% 70.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2056444 4.88% 75.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2047690 4.86% 80.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1162920 2.76% 83.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1093248 2.59% 85.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 719437 1.71% 87.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5337114 12.66% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 19296165 45.76% 45.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7025692 16.66% 62.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3426859 8.13% 70.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2055479 4.87% 75.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2052042 4.87% 80.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1160972 2.75% 83.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1093221 2.59% 85.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 720657 1.71% 87.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5334734 12.65% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 42168585 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 42165821 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -476,192 +461,192 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5337114 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5334734 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 132743851 # The number of ROB reads -system.cpu.rob.rob_writes 195810249 # The number of ROB writes -system.cpu.timesIdled 70469 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 4248698 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 132743434 # The number of ROB reads +system.cpu.rob.rob_writes 195808907 # The number of ROB writes +system.cpu.timesIdled 70658 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 4263775 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.600130 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.600130 # CPI: Total CPI of All Threads -system.cpu.ipc 1.666306 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.666306 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 115907691 # number of integer regfile reads -system.cpu.int_regfile_writes 57507162 # number of integer regfile writes -system.cpu.fp_regfile_reads 249392 # number of floating regfile reads -system.cpu.fp_regfile_writes 240337 # number of floating regfile writes -system.cpu.misc_regfile_reads 38035 # number of misc regfile reads +system.cpu.cpi 0.600269 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.600269 # CPI: Total CPI of All Threads +system.cpu.ipc 1.665920 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.665920 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 115915036 # number of integer regfile reads +system.cpu.int_regfile_writes 57508829 # number of integer regfile writes +system.cpu.fp_regfile_reads 249335 # number of floating regfile reads +system.cpu.fp_regfile_writes 239876 # number of floating regfile writes +system.cpu.misc_regfile_reads 38020 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 91216 # number of replacements -system.cpu.icache.tagsinuse 1928.922459 # Cycle average of tags in use -system.cpu.icache.total_refs 13810559 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 93264 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 148.080277 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 19641578000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1928.922459 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.941857 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.941857 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13810559 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13810559 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13810559 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13810559 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13810559 # number of overall hits -system.cpu.icache.overall_hits::total 13810559 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 105664 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 105664 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 105664 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 105664 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 105664 # number of overall misses -system.cpu.icache.overall_misses::total 105664 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1863781999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1863781999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1863781999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1863781999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1863781999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1863781999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13916223 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13916223 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13916223 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13916223 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13916223 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13916223 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007593 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007593 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007593 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007593 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007593 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007593 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17638.760590 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17638.760590 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17638.760590 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17638.760590 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17638.760590 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17638.760590 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1009 # number of cycles access was blocked +system.cpu.icache.replacements 91603 # number of replacements +system.cpu.icache.tagsinuse 1929.170608 # Cycle average of tags in use +system.cpu.icache.total_refs 13806208 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 93651 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 147.421896 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 19644478000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 1929.170608 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.941978 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.941978 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13806208 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13806208 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13806208 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13806208 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13806208 # number of overall hits +system.cpu.icache.overall_hits::total 13806208 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 106133 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 106133 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 106133 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 106133 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 106133 # number of overall misses +system.cpu.icache.overall_misses::total 106133 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1879500499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1879500499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1879500499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1879500499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1879500499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1879500499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13912341 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13912341 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13912341 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13912341 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13912341 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13912341 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007629 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007629 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007629 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007629 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007629 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007629 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17708.917104 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17708.917104 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17708.917104 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17708.917104 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17708.917104 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17708.917104 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 329 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 14 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 72.071429 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 25.307692 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12399 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 12399 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 12399 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 12399 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 12399 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 12399 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 93265 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 93265 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 93265 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 93265 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 93265 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 93265 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1450659000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1450659000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1450659000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1450659000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1450659000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1450659000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006702 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006702 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006702 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006702 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006702 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006702 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15554.162869 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15554.162869 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15554.162869 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15554.162869 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15554.162869 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15554.162869 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12481 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 12481 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 12481 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 12481 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 12481 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 12481 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 93652 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 93652 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 93652 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 93652 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 93652 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 93652 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1448205000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1448205000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1448205000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1448205000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1448205000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1448205000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006732 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006732 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006732 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006732 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006732 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006732 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15463.684705 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15463.684705 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15463.684705 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15463.684705 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15463.684705 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15463.684705 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 132416 # number of replacements -system.cpu.l2cache.tagsinuse 30823.572935 # Cycle average of tags in use -system.cpu.l2cache.total_refs 159534 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 164488 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.969882 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 132413 # number of replacements +system.cpu.l2cache.tagsinuse 30824.130718 # Cycle average of tags in use +system.cpu.l2cache.total_refs 159933 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 164484 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.972332 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 26655.364859 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2126.856896 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 2041.351180 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.813457 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.064907 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.062297 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.940661 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 85595 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 34249 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 119844 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 168913 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 168913 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12619 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12619 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 85595 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 46868 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 132463 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 85595 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 46868 # number of overall hits -system.cpu.l2cache.overall_hits::total 132463 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 7670 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 27858 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 35528 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 130801 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130801 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 7670 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 158659 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 166329 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 7670 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 158659 # number of overall misses -system.cpu.l2cache.overall_misses::total 166329 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 500468500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1609621000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2110089500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12172380500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 12172380500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 500468500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13782001500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 14282470000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 500468500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13782001500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 14282470000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 93265 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 62107 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 155372 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 168913 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 168913 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 143420 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 143420 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 93265 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 205527 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 298792 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 93265 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 205527 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 298792 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.082239 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.448548 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.228664 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.912014 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.912014 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.082239 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.771962 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.556672 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082239 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.771962 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.556672 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65250.130378 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57779.488836 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 59392.296217 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 93060.301527 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 93060.301527 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65250.130378 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86865.551277 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 85868.790169 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65250.130378 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86865.551277 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 85868.790169 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 26654.476755 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2125.293059 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 2044.360903 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.813430 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.064859 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.062389 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.940678 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 85980 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 34244 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 120224 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 168922 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 168922 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 12628 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 12628 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 85980 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 46872 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 132852 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 85980 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 46872 # number of overall hits +system.cpu.l2cache.overall_hits::total 132852 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 7672 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 27862 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 35534 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 130796 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 130796 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 7672 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 158658 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 166330 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 7672 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 158658 # number of overall misses +system.cpu.l2cache.overall_misses::total 166330 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 493837000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1614539500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2108376500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12203454500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 12203454500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 493837000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 13817994000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 14311831000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 493837000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 13817994000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 14311831000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 93652 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 62106 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 155758 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 168922 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 168922 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 143424 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 143424 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 93652 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 205530 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 299182 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 93652 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 205530 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 299182 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.081920 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.448620 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.228136 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911953 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.911953 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.081920 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.771946 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.555949 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.081920 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.771946 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.555949 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 64368.743483 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57947.724499 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 59334.060337 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 93301.435059 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 93301.435059 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 64368.743483 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87092.954657 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 86044.796489 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 64368.743483 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87092.954657 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 86044.796489 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -670,164 +655,164 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 114016 # number of writebacks -system.cpu.l2cache.writebacks::total 114016 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7670 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27858 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 35528 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130801 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130801 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 7670 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158659 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 166329 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 7670 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158659 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 166329 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 404789823 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1267031559 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1671821382 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10582502021 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10582502021 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 404789823 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11849533580 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12254323403 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 404789823 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11849533580 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12254323403 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082239 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448548 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.228664 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912014 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912014 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082239 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771962 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.556672 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082239 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771962 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.556672 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52775.726597 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45481.784730 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 47056.445114 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80905.360211 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80905.360211 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52775.726597 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74685.543083 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73675.206386 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52775.726597 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74685.543083 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73675.206386 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 114013 # number of writebacks +system.cpu.l2cache.writebacks::total 114013 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7672 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27862 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 35534 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130796 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130796 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 7672 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158658 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 166330 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 7672 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158658 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 166330 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 398141894 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1271865950 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1670007844 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10613542919 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10613542919 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 398141894 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11885408869 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12283550763 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 398141894 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11885408869 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12283550763 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.081920 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448620 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.228136 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911953 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911953 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.081920 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771946 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.555949 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.081920 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771946 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.555949 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 51895.450209 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45648.767138 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 46997.462824 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81145.776010 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81145.776010 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 51895.450209 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74912.130929 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73850.482553 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 51895.450209 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74912.130929 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73850.482553 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 201431 # number of replacements -system.cpu.dcache.tagsinuse 4076.502318 # Cycle average of tags in use -system.cpu.dcache.total_refs 34195386 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 205527 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 166.379045 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 178801000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.502318 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995240 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995240 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20621336 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20621336 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13573997 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13573997 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 53 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 53 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 34195333 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34195333 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34195333 # number of overall hits -system.cpu.dcache.overall_hits::total 34195333 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 266907 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 266907 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1039380 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1039380 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1306287 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1306287 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1306287 # number of overall misses -system.cpu.dcache.overall_misses::total 1306287 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12007604500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12007604500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 79088080451 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 79088080451 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 91095684951 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 91095684951 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 91095684951 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 91095684951 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20888243 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20888243 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 201434 # number of replacements +system.cpu.dcache.tagsinuse 4076.506217 # Cycle average of tags in use +system.cpu.dcache.total_refs 34191197 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 205530 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 166.356235 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 178802000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4076.506217 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995241 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995241 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20617082 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20617082 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574055 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574055 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 60 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 60 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34191137 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34191137 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34191137 # number of overall hits +system.cpu.dcache.overall_hits::total 34191137 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 267027 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 267027 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1039322 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1039322 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1306349 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1306349 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1306349 # number of overall misses +system.cpu.dcache.overall_misses::total 1306349 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12066091500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12066091500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 79222219902 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 79222219902 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 91288311402 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 91288311402 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 91288311402 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 91288311402 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20884109 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20884109 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 53 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 53 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35501620 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35501620 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35501620 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35501620 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012778 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012778 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071125 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071125 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036795 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036795 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036795 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036795 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44987.971466 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 44987.971466 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76091.593499 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76091.593499 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 69736.348100 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69736.348100 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 69736.348100 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69736.348100 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4377310 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 60 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 60 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35497486 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35497486 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35497486 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35497486 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012786 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012786 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071121 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071121 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036801 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036801 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036801 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036801 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45186.784482 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 45186.784482 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76224.904218 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76224.904218 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69880.492427 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69880.492427 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69880.492427 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69880.492427 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4400680 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 119 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 112282 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 112252 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 38.984966 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 39.203578 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 119 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168913 # number of writebacks -system.cpu.dcache.writebacks::total 168913 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 204795 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 204795 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895965 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895965 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1100760 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1100760 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1100760 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1100760 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62112 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62112 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143415 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143415 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205527 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205527 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205527 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205527 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2016329500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2016329500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12443477492 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12443477492 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14459806992 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14459806992 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14459806992 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14459806992 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 168922 # number of writebacks +system.cpu.dcache.writebacks::total 168922 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 204918 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 204918 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895901 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895901 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1100819 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1100819 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1100819 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1100819 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62109 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62109 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143421 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143421 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205530 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205530 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205530 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205530 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2021126000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2021126000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12474690492 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12474690492 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14495816492 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14495816492 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14495816492 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14495816492 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002974 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002974 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009814 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009814 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005789 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005789 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005789 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005789 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32462.801069 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32462.801069 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 86765.523076 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 86765.523076 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70354.780598 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 70354.780598 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70354.780598 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 70354.780598 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005790 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005790 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005790 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005790 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32541.596226 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32541.596226 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 86979.525258 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 86979.525258 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70528.956804 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 70528.956804 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70528.956804 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 70528.956804 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index bdf692e24..bd8287e69 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.025578 # Nu sim_ticks 25577832000 # Number of ticks simulated final_tick 25577832000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 153227 # Simulator instruction rate (inst/s) -host_op_rate 217448 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55271946 # Simulator tick rate (ticks/s) -host_mem_usage 270340 # Number of bytes of host memory used -host_seconds 462.76 # Real time elapsed on the host +host_inst_rate 133487 # Simulator instruction rate (inst/s) +host_op_rate 189436 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48151664 # Simulator tick rate (ticks/s) +host_mem_usage 268312 # Number of bytes of host memory used +host_seconds 531.19 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 100626876 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 298304 # Number of bytes read from this memory @@ -85,29 +85,16 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 128779 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 83944 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 312 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 70134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 56500 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2062 # What read queue length does an incoming req see +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 83944 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 70150 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 56485 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2061 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 68 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -137,8 +124,7 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3542 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3543 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 3645 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 3647 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 3649 # What write queue length does an incoming req see @@ -161,7 +147,7 @@ system.physmem.wrQLenPdf::19 3649 # Wh system.physmem.wrQLenPdf::20 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 107 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see @@ -170,15 +156,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3204614448 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 5248634448 # Sum of mem lat for all requests +system.physmem.totQLat 3204596500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 5248699000 # Sum of mem lat for all requests system.physmem.totBusLat 643885000 # Total cycles spent in databus access -system.physmem.totBankLat 1400135000 # Total cycles spent in bank access -system.physmem.avgQLat 24884.99 # Average queueing delay per request -system.physmem.avgBankLat 10872.55 # Average bank access latency per request +system.physmem.totBankLat 1400217500 # Total cycles spent in bank access +system.physmem.avgQLat 24884.85 # Average queueing delay per request +system.physmem.avgBankLat 10873.20 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 40757.55 # Average memory access latency +system.physmem.avgMemAccLat 40758.05 # Average memory access latency system.physmem.avgRdBW 322.23 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 210.04 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 322.23 # Average consumed read bandwidth in MB/s @@ -247,23 +232,23 @@ system.cpu.workload.num_syscalls 1946 # Nu system.cpu.numCycles 51155665 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12532709 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 12532708 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 85214691 # Number of instructions fetch has processed system.cpu.fetch.Branches 16629564 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 9594774 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 21193802 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 2370777 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10561174 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 10561405 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 619 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 11680132 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 179650 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46029302 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.592220 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.335381 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheSquashes 179651 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46029532 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.592208 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.335378 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24855702 54.00% 54.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24855932 54.00% 54.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 2137922 4.64% 58.64% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 1963242 4.27% 62.91% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 2041100 4.43% 67.34% # Number of instructions fetched each cycle (Total) @@ -275,42 +260,42 @@ system.cpu.fetch.rateDist::8 10031713 21.79% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46029302 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 46029532 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.325078 # Number of branch fetches per cycle system.cpu.fetch.rate 1.665792 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14615111 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8910636 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19475070 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1390460 # Number of cycles decode is unblocking +system.cpu.decode.IdleCycles 14615115 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8910863 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19475067 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1390462 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1638025 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 3332403 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 104704 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 116875392 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 116875388 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 362618 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 1638025 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16327930 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2553995 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 876400 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19102314 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5530638 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 115006216 # Number of instructions processed by rename +system.cpu.rename.IdleCycles 16327942 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2554176 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 876402 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19102307 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5530680 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 115006208 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 128 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 16441 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4672566 # Number of times rename has blocked due to LSQ full +system.cpu.rename.LSQFullEvents 4672604 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 267 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115315088 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 529845526 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 529838425 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 115315076 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 529845478 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 529838377 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 7101 # Number of floating rename lookups system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16182416 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 16182404 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 20249 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 20243 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13070329 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 13070399 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 29628857 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 22448482 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 3867260 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4365711 # Number of conflicting stores. +system.cpu.memDep0.conflictingStores 4365710 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 111562544 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 35868 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 107265054 # Number of instructions issued @@ -318,23 +303,23 @@ system.cpu.iq.iqSquashedInstsIssued 274406 # Nu system.cpu.iq.iqSquashedInstsExamined 10824806 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 25919657 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2082 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46029302 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.330365 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.988633 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 46029532 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.330353 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.988634 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10776543 23.41% 23.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8085599 17.57% 40.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7427656 16.14% 57.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7135117 15.50% 72.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5408591 11.75% 84.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3911102 8.50% 92.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1839411 4.00% 96.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10776737 23.41% 23.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8085644 17.57% 40.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7427640 16.14% 57.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7135127 15.50% 72.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5408613 11.75% 84.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3911083 8.50% 92.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1839405 4.00% 96.86% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 869812 1.89% 98.75% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 575471 1.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46029302 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46029532 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 112614 4.57% 4.57% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 4.57% # attempts to use FU when none available @@ -366,7 +351,7 @@ system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.57% # at system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.57% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 1347948 54.70% 59.28% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1003479 40.72% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1003472 40.72% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -405,15 +390,15 @@ system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Ty system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 107265054 # Type of FU issued system.cpu.iq.rate 2.096836 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2464043 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.022972 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 263297262 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_cnt 2464036 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.022971 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 263297485 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 122451085 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105577839 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 105577838 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 597 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 998 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 169 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 109728805 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 109728798 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 292 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 2178424 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -427,32 +412,32 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 29 # system.cpu.iew.lsq.thread0.cacheBlocked 510 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 1638025 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1048423 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 45681 # Number of cycles IEW is unblocking +system.cpu.iew.iewBlockCycles 1048533 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 45693 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 111608173 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 293378 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 29628857 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 22448482 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 19948 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 6875 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5224 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5227 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 30026 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 391684 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 181878 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 573562 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106234972 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 106234971 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 28603939 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1030082 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 1030083 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 9761 # number of nop insts executed system.cpu.iew.exec_refs 49948503 # number of memory reference insts executed system.cpu.iew.exec_branches 14602542 # Number of branches executed system.cpu.iew.exec_stores 21344564 # Number of stores executed system.cpu.iew.exec_rate 2.076700 # Inst execution rate -system.cpu.iew.wb_sent 105797759 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105578008 # cumulative count of insts written-back +system.cpu.iew.wb_sent 105797758 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105578007 # cumulative count of insts written-back system.cpu.iew.wb_producers 53282087 # num instructions producing a value -system.cpu.iew.wb_consumers 103565148 # num instructions consuming a value +system.cpu.iew.wb_consumers 103565099 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 2.063858 # insts written-back per cycle system.cpu.iew.wb_fanout 0.514479 # average fanout of values written-back @@ -460,23 +445,23 @@ system.cpu.iew.wb_penalized_rate 0 # fr system.cpu.commit.commitSquashedInsts 10976636 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 500410 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44391277 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.266941 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.764740 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 44391507 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.266930 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.764737 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15317735 34.51% 34.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11646185 26.24% 60.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3462928 7.80% 68.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15317930 34.51% 34.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11646230 26.24% 60.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3462929 7.80% 68.54% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 2873664 6.47% 75.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1875712 4.23% 79.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1949355 4.39% 83.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 685853 1.55% 85.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 564106 1.27% 86.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6015739 13.55% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1875708 4.23% 79.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1949349 4.39% 83.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 685850 1.55% 85.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 564105 1.27% 86.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6015742 13.55% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44391277 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 44391507 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -487,12 +472,12 @@ system.cpu.commit.branches 13741505 # Nu system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6015739 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6015742 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 149959303 # The number of ROB reads +system.cpu.rob.rob_reads 149959530 # The number of ROB reads system.cpu.rob.rob_writes 224865260 # The number of ROB writes -system.cpu.timesIdled 74068 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5126363 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.timesIdled 74070 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5126133 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated @@ -500,19 +485,19 @@ system.cpu.cpi 0.721441 # CP system.cpu.cpi_total 0.721441 # CPI: Total CPI of All Threads system.cpu.ipc 1.386115 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.386115 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 511661177 # number of integer regfile reads -system.cpu.int_regfile_writes 103341315 # number of integer regfile writes +system.cpu.int_regfile_reads 511661173 # number of integer regfile reads +system.cpu.int_regfile_writes 103341311 # number of integer regfile writes system.cpu.fp_regfile_reads 804 # number of floating regfile reads system.cpu.fp_regfile_writes 688 # number of floating regfile writes system.cpu.misc_regfile_reads 49186243 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes system.cpu.icache.replacements 28586 # number of replacements -system.cpu.icache.tagsinuse 1814.278230 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1814.278271 # Cycle average of tags in use system.cpu.icache.total_refs 11645439 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 30619 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 380.333747 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1814.278230 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1814.278271 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.885878 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.885878 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 11645446 # number of ReadReq hits @@ -527,12 +512,12 @@ system.cpu.icache.demand_misses::cpu.inst 34686 # n system.cpu.icache.demand_misses::total 34686 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 34686 # number of overall misses system.cpu.icache.overall_misses::total 34686 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 739119000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 739119000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 739119000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 739119000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 739119000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 739119000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 739337000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 739337000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 739337000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 739337000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 739337000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 739337000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 11680132 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 11680132 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 11680132 # number of demand (read+write) accesses @@ -545,12 +530,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.002970 system.cpu.icache.demand_miss_rate::total 0.002970 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.002970 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.002970 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21308.856599 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21308.856599 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21308.856599 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21308.856599 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21308.856599 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21308.856599 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21315.141556 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21315.141556 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21315.141556 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21315.141556 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21315.141556 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21315.141556 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 761 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 25 # number of cycles access was blocked @@ -571,34 +556,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 30945 system.cpu.icache.demand_mshr_misses::total 30945 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 30945 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 30945 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 600341000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 600341000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 600341000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 600341000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 600341000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 600341000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 600567000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 600567000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 600567000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 600567000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 600567000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 600567000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002649 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.002649 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.002649 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19400.258523 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19400.258523 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19400.258523 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19400.258523 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19400.258523 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19400.258523 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19407.561803 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19407.561803 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19407.561803 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19407.561803 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19407.561803 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19407.561803 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 95649 # number of replacements -system.cpu.l2cache.tagsinuse 30090.049168 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 30090.044330 # Cycle average of tags in use system.cpu.l2cache.total_refs 88124 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 126758 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.695215 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 26935.644891 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1374.538058 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1779.866218 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 26935.640674 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1374.538102 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1779.865554 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.822011 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.041948 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.054317 # Average percentage of cache occupancy @@ -631,19 +616,19 @@ system.cpu.l2cache.demand_misses::total 128855 # nu system.cpu.l2cache.overall_misses::cpu.inst 4676 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 124179 # number of overall misses system.cpu.l2cache.overall_misses::total 128855 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 310311500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1482845500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1793157000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 310537500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1482354000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1792891500 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 23000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6640773000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6640773000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 310311500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8123618500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8433930000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 310311500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8123618500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8433930000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6641217500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6641217500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 310537500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8123571500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8434109000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 310537500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8123571500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8434109000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 30501 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 55382 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 85883 # number of ReadReq accesses(hits+misses) @@ -672,19 +657,19 @@ system.cpu.l2cache.demand_miss_rate::total 0.667902 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.153306 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.764536 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.667902 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66362.596236 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67641.889426 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67416.986240 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66410.928144 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67619.469027 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67407.004286 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 73.717949 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 73.717949 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64941.989301 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64941.989301 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66362.596236 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65418.617480 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 65452.873385 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66362.596236 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65418.617480 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 65452.873385 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64946.336192 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64946.336192 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66410.928144 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65418.238994 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 65454.262543 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66410.928144 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65418.238994 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 65454.262543 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -717,19 +702,19 @@ system.cpu.l2cache.demand_mshr_misses::total 128779 system.cpu.l2cache.overall_mshr_misses::cpu.inst 4661 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 124118 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 128779 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 251333698 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1209966181 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1461299879 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 251555285 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1209463318 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1461018603 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3131809 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3131809 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5384861495 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5384861495 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 251333698 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6594827676 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6846161374 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 251333698 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6594827676 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6846161374 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5385248857 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5385248857 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 251555285 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6594712175 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6846267460 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 251555285 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6594712175 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6846267460 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.152815 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394731 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.308815 # mshr miss rate for ReadReq accesses @@ -743,61 +728,61 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.667508 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.152815 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764160 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.667508 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53922.698563 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55348.162527 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55097.650215 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53970.239219 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55325.159782 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55087.044831 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10037.849359 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10037.849359 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52660.077012 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52660.077012 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53922.698563 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53133.531607 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53162.094550 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53922.698563 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53133.531607 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53162.094550 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52663.865134 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52663.865134 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53970.239219 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53132.601033 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53162.918333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53970.239219 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53132.601033 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53162.918333 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 158328 # number of replacements -system.cpu.dcache.tagsinuse 4072.315266 # Cycle average of tags in use -system.cpu.dcache.total_refs 44370475 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4072.315155 # Cycle average of tags in use +system.cpu.dcache.total_refs 44370468 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 162424 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 273.176840 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 273.176797 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 284606000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4072.315266 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4072.315155 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.994218 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.994218 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26070698 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26070698 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 26070691 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26070691 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 18267224 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 18267224 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15981 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15981 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44337922 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44337922 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44337922 # number of overall hits -system.cpu.dcache.overall_hits::total 44337922 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 124470 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 124470 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 44337915 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44337915 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44337915 # number of overall hits +system.cpu.dcache.overall_hits::total 44337915 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 124477 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 124477 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1582677 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 1582677 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 45 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 45 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1707147 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1707147 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1707147 # number of overall misses -system.cpu.dcache.overall_misses::total 1707147 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4247957000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4247957000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 98254010480 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 98254010480 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 1707154 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1707154 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1707154 # number of overall misses +system.cpu.dcache.overall_misses::total 1707154 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4246899000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4246899000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 98261042480 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 98261042480 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 892500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 892500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 102501967480 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 102501967480 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 102501967480 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 102501967480 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 102507941480 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 102507941480 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 102507941480 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 102507941480 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 26195168 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 26195168 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) @@ -820,16 +805,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.037076 system.cpu.dcache.demand_miss_rate::total 0.037076 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.037076 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.037076 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34128.360247 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34128.360247 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62080.898680 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62080.898680 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34117.941467 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34117.941467 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62085.341785 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62085.341785 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19833.333333 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60042.847792 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60042.847792 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60042.847792 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60042.847792 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60046.100984 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60046.100984 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60046.100984 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60046.100984 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 5655 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 661 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 122 # number of cycles access was blocked @@ -840,16 +825,16 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 129109 # number of writebacks system.cpu.dcache.writebacks::total 129109 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69057 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69057 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69064 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69064 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475334 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 1475334 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 45 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 45 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1544391 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1544391 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1544391 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1544391 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1544398 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1544398 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1544398 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1544398 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55413 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 55413 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107343 # number of WriteReq MSHR misses @@ -858,14 +843,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 162756 system.cpu.dcache.demand_mshr_misses::total 162756 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 162756 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 162756 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1878248000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1878248000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6802862990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6802862990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8681110990 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8681110990 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8681110990 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8681110990 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1877758500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1877758500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6803307490 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6803307490 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8681065990 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8681065990 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8681065990 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8681065990 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002115 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002115 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses @@ -874,14 +859,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003535 system.cpu.dcache.demand_mshr_miss_rate::total 0.003535 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003535 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33895.439698 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33895.439698 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63375.003400 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63375.003400 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53338.193308 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53338.193308 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53338.193308 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53338.193308 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33886.606031 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33886.606031 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63379.144332 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63379.144332 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53337.916820 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53337.916820 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53337.916820 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53337.916820 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index bbfef95ab..4d872659d 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.993559 # Nu sim_ticks 993559170500 # Number of ticks simulated final_tick 993559170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 148425 # Simulator instruction rate (inst/s) -host_op_rate 148425 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 81036604 # Simulator tick rate (ticks/s) -host_mem_usage 464668 # Number of bytes of host memory used -host_seconds 12260.62 # Real time elapsed on the host +host_inst_rate 139940 # Simulator instruction rate (inst/s) +host_op_rate 139940 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 76403951 # Simulator tick rate (ticks/s) +host_mem_usage 449176 # Number of bytes of host memory used +host_seconds 13004.03 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory @@ -85,30 +85,17 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 1959688 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1018171 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1630106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 205346 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 87736 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 35917 # What read queue length does an incoming req see +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 1018058 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1630116 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 205318 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 87737 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 35934 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -137,9 +124,8 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 41624 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 43771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 43773 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 44240 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 44256 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 44259 # What write queue length does an incoming req see @@ -162,7 +148,7 @@ system.physmem.wrQLenPdf::20 44263 # Wh system.physmem.wrQLenPdf::21 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 2640 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 493 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 491 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 24 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 5 # What write queue length does an incoming req see @@ -170,15 +156,14 @@ system.physmem.wrQLenPdf::28 5 # Wh system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 35848625999 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 104288840999 # Sum of mem lat for all requests +system.physmem.totQLat 35843451500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 104284202750 # Sum of mem lat for all requests system.physmem.totBusLat 9795530000 # Total cycles spent in databus access -system.physmem.totBankLat 58644685000 # Total cycles spent in bank access -system.physmem.avgQLat 18298.46 # Average queueing delay per request -system.physmem.avgBankLat 29934.41 # Average bank access latency per request +system.physmem.totBankLat 58645221250 # Total cycles spent in bank access +system.physmem.avgQLat 18295.82 # Average queueing delay per request +system.physmem.avgBankLat 29934.69 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 53232.87 # Average memory access latency +system.physmem.avgMemAccLat 53230.51 # Average memory access latency system.physmem.avgRdBW 126.23 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 65.58 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 126.23 # Average consumed read bandwidth in MB/s @@ -187,13 +172,13 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 1.50 # Data bus utilization in percentage system.physmem.avgRdQLen 0.10 # Average read queue length over time system.physmem.avgWrQLen 10.46 # Average write queue length over time -system.physmem.readRowHits 770935 # Number of row buffer hits during reads -system.physmem.writeRowHits 285714 # Number of row buffer hits during writes +system.physmem.readRowHits 770937 # Number of row buffer hits during reads +system.physmem.writeRowHits 285715 # Number of row buffer hits during writes system.physmem.readRowHitRate 39.35 # Row buffer hit rate for reads system.physmem.writeRowHitRate 28.06 # Row buffer hit rate for writes system.physmem.avgGap 333661.47 # Average gap between requests system.cpu.branchPred.lookups 326540496 # Number of BP lookups -system.cpu.branchPred.condPredicted 252608544 # Number of conditional branches predicted +system.cpu.branchPred.condPredicted 252608543 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 138248451 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 220022753 # Number of BTB lookups system.cpu.branchPred.BTBHits 135563778 # Number of BTB hits @@ -205,22 +190,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444796007 # DTB read hits +system.cpu.dtb.read_hits 444796009 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449693085 # DTB read accesses -system.cpu.dtb.write_hits 160833351 # DTB write hits +system.cpu.dtb.read_accesses 449693087 # DTB read accesses +system.cpu.dtb.write_hits 160833358 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162534655 # DTB write accesses -system.cpu.dtb.data_hits 605629358 # DTB hits +system.cpu.dtb.write_accesses 162534662 # DTB write accesses +system.cpu.dtb.data_hits 605629367 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612227740 # DTB accesses -system.cpu.itb.fetch_hits 232025962 # ITB hits +system.cpu.dtb.data_accesses 612227749 # DTB accesses +system.cpu.itb.fetch_hits 232025963 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 232025984 # ITB accesses +system.cpu.itb.fetch_accesses 232025985 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -237,16 +222,16 @@ system.cpu.workload.num_syscalls 29 # Nu system.cpu.numCycles 1987118342 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 172378846 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 154161650 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 1667662469 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 172378847 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 154161649 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 1667662468 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 3043865086 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 3043865085 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 230 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 575 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 651727789 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 617884568 # Number of Address Generations +system.cpu.regfile_manager.regForwards 651727790 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 617884569 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 120519408 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 11130585 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.execution_unit.mispredicted 131649993 # Number of Branches Incorrectly Predicted @@ -256,12 +241,12 @@ system.cpu.execution_unit.executions 1139371391 # Nu system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1741838166 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1741838474 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7484554 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 415293759 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1571824583 # Number of cycles cpu stages are processed. -system.cpu.activity 79.100703 # Percentage of cycles cpu is active +system.cpu.timesIdled 7484621 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 415293731 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1571824611 # Number of cycles cpu stages are processed. +system.cpu.activity 79.100705 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -279,66 +264,66 @@ system.cpu.cpi_total 1.091955 # CP system.cpu.ipc 0.915789 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC system.cpu.ipc_total 0.915789 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 800261653 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1186856689 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 59.727529 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1053419210 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 933699132 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.idleCycles 800261647 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1186856695 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 59.727530 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1053419200 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 933699142 # Number of cycles 1+ instructions are processed. system.cpu.stage1.utilization 46.987596 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1014725197 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 972393145 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 48.934838 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1577495451 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 409622891 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.idleCycles 1014725184 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 972393158 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 48.934839 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1577495448 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409622894 # Number of cycles 1+ instructions are processed. system.cpu.stage3.utilization 20.613915 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 965781597 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1021336745 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.idleCycles 965781598 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1021336744 # Number of cycles 1+ instructions are processed. system.cpu.stage4.utilization 51.397882 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1 # number of replacements system.cpu.icache.tagsinuse 667.839755 # Cycle average of tags in use -system.cpu.icache.total_refs 232024853 # Total number of references to valid blocks. +system.cpu.icache.total_refs 232024854 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 270110.422584 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 270110.423749 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::cpu.inst 667.839755 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.326094 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.326094 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 232024853 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 232024853 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 232024853 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 232024853 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 232024853 # number of overall hits -system.cpu.icache.overall_hits::total 232024853 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 232024854 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 232024854 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 232024854 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 232024854 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 232024854 # number of overall hits +system.cpu.icache.overall_hits::total 232024854 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1109 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1109 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1109 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1109 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1109 # number of overall misses system.cpu.icache.overall_misses::total 1109 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 64824000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 64824000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 64824000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 64824000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 64824000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 64824000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 232025962 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 232025962 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 232025962 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 232025962 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 232025962 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 232025962 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 64819000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 64819000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 64819000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 64819000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 64819000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 64819000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 232025963 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 232025963 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 232025963 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 232025963 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 232025963 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 232025963 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58452.660054 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 58452.660054 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 58452.660054 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 58452.660054 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 58452.660054 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 58452.660054 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58448.151488 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 58448.151488 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 58448.151488 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 58448.151488 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 58448.151488 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 58448.151488 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 65 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -359,34 +344,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 859 system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51094000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 51094000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51094000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 51094000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51094000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 51094000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51089000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 51089000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51089000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 51089000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51089000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 51089000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59480.791618 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59480.791618 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59480.791618 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 59480.791618 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59480.791618 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 59480.791618 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59474.970896 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59474.970896 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59474.970896 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 59474.970896 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59474.970896 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 59474.970896 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1926957 # number of replacements -system.cpu.l2cache.tagsinuse 30901.189493 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 30901.189526 # Cycle average of tags in use system.cpu.l2cache.total_refs 8958712 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 1956750 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 4.578363 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 67146389752 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15036.220551 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 34.907128 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15830.061814 # Average occupied blocks per requestor +system.cpu.l2cache.warmup_cycle 67146389751 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 15036.225587 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 34.907127 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15830.056812 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.458869 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.001065 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.483095 # Average percentage of cache occupancy @@ -412,17 +397,17 @@ system.cpu.l2cache.demand_misses::total 1959688 # nu system.cpu.l2cache.overall_misses::cpu.inst 859 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1958829 # number of overall misses system.cpu.l2cache.overall_misses::total 1959688 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50231000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 83163632000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 83213863000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 66179053000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 66179053000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 50231000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 149342685000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 149392916000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 50231000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 149342685000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 149392916000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50226000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 83163468000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 83213694000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 66176738000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 66176738000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 50226000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 149340206000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 149390432000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 50226000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 149340206000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 149390432000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7221841 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7222700 # number of ReadReq accesses(hits+misses) @@ -447,17 +432,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.215059 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.214985 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.215059 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 58476.135041 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70625.488947 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70616.632538 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84703.875213 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84703.875213 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 58476.135041 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76240.797436 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76233.010561 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 58476.135041 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76240.797436 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76233.010561 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 58470.314319 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70625.349673 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70616.489122 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84700.912199 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84700.912199 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 58470.314319 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76239.531884 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76231.743012 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 58470.314319 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76239.531884 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76231.743012 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -479,17 +464,17 @@ system.cpu.l2cache.demand_mshr_misses::total 1959688 system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1958829 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 1959688 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 39571189 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 68487354640 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 68526925829 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 56485658700 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 56485658700 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39571189 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 124973013340 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 125012584529 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39571189 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 124973013340 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 125012584529 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 39565474 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 68486082132 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 68525647606 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 56482752358 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 56482752358 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39565474 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 124968834490 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 125008399964 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39565474 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 124968834490 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 125008399964 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163051 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163151 # mshr miss rate for ReadReq accesses @@ -501,51 +486,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.215059 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.215059 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 46066.576251 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58161.876674 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58153.059668 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72297.108661 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72297.108661 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 46066.576251 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63799.858660 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63792.085541 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 46066.576251 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63799.858660 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63792.085541 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 46059.923166 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58160.796015 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58151.974947 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72293.388777 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72293.388777 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 46059.923166 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63797.725320 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63789.950219 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 46059.923166 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63797.725320 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63789.950219 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9107372 # number of replacements system.cpu.dcache.tagsinuse 4082.262475 # Cycle average of tags in use -system.cpu.dcache.total_refs 593512880 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 593512840 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 9111468 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 65.139106 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 65.139102 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 12624962000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 4082.262475 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.996646 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.996646 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 437268758 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 437268758 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 156244122 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 156244122 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 593512880 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 593512880 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 593512880 # number of overall hits -system.cpu.dcache.overall_hits::total 593512880 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 156244082 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 156244082 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 593512840 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 593512840 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 593512840 # number of overall hits +system.cpu.dcache.overall_hits::total 593512840 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 7326905 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 7326905 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4484380 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4484380 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 11811285 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 11811285 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 11811285 # number of overall misses -system.cpu.dcache.overall_misses::total 11811285 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 167288165500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 167288165500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 202507086500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 202507086500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 369795252000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 369795252000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 369795252000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 369795252000 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 4484420 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4484420 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 11811325 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 11811325 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 11811325 # number of overall misses +system.cpu.dcache.overall_misses::total 11811325 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 167288000500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 167288000500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 202511222000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 202511222000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 369799222500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 369799222500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 369799222500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 369799222500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -556,38 +541,38 @@ system.cpu.dcache.overall_accesses::cpu.data 605324165 system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016480 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016480 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027900 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.027900 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027901 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.027901 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.019512 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.019512 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.019512 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.019512 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22832.036924 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22832.036924 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45158.324339 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45158.324339 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31308.638476 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31308.638476 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31308.638476 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31308.638476 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 13465460 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 4770860 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 372579 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22832.014404 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22832.014404 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45158.843730 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45158.843730 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31308.868607 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31308.868607 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31308.868607 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31308.868607 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 13465422 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 4771270 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 372557 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 65753 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.141221 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 72.557298 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.143253 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 72.563533 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 3693293 # number of writebacks system.cpu.dcache.writebacks::total 3693293 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104622 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 104622 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2595195 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2595195 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2699817 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2699817 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2699817 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2699817 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2595235 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2595235 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2699857 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2699857 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2699857 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2699857 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222283 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7222283 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889185 # number of WriteReq MSHR misses @@ -596,14 +581,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9111468 system.cpu.dcache.demand_mshr_misses::total 9111468 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9111468 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9111468 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 150964459500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 150964459500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 79317190500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 79317190500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230281650000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 230281650000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230281650000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 230281650000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 150964297500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 150964297500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 79314869000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 79314869000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230279166500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 230279166500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230279166500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 230279166500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses @@ -612,14 +597,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20902.595412 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20902.595412 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41984.872048 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41984.872048 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25273.825250 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25273.825250 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25273.825250 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25273.825250 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20902.572981 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20902.572981 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41983.643211 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41983.643211 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25273.552681 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25273.552681 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25273.552681 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25273.552681 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index db2985766..e183c5fce 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,117 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.665563 # Number of seconds simulated -sim_ticks 665562897500 # Number of ticks simulated -final_tick 665562897500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.665771 # Number of seconds simulated +sim_ticks 665770972500 # Number of ticks simulated +final_tick 665770972500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 181531 # Simulator instruction rate (inst/s) -host_op_rate 181531 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69595242 # Simulator tick rate (ticks/s) -host_mem_usage 467736 # Number of bytes of host memory used -host_seconds 9563.34 # Real time elapsed on the host +host_inst_rate 179472 # Simulator instruction rate (inst/s) +host_op_rate 179472 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68827168 # Simulator tick rate (ticks/s) +host_mem_usage 452252 # Number of bytes of host memory used +host_seconds 9673.08 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125801472 # Number of bytes read from this memory -system.physmem.bytes_read::total 125863104 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61632 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65262912 # Number of bytes written to this memory -system.physmem.bytes_written::total 65262912 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 963 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1965648 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1966611 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1019733 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1019733 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 92601 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 189015152 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 189107753 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 92601 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 92601 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 98056716 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 98056716 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 98056716 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 92601 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 189015152 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 287164469 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1966611 # Total number of read requests seen -system.physmem.writeReqs 1019733 # Total number of write requests seen -system.physmem.cpureqs 2988993 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 125863104 # Total number of bytes read from memory -system.physmem.bytesWritten 65262912 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 125863104 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 65262912 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 562 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 62016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125796608 # Number of bytes read from this memory +system.physmem.bytes_read::total 125858624 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 62016 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 62016 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65265344 # Number of bytes written to this memory +system.physmem.bytes_written::total 65265344 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 969 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1965572 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1966541 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1019771 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1019771 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 93149 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 188948772 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 189041922 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 93149 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 93149 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 98029723 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 98029723 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 98029723 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 93149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 188948772 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 287071645 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1966541 # Total number of read requests seen +system.physmem.writeReqs 1019771 # Total number of write requests seen +system.physmem.cpureqs 2988947 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 125858624 # Total number of bytes read from memory +system.physmem.bytesWritten 65265344 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 125858624 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 65265344 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 566 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 122665 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 122306 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 122208 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 124220 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 123661 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 122580 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 120700 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 121417 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 122611 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 122314 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 122187 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 124202 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 123643 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 122594 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 120701 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 121432 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 121606 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 122292 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 121462 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 123460 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 125578 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 124270 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 123173 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 124451 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 63478 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 62392 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 63122 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 63842 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 64138 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 63875 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 63473 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 63461 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 63474 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 63840 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 63360 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 64241 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 64652 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 64261 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 63751 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 64373 # Track writes on a per bank basis +system.physmem.perBankRdReqs::9 122264 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 121460 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 123481 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 125598 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 124291 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 123180 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 124411 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 63480 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 62406 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 63107 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 63843 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 64137 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 63874 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 63470 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 63464 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 63489 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 63818 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 63362 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 64260 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 64664 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 64287 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 63760 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 64350 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2649 # Number of times wr buffer was full causing retry -system.physmem.totGap 665562829000 # Total gap between requests +system.physmem.numWrRetry 2635 # Number of times wr buffer was full causing retry +system.physmem.totGap 665770904000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 1966611 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1022382 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1625792 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 234895 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 77536 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 27805 # What read queue length does an incoming req see +system.physmem.readPktSize::6 1966541 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 1019771 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1625771 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 234883 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 77503 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 27794 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -137,90 +124,88 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 42397 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 43965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 44248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 44303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 44315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 44317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 44319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 44319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 44320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 42250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 43943 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 44238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 44300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 44316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 44321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 44321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 44322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 44322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2088 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 38 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 34363983237 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 102498683237 # Sum of mem lat for all requests -system.physmem.totBusLat 9830245000 # Total cycles spent in databus access -system.physmem.totBankLat 58304455000 # Total cycles spent in bank access -system.physmem.avgQLat 17478.70 # Average queueing delay per request -system.physmem.avgBankLat 29655.65 # Average bank access latency per request +system.physmem.totQLat 34478547500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 102599787500 # Sum of mem lat for all requests +system.physmem.totBusLat 9829875000 # Total cycles spent in databus access +system.physmem.totBankLat 58291365000 # Total cycles spent in bank access +system.physmem.avgQLat 17537.63 # Average queueing delay per request +system.physmem.avgBankLat 29650.10 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 52134.35 # Average memory access latency -system.physmem.avgRdBW 189.11 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 98.06 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 189.11 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 98.06 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 52187.74 # Average memory access latency +system.physmem.avgRdBW 189.04 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 98.03 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 189.04 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 98.03 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 2.24 # Data bus utilization in percentage system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 10.79 # Average write queue length over time -system.physmem.readRowHits 776053 # Number of row buffer hits during reads -system.physmem.writeRowHits 286138 # Number of row buffer hits during writes -system.physmem.readRowHitRate 39.47 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 28.06 # Row buffer hit rate for writes -system.physmem.avgGap 222868.77 # Average gap between requests -system.cpu.branchPred.lookups 381322658 # Number of BP lookups -system.cpu.branchPred.condPredicted 296346711 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 16069927 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 262182430 # Number of BTB lookups -system.cpu.branchPred.BTBHits 259521497 # Number of BTB hits +system.physmem.avgWrQLen 10.14 # Average write queue length over time +system.physmem.readRowHits 776350 # Number of row buffer hits during reads +system.physmem.writeRowHits 285987 # Number of row buffer hits during writes +system.physmem.readRowHitRate 39.49 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 28.04 # Row buffer hit rate for writes +system.physmem.avgGap 222940.84 # Average gap between requests +system.cpu.branchPred.lookups 381390262 # Number of BP lookups +system.cpu.branchPred.condPredicted 296397889 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 16086653 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 262140629 # Number of BTB lookups +system.cpu.branchPred.BTBHits 259559256 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.985083 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 24701305 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3076 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.015272 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 24699160 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3055 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 613798645 # DTB read hits -system.cpu.dtb.read_misses 11251599 # DTB read misses +system.cpu.dtb.read_hits 613788534 # DTB read hits +system.cpu.dtb.read_misses 11249325 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 625050244 # DTB read accesses -system.cpu.dtb.write_hits 212271089 # DTB write hits -system.cpu.dtb.write_misses 7143652 # DTB write misses +system.cpu.dtb.read_accesses 625037859 # DTB read accesses +system.cpu.dtb.write_hits 212245958 # DTB write hits +system.cpu.dtb.write_misses 7142739 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 219414741 # DTB write accesses -system.cpu.dtb.data_hits 826069734 # DTB hits -system.cpu.dtb.data_misses 18395251 # DTB misses +system.cpu.dtb.write_accesses 219388697 # DTB write accesses +system.cpu.dtb.data_hits 826034492 # DTB hits +system.cpu.dtb.data_misses 18392064 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 844464985 # DTB accesses -system.cpu.itb.fetch_hits 390709896 # ITB hits -system.cpu.itb.fetch_misses 44 # ITB misses +system.cpu.dtb.data_accesses 844426556 # DTB accesses +system.cpu.itb.fetch_hits 390787767 # ITB hits +system.cpu.itb.fetch_misses 43 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 390709940 # ITB accesses +system.cpu.itb.fetch_accesses 390787810 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -234,98 +219,98 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1331125796 # number of cpu cycles simulated +system.cpu.numCycles 1331541946 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 402151320 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3159313188 # Number of instructions fetch has processed -system.cpu.fetch.Branches 381322658 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 284222802 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 574163176 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 140279243 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 173671179 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 90 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1322 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 55 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 390709896 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8056983 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1266457048 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.494607 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.152796 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 402238482 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3159760476 # Number of instructions fetch has processed +system.cpu.fetch.Branches 381390262 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 284258416 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 574242721 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 140320135 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 173885771 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 30 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1317 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 44 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 390787767 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8065204 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1266865295 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.494157 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.152669 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 692293872 54.66% 54.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42630313 3.37% 58.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 21744461 1.72% 59.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 39673370 3.13% 62.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 129246893 10.21% 73.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 61513639 4.86% 77.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38552077 3.04% 80.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28113770 2.22% 83.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 212688653 16.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 692622574 54.67% 54.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42615431 3.36% 58.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 21758353 1.72% 59.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 39697295 3.13% 62.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 129259260 10.20% 73.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 61526950 4.86% 77.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38544819 3.04% 80.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28129154 2.22% 83.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 212711459 16.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1266457048 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.286466 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.373414 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 433835858 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 155176701 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 542390430 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18584911 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 116469148 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 58290582 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 824 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3086789571 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2029 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 116469148 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 456704578 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 101399871 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7042 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 535436988 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 56439421 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3004825157 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 566473 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1727265 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 50367655 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2246602827 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3897066108 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3895827965 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1238143 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1266865295 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.286428 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.373009 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 433949818 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 155380202 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 542435049 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18604092 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 116496134 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 58311036 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 855 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3087126857 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2089 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 116496134 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 456815247 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 101557658 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 5194 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 535499027 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 56492035 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3005134049 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 566488 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1739616 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 50408333 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2246840239 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3897438135 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3896197591 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1240544 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 870399864 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 162 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 161 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 121306422 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 679329311 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 255341435 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 67772546 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 36892101 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2723405673 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 122 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2508908939 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3097394 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 978157995 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 414914582 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 93 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1266457048 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.981045 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.973109 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 870637276 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 168 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 166 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 121366950 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 679350790 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 255350759 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 67967300 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 37114772 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2723579625 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 126 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2508981641 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3091159 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 978310045 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 415071720 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 97 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1266865295 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.980464 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.972855 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 426262331 33.66% 33.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 201879469 15.94% 49.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 185440300 14.64% 64.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153069981 12.09% 76.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 133127020 10.51% 86.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 81075751 6.40% 93.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 65263497 5.15% 98.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 15238482 1.20% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5100217 0.40% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 426523141 33.67% 33.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 201951837 15.94% 49.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 185492394 14.64% 64.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153160708 12.09% 76.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 133131866 10.51% 86.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 81031270 6.40% 93.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 65244416 5.15% 98.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15224722 1.20% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5104941 0.40% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1266457048 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1266865295 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2147356 11.64% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2143481 11.64% 11.64% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 11.64% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 11.64% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.64% # attempts to use FU when none available @@ -354,118 +339,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.64% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11882629 64.43% 76.08% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4412064 23.92% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11871999 64.46% 76.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4401590 23.90% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1643457358 65.50% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 108 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 284 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 162 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 38 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 26 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 641426814 25.57% 91.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 224024134 8.93% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1643559437 65.51% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 106 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 261 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 16 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 162 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 31 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 641411468 25.56% 91.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 224010136 8.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2508908939 # Type of FU issued -system.cpu.iq.rate 1.884802 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18442049 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007351 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6303917077 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3700456251 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2412530118 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1897292 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1213669 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 850482 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2526413076 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 937912 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62601543 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2508981641 # Type of FU issued +system.cpu.iq.rate 1.884268 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18417070 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007340 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6304440735 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3700781380 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2412589185 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1896071 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1214370 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 849902 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2526461544 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 937167 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62583251 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 234733648 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 263681 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 107887 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 94612933 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 234755127 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 263530 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 107682 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94622257 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 149 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1508556 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 167 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1505929 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 116469148 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 45249808 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1153798 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2865411802 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 8865893 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 679329311 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 255341435 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 122 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 296621 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17062 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 107887 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10351897 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8549059 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18900956 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2461552831 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 625050873 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 47356108 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 116496134 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 45259128 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1153276 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2865598045 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 8882954 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 679350790 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 255350759 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 126 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 296462 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17110 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 107682 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10363121 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8561161 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18924282 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2461596227 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 625038408 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 47385414 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 142006007 # number of nop insts executed -system.cpu.iew.exec_refs 844465652 # number of memory reference insts executed -system.cpu.iew.exec_branches 300780520 # Number of branches executed -system.cpu.iew.exec_stores 219414779 # Number of stores executed -system.cpu.iew.exec_rate 1.849226 # Inst execution rate -system.cpu.iew.wb_sent 2441340597 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2413380600 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1388547079 # num instructions producing a value -system.cpu.iew.wb_consumers 1764258867 # num instructions consuming a value +system.cpu.iew.exec_nop 142018294 # number of nop insts executed +system.cpu.iew.exec_refs 844427141 # number of memory reference insts executed +system.cpu.iew.exec_branches 300792164 # Number of branches executed +system.cpu.iew.exec_stores 219388733 # Number of stores executed +system.cpu.iew.exec_rate 1.848681 # Inst execution rate +system.cpu.iew.wb_sent 2441396740 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2413439087 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1388573479 # num instructions producing a value +system.cpu.iew.wb_consumers 1764243384 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.813037 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.787043 # average fanout of values written-back +system.cpu.iew.wb_rate 1.812515 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.787065 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 824496541 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 824671147 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16069169 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1149987900 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.582434 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.513328 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16085857 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1150369161 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.581910 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.512649 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 636582703 55.36% 55.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174528815 15.18% 70.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 86154838 7.49% 78.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53696009 4.67% 82.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 34510870 3.00% 85.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 25214106 2.19% 87.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 21871895 1.90% 89.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22921084 1.99% 91.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 94507580 8.22% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 636844570 55.36% 55.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 174611268 15.18% 70.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 86171312 7.49% 78.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53631613 4.66% 82.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 34569452 3.01% 85.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 25367501 2.21% 87.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 21831937 1.90% 89.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22907604 1.99% 91.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 94433904 8.21% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1149987900 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1150369161 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -476,189 +461,189 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 94507580 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 94433904 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3613977787 # The number of ROB reads -system.cpu.rob.rob_writes 5405122718 # The number of ROB writes -system.cpu.timesIdled 818240 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 64668748 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3614607330 # The number of ROB reads +system.cpu.rob.rob_writes 5405498913 # The number of ROB writes +system.cpu.timesIdled 817784 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 64676651 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.766758 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.766758 # CPI: Total CPI of All Threads -system.cpu.ipc 1.304192 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.304192 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3317304663 # number of integer regfile reads -system.cpu.int_regfile_writes 1931628776 # number of integer regfile writes -system.cpu.fp_regfile_reads 30090 # number of floating regfile reads -system.cpu.fp_regfile_writes 557 # number of floating regfile writes +system.cpu.cpi 0.766998 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.766998 # CPI: Total CPI of All Threads +system.cpu.ipc 1.303785 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.303785 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3317361939 # number of integer regfile reads +system.cpu.int_regfile_writes 1931707111 # number of integer regfile writes +system.cpu.fp_regfile_reads 30073 # number of floating regfile reads +system.cpu.fp_regfile_writes 529 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 772.264197 # Cycle average of tags in use -system.cpu.icache.total_refs 390708412 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 963 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 405720.053998 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 776.168102 # Cycle average of tags in use +system.cpu.icache.total_refs 390786293 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 969 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 403288.228070 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 772.264197 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.377082 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.377082 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 390708412 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 390708412 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 390708412 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 390708412 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 390708412 # number of overall hits -system.cpu.icache.overall_hits::total 390708412 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1482 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1482 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1482 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1482 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1482 # number of overall misses -system.cpu.icache.overall_misses::total 1482 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 83554999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 83554999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 83554999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 83554999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 83554999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 83554999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 390709894 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 390709894 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 390709894 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 390709894 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 390709894 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 390709894 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 776.168102 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.378988 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.378988 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 390786293 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 390786293 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 390786293 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 390786293 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 390786293 # number of overall hits +system.cpu.icache.overall_hits::total 390786293 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1474 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1474 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1474 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1474 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1474 # number of overall misses +system.cpu.icache.overall_misses::total 1474 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 87004499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 87004499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 87004499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 87004499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 87004499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 87004499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 390787767 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 390787767 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 390787767 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 390787767 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 390787767 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 390787767 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56379.891363 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56379.891363 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56379.891363 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56379.891363 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56379.891363 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56379.891363 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 398 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59026.118725 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 59026.118725 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 59026.118725 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 59026.118725 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 59026.118725 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 59026.118725 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1157 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 56.857143 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 289.250000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 519 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 519 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 519 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 519 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 519 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 519 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 963 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 963 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 963 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 963 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 963 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 963 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59079999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 59079999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59079999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 59079999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59079999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 59079999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 505 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 505 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 505 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 505 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 505 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 505 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 969 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 969 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 969 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 969 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 969 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61752999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 61752999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61752999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 61752999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61752999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 61752999 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61349.947040 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61349.947040 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61349.947040 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 61349.947040 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61349.947040 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 61349.947040 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 63728.585139 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 63728.585139 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 63728.585139 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 63728.585139 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 63728.585139 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 63728.585139 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1933906 # number of replacements -system.cpu.l2cache.tagsinuse 31417.619654 # Cycle average of tags in use -system.cpu.l2cache.total_refs 9058583 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1963686 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.613051 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 27417124252 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14685.670328 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 26.375738 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 16705.573589 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.448171 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000805 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.509814 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.958790 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 6106242 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6106242 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3725054 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3725054 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1108469 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1108469 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 7214711 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7214711 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7214711 # number of overall hits -system.cpu.l2cache.overall_hits::total 7214711 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 963 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1190539 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1191502 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 775109 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 775109 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 963 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1965648 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1966611 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 963 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1965648 # number of overall misses -system.cpu.l2cache.overall_misses::total 1966611 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 58109000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 90112899500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 90171008500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 58086526000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 58086526000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 58109000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 148199425500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 148257534500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 58109000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 148199425500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 148257534500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 963 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7296781 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7297744 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3725054 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3725054 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1883578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 963 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9180359 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9181322 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 963 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9180359 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9181322 # number of overall (read+write) accesses +system.cpu.l2cache.replacements 1933842 # number of replacements +system.cpu.l2cache.tagsinuse 31417.862121 # Cycle average of tags in use +system.cpu.l2cache.total_refs 9058109 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1963616 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.612974 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 27417124251 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14684.455679 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 26.907136 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 16706.499305 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.448134 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000821 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.509842 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.958797 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 6106130 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6106130 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3724718 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3724718 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1108431 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1108431 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 7214561 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7214561 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 7214561 # number of overall hits +system.cpu.l2cache.overall_hits::total 7214561 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 969 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1190438 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1191407 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 775134 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 775134 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 969 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1965572 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1966541 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 969 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1965572 # number of overall misses +system.cpu.l2cache.overall_misses::total 1966541 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 60777000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 90110538000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 90171315000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 58186183500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 58186183500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 60777000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 148296721500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 148357498500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 60777000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 148296721500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 148357498500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 969 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7296568 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7297537 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3724718 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3724718 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883565 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1883565 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 969 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9180133 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9181102 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 969 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9180133 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9181102 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163159 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.163270 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.411509 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.411509 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163150 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.163262 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.411525 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.411525 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.214115 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.214197 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.214111 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.214194 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.214115 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.214197 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60341.640706 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75690.842131 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75678.436545 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74939.816206 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74939.816206 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60341.640706 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75394.691979 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75387.320878 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60341.640706 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75394.691979 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75387.320878 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.214111 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.214194 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 62721.362229 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75695.280225 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75684.728225 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75065.967304 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75065.967304 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 62721.362229 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75447.107254 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75440.836728 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 62721.362229 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75447.107254 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75440.836728 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -667,180 +652,180 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1019733 # number of writebacks -system.cpu.l2cache.writebacks::total 1019733 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 963 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1190539 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1191502 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 775109 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 775109 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 963 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1965648 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1966611 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 963 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1965648 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1966611 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 46150301 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 75292068672 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 75338218973 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48421097021 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48421097021 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 46150301 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 123713165693 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 123759315994 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 46150301 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 123713165693 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 123759315994 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 1019771 # number of writebacks +system.cpu.l2cache.writebacks::total 1019771 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 969 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1190438 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1191407 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 775134 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 775134 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 969 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1965572 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1966541 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 969 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1965572 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1966541 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 48746029 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 75289506732 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 75338252761 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48519819623 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48519819623 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48746029 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 123809326355 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 123858072384 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48746029 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 123809326355 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 123858072384 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163159 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163270 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411509 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411509 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163150 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163262 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411525 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411525 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214115 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214197 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214111 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214194 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214115 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214197 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47923.469367 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63242.001037 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63229.620238 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62470.048756 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62470.048756 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47923.469367 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62937.599048 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62930.247006 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47923.469367 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62937.599048 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62930.247006 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214111 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214194 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 50305.499484 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63245.214561 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63234.690380 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62595.395923 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62595.395923 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50305.499484 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62988.955050 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62982.705361 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50305.499484 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62988.955050 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62982.705361 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9176263 # number of replacements -system.cpu.dcache.tagsinuse 4087.522413 # Cycle average of tags in use -system.cpu.dcache.total_refs 694338200 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9180359 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 75.633012 # Average number of references to valid blocks. +system.cpu.dcache.replacements 9176037 # number of replacements +system.cpu.dcache.tagsinuse 4087.525084 # Cycle average of tags in use +system.cpu.dcache.total_refs 694351222 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9180133 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 75.636292 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 5069314000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.522413 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997930 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997930 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 538691860 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 538691860 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155646338 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155646338 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 694338198 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 694338198 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 694338198 # number of overall hits -system.cpu.dcache.overall_hits::total 694338198 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11282428 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11282428 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5082164 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5082164 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 4087.525084 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997931 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997931 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 538704902 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 538704902 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155646317 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155646317 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 694351219 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 694351219 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 694351219 # number of overall hits +system.cpu.dcache.overall_hits::total 694351219 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11279943 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11279943 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5082185 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5082185 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 16364592 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 16364592 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 16364592 # number of overall misses -system.cpu.dcache.overall_misses::total 16364592 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 295012100000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 295012100000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 224191521595 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 224191521595 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 431500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 431500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 519203621595 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 519203621595 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 519203621595 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 519203621595 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 549974288 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 549974288 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 16362128 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 16362128 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 16362128 # number of overall misses +system.cpu.dcache.overall_misses::total 16362128 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 294923775000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 294923775000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 224062273308 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 224062273308 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 49500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 49500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 518986048308 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 518986048308 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 518986048308 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 518986048308 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 549984845 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 549984845 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 710702790 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 710702790 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 710702790 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 710702790 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020514 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020514 # miss rate for ReadReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 710713347 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 710713347 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 710713347 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 710713347 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020510 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020510 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.031620 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.031620 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.333333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.333333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023026 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023026 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023026 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023026 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26147.926670 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26147.926670 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44113.397678 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44113.397678 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 431500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 431500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31727.257337 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31727.257337 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31727.257337 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31727.257337 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12329196 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 5816488 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 735313 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.250000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.250000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.023022 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023022 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023022 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023022 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26145.856854 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26145.856854 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44087.783760 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44087.783760 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31718.737826 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31718.737826 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31718.737826 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31718.737826 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 12309965 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 5809756 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 734892 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 65134 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.767276 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 89.300335 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.750713 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 89.196979 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3725054 # number of writebacks -system.cpu.dcache.writebacks::total 3725054 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3985636 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3985636 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3198598 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3198598 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7184234 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7184234 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7184234 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7184234 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296792 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7296792 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883566 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883566 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3724718 # number of writebacks +system.cpu.dcache.writebacks::total 3724718 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3983366 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3983366 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3198630 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3198630 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7181996 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7181996 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7181996 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7181996 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296577 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7296577 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883555 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1883555 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9180358 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9180358 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9180358 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9180358 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 159255490500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 159255490500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71503545346 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 71503545346 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 429500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 429500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230759035846 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 230759035846 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230759035846 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 230759035846 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013268 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013268 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 9180132 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9180132 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9180132 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9180132 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 159251608500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 159251608500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71602703007 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 71602703007 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 47500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 47500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230854311507 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 230854311507 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230854311507 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 230854311507 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013267 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013267 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011719 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.333333 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.250000 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012917 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.012917 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012917 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.012917 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21825.411839 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21825.411839 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37961.794461 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37961.794461 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 429500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 429500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25136.169618 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25136.169618 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25136.169618 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25136.169618 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21825.522913 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21825.522913 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38014.660048 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38014.660048 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 47500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 47500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25147.166893 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25147.166893 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25147.166893 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25147.166893 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index fe58c49f1..dd9108dcd 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,115 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.517386 # Number of seconds simulated -sim_ticks 517386177000 # Number of ticks simulated -final_tick 517386177000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.517371 # Number of seconds simulated +sim_ticks 517371024000 # Number of ticks simulated +final_tick 517371024000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 165493 # Simulator instruction rate (inst/s) -host_op_rate 184620 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55435711 # Simulator tick rate (ticks/s) -host_mem_usage 502788 # Number of bytes of host memory used -host_seconds 9333.08 # Real time elapsed on the host +host_inst_rate 170437 # Simulator instruction rate (inst/s) +host_op_rate 190135 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57090080 # Simulator tick rate (ticks/s) +host_mem_usage 485276 # Number of bytes of host memory used +host_seconds 9062.36 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1723073835 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 48000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 143728256 # Number of bytes read from this memory -system.physmem.bytes_read::total 143776256 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 48000 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 48000 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 70436224 # Number of bytes written to this memory -system.physmem.bytes_written::total 70436224 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 750 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2245754 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2246504 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1100566 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1100566 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 92774 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 277796861 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 277889635 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 92774 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 92774 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 136138589 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 136138589 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 136138589 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 92774 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 277796861 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 414028224 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2246504 # Total number of read requests seen -system.physmem.writeReqs 1100566 # Total number of write requests seen -system.physmem.cpureqs 3350665 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 143776256 # Total number of bytes read from memory -system.physmem.bytesWritten 70436224 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 143776256 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 70436224 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 651 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 48064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 143734144 # Number of bytes read from this memory +system.physmem.bytes_read::total 143782208 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 48064 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 48064 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 70446784 # Number of bytes written to this memory +system.physmem.bytes_written::total 70446784 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 751 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2245846 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2246597 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1100731 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1100731 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 92900 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 277816378 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 277909279 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 92900 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 92900 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 136162987 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 136162987 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 136162987 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 92900 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 277816378 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 414072265 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2246597 # Total number of read requests seen +system.physmem.writeReqs 1100731 # Total number of write requests seen +system.physmem.cpureqs 3350452 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 143782208 # Total number of bytes read from memory +system.physmem.bytesWritten 70446784 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 143782208 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 70446784 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 642 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 141458 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 139475 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 141540 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 141707 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 142337 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 139999 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 141291 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 140517 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 138551 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 136478 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 140625 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 140699 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 141026 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 139159 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 139234 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 141757 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 69121 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 68349 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 69146 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 69473 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 69281 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 68946 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 69052 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 68358 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 67825 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 67029 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 69533 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 69302 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 69105 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 68630 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 141495 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 139690 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 141603 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 141749 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 142295 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 140068 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 141091 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 140693 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 138519 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 136203 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 140642 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 140693 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 141066 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 139208 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 139271 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 141669 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 69094 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 68448 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 69171 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 69468 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 69338 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 68952 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 69046 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 68406 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 67828 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 66957 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 69534 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 69263 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 69109 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 68653 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 68505 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 68911 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 68959 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 3595 # Number of times wr buffer was full causing retry -system.physmem.totGap 517386097500 # Total gap between requests +system.physmem.numWrRetry 3124 # Number of times wr buffer was full causing retry +system.physmem.totGap 517370944500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 2246504 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1104161 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1563469 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 451045 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 162632 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 68688 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.physmem.readPktSize::6 2246597 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 1100731 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1563680 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 451075 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 162592 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 68583 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -137,70 +124,68 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 44097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 47155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 47729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 47801 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 47826 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 47832 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 47832 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 47832 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 47832 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 47851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 47851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 47851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 47851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 47851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 47851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 47851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 47850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 47850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 47850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 47850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 47850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 47850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 47850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 3754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 51687050307 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 131176334057 # Sum of mem lat for all requests -system.physmem.totBusLat 11229265000 # Total cycles spent in databus access -system.physmem.totBankLat 68260018750 # Total cycles spent in bank access -system.physmem.avgQLat 23014.44 # Average queueing delay per request -system.physmem.avgBankLat 30393.81 # Average bank access latency per request +system.physmem.wrQLenPdf::0 44125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 47135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 47739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 47809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 47829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 47835 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 47837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 47838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 47840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 47858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 47858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 47858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 47858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 47858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 47858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 47858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 47858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 47858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 47858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 47858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 47857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 47857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 47857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 3733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 18 # What write queue length does an incoming req see +system.physmem.totQLat 51812524750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 131293078500 # Sum of mem lat for all requests +system.physmem.totBusLat 11229775000 # Total cycles spent in databus access +system.physmem.totBankLat 68250778750 # Total cycles spent in bank access +system.physmem.avgQLat 23069.26 # Average queueing delay per request +system.physmem.avgBankLat 30388.31 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 58408.25 # Average memory access latency -system.physmem.avgRdBW 277.89 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 136.14 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 277.89 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 136.14 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 58457.57 # Average memory access latency +system.physmem.avgRdBW 277.91 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 136.16 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 277.91 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 136.16 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.23 # Data bus utilization in percentage system.physmem.avgRdQLen 0.25 # Average read queue length over time -system.physmem.avgWrQLen 10.38 # Average write queue length over time -system.physmem.readRowHits 827421 # Number of row buffer hits during reads -system.physmem.writeRowHits 271011 # Number of row buffer hits during writes -system.physmem.readRowHitRate 36.84 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 24.62 # Row buffer hit rate for writes -system.physmem.avgGap 154578.81 # Average gap between requests -system.cpu.branchPred.lookups 303247532 # Number of BP lookups -system.cpu.branchPred.condPredicted 249450034 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15218023 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 175041543 # Number of BTB lookups -system.cpu.branchPred.BTBHits 161435617 # Number of BTB hits +system.physmem.avgWrQLen 10.92 # Average write queue length over time +system.physmem.readRowHits 827855 # Number of row buffer hits during reads +system.physmem.writeRowHits 271156 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.86 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 24.63 # Row buffer hit rate for writes +system.physmem.avgGap 154562.37 # Average gap between requests +system.cpu.branchPred.lookups 303290886 # Number of BP lookups +system.cpu.branchPred.condPredicted 249488582 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15222231 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 174596646 # Number of BTB lookups +system.cpu.branchPred.BTBHits 161469311 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.227030 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 17558020 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 197 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.481336 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 17557313 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 202 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -244,133 +229,133 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1034772355 # number of cpu cycles simulated +system.cpu.numCycles 1034742049 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 298171037 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2186159989 # Number of instructions fetch has processed -system.cpu.fetch.Branches 303247532 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 178993637 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 435067157 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 87822274 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 155469980 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 663 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 288529454 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5728473 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 958589014 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.523348 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.213310 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 298209547 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2186343540 # Number of instructions fetch has processed +system.cpu.fetch.Branches 303290886 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 179026624 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 435120674 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 87852250 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 155399906 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 380 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 288562414 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5732154 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 958634216 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.523474 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.213325 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 523521931 54.61% 54.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25504837 2.66% 57.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 39086427 4.08% 61.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 48350867 5.04% 66.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 43002654 4.49% 70.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46446539 4.85% 75.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38408277 4.01% 79.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18709630 1.95% 81.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 175557852 18.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 523513675 54.61% 54.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25518990 2.66% 57.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 39095186 4.08% 61.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 48349741 5.04% 66.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 43010158 4.49% 70.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46440341 4.84% 75.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38425121 4.01% 79.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18710957 1.95% 81.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 175570047 18.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 958589014 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.293057 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.112697 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 329732299 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 133726687 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 405163333 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20087198 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 69879497 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46055159 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 678 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2366957956 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2458 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 69879497 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 353264569 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 63487571 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 18775 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 400193247 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 71745355 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2304463172 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 133379 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5038858 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 58609164 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 17 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2279851599 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10642208168 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10642204755 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3413 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 958634216 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.293108 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.112936 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 329763250 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 133666994 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 405221512 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20079412 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 69903048 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46058380 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 679 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2367190993 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2433 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 69903048 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 353304996 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 63447183 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 15614 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 400231748 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 71731627 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2304653779 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 133097 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5040028 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 58589233 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 7 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2280042978 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10643127773 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10643124880 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2893 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 573531669 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 681 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 678 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 158828994 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 624462299 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 220966139 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 86157140 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 71007424 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2201342631 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 714 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2018151759 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3999657 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 473702297 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1125076843 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 544 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 958589014 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.105336 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.906417 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 573723048 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 497 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 494 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 158827938 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 624515157 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 220983969 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 86332349 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 71315853 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2201513470 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 522 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2018112827 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4002858 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 473886256 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1126241029 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 352 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 958634216 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.105196 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.906381 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 277560944 28.96% 28.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 151408943 15.79% 44.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 161184316 16.81% 61.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 119741050 12.49% 74.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 124054843 12.94% 87.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 73850392 7.70% 94.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 38407609 4.01% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9813288 1.02% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2567629 0.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 277594004 28.96% 28.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 151404549 15.79% 44.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 161201477 16.82% 61.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 119812250 12.50% 74.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 123999377 12.94% 87.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 73820536 7.70% 94.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 38419650 4.01% 98.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9808498 1.02% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2573875 0.27% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 958589014 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 958634216 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 872793 3.65% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5710 0.02% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18283969 76.42% 80.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4762893 19.91% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 872312 3.66% 3.66% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5645 0.02% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18268766 76.62% 80.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4697940 19.70% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1236667909 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 925774 0.05% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1236677496 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 926030 0.05% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -392,90 +377,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 51 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 33 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 24 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 8 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 5 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 587469094 29.11% 90.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193088896 9.57% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 587482532 29.11% 90.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193026708 9.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2018151759 # Type of FU issued -system.cpu.iq.rate 1.950334 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23925365 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011855 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5022817228 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2675235301 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1957490366 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 326 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 628 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 132 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2042076961 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 163 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 64626006 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2018112827 # Type of FU issued +system.cpu.iq.rate 1.950354 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23844663 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011815 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5022707128 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2675590256 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1957438118 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 263 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 556 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 103 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2041957357 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 133 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 64629974 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 138535530 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 270863 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 192819 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 46119094 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 138588388 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 271831 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 192988 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 46136924 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4653355 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 4659196 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 69879497 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28935964 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1499081 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2201343583 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6151222 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 624462299 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 220966139 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 652 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 473850 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 90091 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 192819 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8153540 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 9614603 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 17768143 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1988132356 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 573881676 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 30019403 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 69903048 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28888784 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1501235 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2201514122 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6139547 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 624515157 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 220983969 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 460 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 475783 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 89669 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 192988 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8156378 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 9617829 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 17774207 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1988116656 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 573901246 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29996171 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 238 # number of nop insts executed -system.cpu.iew.exec_refs 764075762 # number of memory reference insts executed -system.cpu.iew.exec_branches 238335526 # Number of branches executed -system.cpu.iew.exec_stores 190194086 # Number of stores executed -system.cpu.iew.exec_rate 1.921323 # Inst execution rate -system.cpu.iew.wb_sent 1965930006 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1957490498 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1296385031 # num instructions producing a value -system.cpu.iew.wb_consumers 2061135459 # num instructions consuming a value +system.cpu.iew.exec_nop 130 # number of nop insts executed +system.cpu.iew.exec_refs 764045166 # number of memory reference insts executed +system.cpu.iew.exec_branches 238330381 # Number of branches executed +system.cpu.iew.exec_stores 190143920 # Number of stores executed +system.cpu.iew.exec_rate 1.921365 # Inst execution rate +system.cpu.iew.wb_sent 1965882705 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1957438221 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1296419261 # num instructions producing a value +system.cpu.iew.wb_consumers 2061223018 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.891711 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.628966 # average fanout of values written-back +system.cpu.iew.wb_rate 1.891716 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.628956 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 478367692 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 478537797 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15217365 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 888709517 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.938849 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.727981 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15221576 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 888731168 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.938802 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.727796 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 401294450 45.15% 45.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 192123349 21.62% 66.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 72572906 8.17% 74.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35244916 3.97% 78.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18969010 2.13% 81.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30763331 3.46% 84.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 20056672 2.26% 86.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11441847 1.29% 88.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106243036 11.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 401249220 45.15% 45.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 192209497 21.63% 66.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72554391 8.16% 74.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35214687 3.96% 78.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19001350 2.14% 81.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30768614 3.46% 84.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 20079948 2.26% 86.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11444333 1.29% 88.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106209128 11.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 888709517 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 888731168 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563041 # Number of instructions committed system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -486,70 +471,70 @@ system.cpu.commit.branches 213462426 # Nu system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106243036 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106209128 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2983907427 # The number of ROB reads -system.cpu.rob.rob_writes 4472910463 # The number of ROB writes -system.cpu.timesIdled 1017511 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 76183341 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2984133091 # The number of ROB reads +system.cpu.rob.rob_writes 4473274350 # The number of ROB writes +system.cpu.timesIdled 1017651 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 76107833 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563023 # Number of Instructions Simulated system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated -system.cpu.cpi 0.669945 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.669945 # CPI: Total CPI of All Threads -system.cpu.ipc 1.492660 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.492660 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9956386896 # number of integer regfile reads -system.cpu.int_regfile_writes 1937427158 # number of integer regfile writes -system.cpu.fp_regfile_reads 137 # number of floating regfile reads -system.cpu.fp_regfile_writes 146 # number of floating regfile writes -system.cpu.misc_regfile_reads 737590270 # number of misc regfile reads +system.cpu.cpi 0.669925 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.669925 # CPI: Total CPI of All Threads +system.cpu.ipc 1.492703 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.492703 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9956233395 # number of integer regfile reads +system.cpu.int_regfile_writes 1937436072 # number of integer regfile writes +system.cpu.fp_regfile_reads 98 # number of floating regfile reads +system.cpu.fp_regfile_writes 104 # number of floating regfile writes +system.cpu.misc_regfile_reads 737527238 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.icache.replacements 21 # number of replacements -system.cpu.icache.tagsinuse 626.247624 # Cycle average of tags in use -system.cpu.icache.total_refs 288528273 # Total number of references to valid blocks. +system.cpu.icache.replacements 22 # number of replacements +system.cpu.icache.tagsinuse 625.709575 # Cycle average of tags in use +system.cpu.icache.total_refs 288561231 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 779 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 370382.892169 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 370425.200257 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 626.247624 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.305785 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.305785 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 288528273 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 288528273 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 288528273 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 288528273 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 288528273 # number of overall hits -system.cpu.icache.overall_hits::total 288528273 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1181 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1181 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1181 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1181 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1181 # number of overall misses -system.cpu.icache.overall_misses::total 1181 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 66140500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 66140500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 66140500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 66140500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 66140500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 66140500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 288529454 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 288529454 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 288529454 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 288529454 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 288529454 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 288529454 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 625.709575 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.305522 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.305522 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 288561231 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 288561231 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 288561231 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 288561231 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 288561231 # number of overall hits +system.cpu.icache.overall_hits::total 288561231 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1183 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1183 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1183 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1183 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1183 # number of overall misses +system.cpu.icache.overall_misses::total 1183 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 68862000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 68862000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 68862000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 68862000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 68862000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 68862000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 288562414 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 288562414 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 288562414 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 288562414 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 288562414 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 288562414 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56003.810330 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56003.810330 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56003.810330 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56003.810330 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56003.810330 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56003.810330 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58209.636517 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 58209.636517 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 58209.636517 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 58209.636517 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 58209.636517 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 58209.636517 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 195 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -558,120 +543,120 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 65 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 402 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 402 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 402 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 402 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 402 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 402 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 404 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 404 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 404 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 404 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 404 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 404 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 779 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 779 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 779 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 779 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 779 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 779 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46510000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 46510000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46510000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 46510000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46510000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 46510000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46813500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 46813500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46813500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 46813500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46813500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 46813500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59704.749679 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59704.749679 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59704.749679 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 59704.749679 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59704.749679 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 59704.749679 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60094.351733 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60094.351733 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60094.351733 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60094.351733 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60094.351733 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60094.351733 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2213813 # number of replacements -system.cpu.l2cache.tagsinuse 31531.943712 # Cycle average of tags in use -system.cpu.l2cache.total_refs 9246179 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2243587 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.121159 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 20448147252 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14437.603993 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 20.351640 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 17073.988080 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.440601 # Average percentage of cache occupancy +system.cpu.l2cache.replacements 2213910 # number of replacements +system.cpu.l2cache.tagsinuse 31531.957469 # Cycle average of tags in use +system.cpu.l2cache.total_refs 9247495 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2243685 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.121566 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 20448147251 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14435.927117 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 20.343245 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 17075.687107 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.440550 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.000621 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.521057 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.521109 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.962279 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 28 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 6289367 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6289395 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3781250 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3781250 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1066794 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1066794 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 28 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7356161 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7356189 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 28 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7356161 # number of overall hits -system.cpu.l2cache.overall_hits::total 7356189 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 751 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1419105 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1419856 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 826656 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 826656 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 751 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2245761 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2246512 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 751 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2245761 # number of overall misses -system.cpu.l2cache.overall_misses::total 2246512 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45442000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 113741424500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 113786866500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70408170000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 70408170000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 45442000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 184149594500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 184195036500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 45442000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 184149594500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 184195036500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_hits::cpu.inst 27 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 6290241 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6290268 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3781695 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3781695 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1066899 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1066899 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 27 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7357140 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7357167 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 27 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 7357140 # number of overall hits +system.cpu.l2cache.overall_hits::total 7357167 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 752 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1419201 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1419953 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 826653 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 826653 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 752 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2245854 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2246606 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 752 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2245854 # number of overall misses +system.cpu.l2cache.overall_misses::total 2246606 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45758500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 113786309000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 113832067500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70488863500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 70488863500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 45758500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 184275172500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 184320931000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 45758500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 184275172500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 184320931000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 779 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7708472 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7709251 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3781250 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3781250 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893450 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1893450 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7709442 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7710221 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3781695 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3781695 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893552 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1893552 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 779 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9601922 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9602701 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9602994 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9603773 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 779 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9601922 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9602701 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.964056 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184097 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.184176 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436587 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.436587 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.964056 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.233887 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.233946 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964056 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.233887 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.233946 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60508.655126 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80150.111866 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 80139.722972 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85172.272384 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85172.272384 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60508.655126 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81998.749867 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 81991.565814 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60508.655126 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81998.749867 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 81991.565814 # average overall miss latency +system.cpu.l2cache.overall_accesses::cpu.data 9602994 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9603773 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965340 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184086 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.184165 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436562 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.436562 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965340 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.233870 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.233930 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965340 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.233870 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.233930 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60849.069149 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80176.316815 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 80166.081201 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85270.196201 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85270.196201 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60849.069149 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82051.269806 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82044.172855 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60849.069149 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82051.269806 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82044.172855 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -680,187 +665,187 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1100566 # number of writebacks -system.cpu.l2cache.writebacks::total 1100566 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1100731 # number of writebacks +system.cpu.l2cache.writebacks::total 1100731 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 750 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419098 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1419848 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826656 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 826656 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 750 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2245754 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2246504 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 750 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2245754 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2246504 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35808198 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 96120907910 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 96156716108 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60148132877 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60148132877 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35808198 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156269040787 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 156304848985 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35808198 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156269040787 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 156304848985 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962773 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184096 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184175 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436587 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436587 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962773 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233886 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.233945 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962773 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233886 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.233945 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47744.264000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67733.805495 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67723.246508 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72760.777006 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72760.777006 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47744.264000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69584.220171 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69576.928857 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47744.264000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69584.220171 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69576.928857 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 751 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419193 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1419944 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826653 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 826653 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 751 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2245846 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2246597 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 751 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2245846 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2246597 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 36118599 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 96162576934 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 96198695533 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60228963949 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60228963949 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 36118599 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156391540883 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 156427659482 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 36118599 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156391540883 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 156427659482 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964056 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184085 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184164 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436562 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436562 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964056 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233869 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.233929 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964056 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233869 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.233929 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48094.006658 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67758.632500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67748.231996 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72858.822201 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72858.822201 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48094.006658 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69635.914877 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69628.713776 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48094.006658 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69635.914877 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69628.713776 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9597826 # number of replacements -system.cpu.dcache.tagsinuse 4088.019917 # Cycle average of tags in use -system.cpu.dcache.total_refs 656092202 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9601922 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 68.329258 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 3440649000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4088.019917 # Average occupied blocks per requestor +system.cpu.dcache.replacements 9598898 # number of replacements +system.cpu.dcache.tagsinuse 4088.019682 # Cycle average of tags in use +system.cpu.dcache.total_refs 656099070 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9602994 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 68.322345 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 3440663000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4088.019682 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.998052 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.998052 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 489045122 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 489045122 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 167046955 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 167046955 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 64 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 64 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 489051603 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 489051603 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 167047341 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 167047341 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 65 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 65 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 656092077 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 656092077 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 656092077 # number of overall hits -system.cpu.dcache.overall_hits::total 656092077 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11476427 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11476427 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5539092 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5539092 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 656098944 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 656098944 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 656098944 # number of overall hits +system.cpu.dcache.overall_hits::total 656098944 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11478513 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11478513 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5538706 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5538706 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 17015519 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 17015519 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 17015519 # number of overall misses -system.cpu.dcache.overall_misses::total 17015519 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 322914399500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 322914399500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 229337265001 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 229337265001 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 188000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 188000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 552251664501 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 552251664501 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 552251664501 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 552251664501 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 500521549 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 500521549 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 17017219 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17017219 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 17017219 # number of overall misses +system.cpu.dcache.overall_misses::total 17017219 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 323000428500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 323000428500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 229631369718 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 229631369718 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 423500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 423500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 552631798218 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 552631798218 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 552631798218 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 552631798218 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 500530116 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 500530116 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 67 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 67 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 68 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 68 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 673107596 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 673107596 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 673107596 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 673107596 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022929 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022929 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032095 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032095 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044776 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044776 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025279 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025279 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025279 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025279 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28137.189345 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28137.189345 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41403.404204 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41403.404204 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62666.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62666.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32455.763736 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 32455.763736 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32455.763736 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32455.763736 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 26327984 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1057907 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1182334 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 64553 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.267806 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 16.388193 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 673116163 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 673116163 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 673116163 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 673116163 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022933 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022933 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032092 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032092 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044118 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044118 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025281 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025281 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025281 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025281 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28139.570735 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28139.570735 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41459.389561 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41459.389561 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 141166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 141166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32474.859624 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32474.859624 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32474.859624 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32474.859624 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 26343962 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1054966 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1182360 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 64552 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.280830 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 16.342886 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3781250 # number of writebacks -system.cpu.dcache.writebacks::total 3781250 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3767955 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3767955 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3645642 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3645642 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3781695 # number of writebacks +system.cpu.dcache.writebacks::total 3781695 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3769070 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3769070 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3645155 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3645155 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7413597 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7413597 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7413597 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7413597 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708472 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7708472 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893450 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1893450 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9601922 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9601922 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9601922 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9601922 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 186178488500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 186178488500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83508071510 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 83508071510 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 269686560010 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 269686560010 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 269686560010 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 269686560010 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015401 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015401 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014265 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014265 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24152.450512 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24152.450512 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44103.658143 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44103.658143 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28086.726804 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28086.726804 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28086.726804 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28086.726804 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 7414225 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7414225 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7414225 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7414225 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7709443 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7709443 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893551 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1893551 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9602994 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9602994 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9602994 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9602994 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 186232562000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 186232562000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83589909224 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 83589909224 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 269822471224 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 269822471224 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 269822471224 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 269822471224 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015403 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015403 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010972 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010972 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014266 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014266 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014266 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014266 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24156.422455 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24156.422455 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44144.524876 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44144.524876 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28097.744435 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28097.744435 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28097.744435 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28097.744435 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 7e4c9be17..5e225e744 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.041622 # Nu sim_ticks 41622221000 # Number of ticks simulated final_tick 41622221000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 156492 # Simulator instruction rate (inst/s) -host_op_rate 156492 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 70874179 # Simulator tick rate (ticks/s) -host_mem_usage 228076 # Number of bytes of host memory used -host_seconds 587.27 # Real time elapsed on the host +host_inst_rate 75517 # Simulator instruction rate (inst/s) +host_op_rate 75517 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34200879 # Simulator tick rate (ticks/s) +host_mem_usage 228092 # Number of bytes of host memory used +host_seconds 1216.99 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory @@ -78,28 +78,15 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 4938 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 3236 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1202 # What read queue length does an incoming req see +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 3235 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1203 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 433 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 23375922 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 122137172 # Sum of mem lat for all requests +system.physmem.totQLat 23405750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 122167000 # Sum of mem lat for all requests system.physmem.totBusLat 24690000 # Total cycles spent in databus access system.physmem.totBankLat 74071250 # Total cycles spent in bank access -system.physmem.avgQLat 4733.88 # Average queueing delay per request +system.physmem.avgQLat 4739.93 # Average queueing delay per request system.physmem.avgBankLat 15000.25 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24734.14 # Average memory access latency +system.physmem.avgMemAccLat 24740.18 # Average memory access latency system.physmem.avgRdBW 7.59 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 7.59 # Average consumed read bandwidth in MB/s @@ -288,12 +273,12 @@ system.cpu.stage4.idleCycles 29384711 # Nu system.cpu.stage4.runCycles 53859732 # Number of cycles 1+ instructions are processed. system.cpu.stage4.utilization 64.700694 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 7635 # number of replacements -system.cpu.icache.tagsinuse 1492.649363 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1492.649326 # Cycle average of tags in use system.cpu.icache.total_refs 9945578 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 9520 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1044.703571 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1492.649363 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1492.649326 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.728833 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.728833 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 9945578 # number of ReadReq hits @@ -308,12 +293,12 @@ system.cpu.icache.demand_misses::cpu.inst 11365 # n system.cpu.icache.demand_misses::total 11365 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 11365 # number of overall misses system.cpu.icache.overall_misses::total 11365 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 259189500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 259189500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 259189500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 259189500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 259189500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 259189500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 259175500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 259175500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 259175500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 259175500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 259175500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 259175500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 9956943 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 9956943 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 9956943 # number of demand (read+write) accesses @@ -326,12 +311,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001141 system.cpu.icache.demand_miss_rate::total 0.001141 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001141 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001141 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22805.939287 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22805.939287 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22805.939287 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22805.939287 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22805.939287 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22805.939287 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22804.707435 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22804.707435 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22804.707435 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22804.707435 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22804.707435 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22804.707435 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -352,34 +337,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 9520 system.cpu.icache.demand_mshr_misses::total 9520 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 9520 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 9520 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 209613500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 209613500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 209613500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 209613500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 209613500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 209613500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 209599500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 209599500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 209599500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 209599500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 209599500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 209599500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000956 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000956 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22018.224790 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22018.224790 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22018.224790 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22018.224790 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22018.224790 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22018.224790 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22016.754202 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22016.754202 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22016.754202 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22016.754202 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22016.754202 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22016.754202 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2190.263467 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2190.263404 # Cycle average of tags in use system.cpu.l2cache.total_refs 6793 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.069775 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 17.839012 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1821.325234 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 351.099221 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1821.325190 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 351.099202 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000544 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.055582 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.010715 # Average percentage of cache occupancy @@ -408,17 +393,17 @@ system.cpu.l2cache.demand_misses::total 4938 # nu system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4938 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 132557500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 132543500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 24069000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 156626500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84092000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 84092000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 132557500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 108161000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 240718500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 132557500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 108161000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 240718500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 156612500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84148000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 84148000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 132543500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 108217000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 240760500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 132543500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 108217000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 240760500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 9520 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 9995 # number of ReadReq accesses(hits+misses) @@ -443,17 +428,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.420506 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293487 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.420506 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47443.629205 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47438.618468 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57035.545024 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 48702.269900 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48833.914053 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48833.914053 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47443.629205 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50448.227612 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 48748.177400 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47443.629205 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50448.227612 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 48748.177400 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 48697.916667 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48866.434379 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48866.434379 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47438.618468 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50474.347015 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 48756.682868 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47438.618468 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50474.347015 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 48756.682868 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -473,17 +458,17 @@ system.cpu.l2cache.demand_mshr_misses::total 4938 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 97843336 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18812201 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 116655537 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63127136 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63127136 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97843336 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 81939337 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 179782673 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97843336 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 81939337 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 179782673 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 97826921 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18811852 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 116638773 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63182194 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63182194 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97826921 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 81994046 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 179820967 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97826921 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 81994046 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 179820967 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321761 # mshr miss rate for ReadReq accesses @@ -495,25 +480,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.420506 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.420506 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35019.089477 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44578.675355 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36273.487873 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36659.196283 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36659.196283 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35019.089477 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38217.974347 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36407.993722 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35019.089477 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38217.974347 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36407.993722 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35013.214388 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44577.848341 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36268.275187 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36691.169570 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36691.169570 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35013.214388 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38243.491604 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36415.748684 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35013.214388 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38243.491604 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36415.748684 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1441.801688 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1441.801521 # Cycle average of tags in use system.cpu.dcache.total_refs 26488625 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 11915.710751 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1441.801688 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 1441.801521 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.352002 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.352002 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 19995623 # number of ReadReq hits @@ -534,12 +519,12 @@ system.cpu.dcache.overall_misses::cpu.data 8676 # system.cpu.dcache.overall_misses::total 8676 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 31383500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 31383500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 345698500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 345698500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 377082000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 377082000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 377082000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 377082000 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 346048500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 346048500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 377432000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 377432000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 377432000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 377432000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -558,17 +543,17 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.000327 system.cpu.dcache.overall_miss_rate::total 0.000327 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54580 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 54580 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42673.558820 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42673.558820 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 43462.655602 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 43462.655602 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 43462.655602 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 43462.655602 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 13684 # number of cycles access was blocked +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42716.763363 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42716.763363 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 43502.996773 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 43502.996773 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 43502.996773 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 43502.996773 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 13712 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 822 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.647202 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.681265 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -592,12 +577,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 2223 system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25092500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 25092500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86109500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 86109500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 111202000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 111202000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 111202000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 111202000 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86165500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 86165500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 111258000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 111258000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 111258000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 111258000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -608,12 +593,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52826.315789 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52826.315789 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49261.727689 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49261.727689 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50023.391813 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 50023.391813 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50023.391813 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 50023.391813 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49293.764302 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49293.764302 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50048.582996 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 50048.582996 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50048.582996 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 50048.582996 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index c7256bad9..a102acf91 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.023427 # Nu sim_ticks 23426793000 # Number of ticks simulated final_tick 23426793000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 213464 # Simulator instruction rate (inst/s) -host_op_rate 213464 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59405864 # Simulator tick rate (ticks/s) -host_mem_usage 230136 # Number of bytes of host memory used -host_seconds 394.35 # Real time elapsed on the host +host_inst_rate 128339 # Simulator instruction rate (inst/s) +host_op_rate 128339 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35715987 # Simulator tick rate (ticks/s) +host_mem_usage 230140 # Number of bytes of host memory used +host_seconds 655.92 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 195968 # Number of bytes read from this memory @@ -78,28 +78,15 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 5228 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 3174 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1385 # What read queue length does an incoming req see +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 3175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1384 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 549 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 106 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 28657456 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 133887456 # Sum of mem lat for all requests +system.physmem.totQLat 28652250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 133882250 # Sum of mem lat for all requests system.physmem.totBusLat 26140000 # Total cycles spent in databus access system.physmem.totBankLat 79090000 # Total cycles spent in bank access -system.physmem.avgQLat 5481.53 # Average queueing delay per request +system.physmem.avgQLat 5480.54 # Average queueing delay per request system.physmem.avgBankLat 15128.16 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25609.69 # Average memory access latency +system.physmem.avgMemAccLat 25608.69 # Average memory access latency system.physmem.avgRdBW 14.28 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 14.28 # Average consumed read bandwidth in MB/s @@ -579,7 +564,7 @@ system.cpu.l2cache.sampled_refs 3590 # Sa system.cpu.l2cache.avg_refs 2.367688 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 17.668263 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2005.213140 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2005.213141 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 381.714191 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000539 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.061194 # Average percentage of cache occupancy @@ -674,17 +659,17 @@ system.cpu.l2cache.demand_mshr_misses::total 5228 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3062 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2166 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5228 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 106921693 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 23470923 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 130392616 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 65567754 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 65567754 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106921693 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 89038677 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 195960370 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106921693 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 89038677 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 195960370 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 106919101 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 23470588 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 130389689 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 65567128 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 65567128 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106919101 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 89037716 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 195956817 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106919101 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 89037716 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 195956817 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.266446 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.893411 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.293388 # mshr miss rate for ReadReq accesses @@ -696,17 +681,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.380523 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.266446 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963952 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.380523 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34918.906924 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50913.065076 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37011.812660 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38456.160704 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38456.160704 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34918.906924 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41107.422438 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37482.855777 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34918.906924 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41107.422438 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37482.855777 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34918.060418 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50912.338395 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37010.981834 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38455.793548 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38455.793548 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34918.060418 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41106.978763 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37482.176167 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34918.060418 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41106.978763 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37482.176167 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 159 # number of replacements system.cpu.dcache.tagsinuse 1459.874578 # Cycle average of tags in use diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 4d507d8ac..d2046c973 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.074156 # Nu sim_ticks 74155951500 # Number of ticks simulated final_tick 74155951500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 108940 # Simulator instruction rate (inst/s) -host_op_rate 119280 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46885764 # Simulator tick rate (ticks/s) -host_mem_usage 245224 # Number of bytes of host memory used -host_seconds 1581.63 # Real time elapsed on the host +host_inst_rate 102580 # Simulator instruction rate (inst/s) +host_op_rate 112316 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44148416 # Simulator tick rate (ticks/s) +host_mem_usage 245240 # Number of bytes of host memory used +host_seconds 1679.70 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 188656503 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 131776 # Number of bytes read from this memory @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 3811 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 2809 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 787 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 160 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 17813284 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 103885784 # Sum of mem lat for all requests +system.physmem.totQLat 17809500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 103882000 # Sum of mem lat for all requests system.physmem.totBusLat 19055000 # Total cycles spent in databus access system.physmem.totBankLat 67017500 # Total cycles spent in bank access -system.physmem.avgQLat 4674.18 # Average queueing delay per request +system.physmem.avgQLat 4673.18 # Average queueing delay per request system.physmem.avgBankLat 17585.28 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27259.46 # Average memory access latency +system.physmem.avgMemAccLat 27258.46 # Average memory access latency system.physmem.avgRdBW 3.29 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 3.29 # Average consumed read bandwidth in MB/s @@ -699,17 +684,17 @@ system.cpu.l2cache.demand_mshr_misses::total 3811 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2060 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1751 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3811 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 78131980 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 30985263 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 109117243 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 36314730 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 36314730 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 78131980 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 67299993 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 145431973 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 78131980 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67299993 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 145431973 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 78130246 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 30984758 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 109115004 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 36313866 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 36313866 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 78130246 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 67298624 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 145428870 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 78130246 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67298624 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 145428870 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.502439 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869845 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.560911 # mshr miss rate for ReadReq accesses @@ -721,17 +706,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.639322 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.502439 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.940892 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.639322 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37928.145631 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45904.093333 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39896.615356 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33749.749071 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33749.749071 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37928.145631 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38435.175899 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38161.105484 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37928.145631 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38435.175899 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38161.105484 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37927.303883 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45903.345185 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39895.796709 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33748.946097 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33748.946097 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37927.303883 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38434.394061 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38160.291262 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37927.303883 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38434.394061 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38160.291262 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 57 # number of replacements system.cpu.dcache.tagsinuse 1410.136977 # Cycle average of tags in use diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index ea454cb40..f1f025306 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.082836 # Nu sim_ticks 82836235000 # Number of ticks simulated final_tick 82836235000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72340 # Simulator instruction rate (inst/s) -host_op_rate 121249 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45372545 # Simulator tick rate (ticks/s) +host_inst_rate 70076 # Simulator instruction rate (inst/s) +host_op_rate 117454 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43952394 # Simulator tick rate (ticks/s) host_mem_usage 275820 # Number of bytes of host memory used -host_seconds 1825.69 # Real time elapsed on the host +host_seconds 1884.68 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221362961 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 218368 # Number of bytes read from this memory @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 5362 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 153 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 4169 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 943 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 199 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 15727084 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 132185834 # Sum of mem lat for all requests +system.physmem.totQLat 15721750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 132180500 # Sum of mem lat for all requests system.physmem.totBusLat 26795000 # Total cycles spent in databus access system.physmem.totBankLat 89663750 # Total cycles spent in bank access -system.physmem.avgQLat 2933.06 # Average queueing delay per request +system.physmem.avgQLat 2932.07 # Average queueing delay per request system.physmem.avgBankLat 16722.07 # Average bank access latency per request system.physmem.avgBusLat 4997.20 # Average bus latency per request -system.physmem.avgMemAccLat 24652.34 # Average memory access latency +system.physmem.avgMemAccLat 24651.34 # Average memory access latency system.physmem.avgRdBW 4.14 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 4.14 # Average consumed read bandwidth in MB/s @@ -648,19 +633,19 @@ system.cpu.l2cache.demand_mshr_misses::total 5362 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3413 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1949 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5362 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 121268321 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18645617 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 139913938 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 121265541 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18645311 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 139910852 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1530153 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1530153 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 49242500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 49242500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 121268321 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 67888117 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 189156438 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 121268321 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67888117 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 189156438 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 49241002 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 49241002 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 121265541 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 67886313 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 189151854 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 121265541 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67886313 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 189151854 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.496581 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.929245 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.521721 # mshr miss rate for ReadReq accesses @@ -674,19 +659,19 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.605260 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.496581 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.981370 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.605260 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35531.298271 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47323.901015 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36751.756764 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35530.483739 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47323.124365 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36750.946152 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31667.202572 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31667.202572 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35531.298271 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34832.281683 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35277.217083 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35531.298271 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34832.281683 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35277.217083 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31666.239228 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31666.239228 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35530.483739 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34831.356080 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35276.362178 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35530.483739 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34831.356080 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35276.362178 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 56 # number of replacements system.cpu.dcache.tagsinuse 1416.460930 # Cycle average of tags in use |