diff options
Diffstat (limited to 'tests/long/se')
28 files changed, 2880 insertions, 3428 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini index e8166ece0..cdddacd16 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini @@ -23,6 +23,7 @@ load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem +mmap_using_noreserve=false num_work_ids=16 readfile= symbolfile= @@ -167,6 +168,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +sys=system tlb=system.cpu.dtb [system.cpu.dstage2_mmu.stage2_tlb] @@ -184,7 +186,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[5] [system.cpu.dtb] type=ArmTLB @@ -661,6 +662,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +sys=system tlb=system.cpu.itb [system.cpu.istage2_mmu.stage2_tlb] @@ -678,7 +680,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB @@ -737,13 +738,16 @@ size=2097152 type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 -header_cycles=1 +forward_latency=0 +frontend_latency=1 +response_latency=1 snoop_filter=Null +snoop_response_latency=1 system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -759,9 +763,9 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf +executable=/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in kvmInSE=false max_stack_size=67108864 output=cout @@ -792,11 +796,14 @@ transition_latency=100000000 type=CoherentXBar clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=4 +frontend_latency=3 +response_latency=2 snoop_filter=Null +snoop_response_latency=4 system=system use_default_range=false -width=8 +width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side @@ -827,7 +834,7 @@ IDD62=0.000000 VDD=1.500000 VDD2=0.000000 activation_limit=4 -addr_mapping=RoRaBaChCo +addr_mapping=RoRaBaCoCh bank_groups_per_rank=0 banks_per_rank=8 burst_length=8 diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simerr b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simerr index 1a4f96712..e9c9539d6 100644..100755 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simerr +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simerr @@ -1 +1,2 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting gdb connections diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout index aed824289..be80117c3 100644..100755 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout @@ -1,14 +1,12 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 7 2014 10:57:46 -gem5 started May 7 2014 16:03:40 -gem5 executing on cz3211bhr8 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing +gem5 compiled Mar 15 2015 20:30:55 +gem5 started Mar 15 2015 20:31:14 +gem5 executing on zizzer2 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x11aa5150 + 0: system.cpu.isa: ISA system set to: 0 0x45a0240 info: Entering event queue @ 0. Starting simulation... MCF SPEC version 1.6.I @@ -26,4 +24,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 61276704500 because target called exit() +Exiting @ tick 61589191500 because target called exit() diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index 2c11d0b34..bce6e86b0 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.061593 # Number of seconds simulated -sim_ticks 61592600500 # Number of ticks simulated -final_tick 61592600500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.061589 # Number of seconds simulated +sim_ticks 61589191500 # Number of ticks simulated +final_tick 61589191500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 271325 # Simulator instruction rate (inst/s) -host_op_rate 272676 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 184448880 # Simulator tick rate (ticks/s) -host_mem_usage 445184 # Number of bytes of host memory used -host_seconds 333.93 # Real time elapsed on the host +host_inst_rate 169101 # Simulator instruction rate (inst/s) +host_op_rate 169943 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 114949938 # Simulator tick rate (ticks/s) +host_mem_usage 374724 # Number of bytes of host memory used +host_seconds 535.79 # Real time elapsed on the host sim_insts 90602849 # Number of instructions simulated sim_ops 91054080 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 49600 # Nu system.physmem.num_reads::cpu.inst 775 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory system.physmem.num_reads::total 15575 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 805292 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 15378471 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 16183762 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 805292 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 805292 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 805292 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 15378471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 16183762 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 805336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 15379322 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 16184658 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 805336 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 805336 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 805336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 15379322 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 16184658 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15575 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 15575 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 61592506000 # Total gap between requests +system.physmem.totGap 61589097000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1549 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 642.644287 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 437.986910 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 400.933627 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 248 16.01% 16.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 186 12.01% 28.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 90 5.81% 33.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 71 4.58% 38.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 77 4.97% 43.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 93 6.00% 49.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 43 2.78% 52.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 36 2.32% 54.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 705 45.51% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1549 # Bytes accessed per row activation -system.physmem.totQLat 77242000 # Total ticks spent queuing -system.physmem.totMemAccLat 369273250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1548 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 642.728682 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 437.613794 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 401.141843 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 250 16.15% 16.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 184 11.89% 28.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 91 5.88% 33.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 69 4.46% 38.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 77 4.97% 43.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 93 6.01% 49.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 43 2.78% 52.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 36 2.33% 54.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 705 45.54% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1548 # Bytes accessed per row activation +system.physmem.totQLat 76265750 # Total ticks spent queuing +system.physmem.totMemAccLat 368297000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 77875000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4959.36 # Average queueing delay per DRAM burst +system.physmem.avgQLat 4896.68 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23709.36 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 23646.68 # Average memory access latency per DRAM burst system.physmem.avgRdBW 16.18 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 16.18 # Average system read bandwidth in MiByte/s @@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.13 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 14018 # Number of row buffer hits during reads +system.physmem.readRowHits 14017 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 90.00 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 3954575.02 # Average gap between requests +system.physmem.avgGap 3954356.15 # Average gap between requests system.physmem.pageHitRate 90.00 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6373080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3477375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 63718200 # Energy for read commands per rank (pJ) +system.physmem_0.actEnergy 6365520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3473250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 63663600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2539008855 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34726497750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41361784860 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.572046 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 57760380750 # Time in different power states -system.physmem_0.memoryStateTime::REF 2056600000 # Time in different power states +system.physmem_0.refreshEnergy 4022201040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2552305815 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34710162000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41358171225 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.598278 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57736612750 # Time in different power states +system.physmem_0.memoryStateTime::REF 2056340000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1772530500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1792195250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 5329800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2908125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 57478200 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 5322240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2904000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2571546735 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 34697955750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41357928210 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.509428 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57713961000 # Time in different power states -system.physmem_1.memoryStateTime::REF 2056600000 # Time in different power states +system.physmem_1.refreshEnergy 4022201040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2572075980 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 34692811500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41352777360 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.510839 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57709022500 # Time in different power states +system.physmem_1.memoryStateTime::REF 2056340000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1819631500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1820633500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 20789446 # Number of BP lookups -system.cpu.branchPred.condPredicted 17091418 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 765966 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8973614 # Number of BTB lookups -system.cpu.branchPred.BTBHits 8867024 # Number of BTB hits +system.cpu.branchPred.lookups 20789992 # Number of BP lookups +system.cpu.branchPred.condPredicted 17092121 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 765794 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8976081 # Number of BTB lookups +system.cpu.branchPred.BTBHits 8866607 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.812184 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 62715 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 98.780381 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 62695 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -377,89 +377,97 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 123185201 # number of cpu cycles simulated +system.cpu.numCycles 123178383 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90602849 # Number of instructions committed system.cpu.committedOps 91054080 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2068247 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2068275 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.359617 # CPI: cycles per instruction -system.cpu.ipc 0.735501 # IPC: instructions per cycle -system.cpu.tickCycles 109827605 # Number of cycles that the object actually ticked -system.cpu.idleCycles 13357596 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.359542 # CPI: cycles per instruction +system.cpu.ipc 0.735542 # IPC: instructions per cycle +system.cpu.tickCycles 109824698 # Number of cycles that the object actually ticked +system.cpu.idleCycles 13353685 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 946107 # number of replacements -system.cpu.dcache.tags.tagsinuse 3616.143974 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26267423 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3616.117477 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26267654 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 950203 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 27.644012 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 27.644255 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 20661192250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3616.143974 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.882848 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.882848 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3616.117477 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.882841 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.882841 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 252 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2247 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1597 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 260 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2243 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1593 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 55463259 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 55463259 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21598839 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21598839 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4660810 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4660810 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 55463725 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 55463725 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21598560 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21598560 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4660812 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4660812 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 26259649 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26259649 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26259649 # number of overall hits -system.cpu.dcache.overall_hits::total 26259649 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 26259372 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26259372 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26259880 # number of overall hits +system.cpu.dcache.overall_hits::total 26259880 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 914934 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 914934 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 74171 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 74171 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 989105 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 989105 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 989105 # number of overall misses -system.cpu.dcache.overall_misses::total 989105 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11918412494 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11918412494 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2568231500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2568231500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14486643994 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14486643994 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14486643994 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14486643994 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22513773 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22513773 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 74169 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 74169 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 989103 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 989103 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 989107 # number of overall misses +system.cpu.dcache.overall_misses::total 989107 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11918328994 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11918328994 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2566867500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2566867500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14485196494 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14485196494 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14485196494 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14485196494 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22513494 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22513494 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 512 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 27248754 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 27248754 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 27248754 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 27248754 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 27248475 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 27248475 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 27248987 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 27248987 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040639 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.040639 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015664 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.015664 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.036299 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.036299 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.036299 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.036299 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13026.527043 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13026.527043 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34625.817368 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34625.817368 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14646.214501 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14646.214501 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14646.214501 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14646.214501 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13026.435780 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13026.435780 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34608.360636 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34608.360636 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14644.780669 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14644.780669 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14644.721445 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14644.721445 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -468,101 +476,109 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 943286 # number of writebacks -system.cpu.dcache.writebacks::total 943286 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11499 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 11499 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27403 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 27403 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 38902 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 38902 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 38902 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 38902 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903435 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 903435 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46768 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 46768 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 950203 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 950203 # number of demand (read+write) MSHR misses +system.cpu.dcache.writebacks::writebacks 943285 # number of writebacks +system.cpu.dcache.writebacks::total 943285 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11501 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 11501 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27402 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 27402 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 38903 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 38903 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 38903 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 38903 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903433 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 903433 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46767 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 46767 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 950200 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 950200 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 950203 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 950203 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10413322256 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10413322256 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1464464500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1464464500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11877786756 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11877786756 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11877786756 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11877786756 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040128 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040128 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10413180006 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10413180006 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1463830500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1463830500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 155500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 155500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11877010506 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11877010506 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11877166006 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11877166006 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040129 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040129 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009877 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009877 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.034871 # mshr miss rate for demand accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005859 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005859 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034872 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.034872 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034871 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11526.365766 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11526.365766 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31313.387359 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31313.387359 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12500.262319 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12500.262319 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12500.262319 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12500.262319 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11526.233828 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11526.233828 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31300.500353 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31300.500353 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 51833.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 51833.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12499.484852 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12499.484852 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12499.609037 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12499.609037 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 5 # number of replacements -system.cpu.icache.tags.tagsinuse 690.370829 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27857028 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 690.367878 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27855563 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 803 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 34691.193026 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 34689.368618 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 690.370829 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.337095 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.337095 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 690.367878 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.337094 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.337094 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 55716465 # Number of tag accesses -system.cpu.icache.tags.data_accesses 55716465 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 27857028 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27857028 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27857028 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27857028 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27857028 # number of overall hits -system.cpu.icache.overall_hits::total 27857028 # number of overall hits +system.cpu.icache.tags.tag_accesses 55713535 # Number of tag accesses +system.cpu.icache.tags.data_accesses 55713535 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 27855563 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27855563 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27855563 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27855563 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27855563 # number of overall hits +system.cpu.icache.overall_hits::total 27855563 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 803 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 803 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 803 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 803 # number of overall misses system.cpu.icache.overall_misses::total 803 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 61138997 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 61138997 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 61138997 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 61138997 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 61138997 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 61138997 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27857831 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27857831 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27857831 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27857831 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27857831 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27857831 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 60778747 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 60778747 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 60778747 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 60778747 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 60778747 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 60778747 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27856366 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27856366 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27856366 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27856366 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27856366 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27856366 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76138.227895 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 76138.227895 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 76138.227895 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 76138.227895 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 76138.227895 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 76138.227895 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75689.597758 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75689.597758 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75689.597758 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75689.597758 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75689.597758 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75689.597758 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -577,38 +593,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 803 system.cpu.icache.demand_mshr_misses::total 803 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 803 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59598503 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 59598503 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59598503 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 59598503 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59598503 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 59598503 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59238753 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 59238753 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59238753 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 59238753 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59238753 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 59238753 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74219.804483 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74219.804483 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74219.804483 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 74219.804483 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74219.804483 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 74219.804483 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73771.797011 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73771.797011 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73771.797011 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 73771.797011 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73771.797011 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 73771.797011 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10238.643668 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 10238.331530 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1831333 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15558 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 117.710053 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9347.860585 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 675.375683 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 215.407400 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.285274 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 9347.552494 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 675.372759 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 215.406276 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.285265 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020611 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.006574 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.312459 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.312449 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 15558 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id @@ -616,15 +632,15 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13878 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474792 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 15216662 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 15216662 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 15216653 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 15216653 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 25 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 903173 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 903198 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 943286 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 943286 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 32224 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 32224 # number of ReadExReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 903174 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 903199 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 943285 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 943285 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 32223 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 32223 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 25 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 935397 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 935422 # number of demand (read+write) hits @@ -642,24 +658,24 @@ system.cpu.l2cache.demand_misses::total 15584 # nu system.cpu.l2cache.overall_misses::cpu.inst 778 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14806 # number of overall misses system.cpu.l2cache.overall_misses::total 15584 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 58533000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22267750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 80800750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1073909000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1073909000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 58533000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1096176750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1154709750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 58533000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1096176750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1154709750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 58173250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22267000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 80440250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1073291000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1073291000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 58173250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1095558000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1153731250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 58173250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1095558000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1153731250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 803 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 903435 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 904238 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 943286 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 943286 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 46768 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 46768 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 903436 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 904239 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 943285 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 943285 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 46767 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 46767 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 803 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 950203 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 951006 # number of demand (read+write) accesses @@ -669,25 +685,25 @@ system.cpu.l2cache.overall_accesses::total 951006 # system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.968867 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000290 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.001150 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.310982 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.310982 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.310989 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.310989 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.968867 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.015582 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.016387 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.968867 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016387 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75235.218509 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84991.412214 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 77693.028846 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73838.627613 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73838.627613 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75235.218509 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74035.982034 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74095.851514 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75235.218509 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74035.982034 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74095.851514 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74772.814910 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84988.549618 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 77346.394231 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73796.135864 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73796.135864 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74772.814910 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73994.191544 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74033.062757 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74772.814910 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73994.191544 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74033.062757 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -716,70 +732,70 @@ system.cpu.l2cache.demand_mshr_misses::total 15575 system.cpu.l2cache.overall_mshr_misses::cpu.inst 775 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15575 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 48659000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18669250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 67328250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 892098500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 892098500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48659000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 910767750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 959426750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48659000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 910767750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 959426750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 48299750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18668000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 66967750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 891481000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 891481000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48299750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 910149000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 958448750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48299750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 910149000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 958448750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000283 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001140 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.310982 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.310982 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.310989 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.310989 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62785.806452 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72926.757812 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65303.831232 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61337.905666 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61337.905666 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62785.806452 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61538.361486 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61600.433387 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62785.806452 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61538.361486 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61600.433387 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62322.258065 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72921.875000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64954.170708 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61295.448295 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61295.448295 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62322.258065 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61496.554054 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61537.640449 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62322.258065 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61496.554054 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61537.640449 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 904238 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 904238 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 943286 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 46768 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 46768 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 904239 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 904239 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 943285 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 46767 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 46767 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1606 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843692 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2845298 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843691 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2845297 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121183296 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 121234688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121183232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 121234624 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1894292 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1894291 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 1894292 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 1894291 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1894292 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1890432000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1894291 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1890430500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1372497 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1372247 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1428682244 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1428681994 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) system.membus.trans_dist::ReadReq 1031 # Transaction distribution system.membus.trans_dist::ReadResp 1031 # Transaction distribution @@ -800,7 +816,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 15575 # Request fanout histogram -system.membus.reqLayer0.occupancy 21632500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 21630500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 82148250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini index 452217687..e9edac26f 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini @@ -23,6 +23,7 @@ load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem +mmap_using_noreserve=false num_work_ids=16 readfile= symbolfile= @@ -167,6 +168,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +sys=system tlb=system.cpu.dtb [system.cpu.dstage2_mmu.stage2_tlb] @@ -184,7 +186,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[5] [system.cpu.dtb] type=ArmTLB @@ -661,6 +662,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +sys=system tlb=system.cpu.itb [system.cpu.istage2_mmu.stage2_tlb] @@ -678,7 +680,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB @@ -737,13 +738,16 @@ size=2097152 type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 -header_cycles=1 +forward_latency=0 +frontend_latency=1 +response_latency=1 snoop_filter=Null +snoop_response_latency=1 system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -759,9 +763,9 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser +executable=/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in kvmInSE=false max_stack_size=67108864 output=cout @@ -792,11 +796,14 @@ transition_latency=100000000 type=CoherentXBar clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=4 +frontend_latency=3 +response_latency=2 snoop_filter=Null +snoop_response_latency=4 system=system use_default_range=false -width=8 +width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side @@ -827,7 +834,7 @@ IDD62=0.000000 VDD=1.500000 VDD2=0.000000 activation_limit=4 -addr_mapping=RoRaBaChCo +addr_mapping=RoRaBaCoCh bank_groups_per_rank=0 banks_per_rank=8 burst_length=8 diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/minor-timing/simerr index 5d8946ede..be90b0340 100644..100755 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/simerr +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/simerr @@ -1,2 +1,3 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4] diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout b/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout index 7e896fb1e..83790a04a 100644..100755 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout @@ -1,14 +1,12 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 7 2014 10:57:46 -gem5 started May 7 2014 15:30:22 -gem5 executing on cz3211bhr8 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing +gem5 compiled Mar 15 2015 20:30:55 +gem5 started Mar 15 2015 20:31:14 +gem5 executing on zizzer2 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x1e6be7a0 + 0: system.cpu.isa: ISA system set to: 0 0x3275620 info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: ************************************************* @@ -70,4 +68,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 377875396500 because target called exit() +Exiting @ tick 366358475500 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 8128561b2..409fcf8a5 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.366359 # Number of seconds simulated -sim_ticks 366358704500 # Number of ticks simulated -final_tick 366358704500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.366358 # Number of seconds simulated +sim_ticks 366358475500 # Number of ticks simulated +final_tick 366358475500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 242855 # Simulator instruction rate (inst/s) -host_op_rate 263044 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 175631724 # Simulator tick rate (ticks/s) -host_mem_usage 316616 # Number of bytes of host memory used -host_seconds 2085.95 # Real time elapsed on the host +host_inst_rate 156500 # Simulator instruction rate (inst/s) +host_op_rate 169511 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 113180486 # Simulator tick rate (ticks/s) +host_mem_usage 245616 # Number of bytes of host memory used +host_seconds 3236.94 # Real time elapsed on the host sim_insts 506582155 # Number of instructions simulated sim_ops 548695378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 221696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9006016 # Number of bytes read from this memory -system.physmem.bytes_read::total 9227712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9004224 # Number of bytes read from this memory +system.physmem.bytes_read::total 9225920 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 221696 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 221696 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6179648 # Number of bytes written to this memory -system.physmem.bytes_written::total 6179648 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 6180352 # Number of bytes written to this memory +system.physmem.bytes_written::total 6180352 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 3464 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140719 # Number of read requests responded to by this memory -system.physmem.num_reads::total 144183 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 96557 # Number of write requests responded to by this memory -system.physmem.num_writes::total 96557 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.data 140691 # Number of read requests responded to by this memory +system.physmem.num_reads::total 144155 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96568 # Number of write requests responded to by this memory +system.physmem.num_writes::total 96568 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 605134 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 24582509 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25187642 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 24577633 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25182767 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 605134 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 605134 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 16867753 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 16867753 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 16867753 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 16869685 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 16869685 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 16869685 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 605134 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 24582509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42055395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 144183 # Number of read requests accepted -system.physmem.writeReqs 96557 # Number of write requests accepted -system.physmem.readBursts 144183 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 96557 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9220288 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7424 # Total number of bytes read from write queue -system.physmem.bytesWritten 6178496 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9227712 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6179648 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 116 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu.data 24577633 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42052451 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 144155 # Number of read requests accepted +system.physmem.writeReqs 96568 # Number of write requests accepted +system.physmem.readBursts 144155 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 96568 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9218240 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue +system.physmem.bytesWritten 6178944 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9225920 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6180352 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9347 # Per bank write bursts -system.physmem.perBankRdBursts::1 9007 # Per bank write bursts -system.physmem.perBankRdBursts::2 8992 # Per bank write bursts -system.physmem.perBankRdBursts::3 8698 # Per bank write bursts -system.physmem.perBankRdBursts::4 9455 # Per bank write bursts +system.physmem.perBankRdBursts::0 9365 # Per bank write bursts +system.physmem.perBankRdBursts::1 8967 # Per bank write bursts +system.physmem.perBankRdBursts::2 8978 # Per bank write bursts +system.physmem.perBankRdBursts::3 8700 # Per bank write bursts +system.physmem.perBankRdBursts::4 9448 # Per bank write bursts system.physmem.perBankRdBursts::5 9342 # Per bank write bursts -system.physmem.perBankRdBursts::6 8946 # Per bank write bursts -system.physmem.perBankRdBursts::7 8102 # Per bank write bursts -system.physmem.perBankRdBursts::8 8570 # Per bank write bursts +system.physmem.perBankRdBursts::6 8938 # Per bank write bursts +system.physmem.perBankRdBursts::7 8105 # Per bank write bursts +system.physmem.perBankRdBursts::8 8575 # Per bank write bursts system.physmem.perBankRdBursts::9 8679 # Per bank write bursts -system.physmem.perBankRdBursts::10 8773 # Per bank write bursts -system.physmem.perBankRdBursts::11 9476 # Per bank write bursts -system.physmem.perBankRdBursts::12 9374 # Per bank write bursts -system.physmem.perBankRdBursts::13 9521 # Per bank write bursts -system.physmem.perBankRdBursts::14 8712 # Per bank write bursts -system.physmem.perBankRdBursts::15 9073 # Per bank write bursts -system.physmem.perBankWrBursts::0 6191 # Per bank write bursts -system.physmem.perBankWrBursts::1 6098 # Per bank write bursts +system.physmem.perBankRdBursts::10 8775 # Per bank write bursts +system.physmem.perBankRdBursts::11 9474 # Per bank write bursts +system.physmem.perBankRdBursts::12 9378 # Per bank write bursts +system.physmem.perBankRdBursts::13 9522 # Per bank write bursts +system.physmem.perBankRdBursts::14 8708 # Per bank write bursts +system.physmem.perBankRdBursts::15 9081 # Per bank write bursts +system.physmem.perBankWrBursts::0 6205 # Per bank write bursts +system.physmem.perBankWrBursts::1 6092 # Per bank write bursts system.physmem.perBankWrBursts::2 6005 # Per bank write bursts -system.physmem.perBankWrBursts::3 5815 # Per bank write bursts -system.physmem.perBankWrBursts::4 6163 # Per bank write bursts +system.physmem.perBankWrBursts::3 5814 # Per bank write bursts +system.physmem.perBankWrBursts::4 6161 # Per bank write bursts system.physmem.perBankWrBursts::5 6174 # Per bank write bursts -system.physmem.perBankWrBursts::6 6014 # Per bank write bursts -system.physmem.perBankWrBursts::7 5494 # Per bank write bursts -system.physmem.perBankWrBursts::8 5727 # Per bank write bursts +system.physmem.perBankWrBursts::6 6015 # Per bank write bursts +system.physmem.perBankWrBursts::7 5497 # Per bank write bursts +system.physmem.perBankWrBursts::8 5724 # Per bank write bursts system.physmem.perBankWrBursts::9 5822 # Per bank write bursts system.physmem.perBankWrBursts::10 5961 # Per bank write bursts -system.physmem.perBankWrBursts::11 6445 # Per bank write bursts -system.physmem.perBankWrBursts::12 6308 # Per bank write bursts +system.physmem.perBankWrBursts::11 6444 # Per bank write bursts +system.physmem.perBankWrBursts::12 6310 # Per bank write bursts system.physmem.perBankWrBursts::13 6277 # Per bank write bursts -system.physmem.perBankWrBursts::14 5998 # Per bank write bursts -system.physmem.perBankWrBursts::15 6047 # Per bank write bursts +system.physmem.perBankWrBursts::14 5996 # Per bank write bursts +system.physmem.perBankWrBursts::15 6049 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 366358675500 # Total gap between requests +system.physmem.totGap 366358446500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 144183 # Read request sizes (log2) +system.physmem.readPktSize::6 144155 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 96557 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 143693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 352 # What read queue length does an incoming req see +system.physmem.writePktSize::6 96568 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 143662 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 351 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,26 +144,26 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2930 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5660 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 5642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5579 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 3 # What write queue length does an incoming req see @@ -193,34 +193,34 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65205 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 236.159558 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 156.546491 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 241.906067 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24752 37.96% 37.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18185 27.89% 65.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7019 10.76% 76.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7903 12.12% 88.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2061 3.16% 91.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1167 1.79% 93.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 745 1.14% 94.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 604 0.93% 95.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 2769 4.25% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65205 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5568 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.873563 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 382.195910 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5565 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 65262 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 235.919953 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 156.506308 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 241.385533 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24794 37.99% 37.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18171 27.84% 65.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7030 10.77% 76.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7953 12.19% 88.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2052 3.14% 91.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1171 1.79% 93.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 739 1.13% 94.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 589 0.90% 95.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2763 4.23% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65262 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5572 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.848887 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 382.035418 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5569 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 2 0.04% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5568 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5568 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.338182 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.234627 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.449204 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 2631 47.25% 47.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 2778 49.89% 97.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 61 1.10% 98.24% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5572 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5572 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.326992 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.223724 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.446858 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 2657 47.68% 47.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 2761 49.55% 97.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 56 1.01% 98.24% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::22-23 29 0.52% 98.76% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24-25 20 0.36% 99.12% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::26-27 10 0.18% 99.30% # Writes before turning the bus around for reads @@ -239,66 +239,66 @@ system.physmem.wrPerTurnAround::58-59 1 0.02% 99.95% # Wr system.physmem.wrPerTurnAround::60-61 1 0.02% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::72-73 1 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::78-79 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5568 # Writes before turning the bus around for reads -system.physmem.totQLat 1536843000 # Total ticks spent queuing -system.physmem.totMemAccLat 4238099250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 720335000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10667.56 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 5572 # Writes before turning the bus around for reads +system.physmem.totQLat 1537104750 # Total ticks spent queuing +system.physmem.totMemAccLat 4237761000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 720175000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10671.74 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29417.56 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 25.17 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 16.86 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 25.19 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29421.74 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 25.16 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 16.87 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 25.18 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 16.87 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.33 # Data bus utilization in percentage system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.79 # Average write queue length when enqueuing -system.physmem.readRowHits 110982 # Number of row buffer hits during reads -system.physmem.writeRowHits 64419 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.03 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.72 # Row buffer hit rate for writes -system.physmem.avgGap 1521802.26 # Average gap between requests -system.physmem.pageHitRate 72.89 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 248111640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 135378375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 560734200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 310741920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 23928765120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 47516601060 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 178134108000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 250834440315 # Total energy per rank (pJ) -system.physmem_0.averagePower 684.668623 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 296034178750 # Time in different power states +system.physmem.avgWrQLen 20.57 # Average write queue length when enqueuing +system.physmem.readRowHits 110916 # Number of row buffer hits during reads +system.physmem.writeRowHits 64397 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.01 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.69 # Row buffer hit rate for writes +system.physmem.avgGap 1521908.78 # Average gap between requests +system.physmem.pageHitRate 72.86 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 248466960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 135572250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 560157000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 310566960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 23928256560 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 47486087820 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 178156194000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 250825301550 # Total energy per rank (pJ) +system.physmem_0.averagePower 684.658255 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 296072654000 # Time in different power states system.physmem_0.memoryStateTime::REF 12233260000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 58091210000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 58046909500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 244838160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 133592250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 562988400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 314830800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 23928765120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 46994125095 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 178592423250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 250771563075 # Total energy per rank (pJ) -system.physmem_1.averagePower 684.496987 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 296797282750 # Time in different power states +system.physmem_1.actEnergy 244634040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 133480875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 562879200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 314740080 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 23928256560 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 47146698135 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 178453904250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 250784593140 # Total energy per rank (pJ) +system.physmem_1.averagePower 684.547137 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 296568978750 # Time in different power states system.physmem_1.memoryStateTime::REF 12233260000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 57328110000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 57550826250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 132587783 # Number of BP lookups -system.cpu.branchPred.condPredicted 98513206 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6558220 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 68845364 # Number of BTB lookups -system.cpu.branchPred.BTBHits 64852055 # Number of BTB hits +system.cpu.branchPred.lookups 132589371 # Number of BP lookups +system.cpu.branchPred.condPredicted 98514041 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6557944 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 68842060 # Number of BTB lookups +system.cpu.branchPred.BTBHits 64854431 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.199596 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 10016928 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 17846 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.207569 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 10017867 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 17926 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -417,24 +417,24 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 732717409 # number of cpu cycles simulated +system.cpu.numCycles 732716951 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 506582155 # Number of instructions committed system.cpu.committedOps 548695378 # Number of ops (including micro ops) committed -system.cpu.discardedOps 13466110 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 13466923 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.446394 # CPI: cycles per instruction +system.cpu.cpi 1.446393 # CPI: cycles per instruction system.cpu.ipc 0.691375 # IPC: instructions per cycle -system.cpu.tickCycles 695820940 # Number of cycles that the object actually ticked -system.cpu.idleCycles 36896469 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1139887 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.954708 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 171283476 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1143983 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 149.725543 # Average number of references to valid blocks. +system.cpu.tickCycles 695825303 # Number of cycles that the object actually ticked +system.cpu.idleCycles 36891648 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1139854 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.954710 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 171283379 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1143950 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 149.729778 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 4900143250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.954708 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.954710 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.993885 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.993885 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -443,64 +443,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 system.cpu.dcache.tags.age_task_id_blocks_1024::2 545 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 3507 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 346821767 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 346821767 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 114767712 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114767712 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 53538682 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53538682 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 346821558 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 346821558 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114764882 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114764882 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 53538642 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53538642 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2773 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2773 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168306394 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168306394 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168306394 # number of overall hits -system.cpu.dcache.overall_hits::total 168306394 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 854792 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 854792 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 700624 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 700624 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1555416 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1555416 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1555416 # number of overall misses -system.cpu.dcache.overall_misses::total 1555416 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14024046732 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14024046732 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22031424000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22031424000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 36055470732 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 36055470732 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 36055470732 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 36055470732 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 115622504 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 115622504 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 168303524 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168303524 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168306297 # number of overall hits +system.cpu.dcache.overall_hits::total 168306297 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 854741 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 854741 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 700664 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 700664 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 20 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 20 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1555405 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1555405 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1555425 # number of overall misses +system.cpu.dcache.overall_misses::total 1555425 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14025846982 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14025846982 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22027401500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22027401500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 36053248482 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 36053248482 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 36053248482 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 36053248482 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 115619623 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 115619623 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2793 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2793 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 169861810 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 169861810 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 169861810 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 169861810 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 169858929 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 169858929 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 169861722 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 169861722 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007393 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.007393 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012917 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.012917 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012918 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.012918 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007161 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.007161 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.009157 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.009157 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.009157 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.009157 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16406.385100 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16406.385100 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31445.431501 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31445.431501 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23180.596530 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23180.596530 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23180.596530 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23180.596530 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16409.470216 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16409.470216 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31437.895339 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31437.895339 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23179.331738 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23179.331738 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23179.033693 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23179.033693 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -509,103 +517,111 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1068568 # number of writebacks -system.cpu.dcache.writebacks::total 1068568 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66956 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 66956 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344477 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 344477 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 411433 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 411433 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 411433 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 411433 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787836 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 787836 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356147 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 356147 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1143983 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1143983 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1143983 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1143983 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11930645015 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11930645015 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10967643750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10967643750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22898288765 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 22898288765 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22898288765 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22898288765 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006814 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006814 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006566 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006566 # mshr miss rate for WriteReq accesses +system.cpu.dcache.writebacks::writebacks 1068578 # number of writebacks +system.cpu.dcache.writebacks::total 1068578 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66974 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 66974 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344497 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 344497 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 411471 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 411471 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 411471 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 411471 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787767 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 787767 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356167 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 356167 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 16 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 16 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1143934 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1143934 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1143950 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1143950 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11930687015 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11930687015 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10965407750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10965407750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1449000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1449000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22896094765 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 22896094765 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22897543765 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22897543765 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006813 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006813 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006567 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006567 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005729 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005729 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006735 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006735 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006735 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006735 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15143.564162 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15143.564162 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30795.272037 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30795.272037 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20016.284127 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20016.284127 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20016.284127 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20016.284127 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15144.943892 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15144.943892 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30787.264822 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30787.264822 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 90562.500000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 90562.500000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20015.223575 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20015.223575 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20016.210293 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20016.210293 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 17670 # number of replacements -system.cpu.icache.tags.tagsinuse 1190.214047 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 200949213 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 19542 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10282.939975 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 17681 # number of replacements +system.cpu.icache.tags.tagsinuse 1190.210021 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 200953825 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 19553 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10277.390937 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1190.214047 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.581159 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.581159 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1190.210021 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.581157 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.581157 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 303 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1405 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 298 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1410 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 401957052 # Number of tag accesses -system.cpu.icache.tags.data_accesses 401957052 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 200949213 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 200949213 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 200949213 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 200949213 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 200949213 # number of overall hits -system.cpu.icache.overall_hits::total 200949213 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 19542 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 19542 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 19542 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 19542 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 19542 # number of overall misses -system.cpu.icache.overall_misses::total 19542 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 494400997 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 494400997 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 494400997 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 494400997 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 494400997 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 494400997 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 200968755 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 200968755 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 200968755 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 200968755 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 200968755 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 200968755 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 401966309 # Number of tag accesses +system.cpu.icache.tags.data_accesses 401966309 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 200953825 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 200953825 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 200953825 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 200953825 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 200953825 # number of overall hits +system.cpu.icache.overall_hits::total 200953825 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 19553 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 19553 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 19553 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 19553 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 19553 # number of overall misses +system.cpu.icache.overall_misses::total 19553 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 493452495 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 493452495 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 493452495 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 493452495 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 493452495 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 493452495 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 200973378 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 200973378 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 200973378 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 200973378 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 200973378 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 200973378 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000097 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000097 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000097 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000097 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000097 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000097 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25299.406253 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25299.406253 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25299.406253 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25299.406253 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25299.406253 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25299.406253 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25236.664195 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25236.664195 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25236.664195 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25236.664195 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25236.664195 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25236.664195 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -614,122 +630,122 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19542 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 19542 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 19542 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 19542 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 19542 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 19542 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 463701003 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 463701003 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 463701003 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 463701003 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 463701003 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 463701003 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19553 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 19553 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 19553 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 19553 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 19553 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 19553 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 462727005 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 462727005 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 462727005 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 462727005 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 462727005 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 462727005 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000097 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000097 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000097 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23728.431225 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23728.431225 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23728.431225 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 23728.431225 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23728.431225 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 23728.431225 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23665.269012 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23665.269012 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23665.269012 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 23665.269012 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23665.269012 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 23665.269012 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 111429 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27648.762381 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1684764 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 142617 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 11.813206 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 111401 # number of replacements +system.cpu.l2cache.tags.tagsinuse 27648.660571 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1684556 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 142587 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 11.814233 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 163811788500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23520.899956 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 390.576322 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3737.286102 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.717801 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011919 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.114053 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.843773 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31188 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 23520.663233 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 390.227273 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3737.770065 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.717794 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011909 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.114068 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.843770 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 31186 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 321 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4941 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25858 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951782 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 18355761 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 18355761 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 16076 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 747713 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 763789 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1068568 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1068568 # number of Writeback hits +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4927 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25871 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951721 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 18355652 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 18355652 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 16087 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 747708 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 763795 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1068578 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1068578 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 255536 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 255536 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 16076 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1003249 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1019325 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 16076 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1003249 # number of overall hits -system.cpu.l2cache.overall_hits::total 1019325 # number of overall hits +system.cpu.l2cache.demand_hits::cpu.inst 16087 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1003244 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1019331 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 16087 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1003244 # number of overall hits +system.cpu.l2cache.overall_hits::total 1019331 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 3466 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 39870 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 43336 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 100864 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 100864 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 39825 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 43291 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 100881 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 100881 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 3466 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 140734 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 144200 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 140706 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 144172 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 3466 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 140734 # number of overall misses -system.cpu.l2cache.overall_misses::total 144200 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 275297000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3285022000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 3560319000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7930866750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7930866750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 275297000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11215888750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 11491185750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 275297000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11215888750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 11491185750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 19542 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 787583 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 807125 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1068568 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1068568 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 356400 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 356400 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 19542 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1143983 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1163525 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 19542 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1143983 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1163525 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.177362 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.050623 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.053692 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283008 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.283008 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.177362 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.123021 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.123934 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.177362 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.123021 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.123934 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79427.870744 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82393.328317 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 82156.151929 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78629.310259 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78629.310259 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79427.870744 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79695.658121 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 79689.221567 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79427.870744 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79695.658121 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 79689.221567 # average overall miss latency +system.cpu.l2cache.overall_misses::cpu.data 140706 # number of overall misses +system.cpu.l2cache.overall_misses::total 144172 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 274192500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3286653000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 3560845500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7928578250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7928578250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 274192500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11215231250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 11489423750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 274192500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11215231250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 11489423750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 19553 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 787533 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 807086 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1068578 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1068578 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 356417 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 356417 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 19553 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1143950 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1163503 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 19553 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1143950 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1163503 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.177262 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.050569 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.053639 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283042 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.283042 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.177262 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.123000 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.123912 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.177262 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.123000 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.123912 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79109.203693 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82527.382298 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 82253.713243 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78593.374867 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78593.374867 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79109.203693 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79706.844413 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79692.476695 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79109.203693 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79706.844413 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79692.476695 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -738,8 +754,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 96557 # number of writebacks -system.cpu.l2cache.writebacks::total 96557 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 96568 # number of writebacks +system.cpu.l2cache.writebacks::total 96568 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 15 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits @@ -750,104 +766,104 @@ system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 system.cpu.l2cache.overall_mshr_hits::cpu.data 15 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3464 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 39855 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 43319 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100864 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 100864 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 39810 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 43274 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100881 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 100881 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 3464 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 140719 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 144183 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 140691 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 144155 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 3464 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 140719 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 144183 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 231582500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2784547250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3016129750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6669444250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6669444250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 231582500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9453991500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9685574000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 231582500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9453991500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9685574000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.177259 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.050604 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053671 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283008 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283008 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.177259 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123008 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123919 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.177259 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123008 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123919 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66854.070439 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69866.948940 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69626.024377 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66123.138583 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66123.138583 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66854.070439 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67183.475579 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67175.561613 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66854.070439 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67183.475579 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67175.561613 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.data 140691 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 144155 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 230478500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2786732250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3017210750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6666945750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6666945750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 230478500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9453678000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9684156500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 230478500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9453678000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9684156500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.177160 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.050550 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053618 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283042 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283042 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.177160 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122987 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123897 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.177160 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122987 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123897 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66535.363741 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70000.810098 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69723.407820 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66087.229012 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66087.229012 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66535.363741 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67194.617993 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67178.776317 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66535.363741 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67194.617993 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67178.776317 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 807125 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 807125 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1068568 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 356400 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 356400 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39084 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3356534 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3395618 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1250688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141603264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 142853952 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 807086 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 807086 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1068578 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 356417 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 356417 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39106 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3356478 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3395584 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1251392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141601792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 142853184 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2232093 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 2232081 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 2232093 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 2232081 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2232093 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2184614500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2232081 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2184618500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 30006497 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 30027495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1744748235 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1744688735 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadReq 43319 # Transaction distribution -system.membus.trans_dist::ReadResp 43319 # Transaction distribution -system.membus.trans_dist::Writeback 96557 # Transaction distribution -system.membus.trans_dist::ReadExReq 100864 # Transaction distribution -system.membus.trans_dist::ReadExResp 100864 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384923 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 384923 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15407360 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15407360 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 43274 # Transaction distribution +system.membus.trans_dist::ReadResp 43274 # Transaction distribution +system.membus.trans_dist::Writeback 96568 # Transaction distribution +system.membus.trans_dist::ReadExReq 100881 # Transaction distribution +system.membus.trans_dist::ReadExResp 100881 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384878 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 384878 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15406272 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15406272 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 240740 # Request fanout histogram +system.membus.snoop_fanout::samples 240723 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 240740 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 240723 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 240740 # Request fanout histogram -system.membus.reqLayer0.occupancy 679202000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 240723 # Request fanout histogram +system.membus.reqLayer0.occupancy 679184500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 765364000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 765222500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini index c190aab09..e1f177c8e 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini @@ -23,6 +23,7 @@ load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem +mmap_using_noreserve=false num_work_ids=16 readfile= symbolfile= @@ -132,6 +133,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -166,6 +168,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +sys=system tlb=system.cpu.dtb [system.cpu.dstage2_mmu.stage2_tlb] @@ -183,7 +186,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[5] [system.cpu.dtb] type=ArmTLB @@ -591,6 +593,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -651,6 +654,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu.istage2_mmu] @@ -658,6 +662,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +sys=system tlb=system.cpu.itb [system.cpu.istage2_mmu.stage2_tlb] @@ -675,7 +680,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB @@ -700,6 +704,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -733,13 +738,16 @@ size=2097152 type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 -header_cycles=1 +forward_latency=0 +frontend_latency=1 +response_latency=1 snoop_filter=Null +snoop_response_latency=1 system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -749,14 +757,16 @@ eventq_index=0 type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing +drivers= egid=100 env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon +executable=/dist/m5/cpu2000/binaries/arm/linux/eon gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -786,11 +796,14 @@ transition_latency=100000000 type=CoherentXBar clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=4 +frontend_latency=3 +response_latency=2 snoop_filter=Null +snoop_response_latency=4 system=system use_default_range=false -width=8 +width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side @@ -821,7 +834,7 @@ IDD62=0.000000 VDD=1.500000 VDD2=0.000000 activation_limit=4 -addr_mapping=RoRaBaChCo +addr_mapping=RoRaBaCoCh bank_groups_per_rank=0 banks_per_rank=8 burst_length=8 @@ -830,6 +843,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/simerr b/tests/long/se/30.eon/ref/arm/linux/minor-timing/simerr index 956bfed52..62f25930d 100644..100755 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/simerr +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/simerr @@ -1,3 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections getting pixel output filename pixels_out.cook opening control file chair.control.cook diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout b/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout index 6f527f164..3857083f4 100644..100755 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout @@ -1,19 +1,17 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 7 2014 10:57:46 -gem5 started May 7 2014 12:10:42 -gem5 executing on cz3211bhr8 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing +gem5 compiled Mar 15 2015 20:30:55 +gem5 started Mar 15 2015 20:31:14 +gem5 executing on zizzer2 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0xc928260 + 0: system.cpu.isa: ISA system set to: 0 0x3ccd9b0 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. -OO-style eon Time= 0.220000 -Exiting @ tick 227450162000 because target called exit() +OO-style eon Time= 0.210000 +Exiting @ tick 216864820000 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index 32197bf04..048a31a06 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.216865 # Nu sim_ticks 216864820000 # Number of ticks simulated final_tick 216864820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 175540 # Simulator instruction rate (inst/s) -host_op_rate 210755 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 139425507 # Simulator tick rate (ticks/s) -host_mem_usage 321524 # Number of bytes of host memory used -host_seconds 1555.42 # Real time elapsed on the host +host_inst_rate 114758 # Simulator instruction rate (inst/s) +host_op_rate 137779 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 91148248 # Simulator tick rate (ticks/s) +host_mem_usage 250616 # Number of bytes of host memory used +host_seconds 2379.25 # Real time elapsed on the host sim_insts 273037856 # Number of instructions simulated sim_ops 327812213 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6626 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 898 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6625 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 899 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1523 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 317.772817 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 188.476979 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.358112 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 549 36.05% 36.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 352 23.11% 59.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 179 11.75% 70.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 73 4.79% 75.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 70 4.60% 80.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 53 3.48% 83.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 37 2.43% 86.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 29 1.90% 88.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 181 11.88% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1523 # Bytes accessed per row activation -system.physmem.totQLat 53728750 # Total ticks spent queuing -system.physmem.totMemAccLat 195928750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1521 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 318.190664 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 188.796192 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.520878 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 546 35.90% 35.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 355 23.34% 59.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 175 11.51% 70.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 75 4.93% 75.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 71 4.67% 80.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 52 3.42% 83.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 37 2.43% 86.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 29 1.91% 88.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 181 11.90% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1521 # Bytes accessed per row activation +system.physmem.totQLat 53624000 # Total ticks spent queuing +system.physmem.totMemAccLat 195824000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 37920000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7084.49 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7070.68 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25834.49 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25820.68 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.24 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.24 # Average system read bandwidth in MiByte/s @@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6056 # Number of row buffer hits during reads +system.physmem.readRowHits 6058 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.85 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.88 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 28595013.65 # Average gap between requests -system.physmem.pageHitRate 79.85 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5027400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2743125 # Energy for precharge commands per rank (pJ) +system.physmem.pageHitRate 79.88 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5012280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2734875 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 29952000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 14164413120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5668320825 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 125145525750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 145015982220 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.698913 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 208188918000 # Time in different power states +system.physmem_0.actBackEnergy 5663385765 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 125149854750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 145015352790 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.696011 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 208196147750 # Time in different power states system.physmem_0.memoryStateTime::REF 7241520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1432738500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1425508750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 6486480 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 3539250 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 29031600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 14164413120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5831746380 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 125002170000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 145037386830 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.797614 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 207947266000 # Time in different power states +system.physmem_1.actBackEnergy 5827279860 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 125006088000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 145036838310 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.795085 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 207953796500 # Time in different power states system.physmem_1.memoryStateTime::REF 7241520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1674122750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1667592250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 33219592 # Number of BP lookups +system.cpu.branchPred.lookups 33219593 # Number of BP lookups system.cpu.branchPred.condPredicted 17177082 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1581285 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 17974979 # Number of BTB lookups system.cpu.branchPred.BTBHits 15661112 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 87.127290 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6612085 # Number of times the RAS was used to get a target. +system.cpu.branchPred.usedRAS 6612086 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -382,19 +382,19 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 273037856 # Number of instructions committed system.cpu.committedOps 327812213 # Number of ops (including micro ops) committed -system.cpu.discardedOps 4054235 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 4054236 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.588533 # CPI: cycles per instruction system.cpu.ipc 0.629512 # IPC: instructions per cycle -system.cpu.tickCycles 430193160 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3536480 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 430193126 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3536514 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 1354 # number of replacements -system.cpu.dcache.tags.tagsinuse 3085.768991 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168782225 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3085.769078 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168782221 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37415.700510 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37415.699623 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3085.768991 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 3085.769078 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.753362 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.753362 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id @@ -406,62 +406,70 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 2432 system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 337583521 # Number of tag accesses system.cpu.dcache.tags.data_accesses 337583521 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 86712977 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86712977 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 86649433 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86649433 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 82047458 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 82047458 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 63540 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 63540 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168760435 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168760435 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168760435 # number of overall hits -system.cpu.dcache.overall_hits::total 168760435 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2061 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2061 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 168696891 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168696891 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168760431 # number of overall hits +system.cpu.dcache.overall_hits::total 168760431 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2059 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2059 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 5219 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 5219 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 7280 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7280 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7280 # number of overall misses -system.cpu.dcache.overall_misses::total 7280 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 137684956 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 137684956 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 400150250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 400150250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 537835206 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 537835206 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 537835206 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 537835206 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86715038 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86715038 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_misses::cpu.data 6 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 6 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 7278 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7278 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7284 # number of overall misses +system.cpu.dcache.overall_misses::total 7284 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 136977706 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 136977706 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 400661500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 400661500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 537639206 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 537639206 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 537639206 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 537639206 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86651492 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86651492 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 63546 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 63546 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168767715 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168767715 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168704169 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168704169 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 168767715 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 168767715 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000064 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000094 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.000094 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66804.927705 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66804.927705 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76671.824104 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76671.824104 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73878.462363 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73878.462363 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73878.462363 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73878.462363 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66526.326372 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66526.326372 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76769.783483 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76769.783483 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 73871.833746 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 73871.833746 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73810.983800 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73810.983800 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -472,56 +480,64 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 1010 # number of writebacks system.cpu.dcache.writebacks::total 1010 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 420 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 420 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 422 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 422 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2349 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 2349 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2769 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2769 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2769 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2769 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1641 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1641 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 2771 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2771 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2771 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2771 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1637 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1637 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 2870 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4511 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4511 # number of demand (read+write) MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4507 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4507 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4511 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109745542 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 109745542 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219964750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 219964750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329710292 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 329710292 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 329710292 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 329710292 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109140792 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 109140792 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 220213500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 220213500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 320750 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 320750 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329354292 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 329354292 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 329675042 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 329675042 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000063 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000063 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66877.234613 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66877.234613 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76642.770035 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76642.770035 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73090.288628 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73090.288628 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73090.288628 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73090.288628 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66671.222969 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66671.222969 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76729.442509 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76729.442509 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80187.500000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80187.500000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73076.168627 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73076.168627 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73082.474396 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73082.474396 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 36897 # number of replacements -system.cpu.icache.tags.tagsinuse 1924.852609 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 73252005 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1924.852858 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 73252007 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 38834 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1886.285343 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1886.285394 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1924.852609 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.939869 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.939869 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1924.852858 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.939870 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.939870 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id @@ -529,44 +545,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 34 system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1487 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146620514 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146620514 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 73252005 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 73252005 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 73252005 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 73252005 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 73252005 # number of overall hits -system.cpu.icache.overall_hits::total 73252005 # number of overall hits +system.cpu.icache.tags.tag_accesses 146620518 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146620518 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 73252007 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 73252007 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 73252007 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 73252007 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 73252007 # number of overall hits +system.cpu.icache.overall_hits::total 73252007 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 38835 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 38835 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 38835 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 38835 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 38835 # number of overall misses system.cpu.icache.overall_misses::total 38835 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 728456748 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 728456748 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 728456748 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 728456748 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 728456748 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 728456748 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 73290840 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 73290840 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 73290840 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 73290840 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 73290840 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 73290840 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 728387498 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 728387498 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 728387498 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 728387498 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 728387498 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 728387498 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 73290842 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 73290842 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 73290842 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 73290842 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 73290842 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 73290842 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000530 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000530 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000530 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000530 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000530 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000530 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18757.737814 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18757.737814 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18757.737814 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18757.737814 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18757.737814 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18757.737814 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18755.954629 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18755.954629 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18755.954629 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18755.954629 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18755.954629 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18755.954629 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -581,34 +597,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 38835 system.cpu.icache.demand_mshr_misses::total 38835 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 38835 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 38835 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 668757252 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 668757252 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 668757252 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 668757252 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 668757252 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 668757252 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 668686502 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 668686502 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 668686502 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 668686502 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 668686502 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 668686502 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000530 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000530 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000530 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17220.477713 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17220.477713 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17220.477713 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17220.477713 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17220.477713 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17220.477713 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17218.655903 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17218.655903 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17218.655903 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 17218.655903 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17218.655903 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 17218.655903 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4197.194159 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 4197.194738 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 35781 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 5646 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 6.337407 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 353.722028 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3165.177467 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 678.294664 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 353.722054 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3165.177954 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 678.294730 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.010795 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096594 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.020700 # Average percentage of cache occupancy @@ -646,17 +662,17 @@ system.cpu.l2cache.demand_misses::total 7628 # nu system.cpu.l2cache.overall_misses::cpu.inst 3424 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 4204 # number of overall misses system.cpu.l2cache.overall_misses::total 7628 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 258115750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 105039500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 363155250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 216891750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 216891750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 258115750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 321931250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 580047000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 258115750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 321931250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 580047000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 258045000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 104755500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 362800500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 217140500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 217140500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 258045000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 321896000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 579941000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 258045000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 321896000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 579941000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 38835 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1641 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 40476 # number of ReadReq accesses(hits+misses) @@ -681,17 +697,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.175979 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088168 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.931944 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.175979 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75384.272780 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77807.037037 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 76069.386259 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75995.707779 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75995.707779 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75384.272780 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76577.366794 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76041.819612 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75384.272780 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76577.366794 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76041.819612 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75363.609813 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77596.666667 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75995.077503 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76082.866153 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76082.866153 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75363.609813 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76568.981922 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76027.923440 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75363.609813 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76568.981922 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76027.923440 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -720,17 +736,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7584 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3422 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4162 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7584 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 215130250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 85732250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 300862500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 181193250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 181193250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 215130250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 266925500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 482055750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 215130250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 266925500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 482055750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 215060000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 85447750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 300507750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 181443000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 181443000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 215060000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 266890750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 481950750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 215060000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 266890750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 481950750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088116 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.797075 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116859 # mshr miss rate for ReadReq accesses @@ -742,17 +758,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.174964 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088116 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.174964 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62866.817650 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65544.533639 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63607.293869 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63487.473721 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63487.473721 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62866.817650 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64133.950024 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63562.203323 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62866.817650 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64133.950024 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63562.203323 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62846.288720 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65327.025994 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63532.293869 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63574.982481 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63574.982481 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62846.288720 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64125.600673 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63548.358386 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62846.288720 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64125.600673 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63548.358386 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 40476 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 40475 # Transaction distribution @@ -781,9 +797,9 @@ system.cpu.toL2Bus.snoop_fanout::max_value 3 # system.cpu.toL2Bus.snoop_fanout::total 44356 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 23188000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 58975248 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 58975998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7577708 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 7577458 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.trans_dist::ReadReq 4730 # Transaction distribution system.membus.trans_dist::ReadResp 4730 # Transaction distribution @@ -804,9 +820,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7584 # Request fanout histogram -system.membus.reqLayer0.occupancy 8969500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8969000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 40264250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 40262750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini index c01955b00..3d0a9003e 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini @@ -23,6 +23,7 @@ load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem +mmap_using_noreserve=false num_work_ids=16 readfile= symbolfile= @@ -132,6 +133,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -166,6 +168,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +sys=system tlb=system.cpu.dtb [system.cpu.dstage2_mmu.stage2_tlb] @@ -183,7 +186,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[5] [system.cpu.dtb] type=ArmTLB @@ -591,6 +593,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -651,6 +654,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu.istage2_mmu] @@ -658,6 +662,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +sys=system tlb=system.cpu.itb [system.cpu.istage2_mmu.stage2_tlb] @@ -675,7 +680,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB @@ -700,6 +704,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -733,13 +738,16 @@ size=2097152 type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 -header_cycles=1 +forward_latency=0 +frontend_latency=1 +response_latency=1 snoop_filter=Null +snoop_response_latency=1 system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -749,14 +757,16 @@ eventq_index=0 type=LiveProcess cmd=perlbmk -I. -I lib mdred.makerand.pl cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing +drivers= egid=100 env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk +executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -786,11 +796,14 @@ transition_latency=100000000 type=CoherentXBar clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=4 +frontend_latency=3 +response_latency=2 snoop_filter=Null +snoop_response_latency=4 system=system use_default_range=false -width=8 +width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side @@ -821,7 +834,7 @@ IDD62=0.000000 VDD=1.500000 VDD2=0.000000 activation_limit=4 -addr_mapping=RoRaBaChCo +addr_mapping=RoRaBaCoCh bank_groups_per_rank=0 banks_per_rank=8 burst_length=8 @@ -830,6 +843,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simerr b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simerr index 2de5e2759..2e6ab1e7e 100644..100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simerr +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simerr @@ -1,2 +1,3 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: fcntl64(3, 2) passed through to host diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout index ca66069ba..b094041b5 100644..100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout @@ -1,1391 +1,651 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 7 2014 10:57:46 -gem5 started May 7 2014 14:12:56 -gem5 executing on cz3211bhr8 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing +gem5 compiled Mar 15 2015 20:30:55 +gem5 started Mar 15 2015 20:31:14 +gem5 executing on zizzer2 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x1273de40 + 0: system.cpu.isa: ISA system set to: 0 0x2ccb000 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. info: Increasing stack size by one page. -1375000: 2038431008 -1374000: 3487365506 -1373000: 4184770123 -1372000: 1943746837 -1371000: 2651673663 -1370000: 1493817016 -1369000: 2894014801 -1368000: 1932092157 -1367000: 1670009799 -1366000: 828662248 -1365000: 1816650195 -1364000: 4173139012 -1363000: 3990577549 -1362000: 1330366815 -1361000: 3316935553 -1360000: 961300001 -1359000: 344963924 -1358000: 1930356625 -1357000: 1640964266 -1356000: 3777883312 -1355000: 1651132665 -1354000: 1971433151 -1353000: 3024027448 -1352000: 1956387036 -1351000: 1490224841 -1350000: 3286956460 -1349000: 2793131848 -1348000: 2529224907 -1347000: 2622295253 -1346000: 1414103189 -1345000: 3861617587 -1344000: 3506378216 -1343000: 1667466720 -1342000: 2899224065 -1341000: 1681491556 -1340000: 1076311729 -1339000: 4066972664 -1338000: 3438059028 -1337000: 2938359730 -1336000: 1214615378 -1335000: 3814432458 -1334000: 2944038793 -1333000: 3428045644 -1332000: 2815822229 -1331000: 1093465585 -1330000: 3012217108 -1329000: 2230916791 -1328000: 208547885 -1327000: 3592585825 -1326000: 3948677052 -1325000: 1817805162 -1324000: 135366494 -1323000: 3309148112 -1322000: 1685035744 -1321000: 3293068577 -1320000: 4097808567 -1319000: 1594097274 -1318000: 2607196971 -1317000: 1763785306 -1316000: 2157394178 -1315000: 2399031328 -1314000: 2954547004 -1313000: 82348686 -1312000: 3120930785 -1311000: 2192747320 -1310000: 1580299400 -1309000: 4085061477 -1308000: 3627048345 -1307000: 3756533178 -1306000: 77997329 -1305000: 1343359499 -1304000: 1124031730 -1303000: 1161755432 -1302000: 1855858423 -1301000: 3985872257 -1300000: 3188250811 -1299000: 3621615933 -1298000: 962624248 -1297000: 447138785 -1296000: 1459144309 -1295000: 3454504226 -1294000: 2154913347 -1293000: 2356291788 -1292000: 458348817 -1291000: 3639562699 -1290000: 3596847973 -1289000: 117168222 -1288000: 3531023849 -1287000: 3135920051 -1286000: 234987844 -1285000: 2048767180 -1284000: 2437301839 -1283000: 522886780 -1282000: 2274133042 -1281000: 1415703448 -1280000: 4145574054 -1279000: 4283494580 -1278000: 3305365779 -1277000: 604711974 -1276000: 2031548723 -1275000: 1809515149 -1274000: 1664703088 -1273000: 4149809153 -1272000: 4045608138 -1271000: 1687605659 -1270000: 1292294527 -1269000: 3120968162 -1268000: 3502898850 -1267000: 371380256 -1266000: 1683884245 -1265000: 1849576817 -1264000: 1559050991 -1263000: 66820972 -1262000: 4023539201 -1261000: 3452295398 -1260000: 4188778026 -1259000: 2008091854 -1258000: 2691158394 -1257000: 2030818206 -1256000: 2715523403 -1255000: 3473414015 -1254000: 138826953 -1253000: 69386516 -1252000: 1174725971 -1251000: 4130510373 -1250000: 1649788328 -1249000: 1589122801 -1248000: 1108688101 -1247000: 2906355484 -1246000: 379539929 -1245000: 914026021 -1244000: 4074858468 -1243000: 505989635 -1242000: 2487288773 -1241000: 1991248111 -1240000: 2415456875 -1239000: 2571192525 -1238000: 2897090536 -1237000: 2761178989 -1236000: 1296601829 -1235000: 594696756 -1234000: 264562726 -1233000: 3630852367 -1232000: 1605618457 -1231000: 2857419452 -1230000: 3028672437 -1229000: 361833758 -1228000: 4046013938 -1227000: 1031775583 -1226000: 3475227831 -1225000: 802168737 -1224000: 3819194009 -1223000: 851157666 -1222000: 2656457905 -1221000: 2579045204 -1220000: 2091024410 -1219000: 4070633834 -1218000: 1926611791 -1217000: 1903813761 -1216000: 3107168794 -1215000: 2975081979 -1214000: 4097089273 -1213000: 328943233 -1212000: 2912404803 -1211000: 181334180 -1210000: 863898367 -1209000: 1894902343 -1208000: 1531985231 -1207000: 1412503751 -1206000: 662457490 -1205000: 3447925432 -1204000: 2320889638 -1203000: 303282255 -1202000: 1568632659 -1201000: 1108711074 -1200000: 953936964 -1199000: 3576987258 -1198000: 466163300 -1197000: 1159551420 -1196000: 529807534 -1195000: 1528979627 -1194000: 1795576953 -1193000: 2050917610 -1192000: 4068219994 -1191000: 3573497288 -1190000: 776005286 -1189000: 2643125982 -1188000: 2240857507 -1187000: 43353719 -1186000: 2474198261 -1185000: 1711347056 -1184000: 3046018343 -1183000: 664346074 -1182000: 3532392595 -1181000: 3145347726 -1180000: 2203928246 -1179000: 4275910811 -1178000: 3260065240 -1177000: 3216083720 -1176000: 3588515377 -1175000: 1432542416 -1174000: 173159992 -1173000: 4115057268 -1172000: 223456174 -1171000: 1192164227 -1170000: 2059254624 -1169000: 279921804 -1168000: 1100495449 -1167000: 264813624 -1166000: 2839280440 -1165000: 301796904 -1164000: 1331933822 -1163000: 647427882 -1162000: 3872813324 -1161000: 2231068824 -1160000: 4222672618 -1159000: 3629229584 -1158000: 2262586804 -1157000: 2837951671 -1156000: 1780662312 -1155000: 31553143 -1154000: 3230861653 -1153000: 1991458597 -1152000: 2277829165 -1151000: 3864184029 -1150000: 630158826 -1149000: 4028889917 -1148000: 1662505287 -1147000: 4121796538 -1146000: 3215277282 -1145000: 2019794999 -1144000: 4124433286 -1143000: 181819953 -1142000: 2704380222 -1141000: 2487909897 -1140000: 1753570204 -1139000: 2337507591 -1138000: 3235449912 -1137000: 3819353806 -1136000: 3435413746 -1135000: 3288196653 -1134000: 2705083758 -1133000: 997301031 -1132000: 1871866706 -1131000: 2298991521 -1130000: 1516060457 -1129000: 3393393053 -1128000: 2795526466 -1127000: 1177801041 -1126000: 4226698729 -1125000: 567826718 -1124000: 2425735007 -1123000: 1090360485 -1122000: 2508061782 -1121000: 3476086116 -1120000: 2952087827 -1119000: 2238445545 -1118000: 2937037425 -1117000: 1773353797 -1116000: 3033333765 -1115000: 3086246055 -1114000: 944390435 -1113000: 2944932895 -1112000: 534683663 -1111000: 2002175399 -1110000: 1876265996 -1109000: 4148000592 -1108000: 3857174625 -1107000: 843045539 -1106000: 307772960 -1105000: 4161975075 -1104000: 3675447412 -1103000: 1232242543 -1102000: 1019583281 -1101000: 1983565552 -1100000: 2490901544 -1099000: 2990982808 -1098000: 1586955629 -1097000: 1629138000 -1096000: 1870655270 -1095000: 2201093764 -1094000: 696079363 -1093000: 1526904315 -1092000: 553848190 -1091000: 4234411636 -1090000: 1027439894 -1089000: 1319115149 -1088000: 1147708285 -1087000: 3364503693 -1086000: 528432422 -1085000: 3289100476 -1084000: 3074065438 -1083000: 3664250869 -1082000: 2950591670 -1081000: 4207904839 -1080000: 3425353965 -1079000: 1069646286 -1078000: 1004956209 -1077000: 2642475281 -1076000: 364759474 -1075000: 2334969932 -1074000: 3907002684 -1073000: 273633783 -1072000: 4113182592 -1071000: 1404306188 -1070000: 3286171051 -1069000: 3531039414 -1068000: 4147513318 -1067000: 2466290219 -1066000: 2089005579 -1065000: 2617563073 -1064000: 3124838472 -1063000: 3731008114 -1062000: 4154022628 -1061000: 3389258714 -1060000: 3915149371 -1059000: 2280932986 -1058000: 2872952978 -1057000: 2381277834 -1056000: 1236179469 -1055000: 3256417375 -1054000: 2700213407 -1053000: 3418122897 -1052000: 3130247908 -1051000: 1897033028 -1050000: 2349143738 -1049000: 3789736749 -1048000: 409522147 -1047000: 3149279018 -1046000: 1323133366 -1045000: 3881472077 -1044000: 3363874422 -1043000: 3931657349 -1042000: 1220007174 -1041000: 3634450249 -1040000: 695184634 -1039000: 529508167 -1038000: 449827627 -1037000: 2817424280 -1036000: 1613482057 -1035000: 2632612792 -1034000: 852422020 -1033000: 4098325966 -1032000: 177298753 -1031000: 2286807874 -1030000: 2745349553 -1029000: 2387386570 -1028000: 2004317534 -1027000: 971343564 -1026000: 1583732447 -1025000: 2340780818 -1024000: 561110245 -1023000: 3012020895 -1022000: 1677066870 -1021000: 3046208682 -1020000: 2695506079 -1019000: 780536149 -1018000: 4225713741 -1017000: 420500410 -1016000: 3642094643 -1015000: 608695027 -1014000: 2161592269 -1013000: 930784800 -1012000: 1924051276 -1011000: 1889733886 -1010000: 1476038251 -1009000: 2908577467 -1008000: 2584082136 -1007000: 1713214537 -1006000: 3374346754 -1005000: 1173203719 -1004000: 1142288559 -1003000: 4195961973 -1002000: 1211260974 -1001000: 474231127 -1000000: 3967090782 -999000: 1543103493 -998000: 1018646803 -997000: 1799037982 -996000: 3416426509 -995000: 3581729971 -994000: 3044504127 -993000: 2975704335 -992000: 280018795 -991000: 330300280 -990000: 3557016064 -989000: 3856724468 -988000: 2124201285 -987000: 3683893247 -986000: 3331663795 -985000: 1980057740 -984000: 2908437859 -983000: 4074086941 -982000: 1162307093 -981000: 3855413476 -980000: 2799155731 -979000: 2477822501 -978000: 497762075 -977000: 1650233426 -976000: 3061573902 -975000: 2224673611 -974000: 868725340 -973000: 1630206962 -972000: 2549398924 -971000: 602424332 -970000: 1172502721 -969000: 2923795552 -968000: 1394164637 -967000: 1088479837 -966000: 898709052 -965000: 3983150961 -964000: 2463803866 -963000: 4181117626 -962000: 2151137820 -961000: 1342513757 -960000: 1507689687 -959000: 3652624918 -958000: 4169721124 -957000: 531022334 -956000: 3161389505 -955000: 1197637232 -954000: 2927231791 -953000: 2552305374 -952000: 2988512039 -951000: 2448639370 -950000: 3560951660 -949000: 948988399 -948000: 2488188856 -947000: 2804177113 -946000: 1991587461 -945000: 2480044082 -944000: 1954588624 -943000: 924231798 -942000: 3269047595 -941000: 2078696579 -940000: 2822989969 -939000: 2295885951 -938000: 1815612561 -937000: 4182254074 -936000: 2753223967 -935000: 2840201908 -934000: 4058383142 -933000: 4270167260 -932000: 1203124158 -931000: 3039861400 -930000: 4247472610 -929000: 2297661055 -928000: 2376159704 -927000: 3861417958 -926000: 1968685250 -925000: 1156966624 -924000: 3568580529 -923000: 866582344 -922000: 2263113297 -921000: 3643523016 -920000: 3252268544 -919000: 2413309783 -918000: 3463124619 -917000: 3965291932 -916000: 1309181143 -915000: 2321282614 -914000: 2286584604 -913000: 3271924727 -912000: 1719841316 -911000: 3966124343 -910000: 607707072 -909000: 61942114 -908000: 903881820 -907000: 4136948835 -906000: 3663861210 -905000: 3251888710 -904000: 227984688 -903000: 495030333 -902000: 863290992 -901000: 3297482717 -900000: 3821175085 -899000: 1679874522 -898000: 2033358728 -897000: 3495513776 -896000: 1613181881 -895000: 1729312232 -894000: 2171317375 -893000: 2508603694 -892000: 151095866 -891000: 1926096901 -890000: 4292888210 -889000: 2716307666 -888000: 737310728 -887000: 4172392976 -886000: 2322084662 -885000: 1034961047 -884000: 665072958 -883000: 368014441 -882000: 1914585160 -881000: 3836900884 -880000: 2073827187 -879000: 1650543625 -878000: 3581099222 -877000: 147580905 -876000: 4009421518 -875000: 3294244820 -874000: 2786720968 -873000: 1682434702 -872000: 620473876 -871000: 742752376 -870000: 385116650 -869000: 3882475387 -868000: 4259210265 -867000: 1329675866 -866000: 539876515 -865000: 2761681036 -864000: 2192063038 -863000: 1512848001 -862000: 3911973718 -861000: 399349760 -860000: 1449497249 -859000: 4241714042 -858000: 18611709 -857000: 1550083097 -856000: 3322762748 -855000: 283796511 -854000: 227907270 -853000: 3162559866 -852000: 1331946455 -851000: 2328467927 -850000: 1640242501 -849000: 3390154083 -848000: 22088346 -847000: 636412590 -846000: 1550672808 -845000: 763937899 -844000: 430123910 -843000: 3413971543 -842000: 900018421 -841000: 3295874222 -840000: 2470678073 -839000: 821401909 -838000: 3923898844 -837000: 429069328 -836000: 2030779868 -835000: 464625222 -834000: 3593024182 -833000: 3564354808 -832000: 2794783695 -831000: 97817593 -830000: 4197446076 -829000: 2367560230 -828000: 2180262123 -827000: 3149571964 -826000: 1364436763 -825000: 21599634 -824000: 448490256 -823000: 3775294409 -822000: 1132631425 -821000: 2046352434 -820000: 3380435217 -819000: 3672496486 -818000: 1634548077 -817000: 2881316258 -816000: 1808599559 -815000: 3298310748 -814000: 3744285741 -813000: 3540737709 -812000: 1143844515 -811000: 3091026783 -810000: 3771757792 -809000: 631375816 -808000: 1353831646 -807000: 3047756240 -806000: 818136890 -805000: 783072818 -804000: 3923416267 -803000: 3233085529 -802000: 674747602 -801000: 758523180 -800000: 2232308489 -799000: 2919643710 -798000: 623631722 -797000: 1302202741 -796000: 1083055596 -795000: 2358048936 -794000: 2836842068 -793000: 1612571734 -792000: 4243459584 -791000: 1585511173 -790000: 1493369943 -789000: 3649557715 -788000: 3223859588 -787000: 4001130195 -786000: 2949323631 -785000: 3887611007 -784000: 4091766333 -783000: 2954277998 -782000: 1281850218 -781000: 771664458 -780000: 2242576209 -779000: 3865479146 -778000: 1885013114 -777000: 2032659742 -776000: 4221167450 -775000: 1962824751 -774000: 209539683 -773000: 262945027 -772000: 452388820 -771000: 2006266573 -770000: 990063860 -769000: 1377951885 -768000: 4240978277 -767000: 2206801004 -766000: 258015097 -765000: 1990217201 -764000: 1336410303 -763000: 1004853228 -762000: 1404152873 -761000: 3356554358 -760000: 4052430907 -759000: 2833671166 -758000: 1561723151 -757000: 1752620777 -756000: 2622547462 -755000: 1843933196 -754000: 3728801998 -753000: 2776832730 -752000: 2626131293 -751000: 1528525830 -750000: 2716112581 -749000: 3306039713 -748000: 915271993 -747000: 4205133363 -746000: 3136321783 -745000: 1203154793 -744000: 3370017183 -743000: 4036456207 -742000: 3377556743 -741000: 3688568185 -740000: 3349738887 -739000: 1606411092 -738000: 331980874 -737000: 744409647 -736000: 3845688101 -735000: 3654026084 -734000: 786733128 -733000: 1938791337 -732000: 843210299 -731000: 622237260 -730000: 2851984401 -729000: 874906210 -728000: 485670931 -727000: 1522238607 -726000: 2167917076 -725000: 2304482464 -724000: 1053513779 -723000: 3535437378 -722000: 2842397393 -721000: 864490421 -720000: 920591184 -719000: 238249003 -718000: 400999105 -717000: 2476588521 -716000: 2501770197 -715000: 2307183887 -714000: 2461504446 -713000: 1055961242 -712000: 2112756603 -711000: 1691285107 -710000: 2318101701 -709000: 1113470660 -708000: 2880817109 -707000: 2105866601 -706000: 1441912219 -705000: 1684930572 -704000: 1652788290 -703000: 2359919145 -702000: 554008403 -701000: 3292620387 -700000: 3528106952 -699000: 3096375697 -698000: 4201459210 -697000: 1450879661 -696000: 3743939389 -695000: 3595614062 -694000: 4101634764 -693000: 364538097 -692000: 4204120947 -691000: 3706729229 -690000: 23134581 -689000: 2585120038 -688000: 488096133 -687000: 3437179533 -686000: 4233790378 -685000: 3093374794 -684000: 4054579709 -683000: 1275606548 -682000: 1966964511 -681000: 354765069 -680000: 3812578933 -679000: 781104418 -678000: 3281747368 -677000: 38547527 -676000: 1005246555 -675000: 74753563 -674000: 676561715 -673000: 1571462591 -672000: 1876054379 -671000: 1899005137 -670000: 4188106842 -669000: 1210903253 -668000: 2909261468 -667000: 3100970839 -666000: 758568698 -665000: 2456763236 -664000: 686978785 -663000: 349808361 -662000: 2804776250 -661000: 2660993423 -660000: 1758165672 -659000: 2116094507 -658000: 473425247 -657000: 563682488 -656000: 1454194093 -655000: 3211379305 -654000: 1298793267 -653000: 3374836733 -652000: 586356525 -651000: 1490379306 -650000: 2444980288 -649000: 47671514 -648000: 568687171 -647000: 452676234 -646000: 2752247721 -645000: 1473254180 -644000: 4189470166 -643000: 2619721788 -642000: 348627393 -641000: 675341258 -640000: 3183922211 -639000: 1266115377 -638000: 2331844572 -637000: 250721255 -636000: 4017517385 -635000: 1279621530 -634000: 1500904407 -633000: 2495457137 -632000: 1919479114 -631000: 1900388354 -630000: 370039669 -629000: 1207459690 -628000: 2314286843 -627000: 80099285 -626000: 2465533600 -625000: 1056979505 -624000: 4289445503 -623000: 1234007489 -622000: 2015973003 -621000: 2281387627 -620000: 1115405564 -619000: 1407699260 -618000: 3940256761 -617000: 3639431367 -616000: 3498942818 -615000: 2982957031 -614000: 3800830694 -613000: 1454837486 -612000: 158454584 -611000: 3414923339 -610000: 3752581462 -609000: 195868045 -608000: 3165948362 -607000: 2335822431 -606000: 3229210414 -605000: 1963422803 -604000: 2355005929 -603000: 2009365872 -602000: 1343084455 -601000: 2935056539 -600000: 2354171524 -599000: 3621510708 -598000: 3992266416 -597000: 682368260 -596000: 3290472265 -595000: 2215475388 -594000: 258049456 -593000: 365234760 -592000: 291875022 -591000: 3307168950 -590000: 2233802778 -589000: 1944100586 -588000: 7070250 -587000: 882601802 -586000: 1231725137 -585000: 4169259917 -584000: 2123453163 -583000: 631823798 -582000: 2039925673 -581000: 2238172862 -580000: 1479379031 -579000: 2363652063 -578000: 3186953219 -577000: 1893181853 -576000: 2598096173 -575000: 938779920 -574000: 927622241 -573000: 3105026014 -572000: 2412852365 -571000: 644810722 -570000: 3576393744 -569000: 2625468928 -568000: 2167447563 -567000: 3391359662 -566000: 3178493511 -565000: 24044406 -564000: 3298992941 -563000: 2054886551 -562000: 42479754 -561000: 2681525651 -560000: 1110769583 -559000: 2140540905 -558000: 780964175 -557000: 1320986796 -556000: 3624725635 -555000: 2920977559 -554000: 4017386186 -553000: 1800018968 -552000: 2137743255 -551000: 2282561617 -550000: 1466333871 -549000: 2567190002 -548000: 3280136825 -547000: 1761114084 -546000: 413841088 -545000: 829808286 -544000: 283842712 -543000: 3524860517 -542000: 1853927454 -541000: 3087398009 -540000: 2535138654 -539000: 2224833733 -538000: 1673737994 -537000: 3963575809 -536000: 289926670 -535000: 2411609896 -534000: 1866933324 -533000: 259728174 -532000: 786327819 -531000: 870136645 -530000: 3603849411 -529000: 1687141824 -528000: 2973109656 -527000: 2120372902 -526000: 3554894341 -525000: 369365218 -524000: 2336210870 -523000: 1352671703 -522000: 4093185231 -521000: 44309897 -520000: 1308207751 -519000: 1489447779 -518000: 497784082 -517000: 2370135551 -516000: 2393982064 -515000: 3453216376 -514000: 349616264 -513000: 1057922348 -512000: 2061823561 -511000: 2221803921 -510000: 2518047997 -509000: 2783356981 -508000: 3842023593 -507000: 3105321997 -506000: 3540124104 -505000: 334821209 -504000: 2867156116 -503000: 3824184936 -502000: 2432119674 -501000: 3759474841 -500000: 3381305904 -499000: 3106640260 -498000: 4241569809 -497000: 2499659818 -496000: 3971155346 -495000: 2297624439 -494000: 3455216298 -493000: 2152855317 -492000: 3915728702 -491000: 1087687366 -490000: 3976823873 -489000: 1813936857 -488000: 2803197060 -487000: 4026575712 -486000: 3867909271 -485000: 644795069 -484000: 1051897856 -483000: 3091023530 -482000: 558963440 -481000: 2516346710 -480000: 2405618228 -479000: 1595155902 -478000: 1699460683 -477000: 645434559 -476000: 1457238083 -475000: 101746166 -474000: 1054127445 -473000: 1703635926 -472000: 3228750510 -471000: 2570095523 -470000: 2671516672 -469000: 219569232 -468000: 245973042 -467000: 1785352151 -466000: 1828704556 -465000: 2993350381 -464000: 1802995474 -463000: 3689392931 -462000: 2612188341 -461000: 1970287287 -460000: 179729165 -459000: 1971694777 -458000: 3031333568 -457000: 844564594 -456000: 979968160 -455000: 2169589334 -454000: 2315813244 -453000: 2333801403 -452000: 27632567 -451000: 3752181065 -450000: 3965825733 -449000: 969798494 -448000: 1028884180 -447000: 1127216392 -446000: 2477366335 -445000: 3752023316 -444000: 1679036165 -443000: 4241934865 -442000: 3360200587 -441000: 3533494907 -440000: 1888455616 -439000: 2668699748 -438000: 2728196631 -437000: 31348508 -436000: 2192326452 -435000: 286955043 -434000: 4097630027 -433000: 1185622743 -432000: 2870795553 -431000: 2246074692 -430000: 14797454 -429000: 2606207217 -428000: 2143322684 -427000: 1289559127 -426000: 3922285071 -425000: 590638427 -424000: 1098669098 -423000: 1597510568 -422000: 1623191243 -421000: 558862770 -420000: 3846690181 -419000: 3187756225 -418000: 2520849981 -417000: 492022774 -416000: 1621927303 -415000: 2828836994 -414000: 2840605981 -413000: 4260845378 -412000: 2200645444 -411000: 393061550 -410000: 3334889686 -409000: 1926958198 -408000: 2939424440 -407000: 4207748941 -406000: 4155428743 -405000: 89797563 -404000: 427509452 -403000: 1154877029 -402000: 4023324583 -401000: 359413604 -400000: 964788206 -399000: 3843097093 -398000: 1871599521 -397000: 2361845870 -396000: 4103568192 -395000: 622493054 -394000: 954921337 -393000: 3664395297 -392000: 2429042528 -391000: 1361036260 -390000: 1944048082 -389000: 1452288555 -388000: 1619598577 -387000: 481096019 -386000: 3719595713 -385000: 1840199850 -384000: 421723640 -383000: 2976677668 -382000: 618336385 -381000: 1777037748 -380000: 901802032 -379000: 621392881 -378000: 3857241587 -377000: 3115040335 -376000: 3173790487 -375000: 2517831056 -374000: 4125976072 -373000: 2294107866 -372000: 4127359945 -371000: 333946663 -370000: 3307391606 -369000: 4268094300 -368000: 91056295 -367000: 882600429 -366000: 730521557 -365000: 3957048081 -364000: 2139992409 -363000: 3504327478 -362000: 2637042137 -361000: 2718540805 -360000: 903036675 -359000: 1858031956 -358000: 1868403889 -357000: 2677157063 -356000: 1865569815 -355000: 224528281 -354000: 3144318856 -353000: 1968806079 -352000: 2836077060 -351000: 1981309964 -350000: 3105869514 -349000: 3793296439 -348000: 1267294125 -347000: 1962520375 -346000: 2150839102 -345000: 3811064048 -344000: 1298671776 -343000: 2150950779 -342000: 3522997671 -341000: 1378798782 -340000: 2213936395 -339000: 2117978968 -338000: 2444486361 -337000: 3928234621 -336000: 1645335376 -335000: 540013781 -334000: 1103798645 -333000: 1723781016 -332000: 1805323374 -331000: 3590394804 -330000: 4178797476 -329000: 3350975600 -328000: 1556948383 -327000: 2282601074 -326000: 1709618426 -325000: 637957139 -324000: 2719080929 -323000: 1847444832 -322000: 547261068 -321000: 581409575 -320000: 586567018 -319000: 1579880779 -318000: 1049735969 -317000: 3233747918 -316000: 351376358 -315000: 3446473138 -314000: 2099035319 -313000: 2827833754 -312000: 2717063452 -311000: 2212978977 -310000: 1583494069 -309000: 3119642323 -308000: 2946038826 -307000: 167580491 -306000: 3916319765 -305000: 3480693946 -304000: 2709010304 -303000: 3265576420 -302000: 3439318492 -301000: 1896109937 -300000: 339896540 -299000: 313850585 -298000: 2600289987 -297000: 4060531515 -296000: 3894455718 -295000: 3183544633 -294000: 1551799240 -293000: 3574197425 -292000: 2380783887 -291000: 3130665581 -290000: 1135162832 -289000: 3460550191 -288000: 3366619355 -287000: 501626025 -286000: 1070097358 -285000: 1023235560 -284000: 925313877 -283000: 3758987940 -282000: 1935539406 -281000: 3727463323 -280000: 4040081802 -279000: 2462105177 -278000: 322183212 -277000: 2437872102 -276000: 1085894622 -275000: 2118601354 -274000: 1720719726 -273000: 56294175 -272000: 2046218040 -271000: 2871320919 -270000: 3111863367 -269000: 726835633 -268000: 916866344 -267000: 1208374677 -266000: 2914608557 -265000: 449456198 -264000: 2645640532 -263000: 997311800 -262000: 2872564998 -261000: 1964496124 -260000: 2802080932 -259000: 387636194 -258000: 3813984224 -257000: 1921258264 -256000: 1414333533 -255000: 997845727 -254000: 3671258247 -253000: 3244313331 -252000: 44297738 -251000: 1055697350 -250000: 403951609 -249000: 3558182356 -248000: 3441722116 -247000: 3598259825 -246000: 2495236386 -245000: 4150113079 -244000: 4092477475 -243000: 1352323466 -242000: 4228179784 -241000: 3509286314 -240000: 1117669666 -239000: 1821539001 -238000: 2685425558 -237000: 3282158412 -236000: 976807931 -235000: 1960913234 -234000: 675404937 -233000: 2016845981 -232000: 3778769531 -231000: 1321297859 -230000: 84609577 -229000: 2736973360 -228000: 1143462599 -227000: 1152334102 -226000: 2661675401 -225000: 3384049744 -224000: 3321570349 -223000: 2151575803 -222000: 2950365334 -221000: 2791341163 -220000: 2912181889 -219000: 700726300 -218000: 3236687629 -217000: 384678680 -216000: 3027284798 -215000: 2124466541 -214000: 1634885735 -213000: 3025139089 -212000: 1913485355 -211000: 2451444114 -210000: 1597224573 -209000: 2863042887 -208000: 1462999033 -207000: 853998677 -206000: 1532111742 -205000: 3533822378 -204000: 1057056422 -203000: 2585913344 -202000: 1776380902 -201000: 2652271540 -200000: 2500553547 -199000: 3943435104 -198000: 615742187 -197000: 2089667313 -196000: 1649690458 -195000: 582691711 -194000: 1197398266 -193000: 2682453813 -192000: 1739971049 -191000: 1543584807 -190000: 4224852565 -189000: 2330603128 -188000: 2738873539 -187000: 2462336661 -186000: 538134005 -185000: 618406175 -184000: 3258203829 -183000: 3565635398 -182000: 2437456159 -181000: 1103703144 -180000: 3142082412 -179000: 3635072449 -178000: 2831183465 -177000: 3067391696 -176000: 4243880329 -175000: 3847103503 -174000: 1886736895 -173000: 3994782354 -172000: 2180961421 -171000: 2657714328 -170000: 1783032069 -169000: 3288794122 -168000: 4214505744 -167000: 3893811403 -166000: 301673242 -165000: 1008606441 -164000: 4241744599 -163000: 4077366883 -162000: 947408771 -161000: 2893412067 -160000: 4239854096 -159000: 837488883 -158000: 1035341013 -157000: 2979612216 -156000: 622879904 -155000: 2239033946 -154000: 1793603359 -153000: 3403674755 -152000: 1757769702 -151000: 3104338771 -150000: 4050901279 -149000: 1064027760 -148000: 1232980113 -147000: 1940798204 -146000: 1520506974 -145000: 1602654645 -144000: 3827165041 -143000: 2333560581 -142000: 1078945096 -141000: 4164769913 -140000: 1004088705 -139000: 1918334274 -138000: 2376094733 -137000: 2114404244 -136000: 610887654 -135000: 2061314834 -134000: 2934949429 -133000: 1384359308 -132000: 2214638498 -131000: 4091637905 -130000: 1178600936 -129000: 3673332079 -128000: 335936353 -127000: 1680711257 -126000: 1535342908 -125000: 1797602927 -124000: 1277174958 -123000: 3114077321 -122000: 149498793 -121000: 864366602 -120000: 104510626 -119000: 1518395286 -118000: 3111302078 -117000: 3110116836 -116000: 3233967498 -115000: 1017896311 -114000: 692827001 -113000: 3779537224 -112000: 2905474934 -111000: 3465999202 -110000: 1915694049 -109000: 2628022627 -108000: 875271541 -107000: 2022225002 -106000: 1671971011 -105000: 3334748297 -104000: 1332184097 -103000: 1555681497 -102000: 3406253965 -101000: 4045141299 -100000: 3058680000 -99000: 555036606 -98000: 46275609 -97000: 3853135904 -96000: 4229006385 -95000: 4108164708 -94000: 2566945975 -93000: 3797900910 -92000: 3355992329 -91000: 1635484145 -90000: 1382023482 -89000: 3690432221 -88000: 1892056918 -87000: 1120722079 -86000: 2675052236 -85000: 4165748502 -84000: 10230467 -83000: 4138070209 -82000: 1570296924 -81000: 3126342757 -80000: 598265835 -79000: 541475291 -78000: 2784920265 -77000: 4169891577 -76000: 1101249184 -75000: 2090307927 -74000: 3780559777 -73000: 19873425 -72000: 1118190767 -71000: 3485912405 -70000: 1322638834 -69000: 1096526516 -68000: 1370553703 -67000: 3631120381 -66000: 1806420191 -65000: 2701118072 -64000: 483879470 -63000: 2124403158 -62000: 1877513812 -61000: 1289006766 -60000: 3733667461 -59000: 3457358686 -58000: 732502949 -57000: 3971773677 -56000: 883589946 -55000: 290212168 -54000: 2244967385 -53000: 3848247179 -52000: 2228476206 -51000: 2372703555 -50000: 1200411530 -49000: 2060190456 -48000: 2511902942 -47000: 4007272287 -46000: 2854231300 -45000: 2518671311 -44000: 815143404 -43000: 1972543143 -42000: 3063716128 -41000: 3326571310 -40000: 3180391453 -39000: 2568545510 -38000: 573110821 -37000: 3814257324 -36000: 4163248735 -35000: 943584186 -34000: 387069186 -33000: 3519377243 -32000: 3861206003 -31000: 2378381393 -30000: 3259365221 -29000: 3960625204 -28000: 3476394666 -27000: 1995310421 -26000: 1884341166 -25000: 3181801013 -24000: 116492838 -23000: 3276567587 -22000: 3693343729 -21000: 2595820568 -20000: 2397879436 -19000: 2692679578 -18000: 2368648652 -17000: 3098196844 -16000: 3913788179 -15000: 1240694507 -14000: 1586030084 -13000: 1211450031 -12000: 3458253062 -11000: 1804606651 -10000: 2128587109 -9000: 1894810186 -8000: 2221431098 -7000: 113605713 -6000: 4020003580 -5000: 2988041351 -4000: 2310084217 -3000: 1475476779 -2000: 760651391 -1000: 4031656975 -0: 2206428413 -Exiting @ tick 1253145998500 because target called exit() +637000: 2581848540 +636000: 4117852332 +635000: 329081094 +634000: 545393176 +633000: 3107247613 +632000: 897887463 +631000: 806367477 +630000: 1682157095 +629000: 1188376072 +628000: 4076707785 +627000: 3521684454 +626000: 3144526095 +625000: 1399223384 +624000: 3380494826 +623000: 4086509498 +622000: 1473819475 +621000: 638751284 +620000: 3149483163 +619000: 1489851375 +618000: 1447059134 +617000: 136329498 +616000: 1288452788 +615000: 3949816816 +614000: 318984246 +613000: 1019963195 +612000: 2875280299 +611000: 2997394777 +610000: 4014932807 +609000: 2291235006 +608000: 355450951 +607000: 201970399 +606000: 3626124461 +605000: 2207253273 +604000: 2243886712 +603000: 46791684 +602000: 3176322294 +601000: 1120582847 +600000: 411705454 +599000: 3162380308 +598000: 2732375303 +597000: 1376844609 +596000: 3003023122 +595000: 3869968535 +594000: 1327286554 +593000: 160655029 +592000: 2038558826 +591000: 3948772976 +590000: 439262378 +589000: 329537197 +588000: 3678661972 +587000: 4240182727 +586000: 2283602206 +585000: 1129811410 +584000: 2831949168 +583000: 1224559023 +582000: 3161562107 +581000: 2695467835 +580000: 1234192577 +579000: 1974816198 +578000: 449576701 +577000: 1424873035 +576000: 2370444290 +575000: 1743089134 +574000: 2624046998 +573000: 2071148441 +572000: 2449219691 +571000: 3774476172 +570000: 1111630327 +569000: 121721805 +568000: 2981212266 +567000: 3811833647 +566000: 3676851843 +565000: 1766252334 +564000: 1622887950 +563000: 1684409857 +562000: 1686489387 +561000: 610219569 +560000: 2705092362 +559000: 108031723 +558000: 1316736987 +557000: 2434129258 +556000: 1411819652 +555000: 1173886179 +554000: 3044539233 +553000: 151590417 +552000: 3759426289 +551000: 3451520306 +550000: 294242855 +549000: 890241051 +548000: 876385779 +547000: 119864600 +546000: 3065674956 +545000: 1670853168 +544000: 997261561 +543000: 660227344 +542000: 3132294889 +541000: 521956271 +540000: 1133928405 +539000: 3838154786 +538000: 58624572 +537000: 3544030439 +536000: 432804999 +535000: 1021857051 +534000: 2644812356 +533000: 773094580 +532000: 901027171 +531000: 3976696839 +530000: 4167278216 +529000: 504481120 +528000: 320399857 +527000: 638048690 +526000: 3348998474 +525000: 2660662065 +524000: 2641437803 +523000: 626927006 +522000: 4063917554 +521000: 3212249308 +520000: 2561025301 +519000: 1078140141 +518000: 653939181 +517000: 2154098204 +516000: 3773089676 +515000: 2568381435 +514000: 3838886937 +513000: 941125346 +512000: 1318900410 +511000: 297013287 +510000: 241723934 +509000: 1835499795 +508000: 2309451230 +507000: 1174814430 +506000: 3615943386 +505000: 51034971 +504000: 3950453295 +503000: 4186097241 +502000: 327518343 +501000: 3052462710 +500000: 1586937404 +499000: 2169094819 +498000: 3613195151 +497000: 817359591 +496000: 1470916579 +495000: 2091261583 +494000: 2080080890 +493000: 1772858697 +492000: 2085609872 +491000: 3280632925 +490000: 1689322569 +489000: 2947406469 +488000: 765163324 +487000: 3122594732 +486000: 3385418480 +485000: 1712345567 +484000: 3675825158 +483000: 1558929764 +482000: 2672493410 +481000: 3822528440 +480000: 3741769935 +479000: 2794026235 +478000: 2541364185 +477000: 3964482316 +476000: 1202478165 +475000: 4027617791 +474000: 1905026738 +473000: 2573787636 +472000: 1170529797 +471000: 2272525618 +470000: 820833429 +469000: 3219769529 +468000: 2121197441 +467000: 269331764 +466000: 3038487237 +465000: 2462675338 +464000: 2703163101 +463000: 547052037 +462000: 3454526671 +461000: 2124641794 +460000: 1043737466 +459000: 1785834964 +458000: 3312335313 +457000: 1213835042 +456000: 3099430685 +455000: 3003350806 +454000: 3646781335 +453000: 1474165966 +452000: 705795987 +451000: 2723908407 +450000: 1323056304 +449000: 1157256530 +448000: 4077983523 +447000: 3189085703 +446000: 2241002747 +445000: 3229050072 +444000: 3500150226 +443000: 1290722604 +442000: 1866107725 +441000: 4238277470 +440000: 847346408 +439000: 2474557496 +438000: 2243092317 +437000: 706909230 +436000: 1303503693 +435000: 1456129560 +434000: 1073061079 +433000: 692226634 +432000: 186498656 +431000: 2203415525 +430000: 2183000701 +429000: 1007776545 +428000: 941117387 +427000: 3805851413 +426000: 1474193180 +425000: 4231673903 +424000: 2622576664 +423000: 388097625 +422000: 1165097488 +421000: 3226044518 +420000: 2531461570 +419000: 1509806310 +418000: 2667519114 +417000: 1751592438 +416000: 1286773513 +415000: 1098182293 +414000: 2111912709 +413000: 1230737431 +412000: 4090873946 +411000: 3998652133 +410000: 2486660396 +409000: 2120483596 +408000: 587404533 +407000: 188697995 +406000: 3265346093 +405000: 4234961905 +404000: 1211873901 +403000: 4265173305 +402000: 2208355316 +401000: 3315952806 +400000: 3917328941 +399000: 2523594649 +398000: 3805986783 +397000: 2624925960 +396000: 3716020189 +395000: 2016201122 +394000: 912930261 +393000: 596904160 +392000: 3571173642 +391000: 2290782861 +390000: 1162492227 +389000: 1738718380 +388000: 2599667355 +387000: 2382332909 +386000: 1471269037 +385000: 2238392684 +384000: 4034826126 +383000: 1378654892 +382000: 3702601850 +381000: 397206179 +380000: 2437704230 +379000: 4187604139 +378000: 779452169 +377000: 2010372403 +376000: 531902409 +375000: 1371470602 +374000: 4137796987 +373000: 567426549 +372000: 3082742955 +371000: 2271575596 +370000: 759731212 +369000: 4063369437 +368000: 299356452 +367000: 536656228 +366000: 3014961694 +365000: 3016542135 +364000: 2841873124 +363000: 524434057 +362000: 2887828889 +361000: 3865529589 +360000: 671363647 +359000: 3104594256 +358000: 1502485940 +357000: 1776624159 +356000: 4222478488 +355000: 4127624139 +354000: 2439477793 +353000: 1593794891 +352000: 591275342 +351000: 2177291538 +350000: 1923444781 +349000: 758084193 +348000: 775471359 +347000: 191356974 +346000: 494488375 +345000: 1990489399 +344000: 124118372 +343000: 2046377904 +342000: 1395427716 +341000: 1342299790 +340000: 38145994 +339000: 2291884417 +338000: 351940574 +337000: 3984301480 +336000: 2468666235 +335000: 371500747 +334000: 969922131 +333000: 240854580 +332000: 1644465214 +331000: 1539846168 +330000: 940087216 +329000: 1491329232 +328000: 2281687201 +327000: 3030170550 +326000: 3648503863 +325000: 2037898355 +324000: 174369956 +323000: 2433605668 +322000: 2334905107 +321000: 1597704047 +320000: 302297707 +319000: 3209203690 +318000: 3894539879 +317000: 2868907580 +316000: 2808087076 +315000: 4034586233 +314000: 3694191694 +313000: 2001671958 +312000: 559582279 +311000: 3043016195 +310000: 2785098502 +309000: 4104602138 +308000: 966154914 +307000: 2446376687 +306000: 789956605 +305000: 1708137092 +304000: 1733063901 +303000: 2924555399 +302000: 971356234 +301000: 481382543 +300000: 2647080988 +299000: 4065744916 +298000: 921140 +297000: 654346784 +296000: 485492098 +295000: 217516816 +294000: 4050820137 +293000: 534726686 +292000: 1686691079 +291000: 1316587195 +290000: 3746020838 +289000: 1641967381 +288000: 3492475215 +287000: 3154885393 +286000: 3686450617 +285000: 3589739293 +284000: 3558041700 +283000: 4130142319 +282000: 3132446063 +281000: 982677436 +280000: 799322395 +279000: 151715214 +278000: 3765942871 +277000: 1712470933 +276000: 3807622752 +275000: 4163730108 +274000: 1633425299 +273000: 1654241631 +272000: 1131025394 +271000: 1375475855 +270000: 553294237 +269000: 4091487177 +268000: 2841855980 +267000: 2997369904 +266000: 454385594 +265000: 3757482634 +264000: 3856197465 +263000: 1084605457 +262000: 2552759023 +261000: 3786548799 +260000: 272762545 +259000: 2670277860 +258000: 76233700 +257000: 476168167 +256000: 8969192 +255000: 1998841030 +254000: 1240074303 +253000: 1771564446 +252000: 710374418 +251000: 821383716 +250000: 3157726088 +249000: 3083379502 +248000: 2563632690 +247000: 33723341 +246000: 3303336748 +245000: 4110677892 +244000: 3811702913 +243000: 53856215 +242000: 243571468 +241000: 52177779 +240000: 46805590 +239000: 1622010618 +238000: 1321640849 +237000: 3106837291 +236000: 4102944642 +235000: 137904396 +234000: 339510135 +233000: 88415957 +232000: 3157666382 +231000: 2571005912 +230000: 3586247649 +229000: 4172761781 +228000: 2463305780 +227000: 956927307 +226000: 2169861547 +225000: 1751989251 +224000: 673059158 +223000: 2782464516 +222000: 3741392140 +221000: 2856154963 +220000: 3778376854 +219000: 1538476717 +218000: 2879698522 +217000: 3734645735 +216000: 1899042577 +215000: 371356008 +214000: 2416663698 +213000: 1595919347 +212000: 2816045438 +211000: 132438808 +210000: 1098603890 +209000: 834913667 +208000: 2707567283 +207000: 3154122448 +206000: 3696516104 +205000: 1427952551 +204000: 280496321 +203000: 1185678745 +202000: 3461951699 +201000: 1369208434 +200000: 3900136261 +199000: 870818876 +198000: 327248310 +197000: 3116959470 +196000: 1544241188 +195000: 1568248814 +194000: 2978831302 +193000: 205660429 +192000: 1704239501 +191000: 3570135474 +190000: 3878512103 +189000: 1212729210 +188000: 1873588815 +187000: 324853813 +186000: 432676298 +185000: 1641364437 +184000: 1568401301 +183000: 525792402 +182000: 861154382 +181000: 2357325066 +180000: 3626762590 +179000: 4172125462 +178000: 2108738993 +177000: 2084782857 +176000: 3956924509 +175000: 17183073 +174000: 3676839474 +173000: 458250029 +172000: 2635215219 +171000: 1801029767 +170000: 3602628987 +169000: 370704281 +168000: 177963345 +167000: 924067814 +166000: 3577678376 +165000: 3717789117 +164000: 3285809386 +163000: 3738962897 +162000: 3172510171 +161000: 417992786 +160000: 2591600214 +159000: 3315096579 +158000: 3590763949 +157000: 198872871 +156000: 2960653534 +155000: 2246563682 +154000: 2304045306 +153000: 2647353543 +152000: 2043381015 +151000: 3952056867 +150000: 2644058641 +149000: 3477151018 +148000: 1740210241 +147000: 3314851112 +146000: 1604832482 +145000: 2572410736 +144000: 1965059167 +143000: 889666293 +142000: 1024747903 +141000: 226685285 +140000: 3149168519 +139000: 403638872 +138000: 1725889104 +137000: 1417402331 +136000: 422304488 +135000: 2595894054 +134000: 4266597695 +133000: 1116326556 +132000: 3537080833 +131000: 2181246909 +130000: 1241997223 +129000: 628191304 +128000: 3074132403 +127000: 2112958836 +126000: 1371260930 +125000: 2272975771 +124000: 1379085607 +123000: 1998991877 +122000: 2760271255 +121000: 3784187756 +120000: 311188417 +119000: 1123593459 +118000: 1249155194 +117000: 908703020 +116000: 3765244393 +115000: 3040869794 +114000: 437536659 +113000: 3343598822 +112000: 2419089776 +111000: 1263143640 +110000: 1384687523 +109000: 1727931349 +108000: 2861733388 +107000: 963829093 +106000: 431354627 +105000: 3568623360 +104000: 2957399361 +103000: 1071045618 +102000: 3968457714 +101000: 3448338394 +100000: 2586060251 +99000: 3401651822 +98000: 1579089478 +97000: 3722618916 +96000: 759319595 +95000: 1269278712 +94000: 150489448 +93000: 390013662 +92000: 3663029784 +91000: 555197170 +90000: 166476858 +89000: 1658807720 +88000: 3430520531 +87000: 2946861093 +86000: 3000600326 +85000: 300034452 +84000: 2813719249 +83000: 3009927425 +82000: 1127728469 +81000: 2667791855 +80000: 2632316050 +79000: 2180301200 +78000: 418999983 +77000: 4254858933 +76000: 2728734498 +75000: 1863202698 +74000: 4226419921 +73000: 1917572494 +72000: 3117082625 +71000: 1032601538 +70000: 2992135524 +69000: 670119660 +68000: 638731522 +67000: 1460114012 +66000: 1232274665 +65000: 3667669961 +64000: 191277965 +63000: 3868442802 +62000: 700664540 +61000: 2271087482 +60000: 3274078227 +59000: 159900296 +58000: 2778747772 +57000: 2788477153 +56000: 3965957780 +55000: 2276993918 +54000: 1986966104 +53000: 3416414682 +52000: 2162594060 +51000: 2947744069 +50000: 4024793290 +49000: 631161701 +48000: 728285173 +47000: 1487641693 +46000: 4049519424 +45000: 613160608 +44000: 1566126172 +43000: 3731725133 +42000: 2746368727 +41000: 4168967735 +40000: 1319649932 +39000: 2964978784 +38000: 967937134 +37000: 3116555742 +36000: 2279790642 +35000: 2852914953 +34000: 1040410911 +33000: 226200467 +32000: 1765748697 +31000: 1418838964 +30000: 1362983292 +29000: 2877029789 +28000: 583076938 +27000: 2797138728 +26000: 3033567067 +25000: 3902265889 +24000: 3287868661 +23000: 2411740885 +22000: 2747756860 +21000: 1889759908 +20000: 2975722149 +19000: 3027693370 +18000: 2418258302 +17000: 490864179 +16000: 1944489573 +15000: 4212838860 +14000: 1782397962 +13000: 1981080238 +12000: 1213651424 +11000: 1407527546 +10000: 661520991 +9000: 143129551 +8000: 3293448370 +7000: 764314400 +6000: 2246553770 +5000: 2459308892 +4000: 3776833152 +3000: 2208260083 +2000: 2845746745 +1000: 2068042552 +0: 290958364 +Exiting @ tick 545056655500 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index 3406c4e55..ab62c741a 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.545057 # Nu sim_ticks 545056655500 # Number of ticks simulated final_tick 545056655500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 182072 # Simulator instruction rate (inst/s) -host_op_rate 224154 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 154902851 # Simulator tick rate (ticks/s) -host_mem_usage 321108 # Number of bytes of host memory used -host_seconds 3518.70 # Real time elapsed on the host +host_inst_rate 122221 # Simulator instruction rate (inst/s) +host_op_rate 150470 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 103982941 # Simulator tick rate (ticks/s) +host_mem_usage 247272 # Number of bytes of host memory used +host_seconds 5241.79 # Real time elapsed on the host sim_insts 640655084 # Number of instructions simulated sim_ops 788730743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -193,20 +193,20 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 112305 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 203.035662 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 132.214062 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 254.437736 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 47268 42.09% 42.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43750 38.96% 81.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8988 8.00% 89.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1909 1.70% 90.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 489 0.44% 91.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 112303 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 203.039278 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 132.213865 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 254.441282 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 47271 42.09% 42.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43737 38.95% 81.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8997 8.01% 89.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1907 1.70% 90.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 490 0.44% 91.18% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 737 0.66% 91.84% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 726 0.65% 92.49% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 505 0.45% 92.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 7933 7.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 112305 # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 112303 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4009 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 48.526066 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::gmean 36.050433 # Reads before turning the bus around for writes @@ -223,12 +223,12 @@ system.physmem.wrPerTurnAround::stdev 0.855134 # Wr system.physmem.wrPerTurnAround::16 3044 75.93% 75.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::18 965 24.07% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4009 # Writes before turning the bus around for reads -system.physmem.totQLat 2737356250 # Total ticks spent queuing -system.physmem.totMemAccLat 8179187500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 2738025750 # Total ticks spent queuing +system.physmem.totMemAccLat 8179857000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1451155000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9431.65 # Average queueing delay per DRAM burst +system.physmem.avgQLat 9433.95 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28181.65 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28183.95 # Average memory access latency per DRAM burst system.physmem.avgRdBW 34.08 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 7.76 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 34.11 # Average system read bandwidth in MiByte/s @@ -239,39 +239,39 @@ system.physmem.busUtilRead 0.27 # Da system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 23.96 # Average write queue length when enqueuing -system.physmem.readRowHits 193898 # Number of row buffer hits during reads +system.physmem.readRowHits 193900 # Number of row buffer hits during reads system.physmem.writeRowHits 50093 # Number of row buffer hits during writes system.physmem.readRowHitRate 66.81 # Row buffer hit rate for reads system.physmem.writeRowHitRate 75.79 # Row buffer hit rate for writes system.physmem.avgGap 1528348.80 # Average gap between requests system.physmem.pageHitRate 68.47 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 424002600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 231350625 # Energy for precharge commands per rank (pJ) +system.physmem_0.actEnergy 424055520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 231379500 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 1134369600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 215570160 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 35600217120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 106884947925 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 233273273250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 377763731280 # Total energy per rank (pJ) -system.physmem_0.averagePower 693.076638 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 387358600750 # Time in different power states +system.physmem_0.actBackEnergy 106906564890 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 233254311000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 377766467790 # Total energy per rank (pJ) +system.physmem_0.averagePower 693.081659 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 387327017750 # Time in different power states system.physmem_0.memoryStateTime::REF 18200520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 139494961250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 139526544250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 424962720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 231874500 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 424894680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 231837375 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1129096800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 212589360 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 35600217120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 105917359815 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 234122034750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 377638135065 # Total energy per rank (pJ) -system.physmem_1.averagePower 692.846209 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 388771820250 # Time in different power states +system.physmem_1.actBackEnergy 105911923725 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 234126803250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 377637362310 # Total energy per rank (pJ) +system.physmem_1.averagePower 692.844791 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 388779883250 # Time in different power states system.physmem_1.memoryStateTime::REF 18200520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 138081006000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 138072943000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 155213668 # Number of BP lookups system.cpu.branchPred.condPredicted 105449696 # Number of conditional branches predicted @@ -409,13 +409,13 @@ system.cpu.discardedOps 22623250 # Nu system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.701560 # CPI: cycles per instruction system.cpu.ipc 0.587696 # IPC: instructions per cycle -system.cpu.tickCycles 1030411592 # Number of cycles that the object actually ticked -system.cpu.idleCycles 59701719 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 1030410775 # Number of cycles that the object actually ticked +system.cpu.idleCycles 59702536 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 778141 # number of replacements system.cpu.dcache.tags.tagsinuse 4092.460106 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 378456482 # Total number of references to valid blocks. +system.cpu.dcache.tags.total_refs 378456342 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 782237 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 483.813067 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 483.812888 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 802330000 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 4092.460106 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999136 # Average percentage of cache occupancy @@ -429,62 +429,70 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1594 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 759397955 # Number of tag accesses system.cpu.dcache.tags.data_accesses 759397955 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 249631239 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 249631239 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 249627614 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 249627614 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 128813765 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 128813765 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 3485 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 3485 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 378445004 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 378445004 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 378445004 # number of overall hits -system.cpu.dcache.overall_hits::total 378445004 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 713665 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 713665 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 378441379 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 378441379 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 378444864 # number of overall hits +system.cpu.dcache.overall_hits::total 378444864 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 713664 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 713664 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 137712 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 137712 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 851377 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 851377 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 851377 # number of overall misses -system.cpu.dcache.overall_misses::total 851377 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24698082718 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24698082718 # number of ReadReq miss cycles +system.cpu.dcache.SoftPFReq_misses::cpu.data 141 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 141 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 851376 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 851376 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 851517 # number of overall misses +system.cpu.dcache.overall_misses::total 851517 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24697977718 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24697977718 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 10190251750 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 10190251750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34888334468 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34888334468 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34888334468 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34888334468 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 250344904 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 250344904 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 34888229468 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34888229468 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34888229468 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34888229468 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 250341278 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250341278 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 3626 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 3626 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 379296381 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 379296381 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 379292755 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 379292755 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 379296381 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 379296381 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002851 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002851 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001068 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001068 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038886 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.038886 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.002245 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002245 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34607.389627 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34607.389627 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34607.290991 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34607.290991 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73996.832157 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 73996.832157 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40978.713858 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40978.713858 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40978.713858 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40978.713858 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40978.638660 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40978.638660 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40971.853137 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40971.853137 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -495,54 +503,62 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 91420 # number of writebacks system.cpu.dcache.writebacks::total 91420 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 750 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 750 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 888 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 888 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68390 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 68390 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 69140 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 69140 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 69140 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 69140 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712915 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712915 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 69278 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 69278 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 69278 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 69278 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712776 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712776 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69322 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 69322 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 782237 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 782237 # number of demand (read+write) MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 782098 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 782098 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 782237 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 782237 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23543649027 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23543649027 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23542622277 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23542622277 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5045531250 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 5045531250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28589180277 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28589180277 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28589180277 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28589180277 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002848 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1719000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1719000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28588153527 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28588153527 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28589872527 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28589872527 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038334 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038334 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33024.482620 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33024.482620 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33029.482302 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33029.482302 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72783.982718 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72783.982718 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36547.977502 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36547.977502 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36547.977502 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 36547.977502 # average overall mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12366.906475 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12366.906475 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36553.160252 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36553.160252 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36548.862464 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 36548.862464 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 23596 # number of replacements -system.cpu.icache.tags.tagsinuse 1712.064969 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1712.064970 # Cycle average of tags in use system.cpu.icache.tags.total_refs 291953853 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 25347 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 11518.280388 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1712.064969 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1712.064970 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.835969 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.835969 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id @@ -564,12 +580,12 @@ system.cpu.icache.demand_misses::cpu.inst 25348 # n system.cpu.icache.demand_misses::total 25348 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 25348 # number of overall misses system.cpu.icache.overall_misses::total 25348 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 499968245 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 499968245 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 499968245 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 499968245 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 499968245 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 499968245 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 499948995 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 499948995 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 499948995 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 499948995 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 499948995 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 499948995 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 291979201 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 291979201 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 291979201 # number of demand (read+write) accesses @@ -582,12 +598,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19724.169362 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19724.169362 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19724.169362 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19724.169362 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19724.169362 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19724.169362 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19723.409934 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19723.409934 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19723.409934 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19723.409934 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19723.409934 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19723.409934 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -602,34 +618,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 25348 system.cpu.icache.demand_mshr_misses::total 25348 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 25348 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 25348 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 460840255 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 460840255 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 460840255 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 460840255 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 460840255 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 460840255 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 460820505 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 460820505 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 460820505 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 460820505 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 460820505 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 460820505 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18180.537123 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18180.537123 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18180.537123 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18180.537123 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18180.537123 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18180.537123 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18179.757969 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18179.757969 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18179.757969 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18179.757969 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18179.757969 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18179.757969 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 257753 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32573.758002 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 32573.758043 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 538992 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 290497 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.855413 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2882.231587 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.601373 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29601.925042 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 2882.231572 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.601388 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29601.925083 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.087959 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002734 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.903379 # Average percentage of cache occupancy @@ -667,17 +683,17 @@ system.cpu.l2cache.demand_misses::total 290566 # nu system.cpu.l2cache.overall_misses::cpu.inst 2582 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 287984 # number of overall misses system.cpu.l2cache.overall_misses::total 290566 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 196449750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17674937000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17871386750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 196430000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17675629250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 17872059250 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4942281750 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 4942281750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 196449750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 22617218750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22813668500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 196449750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 22617218750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22813668500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 196430000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 22617911000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22814341000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 196430000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 22617911000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22814341000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 25348 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 712915 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 738263 # number of ReadReq accesses(hits+misses) @@ -702,17 +718,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.359796 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.101862 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.368154 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.359796 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76084.333850 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79655.225717 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 79614.151910 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76076.684741 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79658.345464 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 79617.147789 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74779.951128 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74779.951128 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76084.333850 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78536.372680 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 78514.583606 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76084.333850 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78536.372680 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 78514.583606 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76076.684741 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78538.776460 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78516.898054 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76076.684741 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78538.776460 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78516.898054 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -743,17 +759,17 @@ system.cpu.l2cache.demand_mshr_misses::total 290534 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2577 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 287957 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 290534 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 163845000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14897681250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15061526250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 163824250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14898374500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15062198750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4113937750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4113937750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 163845000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19011619000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19175464000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 163845000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19011619000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19175464000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 163824250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19012312250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19176136500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 163824250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19012312250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19176136500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.101665 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311210 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.304015 # mshr miss rate for ReadReq accesses @@ -765,17 +781,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.359757 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101665 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368120 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.359757 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63579.743888 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67147.202591 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67106.241897 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63571.691890 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67150.327225 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67109.238203 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62246.565342 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62246.565342 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63579.743888 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66022.423487 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66000.757226 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63579.743888 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66022.423487 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66000.757226 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63571.691890 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66024.830964 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66003.071930 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63571.691890 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66024.830964 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66003.071930 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 738263 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 738262 # Transaction distribution @@ -804,9 +820,9 @@ system.cpu.toL2Bus.snoop_fanout::max_value 3 # system.cpu.toL2Bus.snoop_fanout::total 899005 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 540922500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 38574245 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 38574495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1224003723 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1224002973 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.trans_dist::ReadReq 224442 # Transaction distribution system.membus.trans_dist::ReadResp 224442 # Transaction distribution @@ -828,9 +844,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 356631 # Request fanout histogram -system.membus.reqLayer0.occupancy 731515500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 731518000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1551221000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1551221500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini index fd6ea1264..97bcd61c2 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini @@ -23,6 +23,7 @@ load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem +mmap_using_noreserve=false num_work_ids=16 readfile= symbolfile= @@ -132,6 +133,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -166,6 +168,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +sys=system tlb=system.cpu.dtb [system.cpu.dstage2_mmu.stage2_tlb] @@ -183,7 +186,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[5] [system.cpu.dtb] type=ArmTLB @@ -591,6 +593,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -651,6 +654,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu.istage2_mmu] @@ -658,6 +662,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +sys=system tlb=system.cpu.itb [system.cpu.istage2_mmu.stage2_tlb] @@ -675,7 +680,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB @@ -700,6 +704,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -733,13 +738,16 @@ size=2097152 type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 -header_cycles=1 +forward_latency=0 +frontend_latency=1 +response_latency=1 snoop_filter=Null +snoop_response_latency=1 system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -749,14 +757,16 @@ eventq_index=0 type=LiveProcess cmd=vortex lendian.raw cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing +drivers= egid=100 env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex +executable=/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -786,11 +796,14 @@ transition_latency=100000000 type=CoherentXBar clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=4 +frontend_latency=3 +response_latency=2 snoop_filter=Null +snoop_response_latency=4 system=system use_default_range=false -width=8 +width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side @@ -821,7 +834,7 @@ IDD62=0.000000 VDD=1.500000 VDD2=0.000000 activation_limit=4 -addr_mapping=RoRaBaChCo +addr_mapping=RoRaBaCoCh bank_groups_per_rank=0 banks_per_rank=8 burst_length=8 @@ -830,6 +843,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simerr b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simerr index 1a4f96712..341b479f7 100644..100755 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simerr +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simerr @@ -1 +1,2 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout index 0b495a4c8..0ebe6ca65 100644..100755 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout @@ -1,14 +1,12 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 7 2014 10:57:46 -gem5 started May 7 2014 17:09:29 -gem5 executing on cz3211bhr8 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing +gem5 compiled Mar 15 2015 20:30:55 +gem5 started Mar 15 2015 20:31:14 +gem5 executing on zizzer2 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0xcee8df0 + 0: system.cpu.isa: ISA system set to: 0 0x3b079b0 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 64581408500 because target called exit() +Exiting @ tick 57738195500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index 20f3ef2c3..6d11e3682 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058730 # Number of seconds simulated -sim_ticks 58730125500 # Number of ticks simulated -final_tick 58730125500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.057738 # Number of seconds simulated +sim_ticks 57738195500 # Number of ticks simulated +final_tick 57738195500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 197162 # Simulator instruction rate (inst/s) -host_op_rate 252141 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 163284235 # Simulator tick rate (ticks/s) -host_mem_usage 321164 # Number of bytes of host memory used -host_seconds 359.68 # Real time elapsed on the host +host_inst_rate 113055 # Simulator instruction rate (inst/s) +host_op_rate 144580 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 92047581 # Simulator tick rate (ticks/s) +host_mem_usage 250264 # Number of bytes of host memory used +host_seconds 627.26 # Real time elapsed on the host sim_insts 70915127 # Number of instructions simulated sim_ops 90690083 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 324352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7923392 # Number of bytes read from this memory -system.physmem.bytes_read::total 8247744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7922944 # Number of bytes read from this memory +system.physmem.bytes_read::total 8247296 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 324352 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 324352 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5372864 # Number of bytes written to this memory -system.physmem.bytes_written::total 5372864 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 5372992 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372992 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 5068 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 123803 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128871 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83951 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83951 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 5522753 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 134911886 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 140434639 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5522753 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5522753 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 91483952 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 91483952 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 91483952 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5522753 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 134911886 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 231918592 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128871 # Number of read requests accepted -system.physmem.writeReqs 83951 # Number of write requests accepted -system.physmem.readBursts 128871 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 83951 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8247360 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue -system.physmem.bytesWritten 5371136 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8247744 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5372864 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::cpu.data 123796 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128864 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83953 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83953 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 5617633 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 137221885 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 142839518 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5617633 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5617633 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 93057844 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 93057844 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 93057844 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 5617633 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 137221885 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 235897362 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128864 # Number of read requests accepted +system.physmem.writeReqs 83953 # Number of write requests accepted +system.physmem.readBursts 128864 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 83953 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 8246976 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue +system.physmem.bytesWritten 5371008 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8247296 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5372992 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 8159 # Per bank write bursts -system.physmem.perBankRdBursts::1 8376 # Per bank write bursts -system.physmem.perBankRdBursts::2 8228 # Per bank write bursts -system.physmem.perBankRdBursts::3 8171 # Per bank write bursts -system.physmem.perBankRdBursts::4 8319 # Per bank write bursts -system.physmem.perBankRdBursts::5 8450 # Per bank write bursts -system.physmem.perBankRdBursts::6 8088 # Per bank write bursts -system.physmem.perBankRdBursts::7 7969 # Per bank write bursts -system.physmem.perBankRdBursts::8 8071 # Per bank write bursts -system.physmem.perBankRdBursts::9 7640 # Per bank write bursts -system.physmem.perBankRdBursts::10 7818 # Per bank write bursts -system.physmem.perBankRdBursts::11 7832 # Per bank write bursts -system.physmem.perBankRdBursts::12 7881 # Per bank write bursts -system.physmem.perBankRdBursts::13 7879 # Per bank write bursts -system.physmem.perBankRdBursts::14 7977 # Per bank write bursts -system.physmem.perBankRdBursts::15 8007 # Per bank write bursts -system.physmem.perBankWrBursts::0 5180 # Per bank write bursts +system.physmem.perBankRdBursts::0 8158 # Per bank write bursts +system.physmem.perBankRdBursts::1 8374 # Per bank write bursts +system.physmem.perBankRdBursts::2 8229 # Per bank write bursts +system.physmem.perBankRdBursts::3 8170 # Per bank write bursts +system.physmem.perBankRdBursts::4 8316 # Per bank write bursts +system.physmem.perBankRdBursts::5 8449 # Per bank write bursts +system.physmem.perBankRdBursts::6 8089 # Per bank write bursts +system.physmem.perBankRdBursts::7 7971 # Per bank write bursts +system.physmem.perBankRdBursts::8 8070 # Per bank write bursts +system.physmem.perBankRdBursts::9 7642 # Per bank write bursts +system.physmem.perBankRdBursts::10 7819 # Per bank write bursts +system.physmem.perBankRdBursts::11 7829 # Per bank write bursts +system.physmem.perBankRdBursts::12 7880 # Per bank write bursts +system.physmem.perBankRdBursts::13 7877 # Per bank write bursts +system.physmem.perBankRdBursts::14 7978 # Per bank write bursts +system.physmem.perBankRdBursts::15 8008 # Per bank write bursts +system.physmem.perBankWrBursts::0 5182 # Per bank write bursts system.physmem.perBankWrBursts::1 5376 # Per bank write bursts system.physmem.perBankWrBursts::2 5285 # Per bank write bursts system.physmem.perBankWrBursts::3 5155 # Per bank write bursts system.physmem.perBankWrBursts::4 5266 # Per bank write bursts system.physmem.perBankWrBursts::5 5517 # Per bank write bursts system.physmem.perBankWrBursts::6 5197 # Per bank write bursts -system.physmem.perBankWrBursts::7 5050 # Per bank write bursts +system.physmem.perBankWrBursts::7 5047 # Per bank write bursts system.physmem.perBankWrBursts::8 5033 # Per bank write bursts -system.physmem.perBankWrBursts::9 5087 # Per bank write bursts +system.physmem.perBankWrBursts::9 5088 # Per bank write bursts system.physmem.perBankWrBursts::10 5251 # Per bank write bursts system.physmem.perBankWrBursts::11 5143 # Per bank write bursts system.physmem.perBankWrBursts::12 5343 # Per bank write bursts system.physmem.perBankWrBursts::13 5363 # Per bank write bursts system.physmem.perBankWrBursts::14 5451 # Per bank write bursts -system.physmem.perBankWrBursts::15 5227 # Per bank write bursts +system.physmem.perBankWrBursts::15 5225 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58730091000 # Total gap between requests +system.physmem.totGap 57738161000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128871 # Read request sizes (log2) +system.physmem.readPktSize::6 128864 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 83951 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 126560 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2284 # What read queue length does an incoming req see +system.physmem.writePktSize::6 83953 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 116707 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 12131 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,25 +144,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 603 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 615 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 19 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -193,98 +193,99 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38559 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 353.122851 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 215.043714 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.345734 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12150 31.51% 31.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8188 21.23% 52.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4125 10.70% 63.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2946 7.64% 71.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2498 6.48% 77.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1699 4.41% 81.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1309 3.39% 85.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1159 3.01% 88.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4485 11.63% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38559 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5160 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.968217 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 360.537784 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5158 99.96% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 38462 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 353.991784 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 215.320111 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 335.607526 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12100 31.46% 31.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8198 21.31% 52.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4148 10.78% 63.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2890 7.51% 71.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2484 6.46% 77.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1581 4.11% 81.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1319 3.43% 85.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1187 3.09% 88.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4555 11.84% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38462 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5156 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.974593 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 361.421207 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5153 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5160 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5160 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.264341 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.248462 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.748642 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4548 88.14% 88.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 7 0.14% 88.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 485 9.40% 97.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 104 2.02% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 10 0.19% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 3 0.06% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 2 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5160 # Writes before turning the bus around for reads -system.physmem.totQLat 1533027250 # Total ticks spent queuing -system.physmem.totMemAccLat 3949246000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 644325000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11896.38 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5156 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5156 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.276571 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.259351 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.782645 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4530 87.86% 87.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 9 0.17% 88.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 479 9.29% 97.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 112 2.17% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 15 0.29% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 8 0.16% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 2 0.04% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5156 # Writes before turning the bus around for reads +system.physmem.totQLat 1653247250 # Total ticks spent queuing +system.physmem.totMemAccLat 4069353500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 644295000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12829.89 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30646.38 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 140.43 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 91.45 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 140.43 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 91.48 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31579.89 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 142.83 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 93.02 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 142.84 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 93.06 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.81 # Data bus utilization in percentage -system.physmem.busUtilRead 1.10 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.71 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.44 # Average write queue length when enqueuing -system.physmem.readRowHits 112070 # Number of row buffer hits during reads -system.physmem.writeRowHits 62147 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.97 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.03 # Row buffer hit rate for writes -system.physmem.avgGap 275958.74 # Average gap between requests -system.physmem.pageHitRate 81.86 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 152069400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 82974375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 512499000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 272270160 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3835559520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 12264762105 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 24475931250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41596065810 # Total energy per rank (pJ) -system.physmem_0.averagePower 708.329716 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 40585694500 # Time in different power states -system.physmem_0.memoryStateTime::REF 1960920000 # Time in different power states +system.physmem.busUtil 1.84 # Data bus utilization in percentage +system.physmem.busUtilRead 1.12 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.73 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.36 # Average write queue length when enqueuing +system.physmem.readRowHits 112168 # Number of row buffer hits during reads +system.physmem.writeRowHits 62144 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.02 # Row buffer hit rate for writes +system.physmem.avgGap 271304.27 # Average gap between requests +system.physmem.pageHitRate 81.91 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 151283160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 82545375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 512694000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 272322000 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3770972400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 11678597190 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 24396798750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 40865212875 # Total energy per rank (pJ) +system.physmem_0.averagePower 707.802856 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 40459125250 # Time in different power states +system.physmem_0.memoryStateTime::REF 1927900000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16178034500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15348292250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 139308120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 76011375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 492024000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 271453680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3835559520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 11655970470 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 25009959000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41480286165 # Total energy per rank (pJ) -system.physmem_1.averagePower 706.358131 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 41477231750 # Time in different power states -system.physmem_1.memoryStateTime::REF 1960920000 # Time in different power states +system.physmem_1.actEnergy 139489560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 76110375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 492070800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 271492560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3770972400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 11151778680 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24858920250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 40760834625 # Total energy per rank (pJ) +system.physmem_1.averagePower 705.994980 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 41228847750 # Time in different power states +system.physmem_1.memoryStateTime::REF 1927900000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15286019500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14578569750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 14827059 # Number of BP lookups -system.cpu.branchPred.condPredicted 9919255 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 395881 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9555564 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6751205 # Number of BTB hits +system.cpu.branchPred.lookups 14838314 # Number of BP lookups +system.cpu.branchPred.condPredicted 9926302 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 397118 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9672403 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6752101 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.652083 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1718768 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 69.807896 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1719649 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -404,89 +405,97 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 117460251 # number of cpu cycles simulated +system.cpu.numCycles 115476391 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915127 # Number of instructions committed system.cpu.committedOps 90690083 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1148249 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1150638 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.656350 # CPI: cycles per instruction -system.cpu.ipc 0.603737 # IPC: instructions per cycle -system.cpu.tickCycles 97003390 # Number of cycles that the object actually ticked -system.cpu.idleCycles 20456861 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 156434 # number of replacements -system.cpu.dcache.tags.tagsinuse 4067.721714 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42666461 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 160530 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 265.784969 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 833735250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4067.721714 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993096 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993096 # Average percentage of cache occupancy +system.cpu.cpi 1.628375 # CPI: cycles per instruction +system.cpu.ipc 0.614109 # IPC: instructions per cycle +system.cpu.tickCycles 96920862 # Number of cycles that the object actually ticked +system.cpu.idleCycles 18555529 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 156418 # number of replacements +system.cpu.dcache.tags.tagsinuse 4067.282815 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42627759 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 160514 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 265.570349 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 830513250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.282815 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992989 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 710 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3342 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1135 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2916 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 86017904 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 86017904 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22990876 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22990876 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19643747 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19643747 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 86021754 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86021754 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22869180 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22869180 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19642188 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19642188 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 84553 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 84553 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42634623 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42634623 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42634623 # number of overall hits -system.cpu.dcache.overall_hits::total 42634623 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 56072 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 56072 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 206154 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 206154 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 262226 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 262226 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 262226 # number of overall misses -system.cpu.dcache.overall_misses::total 262226 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2301185937 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2301185937 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 16676998250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 16676998250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18978184187 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18978184187 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18978184187 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18978184187 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23046948 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23046948 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 42511368 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42511368 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42595921 # number of overall hits +system.cpu.dcache.overall_hits::total 42595921 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 51489 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 51489 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 207713 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 207713 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 43659 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 43659 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 259202 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 259202 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 302861 # number of overall misses +system.cpu.dcache.overall_misses::total 302861 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1477411436 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1477411436 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 16920342250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 16920342250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18397753686 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18397753686 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18397753686 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18397753686 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22920669 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22920669 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128212 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128212 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42896849 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42896849 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42896849 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42896849 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002433 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002433 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010386 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.010386 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.006113 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.006113 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.006113 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.006113 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41039.840509 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41039.840509 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80895.826664 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 80895.826664 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72373.388554 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72373.388554 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72373.388554 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72373.388554 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 42770570 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42770570 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42898782 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42898782 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002246 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002246 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010464 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010464 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.340522 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.340522 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.006060 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006060 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007060 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007060 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28693.729457 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28693.729457 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81460.198688 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 81460.198688 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70978.440313 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70978.440313 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60746.526248 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60746.526248 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -495,102 +504,110 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128445 # number of writebacks -system.cpu.dcache.writebacks::total 128445 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2576 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2576 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 99120 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 99120 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 101696 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 101696 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 101696 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 101696 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53496 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 53496 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107034 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107034 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 160530 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 160530 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 160530 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 160530 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2163468813 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2163468813 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8402400750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8402400750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10565869563 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10565869563 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10565869563 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10565869563 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002321 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002321 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 128435 # number of writebacks +system.cpu.dcache.writebacks::total 128435 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21989 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 21989 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100683 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 100683 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 122672 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 122672 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 122672 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 122672 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29500 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 29500 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107030 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107030 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23984 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 23984 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 136530 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 136530 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 160514 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 160514 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 558489314 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 558489314 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8444692500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8444692500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1685620500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1685620500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9003181814 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9003181814 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10688802314 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10688802314 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001287 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001287 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003742 # mshr miss rate for demand accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187065 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187065 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003192 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003192 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40441.693080 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40441.693080 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78502.165200 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78502.165200 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65818.660456 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 65818.660456 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65818.660456 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 65818.660456 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18931.841153 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18931.841153 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78900.238251 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78900.238251 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70281.041528 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70281.041528 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65942.882985 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 65942.882985 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66591.090584 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66591.090584 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 42774 # number of replacements -system.cpu.icache.tags.tagsinuse 1856.910000 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25093452 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 44816 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 559.921724 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 42756 # number of replacements +system.cpu.icache.tags.tagsinuse 1854.448619 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25096729 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 44798 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 560.219854 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1856.910000 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.906694 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.906694 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1854.448619 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.905492 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.905492 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 730 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1192 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 918 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1004 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 50321354 # Number of tag accesses -system.cpu.icache.tags.data_accesses 50321354 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 25093452 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25093452 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25093452 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25093452 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25093452 # number of overall hits -system.cpu.icache.overall_hits::total 25093452 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 44817 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 44817 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 44817 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 44817 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 44817 # number of overall misses -system.cpu.icache.overall_misses::total 44817 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 937886990 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 937886990 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 937886990 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 937886990 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 937886990 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 937886990 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25138269 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25138269 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25138269 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25138269 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25138269 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25138269 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001783 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001783 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001783 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001783 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001783 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001783 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20927.036392 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20927.036392 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20927.036392 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20927.036392 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20927.036392 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20927.036392 # average overall miss latency +system.cpu.icache.tags.tag_accesses 50327854 # Number of tag accesses +system.cpu.icache.tags.data_accesses 50327854 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 25096729 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25096729 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25096729 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25096729 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25096729 # number of overall hits +system.cpu.icache.overall_hits::total 25096729 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 44799 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 44799 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 44799 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 44799 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 44799 # number of overall misses +system.cpu.icache.overall_misses::total 44799 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 934736739 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 934736739 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 934736739 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 934736739 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 934736739 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 934736739 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25141528 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25141528 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25141528 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25141528 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25141528 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25141528 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001782 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001782 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001782 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001782 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001782 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001782 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20865.125092 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20865.125092 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20865.125092 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20865.125092 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20865.125092 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20865.125092 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -599,123 +616,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44817 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 44817 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 44817 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 44817 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 44817 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 44817 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 868759010 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 868759010 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 868759010 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 868759010 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 868759010 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 868759010 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001783 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001783 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001783 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001783 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001783 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001783 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19384.586429 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19384.586429 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19384.586429 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19384.586429 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19384.586429 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19384.586429 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44799 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 44799 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 44799 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 44799 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 44799 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 44799 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 865619261 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 865619261 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 865619261 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 865619261 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 865619261 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 865619261 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001782 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001782 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001782 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001782 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001782 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001782 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19322.289806 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19322.289806 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19322.289806 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19322.289806 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19322.289806 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19322.289806 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 95733 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29885.598621 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 99802 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 126851 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.786766 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 95726 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29866.578850 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 99768 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 126844 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.786541 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26636.535052 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1559.339588 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1689.723980 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.812883 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047587 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.051566 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.912036 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 26746.709888 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1560.467773 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1559.401189 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.816245 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047622 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.047589 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.911456 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31118 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1015 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9129 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20264 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 591 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1811 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12771 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15838 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 578 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949646 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 2904221 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 2904221 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 39738 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 31910 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 71648 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 128445 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 128445 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4754 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4754 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 39738 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 36664 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 76402 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 39738 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 36664 # number of overall hits -system.cpu.l2cache.overall_hits::total 76402 # number of overall hits +system.cpu.l2cache.tags.tag_accesses 2903858 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 2903858 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 39720 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 31906 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 71626 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 128435 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 128435 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 4748 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4748 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 39720 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 36654 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 76374 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 39720 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 36654 # number of overall hits +system.cpu.l2cache.overall_hits::total 76374 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 5079 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 21586 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 26665 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 102280 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 102280 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 21578 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 26657 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 102282 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 102282 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 5079 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 123866 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 128945 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 123860 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 128939 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 5079 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 123866 # number of overall misses -system.cpu.l2cache.overall_misses::total 128945 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 406663000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1774587250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2181250250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8245411750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8245411750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 406663000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10019999000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10426662000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 406663000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10019999000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10426662000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 44817 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 53496 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 98313 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 128445 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 128445 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 107034 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 107034 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 44817 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 160530 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 205347 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 44817 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 160530 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 205347 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113328 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.403507 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.271226 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955584 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.955584 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.113328 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.771607 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.627937 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113328 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.771607 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.627937 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80067.532979 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82210.101455 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 81801.997000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80616.071079 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80616.071079 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80067.532979 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80893.861108 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 80861.312963 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80067.532979 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80893.861108 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 80861.312963 # average overall miss latency +system.cpu.l2cache.overall_misses::cpu.data 123860 # number of overall misses +system.cpu.l2cache.overall_misses::total 128939 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 403732250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1855266750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2258999000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8287771000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8287771000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 403732250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10143037750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10546770000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 403732250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10143037750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10546770000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 44799 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 53484 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 98283 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 128435 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 128435 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 107030 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 107030 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 44799 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 160514 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 205313 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 44799 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 160514 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 205313 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113373 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.403448 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.271227 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955639 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.955639 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.113373 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.771646 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.628012 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113373 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.771646 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.628012 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79490.500098 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85979.550932 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 84743.181903 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81028.636515 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81028.636515 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79490.500098 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81891.149281 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81796.585983 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79490.500098 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81891.149281 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81796.585983 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -724,116 +741,116 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 83951 # number of writebacks -system.cpu.l2cache.writebacks::total 83951 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 83953 # number of writebacks +system.cpu.l2cache.writebacks::total 83953 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 10 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 10 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 63 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 64 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 10 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 63 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 64 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 74 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5069 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21523 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 26592 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102280 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102280 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21514 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 26583 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102282 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102282 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 5069 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 123803 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 128872 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 123796 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128865 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 5069 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 123803 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 128872 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 342505250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1501079000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1843584250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6966637250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6966637250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 342505250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8467716250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8810221500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 342505250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8467716250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8810221500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113104 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.402329 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.270483 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955584 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955584 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113104 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771214 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.627582 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113104 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771214 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.627582 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67568.603275 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69743.019096 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69328.529257 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68113.387270 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68113.387270 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67568.603275 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68396.696768 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68364.124868 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67568.603275 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68396.696768 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68364.124868 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.data 123796 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128865 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 339459750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1581559750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1921019500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7009102000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7009102000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 339459750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8590661750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8930121500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 339459750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8590661750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8930121500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113150 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.402251 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.270474 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955639 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955639 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113150 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771247 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.627651 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113150 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771247 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.627651 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66967.794437 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73513.049642 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72264.962570 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68527.228642 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68527.228642 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66967.794437 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69393.694061 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69298.269507 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66967.794437 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69393.694061 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69298.269507 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 98313 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 98312 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 128445 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107034 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107034 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89633 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449505 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 539138 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2868224 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18494400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 21362624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 98283 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 98282 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 128435 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107030 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107030 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89597 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449463 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 539060 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2867072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18492736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 21359808 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 333792 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 333748 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 333792 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 333748 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 333792 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 295341000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 333748 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 295309000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 68175990 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 68157239 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 268644937 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 268247686 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadReq 26591 # Transaction distribution -system.membus.trans_dist::ReadResp 26591 # Transaction distribution -system.membus.trans_dist::Writeback 83951 # Transaction distribution -system.membus.trans_dist::ReadExReq 102280 # Transaction distribution -system.membus.trans_dist::ReadExResp 102280 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341693 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 341693 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620608 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13620608 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 26582 # Transaction distribution +system.membus.trans_dist::ReadResp 26582 # Transaction distribution +system.membus.trans_dist::Writeback 83953 # Transaction distribution +system.membus.trans_dist::ReadExReq 102282 # Transaction distribution +system.membus.trans_dist::ReadExResp 102282 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341681 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 341681 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13620288 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 212822 # Request fanout histogram +system.membus.snoop_fanout::samples 212817 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 212822 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 212817 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 212822 # Request fanout histogram -system.membus.reqLayer0.occupancy 579596500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 212817 # Request fanout histogram +system.membus.reqLayer0.occupancy 578407500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 680391500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 680129500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini index 55081d3ef..634fc5445 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini @@ -23,6 +23,7 @@ load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem +mmap_using_noreserve=false num_work_ids=16 readfile= symbolfile= @@ -132,6 +133,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -166,6 +168,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +sys=system tlb=system.cpu.dtb [system.cpu.dstage2_mmu.stage2_tlb] @@ -183,7 +186,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[5] [system.cpu.dtb] type=ArmTLB @@ -591,6 +593,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -651,6 +654,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu.istage2_mmu] @@ -658,6 +662,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +sys=system tlb=system.cpu.itb [system.cpu.istage2_mmu.stage2_tlb] @@ -675,7 +680,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB @@ -700,6 +704,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -733,13 +738,16 @@ size=2097152 type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 -header_cycles=1 +forward_latency=0 +frontend_latency=1 +response_latency=1 snoop_filter=Null +snoop_response_latency=1 system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -749,14 +757,16 @@ eventq_index=0 type=LiveProcess cmd=bzip2 input.source 1 cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing +drivers= egid=100 env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2 +executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -786,11 +796,14 @@ transition_latency=100000000 type=CoherentXBar clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=4 +frontend_latency=3 +response_latency=2 snoop_filter=Null +snoop_response_latency=4 system=system use_default_range=false -width=8 +width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side @@ -821,7 +834,7 @@ IDD62=0.000000 VDD=1.500000 VDD2=0.000000 activation_limit=4 -addr_mapping=RoRaBaChCo +addr_mapping=RoRaBaCoCh bank_groups_per_rank=0 banks_per_rank=8 burst_length=8 @@ -830,6 +843,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simerr b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simerr index 5d8946ede..be90b0340 100644..100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simerr +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simerr @@ -1,2 +1,3 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4] diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout index 903745948..b4e05a41a 100644..100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout @@ -1,14 +1,12 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 7 2014 10:57:46 -gem5 started May 7 2014 11:11:49 -gem5 executing on cz3211bhr8 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing +gem5 compiled Mar 15 2015 20:30:55 +gem5 started Mar 15 2015 20:31:14 +gem5 executing on zizzer2 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x1f2b7940 + 0: system.cpu.isa: ISA system set to: 0 0x2c50960 info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data @@ -27,4 +25,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 1135900642500 because target called exit() +Exiting @ tick 1121241432500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index 0b1bb03bc..a72b0bcd6 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.121241 # Nu sim_ticks 1121241432500 # Number of ticks simulated final_tick 1121241432500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 243175 # Simulator instruction rate (inst/s) -host_op_rate 261985 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 176527853 # Simulator tick rate (ticks/s) -host_mem_usage 312356 # Number of bytes of host memory used -host_seconds 6351.64 # Real time elapsed on the host +host_inst_rate 170583 # Simulator instruction rate (inst/s) +host_op_rate 183778 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 123831111 # Simulator tick rate (ticks/s) +host_mem_usage 241824 # Number of bytes of host memory used +host_seconds 9054.60 # Real time elapsed on the host sim_insts 1544563087 # Number of instructions simulated sim_ops 1664032480 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -234,8 +234,8 @@ system.physmem.wrPerTurnAround::22 9 0.01% 100.00% # Wr system.physmem.wrPerTurnAround::23 2 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::26 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 60985 # Writes before turning the bus around for reads -system.physmem.totQLat 38434565750 # Total ticks spent queuing -system.physmem.totMemAccLat 76957228250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 38434561000 # Total ticks spent queuing +system.physmem.totMemAccLat 76957223500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 10272710000 # Total ticks spent in databus transfers system.physmem.avgQLat 18707.12 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst @@ -284,13 +284,13 @@ system.physmem_1.memoryStateTime::REF 37440520000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 596864300250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 240141363 # Number of BP lookups -system.cpu.branchPred.condPredicted 186745178 # Number of conditional branches predicted +system.cpu.branchPred.lookups 240141357 # Number of BP lookups +system.cpu.branchPred.condPredicted 186745174 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 14595264 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 132286201 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 132286195 # Number of BTB lookups system.cpu.branchPred.BTBHits 122283419 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.438530 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 92.438534 # BTB Hit Percentage system.cpu.branchPred.usedRAS 15659523 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -416,19 +416,19 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563087 # Number of instructions committed system.cpu.committedOps 1664032480 # Number of ops (including micro ops) committed -system.cpu.discardedOps 40063389 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 40063388 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.451856 # CPI: cycles per instruction system.cpu.ipc 0.688774 # IPC: instructions per cycle -system.cpu.tickCycles 1838984641 # Number of cycles that the object actually ticked -system.cpu.idleCycles 403498224 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 1838984644 # Number of cycles that the object actually ticked +system.cpu.idleCycles 403498221 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 9223361 # number of replacements -system.cpu.dcache.tags.tagsinuse 4085.642530 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 624067003 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4085.642531 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624067002 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9227457 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.631527 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.631526 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 9813070000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4085.642530 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4085.642531 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997471 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997471 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -439,62 +439,70 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1276544027 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1276544027 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 453735354 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 453735354 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 453735352 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 453735352 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 170331527 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 170331527 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 624066881 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 624066881 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 624066881 # number of overall hits -system.cpu.dcache.overall_hits::total 624066881 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7336762 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7336762 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 624066879 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624066879 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 624066880 # number of overall hits +system.cpu.dcache.overall_hits::total 624066880 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7336761 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7336761 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 2254520 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 2254520 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 9591282 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9591282 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9591282 # number of overall misses -system.cpu.dcache.overall_misses::total 9591282 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 192442349996 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 192442349996 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 109711138250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 109711138250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 302153488246 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 302153488246 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 302153488246 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 302153488246 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 461072116 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 461072116 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 9591281 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9591281 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9591283 # number of overall misses +system.cpu.dcache.overall_misses::total 9591283 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 192442274246 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 192442274246 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 109711140250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 109711140250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 302153414496 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 302153414496 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 302153414496 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 302153414496 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 461072113 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 461072113 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 3 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 633658163 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 633658163 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 633658160 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 633658160 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 633658163 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 633658163 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015912 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.015912 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013063 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.013063 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.666667 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.666667 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.015136 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.015136 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015136 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015136 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26229.874977 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26229.874977 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48662.747835 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48662.747835 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31502.930291 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31502.930291 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31502.930291 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31502.930291 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26229.868227 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26229.868227 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48662.748723 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48662.748723 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31502.925886 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31502.925886 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31502.919317 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31502.919317 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -513,44 +521,52 @@ system.cpu.dcache.demand_mshr_hits::cpu.data 363825 system.cpu.dcache.demand_mshr_hits::total 363825 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 363825 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 363825 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7336554 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7336554 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7336553 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7336553 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890903 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1890903 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9227457 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9227457 # number of demand (read+write) MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9227456 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9227456 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9227457 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9227457 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 181020888504 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 181020888504 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83976849000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 83976849000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 264997737504 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 264997737504 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 264997737504 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 264997737504 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 181020814754 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 181020814754 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83976850000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 83976850000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 73750 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 73750 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 264997664754 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 264997664754 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 264997738504 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 264997738504 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015912 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015912 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014562 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.014562 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014562 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014562 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24673.830317 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24673.830317 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44410.976660 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44410.976660 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28718.393107 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28718.393107 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28718.393107 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28718.393107 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24673.823627 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24673.823627 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44410.977189 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44410.977189 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 73750 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 73750 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28718.388335 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28718.388335 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28718.393215 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28718.393215 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 32 # number of replacements system.cpu.icache.tags.tagsinuse 661.433391 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 466139352 # Total number of references to valid blocks. +system.cpu.icache.tags.total_refs 466139348 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 823 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 566390.464156 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 566390.459295 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 661.433391 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.322966 # Average percentage of cache occupancy @@ -560,44 +576,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 32 system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 753 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.386230 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 932281173 # Number of tag accesses -system.cpu.icache.tags.data_accesses 932281173 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 466139352 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 466139352 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 466139352 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 466139352 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 466139352 # number of overall hits -system.cpu.icache.overall_hits::total 466139352 # number of overall hits +system.cpu.icache.tags.tag_accesses 932281165 # Number of tag accesses +system.cpu.icache.tags.data_accesses 932281165 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 466139348 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 466139348 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 466139348 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 466139348 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 466139348 # number of overall hits +system.cpu.icache.overall_hits::total 466139348 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 823 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 823 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 823 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 823 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 823 # number of overall misses system.cpu.icache.overall_misses::total 823 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 63715999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 63715999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 63715999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 63715999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 63715999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 63715999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 466140175 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 466140175 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 466140175 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 466140175 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 466140175 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 466140175 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 63711749 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 63711749 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 63711749 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 63711749 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 63711749 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 63711749 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 466140171 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 466140171 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 466140171 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 466140171 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 466140171 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 466140171 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77419.196841 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 77419.196841 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 77419.196841 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 77419.196841 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 77419.196841 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 77419.196841 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77414.032807 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 77414.032807 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 77414.032807 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 77414.032807 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 77414.032807 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 77414.032807 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -612,24 +628,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 823 system.cpu.icache.demand_mshr_misses::total 823 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 823 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 823 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 62148501 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 62148501 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 62148501 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 62148501 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 62148501 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 62148501 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 62143751 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 62143751 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 62143751 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 62143751 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 62143751 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 62143751 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75514.582017 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75514.582017 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75514.582017 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75514.582017 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75514.582017 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75514.582017 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75508.810450 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75508.810450 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75508.810450 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75508.810450 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75508.810450 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75508.810450 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 2023178 # number of replacements system.cpu.l2cache.tags.tagsinuse 31261.935104 # Cycle average of tags in use @@ -677,17 +693,17 @@ system.cpu.l2cache.demand_misses::total 2055888 # nu system.cpu.l2cache.overall_misses::cpu.inst 791 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2055097 # number of overall misses system.cpu.l2cache.overall_misses::total 2055888 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 60988000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 60983250 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 109821544000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 109882532000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70568051000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 70568051000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 60988000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 180389595000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 180450583000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 60988000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 180389595000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 180450583000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 109882527250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70568052000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 70568052000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 60983250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 180389596000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 180450579250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 60983250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 180389596000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 180450579250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 823 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7336554 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7337377 # number of ReadReq accesses(hits+misses) @@ -712,17 +728,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.222781 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.961118 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.222715 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.222781 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77102.402023 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77096.396966 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 87510.692856 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 87504.136601 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88193.858129 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88193.858129 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77102.402023 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87776.681587 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 87772.574673 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77102.402023 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87776.681587 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 87772.574673 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 87504.132819 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88193.859378 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88193.859378 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77096.396966 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87776.682074 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 87772.572849 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77096.396966 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87776.682074 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 87772.572849 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -753,17 +769,17 @@ system.cpu.l2cache.demand_mshr_misses::total 2055883 system.cpu.l2cache.overall_mshr_misses::cpu.inst 790 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2055093 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 2055883 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 51087500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 51082250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 93955002000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 94006089500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60459125500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60459125500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 51087500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 154414127500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 154465215000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 51087500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 154414127500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 154465215000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 94006084250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60459126500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60459126500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 51082250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 154414128500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 154465210750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 51082250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 154414128500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 154465210750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.959903 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.171054 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171142 # mshr miss rate for ReadReq accesses @@ -775,17 +791,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.222781 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959903 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222715 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.222781 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64667.721519 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64661.075949 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 74867.764828 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74861.347847 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75560.022721 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75560.022721 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64667.721519 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75137.294273 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75133.271203 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64667.721519 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75137.294273 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75133.271203 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74861.343666 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75560.023971 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75560.023971 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64661.075949 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75137.294760 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75133.269135 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64661.075949 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75137.294760 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75133.269135 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 7337377 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 7337377 # Transaction distribution @@ -814,7 +830,7 @@ system.cpu.toL2Bus.snoop_fanout::max_value 3 # system.cpu.toL2Bus.snoop_fanout::total 12929320 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 10165700000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1400999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1401249 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 14190167496 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) @@ -840,7 +856,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 3102414 # Request fanout histogram system.membus.reqLayer0.occupancy 7944829000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 11243795500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 11243795750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini index f2c2bbb56..00a1bf85d 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini @@ -23,6 +23,7 @@ load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem +mmap_using_noreserve=false num_work_ids=16 readfile= symbolfile= @@ -132,6 +133,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -166,6 +168,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +sys=system tlb=system.cpu.dtb [system.cpu.dstage2_mmu.stage2_tlb] @@ -183,7 +186,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[5] [system.cpu.dtb] type=ArmTLB @@ -591,6 +593,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -651,6 +654,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu.istage2_mmu] @@ -658,6 +662,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +sys=system tlb=system.cpu.itb [system.cpu.istage2_mmu.stage2_tlb] @@ -675,7 +680,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB @@ -700,6 +704,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -733,13 +738,16 @@ size=2097152 type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 -header_cycles=1 +forward_latency=0 +frontend_latency=1 +response_latency=1 snoop_filter=Null +snoop_response_latency=1 system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -749,14 +757,16 @@ eventq_index=0 type=LiveProcess cmd=twolf smred cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing +drivers= egid=100 env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf +executable=/dist/m5/cpu2000/binaries/arm/linux/twolf gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -786,11 +796,14 @@ transition_latency=100000000 type=CoherentXBar clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=4 +frontend_latency=3 +response_latency=2 snoop_filter=Null +snoop_response_latency=4 system=system use_default_range=false -width=8 +width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side @@ -821,7 +834,7 @@ IDD62=0.000000 VDD=1.500000 VDD2=0.000000 activation_limit=4 -addr_mapping=RoRaBaChCo +addr_mapping=RoRaBaCoCh bank_groups_per_rank=0 banks_per_rank=8 burst_length=8 @@ -830,6 +843,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simerr b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simerr index 1a4f96712..341b479f7 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simerr +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simerr @@ -1 +1,2 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout index 6876fac87..c2579128c 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout @@ -1,16 +1,14 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 7 2014 10:57:46 -gem5 started May 7 2014 13:16:45 -gem5 executing on cz3211bhr8 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing +gem5 compiled Mar 15 2015 20:30:55 +gem5 started Mar 15 2015 20:31:14 +gem5 executing on zizzer2 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/smred.sav Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x1c024750 + 0: system.cpu.isa: ISA system set to: 0 0x3623b60 info: Entering event queue @ 0. Starting simulation... TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 @@ -26,4 +24,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 133578736500 because target called exit() +122 123 124 Exiting @ tick 131756455500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index f13570e98..f50e78f71 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.131756 # Nu sim_ticks 131756455500 # Number of ticks simulated final_tick 131756455500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 249754 # Simulator instruction rate (inst/s) -host_op_rate 263281 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 190965456 # Simulator tick rate (ticks/s) -host_mem_usage 316672 # Number of bytes of host memory used -host_seconds 689.95 # Real time elapsed on the host +host_inst_rate 150043 # Simulator instruction rate (inst/s) +host_op_rate 158169 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 114724713 # Simulator tick rate (ticks/s) +host_mem_usage 245376 # Number of bytes of host memory used +host_seconds 1148.46 # Real time elapsed on the host sim_insts 172317809 # Number of instructions simulated sim_ops 181650742 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -200,12 +200,12 @@ system.physmem.bytesPerActivate::768-895 22 2.46% 92.18% # By system.physmem.bytesPerActivate::896-1023 16 1.79% 93.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 54 6.03% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 895 # Bytes accessed per row activation -system.physmem.totQLat 26801000 # Total ticks spent queuing -system.physmem.totMemAccLat 99344750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 26795500 # Total ticks spent queuing +system.physmem.totMemAccLat 99339250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 19345000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6927.11 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6925.69 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25677.11 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25675.69 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s @@ -227,14 +227,14 @@ system.physmem_0.preEnergy 1674750 # En system.physmem_0.readEnergy 16169400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 8605343760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3539588850 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 75945927000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 88111773120 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.773044 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 126343733250 # Time in different power states +system.physmem_0.actBackEnergy 3539591415 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 75945924750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 88111773435 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.773046 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 126343729250 # Time in different power states system.physmem_0.memoryStateTime::REF 4399460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1010942750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1010946750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 3681720 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 2008875 # Energy for precharge commands per rank (pJ) @@ -250,13 +250,13 @@ system.physmem_1.memoryStateTime::REF 4399460000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 1080937500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 49934480 # Number of BP lookups -system.cpu.branchPred.condPredicted 39666708 # Number of conditional branches predicted +system.cpu.branchPred.lookups 49934475 # Number of BP lookups +system.cpu.branchPred.condPredicted 39666705 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 5743450 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24374232 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 24374227 # Number of BTB lookups system.cpu.branchPred.BTBHits 23299942 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.592518 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 95.592537 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1908561 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 139 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -386,15 +386,15 @@ system.cpu.discardedOps 11759003 # Nu system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.529226 # CPI: cycles per instruction system.cpu.ipc 0.653925 # IPC: instructions per cycle -system.cpu.tickCycles 257129924 # Number of cycles that the object actually ticked -system.cpu.idleCycles 6382987 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 257129929 # Number of cycles that the object actually ticked +system.cpu.idleCycles 6382982 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1377.698544 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40765677 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1377.698550 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40765676 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22522.473481 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22522.472928 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1377.698544 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1377.698550 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.336352 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.336352 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id @@ -404,64 +404,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1358 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.431641 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 81538036 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 81538036 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 28358222 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28358222 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 81538034 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 81538034 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28357756 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28357756 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 12362641 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 12362641 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 465 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 465 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40720863 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40720863 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40720863 # number of overall hits -system.cpu.dcache.overall_hits::total 40720863 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 790 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 790 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 40720397 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40720397 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40720862 # number of overall hits +system.cpu.dcache.overall_hits::total 40720862 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 789 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 789 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1646 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 1646 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2436 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2436 # number of demand (read+write) misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 2435 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2435 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2436 # number of overall misses system.cpu.dcache.overall_misses::total 2436 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57599734 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57599734 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 127302750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 127302750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 184902484 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 184902484 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 184902484 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 184902484 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28359012 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28359012 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57528734 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57528734 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 127304750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 127304750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 184833484 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 184833484 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 184833484 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 184833484 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28358545 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28358545 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 466 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 466 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 40723299 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 40723299 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 40723299 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 40723299 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 40722832 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 40722832 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 40723298 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 40723298 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000133 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002146 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.002146 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72911.055696 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72911.055696 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77340.674362 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 77340.674362 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 75904.139573 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 75904.139573 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 75904.139573 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 75904.139573 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72913.477820 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72913.477820 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77341.889429 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77341.889429 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 75906.974949 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 75906.974949 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 75875.814450 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 75875.814450 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -480,46 +488,54 @@ system.cpu.dcache.demand_mshr_hits::cpu.data 626 system.cpu.dcache.demand_mshr_hits::total 626 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 626 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 626 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1098 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1098 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1810 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1809 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1809 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1810 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51193764 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 51193764 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85249250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 85249250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136443014 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 136443014 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136443014 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 136443014 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51124264 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 51124264 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85250250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85250250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 69500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 69500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136374514 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 136374514 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136444014 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 136444014 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002146 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002146 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71901.353933 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71901.353933 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77640.482696 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77640.482696 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75382.880663 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75382.880663 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75382.880663 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75382.880663 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71904.731364 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71904.731364 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77641.393443 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77641.393443 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 69500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 69500 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75386.685462 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75386.685462 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75383.433149 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75383.433149 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2891 # number of replacements -system.cpu.icache.tags.tagsinuse 1424.909254 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 71597357 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1424.909257 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 71597353 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4688 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 15272.473763 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 15272.472910 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1424.909254 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1424.909257 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.695756 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.695756 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id @@ -529,44 +545,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 490 system.cpu.icache.tags.age_task_id_blocks_1024::3 129 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1067 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.877441 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 143208780 # Number of tag accesses -system.cpu.icache.tags.data_accesses 143208780 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 71597357 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 71597357 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 71597357 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 71597357 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 71597357 # number of overall hits -system.cpu.icache.overall_hits::total 71597357 # number of overall hits +system.cpu.icache.tags.tag_accesses 143208772 # Number of tag accesses +system.cpu.icache.tags.data_accesses 143208772 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 71597353 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 71597353 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 71597353 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 71597353 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 71597353 # number of overall hits +system.cpu.icache.overall_hits::total 71597353 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 4689 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 4689 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 4689 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 4689 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 4689 # number of overall misses system.cpu.icache.overall_misses::total 4689 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 200362248 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 200362248 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 200362248 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 200362248 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 200362248 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 200362248 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 71602046 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 71602046 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 71602046 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 71602046 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 71602046 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 71602046 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 200357248 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 200357248 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 200357248 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 200357248 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 200357248 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 200357248 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 71602042 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 71602042 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 71602042 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 71602042 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 71602042 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 71602042 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000065 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000065 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000065 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000065 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000065 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000065 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42730.272553 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42730.272553 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42730.272553 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42730.272553 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42730.272553 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42730.272553 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42729.206227 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42729.206227 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42729.206227 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42729.206227 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42729.206227 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42729.206227 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -581,34 +597,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4689 system.cpu.icache.demand_mshr_misses::total 4689 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4689 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4689 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192401752 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 192401752 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192401752 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 192401752 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192401752 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 192401752 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192396752 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 192396752 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192396752 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 192396752 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192396752 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 192396752 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000065 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000065 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000065 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41032.576669 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41032.576669 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41032.576669 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 41032.576669 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41032.576669 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 41032.576669 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41031.510343 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41031.510343 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41031.510343 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 41031.510343 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41031.510343 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 41031.510343 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2001.520500 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2001.520504 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2606 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2787 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.935056 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 3.029170 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.676368 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 490.814962 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.676370 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 490.814964 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046011 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.014978 # Average percentage of cache occupancy @@ -646,17 +662,17 @@ system.cpu.l2cache.demand_misses::total 3886 # nu system.cpu.l2cache.overall_misses::cpu.inst 2164 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1722 # number of overall misses system.cpu.l2cache.overall_misses::total 3886 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 161201250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 161196250 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 49637250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 210838500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84065750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 84065750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 161201250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 133703000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 294904250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 161201250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 133703000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 294904250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 210833500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84066750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 84066750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 161196250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 133704000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 294900250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 161196250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 133704000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 294900250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 4689 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 712 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 5401 # number of ReadReq accesses(hits+misses) @@ -681,17 +697,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.597938 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461506 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.951381 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.597938 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74492.259704 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74489.949168 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78539.952532 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75407.188841 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77124.541284 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77124.541284 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74492.259704 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77644.018583 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75888.896037 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74492.259704 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77644.018583 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75888.896037 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75405.400572 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77125.458716 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77125.458716 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74489.949168 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77644.599303 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75887.866701 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74489.949168 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77644.599303 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75887.866701 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -720,17 +736,17 @@ system.cpu.l2cache.demand_mshr_misses::total 3870 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2162 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3870 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134008500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134003000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 40696500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 174705000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70436750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70436750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134008500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 111133250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 245141750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134008500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 111133250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 245141750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 174699500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70437750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70437750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134003000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 111134250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 245137250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134003000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 111134250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 245137250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867978 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.514719 # mshr miss rate for ReadReq accesses @@ -742,17 +758,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.595476 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.595476 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61983.580019 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61981.036078 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65851.941748 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62843.525180 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64620.871560 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64620.871560 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61983.580019 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65066.305621 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63344.121447 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61983.580019 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65066.305621 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63344.121447 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62841.546763 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64621.788991 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64621.788991 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61981.036078 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65066.891101 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63342.958656 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61981.036078 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65066.891101 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63342.958656 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 5401 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 5400 # Transaction distribution @@ -806,7 +822,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 3869 # Request fanout histogram system.membus.reqLayer0.occupancy 4526500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 20559250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20559750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |