diff options
Diffstat (limited to 'tests/long/se')
13 files changed, 6228 insertions, 6230 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index 477530da6..a4eaa28e3 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.061144 # Number of seconds simulated -sim_ticks 61144411500 # Number of ticks simulated -final_tick 61144411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.061494 # Number of seconds simulated +sim_ticks 61493732000 # Number of ticks simulated +final_tick 61493732000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 271316 # Simulator instruction rate (inst/s) -host_op_rate 272668 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 183101149 # Simulator tick rate (ticks/s) -host_mem_usage 442968 # Number of bytes of host memory used -host_seconds 333.94 # Real time elapsed on the host +host_inst_rate 280016 # Simulator instruction rate (inst/s) +host_op_rate 281410 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 190051649 # Simulator tick rate (ticks/s) +host_mem_usage 385752 # Number of bytes of host memory used +host_seconds 323.56 # Real time elapsed on the host sim_insts 90602849 # Number of instructions simulated sim_ops 91054080 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 996736 # Number of bytes read from this memory -system.physmem.bytes_read::total 996736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 996800 # Number of bytes read from this memory +system.physmem.bytes_read::total 996800 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 49600 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 49600 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 15574 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 16301343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 16301343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 811194 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 811194 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 16301343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 16301343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15574 # Number of read requests accepted +system.physmem.num_reads::cpu.inst 15575 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15575 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 16209782 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 16209782 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 806586 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 806586 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 16209782 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 16209782 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15575 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 15575 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 996736 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 996800 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 996736 # Total read bytes from the system interface side +system.physmem.bytesReadSys 996800 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 993 # Per bank write bursts system.physmem.perBankRdBursts::1 890 # Per bank write bursts -system.physmem.perBankRdBursts::2 950 # Per bank write bursts +system.physmem.perBankRdBursts::2 949 # Per bank write bursts system.physmem.perBankRdBursts::3 1028 # Per bank write bursts system.physmem.perBankRdBursts::4 1050 # Per bank write bursts system.physmem.perBankRdBursts::5 1113 # Per bank write bursts @@ -49,10 +49,10 @@ system.physmem.perBankRdBursts::8 1024 # Pe system.physmem.perBankRdBursts::9 962 # Per bank write bursts system.physmem.perBankRdBursts::10 938 # Per bank write bursts system.physmem.perBankRdBursts::11 899 # Per bank write bursts -system.physmem.perBankRdBursts::12 903 # Per bank write bursts +system.physmem.perBankRdBursts::12 904 # Per bank write bursts system.physmem.perBankRdBursts::13 867 # Per bank write bursts system.physmem.perBankRdBursts::14 877 # Per bank write bursts -system.physmem.perBankRdBursts::15 904 # Per bank write bursts +system.physmem.perBankRdBursts::15 905 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -71,14 +71,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 61144323500 # Total gap between requests +system.physmem.totGap 61493643500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 15574 # Read request sizes (log2) +system.physmem.readPktSize::6 15575 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -86,9 +86,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 15451 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 15453 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -182,29 +182,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1531 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 649.865447 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 447.084914 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 397.724653 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 242 15.81% 15.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 164 10.71% 26.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 94 6.14% 32.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 77 5.03% 37.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 65 4.25% 41.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 106 6.92% 48.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 51 3.33% 52.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 28 1.83% 54.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 704 45.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1531 # Bytes accessed per row activation -system.physmem.totQLat 71490500 # Total ticks spent queuing -system.physmem.totMemAccLat 363503000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4590.37 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1534 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 648.594524 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 444.741065 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 399.329877 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 241 15.71% 15.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 178 11.60% 27.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 90 5.87% 33.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 63 4.11% 37.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 79 5.15% 42.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 102 6.65% 49.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 37 2.41% 51.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 39 2.54% 54.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 705 45.96% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1534 # Bytes accessed per row activation +system.physmem.totQLat 73246500 # Total ticks spent queuing +system.physmem.totMemAccLat 365277750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77875000 # Total ticks spent in databus transfers +system.physmem.avgQLat 4702.83 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23340.37 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 16.30 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 23452.83 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 16.21 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 16.30 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 16.21 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.13 # Data bus utilization in percentage @@ -212,68 +212,45 @@ system.physmem.busUtilRead 0.13 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 14033 # Number of row buffer hits during reads +system.physmem.readRowHits 14031 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.11 # Row buffer hit rate for reads +system.physmem.readRowHitRate 90.09 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 3926051.34 # Average gap between requests -system.physmem.pageHitRate 90.11 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 55905599000 # Time in different power states -system.physmem.memoryStateTime::REF 2041520000 # Time in different power states +system.physmem.avgGap 3948227.51 # Average gap between requests +system.physmem.pageHitRate 90.09 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 56242943250 # Time in different power states +system.physmem.memoryStateTime::REF 2053220000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 3193563500 # Time in different power states +system.physmem.memoryStateTime::ACT 3193793750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 6305040 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 5254200 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 3440250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 2866875 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 63671400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 57454800 # Energy for read commands per rank (pJ) +system.physmem.actEnergy::0 6320160 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 5261760 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 3448500 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 2871000 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 63663600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 57462600 # Energy for read commands per rank (pJ) system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3993213120 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3993213120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 2474179335 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 2524417425 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 34512404250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 34468335750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 41053213395 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 41051542170 # Total energy per rank (pJ) -system.physmem.averagePower::0 671.485556 # Core power per rank (mW) -system.physmem.averagePower::1 671.458220 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 1030 # Transaction distribution -system.membus.trans_dist::ReadResp 1030 # Transaction distribution -system.membus.trans_dist::ReadExReq 14544 # Transaction distribution -system.membus.trans_dist::ReadExResp 14544 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31148 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 31148 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996736 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 996736 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 15574 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 15574 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 15574 # Request fanout histogram -system.membus.reqLayer0.occupancy 21822000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 149565000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 20748984 # Number of BP lookups -system.cpu.branchPred.condPredicted 17053332 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 764055 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8969348 # Number of BTB lookups -system.cpu.branchPred.BTBHits 8846034 # Number of BTB hits +system.physmem.refreshEnergy::0 4016098320 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 4016098320 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 2490497865 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 2514078765 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 34708310250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 34687625250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 41288338695 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 41283397695 # Total energy per rank (pJ) +system.physmem.averagePower::0 671.483256 # Core power per rank (mW) +system.physmem.averagePower::1 671.402899 # Core power per rank (mW) +system.cpu.branchPred.lookups 20789429 # Number of BP lookups +system.cpu.branchPred.condPredicted 17091399 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 765966 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8973618 # Number of BTB lookups +system.cpu.branchPred.BTBHits 8867020 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.625162 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 62305 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 98.812096 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 62716 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -359,69 +336,192 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 122288823 # number of cpu cycles simulated +system.cpu.numCycles 122987464 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90602849 # Number of instructions committed system.cpu.committedOps 91054080 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2027782 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2068195 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.349724 # CPI: cycles per instruction -system.cpu.ipc 0.740892 # IPC: instructions per cycle -system.cpu.tickCycles 109176308 # Number of cycles that the object actually ticked -system.cpu.idleCycles 13112515 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.357435 # CPI: cycles per instruction +system.cpu.ipc 0.736684 # IPC: instructions per cycle +system.cpu.tickCycles 109826570 # Number of cycles that the object actually ticked +system.cpu.idleCycles 13160894 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 946107 # number of replacements +system.cpu.dcache.tags.tagsinuse 3616.604238 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26267660 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 950203 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 27.644261 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 20617906250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 3616.604238 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.882960 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.882960 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 262 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2249 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1585 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 55463255 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 55463255 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 21598813 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21598813 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 4661073 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4661073 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 3887 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.inst 3887 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.inst 26259886 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26259886 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 26259886 # number of overall hits +system.cpu.dcache.overall_hits::total 26259886 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 914958 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 914958 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 73908 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 73908 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 988866 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 988866 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 988866 # number of overall misses +system.cpu.dcache.overall_misses::total 988866 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 11910311744 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11910311744 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 2345697500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2345697500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 14256009244 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14256009244 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 14256009244 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14256009244 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 22513771 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22513771 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 3887 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 3887 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 27248752 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 27248752 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 27248752 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 27248752 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.040640 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040640 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.015609 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015609 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.036290 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036290 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.036290 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036290 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13017.331663 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.331663 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31738.073010 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31738.073010 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14416.522809 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14416.522809 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14416.522809 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14416.522809 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 943286 # number of writebacks +system.cpu.dcache.writebacks::total 943286 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 11523 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 11523 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 27140 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 27140 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 38663 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 38663 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 38663 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 38663 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 903435 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 903435 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 46768 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 46768 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 950203 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 950203 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 950203 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 950203 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 9958869756 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9958869756 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1333434750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1333434750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11292304506 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11292304506 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11292304506 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11292304506 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.040128 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040128 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009877 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009877 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.034871 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.034871 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.034871 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.034871 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11023.338432 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.338432 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28511.690686 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28511.690686 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11884.096878 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11884.096878 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11884.096878 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11884.096878 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 5 # number of replacements -system.cpu.icache.tags.tagsinuse 690.927522 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27773574 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 690.411179 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27857009 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 803 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 34587.265255 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 34691.169365 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 690.927522 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.337367 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.337367 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 690.411179 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.337115 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.337115 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 55549557 # Number of tag accesses -system.cpu.icache.tags.data_accesses 55549557 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 27773574 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27773574 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27773574 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27773574 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27773574 # number of overall hits -system.cpu.icache.overall_hits::total 27773574 # number of overall hits +system.cpu.icache.tags.tag_accesses 55716427 # Number of tag accesses +system.cpu.icache.tags.data_accesses 55716427 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 27857009 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27857009 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27857009 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27857009 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27857009 # number of overall hits +system.cpu.icache.overall_hits::total 27857009 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 803 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 803 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 803 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 803 # number of overall misses system.cpu.icache.overall_misses::total 803 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 55313498 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 55313498 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 55313498 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 55313498 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 55313498 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 55313498 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27774377 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27774377 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27774377 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27774377 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27774377 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27774377 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 55346748 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 55346748 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 55346748 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 55346748 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 55346748 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 55346748 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27857812 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27857812 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27857812 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27857812 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27857812 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27857812 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68883.559153 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68883.559153 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68883.559153 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68883.559153 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68883.559153 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68883.559153 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68924.966376 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68924.966376 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68924.966376 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68924.966376 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68924.966376 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68924.966376 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -436,130 +536,97 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 803 system.cpu.icache.demand_mshr_misses::total 803 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 803 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53373502 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 53373502 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53373502 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 53373502 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53373502 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 53373502 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53408252 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 53408252 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53408252 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 53408252 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53408252 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 53408252 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66467.623910 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66467.623910 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66467.623910 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66467.623910 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66467.623910 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66467.623910 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66510.899128 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66510.899128 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66510.899128 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66510.899128 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66510.899128 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66510.899128 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 904183 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 904183 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 943269 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 46761 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 46761 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1606 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843551 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2845157 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121178240 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 121229632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1894213 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 1894213 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1894213 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1890375500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1371498 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1428579494 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10264.635477 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1831263 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 117.713119 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 10247.121792 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1831334 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 15558 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 117.710117 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9373.658869 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 890.976609 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.286061 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.027190 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.313252 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15557 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 9356.236502 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 890.885290 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.285530 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.027188 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.312717 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15558 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13878 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474762 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 15216022 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 15216022 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 903145 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 903145 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 943269 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 943269 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 32217 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 32217 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 935362 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 935362 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 935362 # number of overall hits -system.cpu.l2cache.overall_hits::total 935362 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1038 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1038 # number of ReadReq misses +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474792 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 15216662 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 15216662 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 903199 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 903199 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 943286 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 943286 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 32224 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 32224 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 935423 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 935423 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 935423 # number of overall hits +system.cpu.l2cache.overall_hits::total 935423 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1039 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1039 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.inst 14544 # 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number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1031344250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 904183 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 904183 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 943269 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 943269 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 46761 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 46761 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 950944 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 950944 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 950944 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 950944 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.001148 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.001148 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.311028 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.311028 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_misses::cpu.inst 15583 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 15583 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 15583 # number of overall misses +system.cpu.l2cache.overall_misses::total 15583 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71718500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 71718500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 958069250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 958069250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1029787750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1029787750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1029787750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1029787750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 904238 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 904238 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 943286 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 943286 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 46768 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 46768 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 951006 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 951006 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 951006 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 951006 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.001149 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.001149 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.310982 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.310982 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016386 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.016386 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016386 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016386 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69106.695568 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69106.695568 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65979.888614 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65979.888614 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66188.181877 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66188.181877 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66188.181877 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66188.181877 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69026.467757 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69026.467757 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65873.848322 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65873.848322 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66084.049926 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 66084.049926 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66084.049926 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66084.049926 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -574,161 +641,94 @@ system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1030 # 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number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 772672000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 831042500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 831042500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 831042500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 831042500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.001139 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001139 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.311028 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311028 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 15575 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15575 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 15575 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15575 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58344750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58344750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 774500250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 774500250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 832845000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 832845000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 832845000 # 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average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53126.512651 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53126.512651 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53360.889945 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53360.889945 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53360.889945 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53360.889945 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56590.446169 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56590.446169 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53252.217409 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53252.217409 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53473.194222 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53473.194222 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53473.194222 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53473.194222 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 946045 # number of replacements -system.cpu.dcache.tags.tagsinuse 3618.157159 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26265609 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 950141 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 27.643907 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 20427116250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 3618.157159 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.883339 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.883339 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 261 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2250 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1585 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 55458945 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 55458945 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 21596750 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21596750 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 4661085 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4661085 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 3887 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 3887 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 26257835 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26257835 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 26257835 # number of overall hits -system.cpu.dcache.overall_hits::total 26257835 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 914897 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 914897 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 73896 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 73896 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 988793 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 988793 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 988793 # number of overall misses -system.cpu.dcache.overall_misses::total 988793 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 11909486494 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11909486494 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 2342568500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2342568500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 14252054994 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14252054994 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 14252054994 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14252054994 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 22511647 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22511647 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 3887 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 27246628 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 27246628 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 27246628 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 27246628 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.040641 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040641 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.015606 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015606 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.036290 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036290 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.036290 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036290 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13017.297569 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.297569 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31700.883674 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31700.883674 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14413.588076 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14413.588076 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14413.588076 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14413.588076 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 943269 # number of writebacks -system.cpu.dcache.writebacks::total 943269 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 11517 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 11517 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 27135 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 27135 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 38652 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 38652 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 38652 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 38652 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 903380 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 903380 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 46761 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 46761 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 950141 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 950141 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 950141 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 950141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 9958325256 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9958325256 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1334896250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1334896250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11293221506 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11293221506 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11293221506 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11293221506 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.040129 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040129 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009876 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.034872 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.034872 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.034872 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.034872 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11023.406823 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.406823 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28547.213490 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28547.213490 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11885.837477 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11885.837477 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11885.837477 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11885.837477 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 904238 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 904238 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 943286 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 46768 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 46768 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1606 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843692 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2845298 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121183296 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 121234688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1894292 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 1894292 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1894292 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1890432000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1370748 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 1428672494 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) +system.membus.trans_dist::ReadReq 1031 # Transaction distribution +system.membus.trans_dist::ReadResp 1031 # Transaction distribution +system.membus.trans_dist::ReadExReq 14544 # Transaction distribution +system.membus.trans_dist::ReadExResp 14544 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31150 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 31150 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 996800 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 15575 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 15575 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 15575 # Request fanout histogram +system.membus.reqLayer0.occupancy 17956500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 146202000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index d4eaaecb0..f1692fa7b 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -1,100 +1,100 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.409380 # Number of seconds simulated -sim_ticks 409379703500 # Number of ticks simulated -final_tick 409379703500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.411003 # Number of seconds simulated +sim_ticks 411003011000 # Number of ticks simulated +final_tick 411003011000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 295886 # Simulator instruction rate (inst/s) -host_op_rate 295886 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 197956312 # Simulator tick rate (ticks/s) -host_mem_usage 239696 # Number of bytes of host memory used -host_seconds 2068.03 # Real time elapsed on the host +host_inst_rate 279515 # Simulator instruction rate (inst/s) +host_op_rate 279515 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 187744969 # Simulator tick rate (ticks/s) +host_mem_usage 239248 # Number of bytes of host memory used +host_seconds 2189.16 # Real time elapsed on the host sim_insts 611901617 # Number of instructions simulated sim_ops 611901617 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 24321024 # Number of bytes read from this memory -system.physmem.bytes_read::total 24321024 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 170880 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 170880 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18723904 # Number of bytes written to this memory -system.physmem.bytes_written::total 18723904 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 380016 # Number of read requests responded to by this memory -system.physmem.num_reads::total 380016 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 292561 # Number of write requests responded to by this memory -system.physmem.num_writes::total 292561 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 59409452 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 59409452 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 417412 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 417412 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 45737255 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 45737255 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 45737255 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 59409452 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 105146708 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 380016 # Number of read requests accepted -system.physmem.writeReqs 292561 # Number of write requests accepted -system.physmem.readBursts 380016 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 292561 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24297984 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 23040 # Total number of bytes read from write queue -system.physmem.bytesWritten 18722304 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24321024 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18723904 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 360 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 24320320 # Number of bytes read from this memory +system.physmem.bytes_read::total 24320320 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 170944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 170944 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18724480 # Number of bytes written to this memory +system.physmem.bytes_written::total 18724480 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 380005 # Number of read requests responded to by this memory +system.physmem.num_reads::total 380005 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 292570 # Number of write requests responded to by this memory +system.physmem.num_writes::total 292570 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 59173094 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 59173094 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 415919 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 415919 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 45558012 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 45558012 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 45558012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 59173094 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 104731106 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 380005 # Number of read requests accepted +system.physmem.writeReqs 292570 # Number of write requests accepted +system.physmem.readBursts 380005 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 292570 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24297088 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 23232 # Total number of bytes read from write queue +system.physmem.bytesWritten 18722944 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24320320 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18724480 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 363 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 23733 # Per bank write bursts -system.physmem.perBankRdBursts::1 23212 # Per bank write bursts -system.physmem.perBankRdBursts::2 23513 # Per bank write bursts -system.physmem.perBankRdBursts::3 24527 # Per bank write bursts -system.physmem.perBankRdBursts::4 25463 # Per bank write bursts -system.physmem.perBankRdBursts::5 23584 # Per bank write bursts -system.physmem.perBankRdBursts::6 23682 # Per bank write bursts -system.physmem.perBankRdBursts::7 23974 # Per bank write bursts -system.physmem.perBankRdBursts::8 23187 # Per bank write bursts -system.physmem.perBankRdBursts::9 23951 # Per bank write bursts -system.physmem.perBankRdBursts::10 24675 # Per bank write bursts -system.physmem.perBankRdBursts::11 22741 # Per bank write bursts -system.physmem.perBankRdBursts::12 23717 # Per bank write bursts -system.physmem.perBankRdBursts::13 24415 # Per bank write bursts -system.physmem.perBankRdBursts::14 22809 # Per bank write bursts -system.physmem.perBankRdBursts::15 22473 # Per bank write bursts -system.physmem.perBankWrBursts::0 17752 # Per bank write bursts -system.physmem.perBankWrBursts::1 17434 # Per bank write bursts +system.physmem.perBankRdBursts::0 23737 # Per bank write bursts +system.physmem.perBankRdBursts::1 23219 # Per bank write bursts +system.physmem.perBankRdBursts::2 23515 # Per bank write bursts +system.physmem.perBankRdBursts::3 24536 # Per bank write bursts +system.physmem.perBankRdBursts::4 25458 # Per bank write bursts +system.physmem.perBankRdBursts::5 23589 # Per bank write bursts +system.physmem.perBankRdBursts::6 23674 # Per bank write bursts +system.physmem.perBankRdBursts::7 23973 # Per bank write bursts +system.physmem.perBankRdBursts::8 23176 # Per bank write bursts +system.physmem.perBankRdBursts::9 23944 # Per bank write bursts +system.physmem.perBankRdBursts::10 24674 # Per bank write bursts +system.physmem.perBankRdBursts::11 22747 # Per bank write bursts +system.physmem.perBankRdBursts::12 23719 # Per bank write bursts +system.physmem.perBankRdBursts::13 24413 # Per bank write bursts +system.physmem.perBankRdBursts::14 22804 # Per bank write bursts +system.physmem.perBankRdBursts::15 22464 # Per bank write bursts +system.physmem.perBankWrBursts::0 17754 # Per bank write bursts +system.physmem.perBankWrBursts::1 17431 # Per bank write bursts system.physmem.perBankWrBursts::2 17902 # Per bank write bursts -system.physmem.perBankWrBursts::3 18771 # Per bank write bursts +system.physmem.perBankWrBursts::3 18773 # Per bank write bursts system.physmem.perBankWrBursts::4 19442 # Per bank write bursts -system.physmem.perBankWrBursts::5 18539 # Per bank write bursts -system.physmem.perBankWrBursts::6 18683 # Per bank write bursts -system.physmem.perBankWrBursts::7 18574 # Per bank write bursts -system.physmem.perBankWrBursts::8 18353 # Per bank write bursts +system.physmem.perBankWrBursts::5 18543 # Per bank write bursts +system.physmem.perBankWrBursts::6 18682 # Per bank write bursts +system.physmem.perBankWrBursts::7 18577 # Per bank write bursts +system.physmem.perBankWrBursts::8 18349 # Per bank write bursts system.physmem.perBankWrBursts::9 18833 # Per bank write bursts -system.physmem.perBankWrBursts::10 19130 # Per bank write bursts -system.physmem.perBankWrBursts::11 17961 # Per bank write bursts -system.physmem.perBankWrBursts::12 18219 # Per bank write bursts +system.physmem.perBankWrBursts::10 19127 # Per bank write bursts +system.physmem.perBankWrBursts::11 17965 # Per bank write bursts +system.physmem.perBankWrBursts::12 18224 # Per bank write bursts system.physmem.perBankWrBursts::13 18693 # Per bank write bursts system.physmem.perBankWrBursts::14 17148 # Per bank write bursts -system.physmem.perBankWrBursts::15 17102 # Per bank write bursts +system.physmem.perBankWrBursts::15 17103 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 409379622500 # Total gap between requests +system.physmem.totGap 411002929500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 380016 # Read request sizes (log2) +system.physmem.readPktSize::6 380005 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 292561 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 378259 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1382 # What read queue length does an incoming req see +system.physmem.writePktSize::6 292570 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 378255 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1372 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -140,42 +140,42 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16914 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17416 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17535 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17637 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17404 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6816 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17420 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17397 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17404 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17430 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17577 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see @@ -189,150 +189,123 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 141528 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 303.959754 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 180.049332 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.018132 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 50528 35.70% 35.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 38641 27.30% 63.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 12939 9.14% 72.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7964 5.63% 77.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5792 4.09% 81.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3807 2.69% 84.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3019 2.13% 86.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2550 1.80% 88.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16288 11.51% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 141528 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17267 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.986332 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 228.214102 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17257 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 7 0.04% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 141657 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 303.679790 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.908631 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 325.510648 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 50805 35.86% 35.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 38362 27.08% 62.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 12861 9.08% 72.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8208 5.79% 77.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5905 4.17% 81.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3832 2.71% 84.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2875 2.03% 86.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2523 1.78% 88.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16286 11.50% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 141657 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17265 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.988184 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 229.046433 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17255 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 6 0.03% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17267 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17267 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.941912 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.866733 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.774183 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17056 98.78% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 152 0.88% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 31 0.18% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 11 0.06% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 2 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 1 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 1 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 2 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 2 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17265 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17265 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.944454 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.865388 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 3.133478 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17065 98.84% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 148 0.86% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 28 0.16% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 9 0.05% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 2 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 3 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 2 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::236-239 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17267 # Writes before turning the bus around for reads -system.physmem.totQLat 4096707750 # Total ticks spent queuing -system.physmem.totMemAccLat 11215257750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1898280000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10790.58 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 17265 # Writes before turning the bus around for reads +system.physmem.totQLat 4080991250 # Total ticks spent queuing +system.physmem.totMemAccLat 11199278750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1898210000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10749.58 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29540.58 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 59.35 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 45.73 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 59.41 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 45.74 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29499.58 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 59.12 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 45.55 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 59.17 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 45.56 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.82 # Data bus utilization in percentage system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.14 # Average write queue length when enqueuing -system.physmem.readRowHits 314853 # Number of row buffer hits during reads -system.physmem.writeRowHits 215803 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.93 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.76 # Row buffer hit rate for writes -system.physmem.avgGap 608673.24 # Average gap between requests -system.physmem.pageHitRate 78.94 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 275372649250 # Time in different power states -system.physmem.memoryStateTime::REF 13670020000 # Time in different power states +system.physmem.avgWrQLen 20.64 # Average write queue length when enqueuing +system.physmem.readRowHits 314689 # Number of row buffer hits during reads +system.physmem.writeRowHits 215833 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.89 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.77 # Row buffer hit rate for writes +system.physmem.avgGap 611088.62 # Average gap between requests +system.physmem.pageHitRate 78.92 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 276203849000 # Time in different power states +system.physmem.memoryStateTime::REF 13724100000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 120335301000 # Time in different power states +system.physmem.memoryStateTime::ACT 121069531000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 544939920 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 524943720 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 297338250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 286427625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1495143000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1465986600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 953104320 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 942425280 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 26738559120 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 26738559120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 61488174015 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 58208465835 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 191689779750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 194566716750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 283207038375 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 282733524930 # Total energy per rank (pJ) -system.physmem.averagePower::0 691.798455 # Core power per rank (mW) -system.physmem.averagePower::1 690.641789 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 173391 # Transaction distribution -system.membus.trans_dist::ReadResp 173391 # Transaction distribution -system.membus.trans_dist::Writeback 292561 # Transaction distribution -system.membus.trans_dist::ReadExReq 206625 # Transaction distribution -system.membus.trans_dist::ReadExResp 206625 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1052593 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1052593 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43044928 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43044928 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 672577 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 672577 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 672577 # Request fanout histogram -system.membus.reqLayer0.occupancy 3204370000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 3607409500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 123709339 # Number of BP lookups -system.cpu.branchPred.condPredicted 87626566 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6391113 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 71478402 # Number of BTB lookups -system.cpu.branchPred.BTBHits 67228425 # Number of BTB hits +system.physmem.actEnergy::0 545847120 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 524837880 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 297833250 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 286369875 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 1495111800 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 1465471800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 953117280 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 942373440 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 26844339600 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 26844339600 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 61600136265 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 58531832820 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 192563272500 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 195254766750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 284299657815 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 283849992165 # Total energy per rank (pJ) +system.physmem.averagePower::0 691.730926 # Core power per rank (mW) +system.physmem.averagePower::1 690.636842 # Core power per rank (mW) +system.cpu.branchPred.lookups 124266527 # Number of BP lookups +system.cpu.branchPred.condPredicted 87927203 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6406168 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 71920312 # Number of BTB lookups +system.cpu.branchPred.BTBHits 67440384 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.054180 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 14930713 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1120398 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.770984 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15061672 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1126459 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 149300115 # DTB read hits -system.cpu.dtb.read_misses 537223 # DTB read misses +system.cpu.dtb.read_hits 149394307 # DTB read hits +system.cpu.dtb.read_misses 568771 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 149837338 # DTB read accesses -system.cpu.dtb.write_hits 57314034 # DTB write hits -system.cpu.dtb.write_misses 66532 # DTB write misses +system.cpu.dtb.read_accesses 149963078 # DTB read accesses +system.cpu.dtb.write_hits 57322555 # DTB write hits +system.cpu.dtb.write_misses 67010 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 57380566 # DTB write accesses -system.cpu.dtb.data_hits 206614149 # DTB hits -system.cpu.dtb.data_misses 603755 # DTB misses +system.cpu.dtb.write_accesses 57389565 # DTB write accesses +system.cpu.dtb.data_hits 206716862 # DTB hits +system.cpu.dtb.data_misses 635781 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 207217904 # DTB accesses -system.cpu.itb.fetch_hits 225746689 # ITB hits +system.cpu.dtb.data_accesses 207352643 # DTB accesses +system.cpu.itb.fetch_hits 226799477 # ITB hits system.cpu.itb.fetch_misses 48 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 225746737 # ITB accesses +system.cpu.itb.fetch_accesses 226799525 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -346,71 +319,187 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 485 # Number of system calls -system.cpu.numCycles 818759407 # number of cpu cycles simulated +system.cpu.numCycles 822006022 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 611901617 # Number of instructions committed system.cpu.committedOps 611901617 # Number of ops (including micro ops) committed -system.cpu.discardedOps 13148655 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 12977706 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.338057 # CPI: cycles per instruction -system.cpu.ipc 0.747352 # IPC: instructions per cycle -system.cpu.tickCycles 736857348 # Number of cycles that the object actually ticked -system.cpu.idleCycles 81902059 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 3155 # number of replacements -system.cpu.icache.tags.tagsinuse 1116.246910 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 225741705 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4984 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 45293.279494 # Average number of references to valid blocks. +system.cpu.cpi 1.343363 # CPI: cycles per instruction +system.cpu.ipc 0.744400 # IPC: instructions per cycle +system.cpu.tickCycles 741717254 # Number of cycles that the object actually ticked +system.cpu.idleCycles 80288768 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 2535461 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.779511 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 202630719 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2539557 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 79.789790 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1608227250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 4087.779511 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.997993 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997993 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 830 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3144 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 414705281 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 414705281 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 146964513 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 146964513 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 55666206 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 55666206 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.inst 202630719 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 202630719 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 202630719 # number of overall hits +system.cpu.dcache.overall_hits::total 202630719 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 1908315 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1908315 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 1543828 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1543828 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 3452143 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3452143 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 3452143 # number of overall misses +system.cpu.dcache.overall_misses::total 3452143 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 36427451000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 36427451000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 45003472500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 45003472500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 81430923500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 81430923500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 81430923500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 81430923500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 148872828 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 148872828 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 57210034 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 57210034 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 206082862 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 206082862 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 206082862 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 206082862 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.012818 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012818 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.026985 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.026985 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.016751 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016751 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.016751 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.016751 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 19088.803997 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19088.803997 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29150.574092 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29150.574092 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 23588.514004 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23588.514004 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 23588.514004 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23588.514004 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 2340066 # number of writebacks +system.cpu.dcache.writebacks::total 2340066 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 143549 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 143549 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 769037 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 769037 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 912586 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 912586 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 912586 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 912586 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1764766 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1764766 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 774791 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 774791 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 2539557 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2539557 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 2539557 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2539557 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 30235919500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30235919500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 21217351500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 21217351500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 51453271000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 51453271000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 51453271000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 51453271000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.011854 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.011854 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.013543 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.013543 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.012323 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012323 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.012323 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012323 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 17133.104049 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17133.104049 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 27384.612754 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27384.612754 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 20260.726969 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20260.726969 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 20260.726969 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20260.726969 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 3180 # number of replacements +system.cpu.icache.tags.tagsinuse 1117.063523 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 226794468 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5009 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 45277.394290 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1116.246910 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.545042 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.545042 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1117.063523 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.545441 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.545441 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 77 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 75 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1590 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 451498362 # Number of tag accesses -system.cpu.icache.tags.data_accesses 451498362 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 225741705 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 225741705 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 225741705 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 225741705 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 225741705 # number of overall hits -system.cpu.icache.overall_hits::total 225741705 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4984 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4984 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4984 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4984 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4984 # number of overall misses -system.cpu.icache.overall_misses::total 4984 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 227159500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 227159500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 227159500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 227159500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 227159500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 227159500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 225746689 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 225746689 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 225746689 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 225746689 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 225746689 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 225746689 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 453603963 # Number of tag accesses +system.cpu.icache.tags.data_accesses 453603963 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 226794468 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 226794468 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 226794468 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 226794468 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 226794468 # number of overall hits +system.cpu.icache.overall_hits::total 226794468 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5009 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5009 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5009 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5009 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5009 # number of overall misses +system.cpu.icache.overall_misses::total 5009 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 228135750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 228135750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 228135750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 228135750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 228135750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 228135750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 226799477 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 226799477 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 226799477 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 226799477 # 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average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 45577.748796 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 45577.748796 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 45577.748796 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45545.168696 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 45545.168696 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 45545.168696 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 45545.168696 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 45545.168696 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 45545.168696 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -419,290 +508,198 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4984 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4984 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4984 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4984 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4984 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4984 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 216090500 # 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number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 217013250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 217013250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 217013250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 217013250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 217013250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 217013250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # 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average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43324.665602 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 43324.665602 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43324.665602 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 43324.665602 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 1766375 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1766375 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2340053 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 778163 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 778163 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9968 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7419161 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7429129 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 318976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312294848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312613824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.l2cache.tags.replacements 347295 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29499.192462 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3711110 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 379718 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 9.773332 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 188708225000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 21419.039362 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 8080.153100 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.653657 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.246587 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.900244 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32423 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 225 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13171 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18829 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.989471 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 40234911 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 40234911 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 1593051 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1593051 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2340066 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2340066 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 571510 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 571510 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2164561 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2164561 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2164561 # number of overall hits +system.cpu.l2cache.overall_hits::total 2164561 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 173378 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 173378 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 206627 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 206627 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 380005 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 380005 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 380005 # number of overall misses +system.cpu.l2cache.overall_misses::total 380005 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12684862500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 12684862500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 14767694250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 14767694250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 27452556750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 27452556750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 27452556750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 27452556750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1766429 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1766429 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2340066 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2340066 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 778137 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 778137 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 2544566 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2544566 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 2544566 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2544566 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.098152 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.098152 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.265541 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.265541 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.149340 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.149340 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.149340 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.149340 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73163.045484 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73163.045484 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71470.302768 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71470.302768 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72242.619834 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72242.619834 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72242.619834 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72242.619834 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 292570 # number of writebacks +system.cpu.l2cache.writebacks::total 292570 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 173378 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 173378 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 206627 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206627 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 380005 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 380005 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 380005 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 380005 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10473281000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10473281000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 12138501750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12138501750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22611782750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 22611782750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22611782750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 22611782750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.098152 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.098152 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.265541 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265541 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.149340 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.149340 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.149340 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.149340 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60407.208527 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60407.208527 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58745.961322 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58745.961322 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59503.908501 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59503.908501 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59503.908501 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59503.908501 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 1766429 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1766429 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2340066 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 778137 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 778137 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10018 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7419180 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7429198 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 320576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312295872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312616448 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4884591 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 4884632 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4884591 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4884632 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4884591 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4782348500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4884632 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4782382000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 8026500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 8065750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3891677000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 347305 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29490.835705 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3711078 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 379729 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 9.772964 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 188662245000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 21414.068024 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8076.767680 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.653505 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.246483 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.899989 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32424 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 224 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13174 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18828 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.989502 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40234620 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40234620 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 1592984 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1592984 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2340053 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2340053 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 571538 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 571538 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2164522 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2164522 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2164522 # number of overall hits -system.cpu.l2cache.overall_hits::total 2164522 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 173391 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 173391 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 206625 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206625 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 380016 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 380016 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 380016 # number of overall misses -system.cpu.l2cache.overall_misses::total 380016 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12672589500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 12672589500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 14785830500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 14785830500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 27458420000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 27458420000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 27458420000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 27458420000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1766375 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1766375 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2340053 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2340053 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 778163 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 778163 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 2544538 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2544538 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 2544538 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2544538 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.098162 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.098162 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.265529 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.265529 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.149346 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.149346 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.149346 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.149346 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73086.777860 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73086.777860 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71558.768300 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71558.768300 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72255.957644 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72255.957644 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72255.957644 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72255.957644 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 292561 # number of writebacks -system.cpu.l2cache.writebacks::total 292561 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 173391 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 173391 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 206625 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206625 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 380016 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 380016 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 380016 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 380016 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10460652500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10460652500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 12167413500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12167413500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22628066000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 22628066000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22628066000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 22628066000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.098162 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.265529 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265529 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.149346 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.149346 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.149346 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.149346 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60329.846993 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60329.846993 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58886.453721 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58886.453721 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59545.034946 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59545.034946 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59545.034946 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59545.034946 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2535458 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.758418 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 202542728 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2539554 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 79.755236 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1608245250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4087.758418 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.997988 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997988 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 828 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3146 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 414529138 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 414529138 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 146876552 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 146876552 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 55666176 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 55666176 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 202542728 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 202542728 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 202542728 # number of overall hits -system.cpu.dcache.overall_hits::total 202542728 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 1908206 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1908206 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 1543858 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1543858 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 3452064 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3452064 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 3452064 # number of overall misses -system.cpu.dcache.overall_misses::total 3452064 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 36392982500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36392982500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 45181402750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 45181402750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 81574385250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 81574385250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 81574385250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 81574385250 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 148784758 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 148784758 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 57210034 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 57210034 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 205994792 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 205994792 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 205994792 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 205994792 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.012825 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012825 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.026986 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.026986 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.016758 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.016758 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.016758 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.016758 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 19071.831081 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19071.831081 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29265.258042 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29265.258042 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 23630.612077 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23630.612077 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 23630.612077 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23630.612077 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2340053 # number of writebacks -system.cpu.dcache.writebacks::total 2340053 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 143482 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 143482 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 769028 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 769028 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 912510 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 912510 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 912510 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 912510 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1764724 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1764724 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 774830 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 774830 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 2539554 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2539554 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 2539554 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2539554 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 30222763750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30222763750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 21236491750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 21236491750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 51459255500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 51459255500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 51459255500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 51459255500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.011861 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.011861 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.013544 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.013544 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.012328 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012328 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.012328 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012328 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 17126.056964 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17126.056964 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 27407.936902 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27407.936902 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 20263.107420 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20263.107420 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 20263.107420 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20263.107420 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.respLayer1.occupancy 3891670500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.trans_dist::ReadReq 173378 # Transaction distribution +system.membus.trans_dist::ReadResp 173378 # Transaction distribution +system.membus.trans_dist::Writeback 292570 # Transaction distribution +system.membus.trans_dist::ReadExReq 206627 # Transaction distribution +system.membus.trans_dist::ReadExResp 206627 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1052580 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1052580 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43044800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43044800 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 672575 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 672575 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 672575 # Request fanout histogram +system.membus.reqLayer0.occupancy 3222733000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 3617871750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index c27afafd9..940b25691 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,101 +1,101 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.361881 # Number of seconds simulated -sim_ticks 361880862500 # Number of ticks simulated -final_tick 361880862500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.365348 # Number of seconds simulated +sim_ticks 365347511000 # Number of ticks simulated +final_tick 365347511000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 214559 # Simulator instruction rate (inst/s) -host_op_rate 232396 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 153272119 # Simulator tick rate (ticks/s) -host_mem_usage 259716 # Number of bytes of host memory used -host_seconds 2361.04 # Real time elapsed on the host +host_inst_rate 224796 # Simulator instruction rate (inst/s) +host_op_rate 243484 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 162123009 # Simulator tick rate (ticks/s) +host_mem_usage 256924 # Number of bytes of host memory used +host_seconds 2253.52 # Real time elapsed on the host sim_insts 506582155 # Number of instructions simulated sim_ops 548695378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 9221824 # Number of bytes read from this memory -system.physmem.bytes_read::total 9221824 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 221696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 221696 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6177344 # Number of bytes written to this memory -system.physmem.bytes_written::total 6177344 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 144091 # Number of read requests responded to by this memory -system.physmem.num_reads::total 144091 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 96521 # Number of write requests responded to by this memory -system.physmem.num_writes::total 96521 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 25483039 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25483039 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 612622 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 612622 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 17070104 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 17070104 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 17070104 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 25483039 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42553143 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 144091 # Number of read requests accepted -system.physmem.writeReqs 96521 # Number of write requests accepted -system.physmem.readBursts 144091 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 96521 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9215168 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6656 # Total number of bytes read from write queue -system.physmem.bytesWritten 6176128 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9221824 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6177344 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 104 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 9224896 # Number of bytes read from this memory +system.physmem.bytes_read::total 9224896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 221312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 221312 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6179008 # Number of bytes written to this memory +system.physmem.bytes_written::total 6179008 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 144139 # Number of read requests responded to by this memory +system.physmem.num_reads::total 144139 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96547 # Number of write requests responded to by this memory +system.physmem.num_writes::total 96547 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 25249648 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25249648 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 605758 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 605758 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 16912687 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 16912687 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 16912687 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 25249648 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42162335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 144139 # Number of read requests accepted +system.physmem.writeReqs 96547 # Number of write requests accepted +system.physmem.readBursts 144139 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 96547 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9218048 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6848 # Total number of bytes read from write queue +system.physmem.bytesWritten 6177856 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9224896 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6179008 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 107 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9338 # Per bank write bursts -system.physmem.perBankRdBursts::1 8967 # Per bank write bursts -system.physmem.perBankRdBursts::2 9003 # Per bank write bursts -system.physmem.perBankRdBursts::3 8705 # Per bank write bursts -system.physmem.perBankRdBursts::4 9445 # Per bank write bursts -system.physmem.perBankRdBursts::5 9343 # Per bank write bursts -system.physmem.perBankRdBursts::6 8943 # Per bank write bursts -system.physmem.perBankRdBursts::7 8100 # Per bank write bursts -system.physmem.perBankRdBursts::8 8560 # Per bank write bursts -system.physmem.perBankRdBursts::9 8672 # Per bank write bursts -system.physmem.perBankRdBursts::10 8773 # Per bank write bursts -system.physmem.perBankRdBursts::11 9480 # Per bank write bursts -system.physmem.perBankRdBursts::12 9371 # Per bank write bursts -system.physmem.perBankRdBursts::13 9512 # Per bank write bursts -system.physmem.perBankRdBursts::14 8706 # Per bank write bursts -system.physmem.perBankRdBursts::15 9069 # Per bank write bursts -system.physmem.perBankWrBursts::0 6189 # Per bank write bursts +system.physmem.perBankRdBursts::0 9344 # Per bank write bursts +system.physmem.perBankRdBursts::1 8969 # Per bank write bursts +system.physmem.perBankRdBursts::2 8998 # Per bank write bursts +system.physmem.perBankRdBursts::3 8704 # Per bank write bursts +system.physmem.perBankRdBursts::4 9453 # Per bank write bursts +system.physmem.perBankRdBursts::5 9341 # Per bank write bursts +system.physmem.perBankRdBursts::6 8940 # Per bank write bursts +system.physmem.perBankRdBursts::7 8101 # Per bank write bursts +system.physmem.perBankRdBursts::8 8571 # Per bank write bursts +system.physmem.perBankRdBursts::9 8677 # Per bank write bursts +system.physmem.perBankRdBursts::10 8772 # Per bank write bursts +system.physmem.perBankRdBursts::11 9476 # Per bank write bursts +system.physmem.perBankRdBursts::12 9379 # Per bank write bursts +system.physmem.perBankRdBursts::13 9523 # Per bank write bursts +system.physmem.perBankRdBursts::14 8710 # Per bank write bursts +system.physmem.perBankRdBursts::15 9074 # Per bank write bursts +system.physmem.perBankWrBursts::0 6191 # Per bank write bursts system.physmem.perBankWrBursts::1 6093 # Per bank write bursts -system.physmem.perBankWrBursts::2 6008 # Per bank write bursts -system.physmem.perBankWrBursts::3 5816 # Per bank write bursts -system.physmem.perBankWrBursts::4 6159 # Per bank write bursts -system.physmem.perBankWrBursts::5 6173 # Per bank write bursts -system.physmem.perBankWrBursts::6 6014 # Per bank write bursts +system.physmem.perBankWrBursts::2 6006 # Per bank write bursts +system.physmem.perBankWrBursts::3 5817 # Per bank write bursts +system.physmem.perBankWrBursts::4 6161 # Per bank write bursts +system.physmem.perBankWrBursts::5 6171 # Per bank write bursts +system.physmem.perBankWrBursts::6 6013 # Per bank write bursts system.physmem.perBankWrBursts::7 5494 # Per bank write bursts -system.physmem.perBankWrBursts::8 5724 # Per bank write bursts -system.physmem.perBankWrBursts::9 5818 # Per bank write bursts +system.physmem.perBankWrBursts::8 5728 # Per bank write bursts +system.physmem.perBankWrBursts::9 5821 # Per bank write bursts system.physmem.perBankWrBursts::10 5961 # Per bank write bursts -system.physmem.perBankWrBursts::11 6447 # Per bank write bursts -system.physmem.perBankWrBursts::12 6306 # Per bank write bursts -system.physmem.perBankWrBursts::13 6267 # Per bank write bursts -system.physmem.perBankWrBursts::14 5992 # Per bank write bursts -system.physmem.perBankWrBursts::15 6041 # Per bank write bursts +system.physmem.perBankWrBursts::11 6446 # Per bank write bursts +system.physmem.perBankWrBursts::12 6308 # Per bank write bursts +system.physmem.perBankWrBursts::13 6280 # Per bank write bursts +system.physmem.perBankWrBursts::14 5994 # Per bank write bursts +system.physmem.perBankWrBursts::15 6045 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 361880833500 # Total gap between requests +system.physmem.totGap 365347483000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 144091 # Read request sizes (log2) +system.physmem.readPktSize::6 144139 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 96521 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 143620 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 348 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see +system.physmem.writePktSize::6 96547 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 143660 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -140,38 +140,38 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5703 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5637 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5604 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5536 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5626 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5584 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see @@ -189,123 +189,98 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64681 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 237.949073 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 157.463319 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 243.404639 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24397 37.72% 37.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18169 28.09% 65.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6808 10.53% 76.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7802 12.06% 88.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2168 3.35% 91.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1166 1.80% 93.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 777 1.20% 94.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 613 0.95% 95.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 2781 4.30% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64681 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5584 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.784921 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 381.788967 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5580 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 64866 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 237.344433 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 157.101707 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 243.291878 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24488 37.75% 37.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18300 28.21% 65.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6859 10.57% 76.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7791 12.01% 88.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2064 3.18% 91.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1161 1.79% 93.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 764 1.18% 94.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 681 1.05% 95.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2758 4.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64866 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5569 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.862992 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 382.285392 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5565 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5584 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5584 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.281877 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.171400 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.885179 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5428 97.21% 97.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 84 1.50% 98.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 28 0.50% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 20 0.36% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 9 0.16% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 7 0.13% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 2 0.04% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 2 0.04% 99.95% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5569 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5569 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.333273 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.210704 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 3.188900 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5418 97.29% 97.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 79 1.42% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 23 0.41% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 20 0.36% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 9 0.16% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 7 0.13% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 5 0.09% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 5 0.09% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::52-55 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::160-163 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5584 # Writes before turning the bus around for reads -system.physmem.totQLat 1580318000 # Total ticks spent queuing -system.physmem.totMemAccLat 4280074250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 719935000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10975.42 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 5569 # Writes before turning the bus around for reads +system.physmem.totQLat 1570268250 # Total ticks spent queuing +system.physmem.totMemAccLat 4270868250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 720160000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10902.22 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29725.42 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 25.46 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 17.07 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 25.48 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 17.07 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29652.22 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 25.23 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 16.91 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 25.25 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 16.91 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.33 # Data bus utilization in percentage system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.42 # Average write queue length when enqueuing -system.physmem.readRowHits 111153 # Number of row buffer hits during reads -system.physmem.writeRowHits 64649 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.20 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.98 # Row buffer hit rate for writes -system.physmem.avgGap 1504001.60 # Average gap between requests -system.physmem.pageHitRate 73.10 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 254039828500 # Time in different power states -system.physmem.memoryStateTime::REF 12083760000 # Time in different power states +system.physmem.avgWrQLen 19.86 # Average write queue length when enqueuing +system.physmem.readRowHits 110988 # Number of row buffer hits during reads +system.physmem.writeRowHits 64704 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.06 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 67.02 # Row buffer hit rate for writes +system.physmem.avgGap 1517942.39 # Average gap between requests +system.physmem.pageHitRate 73.03 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 256543365500 # Time in different power states +system.physmem.memoryStateTime::REF 12199720000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 95752175500 # Time in different power states +system.physmem.memoryStateTime::ACT 96603610750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 246146040 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 242562600 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 134305875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 132350625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 560164800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 562497000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 310469760 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 314539200 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 23635834560 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 23635834560 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 46793455740 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 46253268450 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 176077509750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 176551358250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 247757886525 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 247692410685 # Total energy per rank (pJ) -system.physmem.averagePower::0 684.652353 # Core power per rank (mW) -system.physmem.averagePower::1 684.471418 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 43225 # Transaction distribution -system.membus.trans_dist::ReadResp 43225 # Transaction distribution -system.membus.trans_dist::Writeback 96521 # Transaction distribution -system.membus.trans_dist::ReadExReq 100866 # Transaction distribution -system.membus.trans_dist::ReadExResp 100866 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384703 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 384703 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15399168 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15399168 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 240612 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 240612 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 240612 # Request fanout histogram -system.membus.reqLayer0.occupancy 1075136000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1362650250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 132262855 # Number of BP lookups -system.cpu.branchPred.condPredicted 98270441 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6551317 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 68771118 # Number of BTB lookups -system.cpu.branchPred.BTBHits 64694090 # Number of BTB hits +system.physmem.actEnergy::0 246584520 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 243719280 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 134545125 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 132981750 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 560422200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 562972800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 310625280 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 314778960 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 23862652320 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 23862652320 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 47112370740 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 46678345380 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 177881368500 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 178262092500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 250108568685 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 250057542990 # Total energy per rank (pJ) +system.physmem.averagePower::0 684.578732 # Core power per rank (mW) +system.physmem.averagePower::1 684.439068 # Core power per rank (mW) +system.cpu.branchPred.lookups 132580026 # Number of BP lookups +system.cpu.branchPred.condPredicted 98506360 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6554090 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 69003825 # Number of BTB lookups +system.cpu.branchPred.BTBHits 64853184 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.071598 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9992883 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 17801 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.984912 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 10016062 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 17737 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -391,71 +366,195 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 723761725 # number of cpu cycles simulated +system.cpu.numCycles 730695022 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 506582155 # Number of instructions committed system.cpu.committedOps 548695378 # Number of ops (including micro ops) committed -system.cpu.discardedOps 14127209 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 13461717 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.428715 # CPI: cycles per instruction -system.cpu.ipc 0.699929 # IPC: instructions per cycle -system.cpu.tickCycles 687792337 # Number of cycles that the object actually ticked -system.cpu.idleCycles 35969388 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 17682 # number of replacements -system.cpu.icache.tags.tagsinuse 1187.679119 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 200328523 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 19553 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10245.411088 # Average number of references to valid blocks. +system.cpu.cpi 1.442402 # CPI: cycles per instruction +system.cpu.ipc 0.693288 # IPC: instructions per cycle +system.cpu.tickCycles 695775254 # Number of cycles that the object actually ticked +system.cpu.idleCycles 34919768 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1139848 # number of replacements +system.cpu.dcache.tags.tagsinuse 4071.076883 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 171283127 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1143944 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 149.730343 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 4867376000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.076883 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.993915 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993915 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 550 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3502 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 346820764 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 346820764 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 114767369 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114767369 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 53538676 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53538676 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 1488541 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.inst 1488541 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.inst 168306045 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168306045 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 168306045 # number of overall hits +system.cpu.dcache.overall_hits::total 168306045 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 854653 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 854653 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 700630 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 700630 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 1555283 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1555283 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 1555283 # number of overall misses +system.cpu.dcache.overall_misses::total 1555283 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 13708895232 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13708895232 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20586763000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20586763000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 34295658232 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34295658232 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 34295658232 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34295658232 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 115622022 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 115622022 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 1488541 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 1488541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 169861328 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 169861328 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 169861328 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 169861328 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.007392 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.007392 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012917 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.012917 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.009156 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009156 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.009156 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009156 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16040.305518 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16040.305518 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29383.216534 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29383.216534 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22051.072526 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22051.072526 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22051.072526 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22051.072526 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 1068569 # number of writebacks +system.cpu.dcache.writebacks::total 1068569 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 66869 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 66869 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 344470 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 344470 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 411339 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 411339 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 411339 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 411339 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 787784 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 787784 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 356160 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 356160 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 1143944 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1143944 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 1143944 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1143944 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 11256226015 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11256226015 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10106063500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10106063500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 21362289515 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21362289515 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 21362289515 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 21362289515 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.006813 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006813 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.006566 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006566 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.006735 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006735 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.006735 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006735 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14288.467416 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14288.467416 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28375.065982 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28375.065982 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18674.244119 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18674.244119 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18674.244119 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18674.244119 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # 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Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 301 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1411 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 401938802 # Number of tag accesses +system.cpu.icache.tags.data_accesses 401938802 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 200940130 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 200940130 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 200940130 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 200940130 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 200940130 # number of overall hits +system.cpu.icache.overall_hits::total 200940130 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 19514 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 19514 # 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average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23952.418520 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23952.418520 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23952.418520 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23952.418520 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23952.418520 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -464,44 +563,164 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # 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number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 426999505 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 426999505 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 426999505 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 426999505 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000097 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000097 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000097 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21881.700574 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21881.700574 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21881.700574 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21881.700574 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21881.700574 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21881.700574 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 806891 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 806891 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1068421 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 356400 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 356400 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39106 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3355897 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3395003 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1251392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141578176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 142829568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.l2cache.tags.replacements 111385 # number of replacements +system.cpu.l2cache.tags.tagsinuse 27648.726753 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1684688 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 142574 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 11.816236 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 163201810500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 23524.085448 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4124.641306 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.717898 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.125874 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.843772 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 31189 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 322 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4940 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25859 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951813 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 18355203 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 18355203 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 763758 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 763758 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1068569 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1068569 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 255544 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 255544 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1019302 # 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number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7196834000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7196834000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 10428398500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10428398500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 10428398500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10428398500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 807045 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 807045 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1068569 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1068569 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 356413 # 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miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.123903 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.123903 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74654.388153 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74654.388153 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71348.323072 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71348.323072 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72341.064541 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72341.064541 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72341.064541 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72341.064541 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 96547 # number of writebacks +system.cpu.l2cache.writebacks::total 96547 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 17 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 17 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 17 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 43270 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 43270 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 100869 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 100869 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 144139 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 144139 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 144139 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 144139 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2682518500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2682518500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 5916082000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5916082000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8598600500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8598600500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8598600500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8598600500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.053615 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053615 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.283012 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283012 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.123888 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123888 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.123888 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123888 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61994.880980 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61994.880980 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58651.141580 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58651.141580 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59654.919904 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59654.919904 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59654.919904 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59654.919904 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 807045 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 807045 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1068569 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 356413 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 356413 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39028 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3356457 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3395485 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1248896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141600832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 142849728 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2231712 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 2232027 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -510,262 +729,41 @@ system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Re system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 2231712 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 2232027 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2231712 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2184277000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2232027 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2184582500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 30013998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 29960995 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1744433986 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1744681985 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 111337 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27632.941712 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1684357 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 142526 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 11.817893 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 162521333500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23524.774692 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4108.167019 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.717919 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.125371 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.843290 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31189 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 323 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4930 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25866 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951813 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 18352622 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 18352622 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 763650 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 763650 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1068421 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1068421 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 255534 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 255534 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1019184 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1019184 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1019184 # number of overall hits -system.cpu.l2cache.overall_hits::total 1019184 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 43241 # 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number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10431787000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 10431787000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10431787000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 806891 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 806891 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1068421 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1068421 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 356400 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 356400 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1163291 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1163291 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1163291 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1163291 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.053590 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.053590 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.283013 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.283013 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.123879 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.123879 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.123879 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.123879 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74480.030527 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74480.030527 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71492.832074 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71492.832074 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72389.176098 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72389.176098 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72389.176098 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72389.176098 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 96521 # number of writebacks -system.cpu.l2cache.writebacks::total 96521 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 16 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 16 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 16 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 43225 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 43225 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 100866 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 100866 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 144091 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 144091 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 144091 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 144091 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2672436250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2672436250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 5933940000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5933940000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8606376250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8606376250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8606376250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8606376250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.053570 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053570 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.283013 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283013 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.123865 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123865 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.123865 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123865 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61826.171197 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61826.171197 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58829.932782 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58829.932782 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59728.756480 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59728.756480 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59728.756480 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59728.756480 # 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Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 551 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3499 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 342867294 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 342867294 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 112791129 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 112791129 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 53538706 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53538706 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 1488541 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 1488541 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 166329835 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 166329835 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 166329835 # number of overall hits -system.cpu.dcache.overall_hits::total 166329835 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 854261 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 854261 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 700600 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 700600 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 1554861 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1554861 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 1554861 # number of overall misses -system.cpu.dcache.overall_misses::total 1554861 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 13692452733 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13692452733 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20709081750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20709081750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 34401534483 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34401534483 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 34401534483 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34401534483 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 113645390 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 113645390 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 1488541 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 167884696 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 167884696 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 167884696 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 167884696 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.007517 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.007517 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012917 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.012917 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.009261 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009261 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.009261 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009261 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16028.418403 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16028.418403 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29559.066158 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29559.066158 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22125.151048 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22125.151048 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22125.151048 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22125.151048 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1068421 # number of writebacks -system.cpu.dcache.writebacks::total 1068421 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 66670 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 66670 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 344453 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 344453 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 411123 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 411123 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 411123 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 411123 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 787591 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 787591 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 356147 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 356147 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 1143738 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1143738 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 1143738 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1143738 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 11243518014 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11243518014 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10120311000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10120311000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 21363829014 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 21363829014 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 21363829014 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 21363829014 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.006930 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006930 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.006566 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006566 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.006813 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006813 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.006813 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006813 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14275.833541 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14275.833541 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28416.106271 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28416.106271 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18678.953584 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18678.953584 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18678.953584 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18678.953584 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 43270 # Transaction distribution +system.membus.trans_dist::ReadResp 43270 # Transaction distribution +system.membus.trans_dist::Writeback 96547 # Transaction distribution +system.membus.trans_dist::ReadExReq 100869 # Transaction distribution +system.membus.trans_dist::ReadExResp 100869 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384825 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 384825 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15403904 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15403904 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 240686 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 240686 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 240686 # Request fanout histogram +system.membus.reqLayer0.occupancy 1081853000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 1366563500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index fb931db93..ca5c08420 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -1,58 +1,58 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.220941 # Number of seconds simulated -sim_ticks 220941341500 # Number of ticks simulated -final_tick 220941341500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.226819 # Number of seconds simulated +sim_ticks 226818771000 # Number of ticks simulated +final_tick 226818771000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 295257 # Simulator instruction rate (inst/s) -host_op_rate 295257 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 163632311 # Simulator tick rate (ticks/s) -host_mem_usage 243348 # Number of bytes of host memory used -host_seconds 1350.23 # Real time elapsed on the host +host_inst_rate 285609 # Simulator instruction rate (inst/s) +host_op_rate 285609 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 162496290 # Simulator tick rate (ticks/s) +host_mem_usage 242892 # Number of bytes of host memory used +host_seconds 1395.84 # Real time elapsed on the host sim_insts 398664665 # Number of instructions simulated sim_ops 398664665 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 504000 # Number of bytes read from this memory -system.physmem.bytes_read::total 504000 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 249408 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 249408 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 7875 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7875 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2281148 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2281148 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1128843 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1128843 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2281148 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2281148 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7875 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 503872 # Number of bytes read from this memory +system.physmem.bytes_read::total 503872 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 249280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 249280 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 7873 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7873 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2221474 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2221474 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1099027 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1099027 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2221474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2221474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7873 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7875 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7873 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 504000 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 503872 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 504000 # Total read bytes from the system interface side +system.physmem.bytesReadSys 503872 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 551 # Per bank write bursts -system.physmem.perBankRdBursts::1 675 # Per bank write bursts +system.physmem.perBankRdBursts::1 676 # Per bank write bursts system.physmem.perBankRdBursts::2 471 # Per bank write bursts system.physmem.perBankRdBursts::3 633 # Per bank write bursts system.physmem.perBankRdBursts::4 475 # Per bank write bursts system.physmem.perBankRdBursts::5 478 # Per bank write bursts -system.physmem.perBankRdBursts::6 564 # Per bank write bursts +system.physmem.perBankRdBursts::6 563 # Per bank write bursts system.physmem.perBankRdBursts::7 560 # Per bank write bursts -system.physmem.perBankRdBursts::8 471 # Per bank write bursts +system.physmem.perBankRdBursts::8 469 # Per bank write bursts system.physmem.perBankRdBursts::9 437 # Per bank write bursts system.physmem.perBankRdBursts::10 354 # Per bank write bursts -system.physmem.perBankRdBursts::11 324 # Per bank write bursts +system.physmem.perBankRdBursts::11 323 # Per bank write bursts system.physmem.perBankRdBursts::12 430 # Per bank write bursts system.physmem.perBankRdBursts::13 556 # Per bank write bursts system.physmem.perBankRdBursts::14 473 # Per bank write bursts -system.physmem.perBankRdBursts::15 423 # Per bank write bursts +system.physmem.perBankRdBursts::15 424 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -71,14 +71,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 220941260000 # Total gap between requests +system.physmem.totGap 226818689500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7875 # Read request sizes (log2) +system.physmem.readPktSize::6 7873 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -86,9 +86,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6821 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 971 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 83 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6808 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 980 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 85 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -182,29 +182,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1518 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 330.160738 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 197.894458 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 332.998951 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 519 34.19% 34.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 336 22.13% 56.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 186 12.25% 68.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 110 7.25% 75.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 56 3.69% 79.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 56 3.69% 83.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 37 2.44% 85.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 28 1.84% 87.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 190 12.52% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1518 # Bytes accessed per row activation -system.physmem.totQLat 53358500 # Total ticks spent queuing -system.physmem.totMemAccLat 201014750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 39375000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6775.68 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1523 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 329.076822 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 197.330219 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 334.077184 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 516 33.88% 33.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 348 22.85% 56.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 193 12.67% 69.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 104 6.83% 76.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 58 3.81% 80.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 41 2.69% 82.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 32 2.10% 84.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 40 2.63% 87.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 191 12.54% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1523 # Bytes accessed per row activation +system.physmem.totQLat 50615750 # Total ticks spent queuing +system.physmem.totMemAccLat 198234500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 39365000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6429.03 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25525.68 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.28 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25179.03 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.22 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.28 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.22 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage @@ -212,88 +212,65 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6348 # Number of row buffer hits during reads +system.physmem.readRowHits 6341 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.61 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.54 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 28056033.02 # Average gap between requests -system.physmem.pageHitRate 80.61 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 211835989750 # Time in different power states -system.physmem.memoryStateTime::REF 7377500000 # Time in different power states +system.physmem.avgGap 28809690.02 # Average gap between requests +system.physmem.pageHitRate 80.54 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 217525128250 # Time in different power states +system.physmem.memoryStateTime::REF 7573800000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1721627750 # Time in different power states +system.physmem.memoryStateTime::ACT 1714919250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 6743520 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 4717440 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 3679500 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 2574000 # Energy for precharge commands per rank (pJ) +system.physmem.actEnergy::0 6698160 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 4808160 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 3654750 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 2623500 # Energy for precharge commands per rank (pJ) system.physmem.readEnergy::0 34164000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 26902200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 26910000 # Energy for read commands per rank (pJ) system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 14430390000 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 14430390000 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 5688842535 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 5444083395 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 127570849500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 127785550500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 147734669055 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 147694217535 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.679022 # Core power per rank (mW) -system.physmem.averagePower::1 668.495929 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 4737 # Transaction distribution -system.membus.trans_dist::ReadResp 4737 # Transaction distribution -system.membus.trans_dist::ReadExReq 3138 # Transaction distribution -system.membus.trans_dist::ReadExResp 3138 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15750 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15750 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 504000 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 504000 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7875 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7875 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7875 # Request fanout histogram -system.membus.reqLayer0.occupancy 9512000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 74011500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 46221231 # Number of BP lookups -system.cpu.branchPred.condPredicted 26710053 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1012987 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 25408308 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21330923 # Number of BTB hits +system.physmem.refreshEnergy::0 14814352800 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 14814352800 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 5823022815 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 5572463355 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 130980318750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 131200107750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 151662211275 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 151621265565 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.664178 # Core power per rank (mW) +system.physmem.averagePower::1 668.483652 # Core power per rank (mW) +system.cpu.branchPred.lookups 46273762 # Number of BP lookups +system.cpu.branchPred.condPredicted 26730646 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1017469 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 25595417 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21359944 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.952552 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 8326726 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 83.452221 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 8341649 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 95595776 # DTB read hits -system.cpu.dtb.read_misses 118 # DTB read misses +system.cpu.dtb.read_hits 95585470 # DTB read hits +system.cpu.dtb.read_misses 115 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 95595894 # DTB read accesses -system.cpu.dtb.write_hits 73604420 # DTB write hits -system.cpu.dtb.write_misses 858 # DTB write misses +system.cpu.dtb.read_accesses 95585585 # DTB read accesses +system.cpu.dtb.write_hits 73606436 # DTB write hits +system.cpu.dtb.write_misses 857 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73605278 # DTB write accesses -system.cpu.dtb.data_hits 169200196 # DTB hits -system.cpu.dtb.data_misses 976 # DTB misses +system.cpu.dtb.write_accesses 73607293 # DTB write accesses +system.cpu.dtb.data_hits 169191906 # DTB hits +system.cpu.dtb.data_misses 972 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 169201172 # DTB accesses -system.cpu.itb.fetch_hits 98242303 # ITB hits -system.cpu.itb.fetch_misses 1225 # ITB misses +system.cpu.dtb.data_accesses 169192878 # DTB accesses +system.cpu.itb.fetch_hits 98781228 # ITB hits +system.cpu.itb.fetch_misses 1237 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 98243528 # ITB accesses +system.cpu.itb.fetch_accesses 98782465 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -307,253 +284,26 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 441882683 # number of cpu cycles simulated +system.cpu.numCycles 453637542 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664665 # Number of instructions committed system.cpu.committedOps 398664665 # Number of ops (including micro ops) committed -system.cpu.discardedOps 4446127 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 4467797 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.108407 # CPI: cycles per instruction -system.cpu.ipc 0.902196 # IPC: instructions per cycle -system.cpu.tickCycles 437732110 # Number of cycles that the object actually ticked -system.cpu.idleCycles 4150573 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 3195 # number of replacements -system.cpu.icache.tags.tagsinuse 1919.708570 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 98237130 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5173 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18990.359559 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1919.708570 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.937358 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.937358 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 198 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 398 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1282 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 196489779 # Number of tag accesses -system.cpu.icache.tags.data_accesses 196489779 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 98237130 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 98237130 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 98237130 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 98237130 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 98237130 # number of overall hits -system.cpu.icache.overall_hits::total 98237130 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5173 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5173 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5173 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5173 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5173 # number of overall misses -system.cpu.icache.overall_misses::total 5173 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 293560000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 293560000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 293560000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 293560000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 293560000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 293560000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 98242303 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 98242303 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 98242303 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 98242303 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 98242303 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 98242303 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000053 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000053 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000053 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000053 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000053 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56748.501836 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56748.501836 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56748.501836 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56748.501836 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56748.501836 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56748.501836 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5173 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 5173 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 5173 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 5173 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 5173 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281592000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 281592000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281592000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 281592000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281592000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 281592000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54434.950706 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54434.950706 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54434.950706 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54434.950706 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54434.950706 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54434.950706 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 6139 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 6139 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 654 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3199 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3199 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10346 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8984 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 19330 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 331072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 639488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 9992 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 9992 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 9992 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5650000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 8570500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6975500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4427.627399 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1491 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5274 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.282708 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 373.083919 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4054.543479 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011386 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123735 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.135120 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5274 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 612 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4444 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160950 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 88409 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 88409 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 1402 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1402 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 654 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 654 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 61 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 61 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1463 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1463 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1463 # number of overall hits -system.cpu.l2cache.overall_hits::total 1463 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 4737 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4737 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 3138 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 3138 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 7875 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7875 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 7875 # number of overall misses -system.cpu.l2cache.overall_misses::total 7875 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 325756750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 325756750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 212895750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 212895750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 538652500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 538652500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 538652500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 538652500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 6139 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 6139 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 654 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 654 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 3199 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 3199 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 9338 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9338 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 9338 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9338 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.771624 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.771624 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.980932 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.980932 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.843328 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.843328 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.843328 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.843328 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68768.577159 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68768.577159 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67844.407266 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67844.407266 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68400.317460 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68400.317460 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68400.317460 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68400.317460 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4737 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4737 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 3138 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 3138 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 7875 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7875 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 7875 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7875 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266376250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266376250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 173100750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 173100750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 439477000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 439477000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 439477000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 439477000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.771624 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.771624 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.980932 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980932 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.843328 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.843328 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.843328 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.843328 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56233.111674 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56233.111674 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55162.762906 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55162.762906 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55806.603175 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55806.603175 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55806.603175 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55806.603175 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.cpi 1.137893 # CPI: cycles per instruction +system.cpu.ipc 0.878818 # IPC: instructions per cycle +system.cpu.tickCycles 450174331 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3463211 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 771 # number of replacements -system.cpu.dcache.tags.tagsinuse 3291.748199 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168007181 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3291.955317 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168028615 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40337.858583 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40343.004802 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 3291.748199 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.803649 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.803649 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.inst 3291.955317 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.803700 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.803700 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id @@ -561,40 +311,40 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 216 system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 3114 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336032765 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336032765 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 94492394 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94492394 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 73514787 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73514787 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 168007181 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168007181 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 168007181 # number of overall hits -system.cpu.dcache.overall_hits::total 168007181 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 1176 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1176 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 5943 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5943 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 336075633 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336075633 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 94513823 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94513823 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 73514792 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73514792 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.inst 168028615 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168028615 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 168028615 # number of overall hits +system.cpu.dcache.overall_hits::total 168028615 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 1181 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1181 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 5938 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5938 # number of WriteReq misses system.cpu.dcache.demand_misses::cpu.inst 7119 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 7119 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 7119 # number of overall misses system.cpu.dcache.overall_misses::total 7119 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 81019000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 81019000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 393760000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 393760000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 474779000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 474779000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 474779000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 474779000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 94493570 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 94493570 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 81052500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 81052500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 391543250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 391543250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 472595750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 472595750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 472595750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 472595750 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 94515004 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 94515004 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 73520730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 168014300 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168014300 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 168014300 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168014300 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.inst 168035734 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168035734 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 168035734 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168035734 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000081 # miss rate for WriteReq accesses @@ -603,14 +353,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.000042 system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68893.707483 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68893.707483 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66256.099613 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66256.099613 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66691.810648 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66691.810648 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66691.810648 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66691.810648 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68630.397968 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68630.397968 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65938.573594 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65938.573594 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66385.131339 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66385.131339 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66385.131339 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66385.131339 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -621,30 +371,30 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 654 # number of writebacks system.cpu.dcache.writebacks::total 654 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 208 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 208 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2746 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2746 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 211 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 211 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2743 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2743 # number of WriteReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.inst 2954 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 2954 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.inst 2954 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 2954 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 968 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 968 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 3197 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3197 # number of WriteReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 970 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 970 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 3195 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3195 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.inst 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 4165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 64462750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 64462750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 216604250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 216604250 # 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number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 278643500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 278643500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for WriteReq accesses @@ -653,14 +403,264 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66593.750000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66593.750000 # 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average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56088.735220 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54510.121135 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54510.121135 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55459.735806 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55459.735806 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55459.735806 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55459.735806 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 6141 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 6141 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 654 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3198 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3198 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10348 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8984 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 19332 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 331136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 639552 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 9993 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 9993 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 9993 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5650500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 8565500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 6972500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 4736 # Transaction distribution +system.membus.trans_dist::ReadResp 4736 # Transaction distribution +system.membus.trans_dist::ReadExReq 3137 # Transaction distribution +system.membus.trans_dist::ReadExResp 3137 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15746 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15746 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 503872 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 503872 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 7873 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 7873 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 7873 # Request fanout histogram +system.membus.reqLayer0.occupancy 9387500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 73875500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index 3f279951b..a544f3c3c 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.212377 # Number of seconds simulated -sim_ticks 212377413000 # Number of ticks simulated -final_tick 212377413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.216828 # Number of seconds simulated +sim_ticks 216828260500 # Number of ticks simulated +final_tick 216828260500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 195363 # Simulator instruction rate (inst/s) -host_op_rate 234555 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 151959329 # Simulator tick rate (ticks/s) -host_mem_usage 264884 # Number of bytes of host memory used -host_seconds 1397.59 # Real time elapsed on the host +host_inst_rate 172164 # Simulator instruction rate (inst/s) +host_op_rate 206702 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 136721287 # Simulator tick rate (ticks/s) +host_mem_usage 262128 # Number of bytes of host memory used +host_seconds 1585.91 # Real time elapsed on the host sim_insts 273037856 # Number of instructions simulated sim_ops 327812213 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 485312 # Number of bytes read from this memory -system.physmem.bytes_read::total 485312 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 219008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 219008 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 7583 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2285139 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2285139 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1031221 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1031221 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2285139 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2285139 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7583 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 485440 # Number of bytes read from this memory +system.physmem.bytes_read::total 485440 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 219072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219072 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 7585 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7585 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2238823 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2238823 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1010348 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1010348 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2238823 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2238823 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7585 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7583 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7585 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 485312 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 485440 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 485312 # Total read bytes from the system interface side +system.physmem.bytesReadSys 485440 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -43,16 +43,16 @@ system.physmem.perBankRdBursts::2 628 # Pe system.physmem.perBankRdBursts::3 541 # Per bank write bursts system.physmem.perBankRdBursts::4 466 # Per bank write bursts system.physmem.perBankRdBursts::5 349 # Per bank write bursts -system.physmem.perBankRdBursts::6 173 # Per bank write bursts +system.physmem.perBankRdBursts::6 172 # Per bank write bursts system.physmem.perBankRdBursts::7 228 # Per bank write bursts system.physmem.perBankRdBursts::8 209 # Per bank write bursts -system.physmem.perBankRdBursts::9 310 # Per bank write bursts +system.physmem.perBankRdBursts::9 311 # Per bank write bursts system.physmem.perBankRdBursts::10 342 # Per bank write bursts system.physmem.perBankRdBursts::11 428 # Per bank write bursts system.physmem.perBankRdBursts::12 554 # Per bank write bursts -system.physmem.perBankRdBursts::13 705 # Per bank write bursts +system.physmem.perBankRdBursts::13 706 # Per bank write bursts system.physmem.perBankRdBursts::14 637 # Per bank write bursts -system.physmem.perBankRdBursts::15 540 # Per bank write bursts +system.physmem.perBankRdBursts::15 541 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -71,14 +71,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 212377186000 # Total gap between requests +system.physmem.totGap 216828031000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7583 # Read request sizes (log2) +system.physmem.readPktSize::6 7585 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -86,8 +86,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6625 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 897 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6628 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 896 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -182,29 +182,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1498 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 322.691589 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 189.527839 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 333.553355 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 554 36.98% 36.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 333 22.23% 59.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 160 10.68% 69.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 67 4.47% 74.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 72 4.81% 79.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 61 4.07% 83.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 43 2.87% 86.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 33 2.20% 88.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 175 11.68% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1498 # Bytes accessed per row activation -system.physmem.totQLat 52768250 # Total ticks spent queuing -system.physmem.totMemAccLat 194949500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37915000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6958.76 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1505 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 321.360797 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 189.317321 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 333.826076 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 548 36.41% 36.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 349 23.19% 59.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 163 10.83% 70.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 68 4.52% 74.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 69 4.58% 79.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 60 3.99% 83.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 33 2.19% 85.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 33 2.19% 87.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 182 12.09% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1505 # Bytes accessed per row activation +system.physmem.totQLat 50683250 # Total ticks spent queuing +system.physmem.totMemAccLat 192902000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37925000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6682.04 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25708.76 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25432.04 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.24 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.24 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage @@ -212,68 +212,45 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6077 # Number of row buffer hits during reads +system.physmem.readRowHits 6073 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.14 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.07 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 28007013.85 # Average gap between requests -system.physmem.pageHitRate 80.14 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 202838268250 # Time in different power states -system.physmem.memoryStateTime::REF 7091500000 # Time in different power states +system.physmem.avgGap 28586424.65 # Average gap between requests +system.physmem.pageHitRate 80.07 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 207228229000 # Time in different power states +system.physmem.memoryStateTime::REF 7240220000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 2441586750 # Time in different power states +system.physmem.memoryStateTime::ACT 2356912000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 4921560 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 6380640 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 2685375 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 3481500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 29897400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 28977000 # Energy for read commands per rank (pJ) +system.physmem.actEnergy::0 5012280 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 6342840 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 2734875 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 3460875 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 29905200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 29000400 # Energy for read commands per rank (pJ) system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 13870974000 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 13870974000 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 5549858010 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 5731608780 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 122553840750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 122394410250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 142012177095 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 142035832170 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.700966 # Core power per rank (mW) -system.physmem.averagePower::1 668.812352 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 4730 # Transaction distribution -system.membus.trans_dist::ReadResp 4730 # Transaction distribution -system.membus.trans_dist::ReadExReq 2853 # Transaction distribution -system.membus.trans_dist::ReadExResp 2853 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15166 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15166 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 485312 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7583 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7583 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7583 # Request fanout histogram -system.membus.reqLayer0.occupancy 8812500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 70869750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 33146132 # Number of BP lookups -system.cpu.branchPred.condPredicted 17115100 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1582628 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18038080 # Number of BTB lookups -system.cpu.branchPred.BTBHits 15622031 # Number of BTB hits +system.physmem.refreshEnergy::0 14161870320 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 14161870320 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 5651949285 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 5745162240 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 125136528000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 125054762250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 144987999960 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 145000598925 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.689925 # Core power per rank (mW) +system.physmem.averagePower::1 668.748031 # Core power per rank (mW) +system.cpu.branchPred.lookups 33221230 # Number of BP lookups +system.cpu.branchPred.condPredicted 17174007 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1583983 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 17995686 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15666979 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 86.605842 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6627212 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 87.059638 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6611215 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -359,314 +336,75 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 424754826 # number of cpu cycles simulated +system.cpu.numCycles 433656521 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 273037856 # Number of instructions committed system.cpu.committedOps 327812213 # Number of ops (including micro ops) committed -system.cpu.discardedOps 4318159 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 4064410 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.555663 # CPI: cycles per instruction -system.cpu.ipc 0.642813 # IPC: instructions per cycle -system.cpu.tickCycles 420995875 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3758951 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 36952 # number of replacements -system.cpu.icache.tags.tagsinuse 1924.941243 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 73208046 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 38889 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1882.487233 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1924.941243 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.939913 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.939913 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1488 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146532761 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146532761 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 73208046 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 73208046 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 73208046 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 73208046 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 73208046 # number of overall hits -system.cpu.icache.overall_hits::total 73208046 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 38890 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 38890 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 38890 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 38890 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 38890 # number of overall misses -system.cpu.icache.overall_misses::total 38890 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 705005996 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 705005996 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 705005996 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 705005996 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 705005996 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 705005996 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 73246936 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 73246936 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 73246936 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 73246936 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 73246936 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 73246936 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000531 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000531 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000531 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000531 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000531 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000531 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18128.207663 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18128.207663 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18128.207663 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18128.207663 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18128.207663 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18128.207663 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38890 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 38890 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 38890 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 38890 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 38890 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 38890 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 625833004 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 625833004 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 625833004 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 625833004 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 625833004 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 625833004 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000531 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000531 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000531 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16092.388892 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16092.388892 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16092.388892 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16092.388892 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16092.388892 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16092.388892 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 40531 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 40530 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1009 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2869 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2869 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77779 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10029 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 87808 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2488896 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2842112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 44409 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 44409 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 44409 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 23213500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 59030996 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7495960 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4198.136942 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 35837 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5644 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.349575 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 353.492030 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3844.644913 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.010788 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117329 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.128117 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5644 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1251 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4259 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172241 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 363785 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 363785 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 35758 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 35758 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1009 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1009 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 16 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 35774 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 35774 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 35774 # number of overall hits -system.cpu.l2cache.overall_hits::total 35774 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 4773 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4773 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 2853 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 2853 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 7626 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7626 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 7626 # number of overall misses -system.cpu.l2cache.overall_misses::total 7626 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 328394750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 328394750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 194183750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 194183750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 522578500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 522578500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 522578500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 522578500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 40531 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 40531 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1009 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1009 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 2869 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2869 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 43400 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 43400 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 43400 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 43400 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.117762 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.117762 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.994423 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.994423 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.175714 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.175714 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.175714 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.175714 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68802.587471 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68802.587471 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68063.003856 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68063.003856 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68525.898243 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68525.898243 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68525.898243 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68525.898243 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 43 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 43 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 43 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 43 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 43 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 43 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4730 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4730 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 2853 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 2853 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 7583 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7583 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 7583 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7583 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266721500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266721500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 158370750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158370750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425092250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 425092250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425092250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 425092250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.116701 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116701 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.994423 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994423 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.174724 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.174724 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.174724 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.174724 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56389.323467 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56389.323467 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55510.252366 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55510.252366 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56058.584993 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56058.584993 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56058.584993 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56058.584993 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1353 # number of replacements -system.cpu.dcache.tags.tagsinuse 3085.890938 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168774540 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4510 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37422.292683 # Average number of references to valid blocks. +system.cpu.cpi 1.588265 # CPI: cycles per instruction +system.cpu.ipc 0.629618 # IPC: instructions per cycle +system.cpu.tickCycles 430211091 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3445430 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1354 # number of replacements +system.cpu.dcache.tags.tagsinuse 3086.009332 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168783807 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37416.051208 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 3085.890938 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.753391 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.753391 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.inst 3086.009332 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.753420 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.753420 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 671 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2433 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 672 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2432 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 337568172 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 337568172 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 86705299 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86705299 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 82047451 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82047451 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 337586705 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 337586705 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 86714567 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86714567 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 82047450 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82047450 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.inst 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.inst 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 168752750 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168752750 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 168752750 # number of overall hits -system.cpu.dcache.overall_hits::total 168752750 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 2065 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2065 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 5226 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5226 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 7291 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7291 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 7291 # number of overall misses -system.cpu.dcache.overall_misses::total 7291 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 127168958 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 127168958 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 358839500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 358839500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 486008458 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 486008458 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 486008458 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 486008458 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 86707364 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86707364 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.inst 168762017 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168762017 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 168762017 # number of overall hits +system.cpu.dcache.overall_hits::total 168762017 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 2063 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2063 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 5227 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5227 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 7290 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7290 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 7290 # number of overall misses +system.cpu.dcache.overall_misses::total 7290 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 126122956 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 126122956 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 360338500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 360338500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 486461456 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 486461456 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 486461456 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 486461456 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 86716630 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86716630 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.inst 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 168760041 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168760041 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 168760041 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168760041 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.inst 168769307 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168769307 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 168769307 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168769307 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000064 # miss rate for WriteReq accesses @@ -675,14 +413,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.000043 system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.000043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61583.030508 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61583.030508 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68664.274780 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 68664.274780 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66658.683034 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66658.683034 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66658.683034 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66658.683034 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61135.703345 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 61135.703345 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68937.918500 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 68937.918500 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66729.966529 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66729.966529 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66729.966529 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66729.966529 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -691,32 +429,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1009 # number of writebacks -system.cpu.dcache.writebacks::total 1009 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 424 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 424 # number of ReadReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1010 # number of writebacks +system.cpu.dcache.writebacks::total 1010 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 422 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 422 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2357 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 2357 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 2781 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2781 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 2781 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2781 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 2779 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2779 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 2779 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2779 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1641 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1641 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 2869 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2869 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 4510 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4510 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 4510 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4510 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 100686290 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 100686290 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 197251750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 197251750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 297938040 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 297938040 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 297938040 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 297938040 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 2870 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2870 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 4511 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4511 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 4511 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 99847542 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 99847542 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 197786250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 197786250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 297633792 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 297633792 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 297633792 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 297633792 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for WriteReq accesses @@ -725,14 +463,276 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61356.666667 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61356.666667 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68752.788428 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68752.788428 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66061.649667 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66061.649667 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66061.649667 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66061.649667 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60845.546618 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60845.546618 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68915.069686 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68915.069686 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 65979.559299 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 65979.559299 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 65979.559299 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 65979.559299 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 36927 # number of replacements +system.cpu.icache.tags.tagsinuse 1924.993605 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 73270396 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 38864 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1885.302491 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1924.993605 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.939938 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.939938 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1487 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 146657386 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146657386 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 73270396 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 73270396 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 73270396 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 73270396 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 73270396 # number of overall hits +system.cpu.icache.overall_hits::total 73270396 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 38865 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 38865 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 38865 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 38865 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 38865 # number of overall misses +system.cpu.icache.overall_misses::total 38865 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 703294747 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 703294747 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 703294747 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 703294747 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 703294747 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 703294747 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 73309261 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 73309261 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 73309261 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 73309261 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 73309261 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 73309261 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000530 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000530 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000530 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000530 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000530 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000530 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18095.838081 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18095.838081 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18095.838081 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18095.838081 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18095.838081 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18095.838081 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38865 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 38865 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 38865 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 38865 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 38865 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 38865 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 624165253 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 624165253 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 624165253 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 624165253 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 624165253 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 624165253 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000530 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000530 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000530 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16059.828972 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16059.828972 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16059.828972 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16059.828972 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16059.828972 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16059.828972 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 4198.559652 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 35809 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5647 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.341243 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 353.760812 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3844.798840 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.010796 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117334 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.128130 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 5647 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1252 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4260 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172333 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 363605 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 363605 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 35730 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 35730 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1010 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1010 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 16 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 35746 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 35746 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 35746 # number of overall hits +system.cpu.l2cache.overall_hits::total 35746 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 4776 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4776 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 2854 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 2854 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 7630 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7630 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 7630 # number of overall misses +system.cpu.l2cache.overall_misses::total 7630 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 326194750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 326194750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 194720750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 194720750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 520915500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 520915500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 520915500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 520915500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 40506 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 40506 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1010 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1010 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 2870 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2870 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 43376 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 43376 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 43376 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 43376 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.117908 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.117908 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.994425 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.994425 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.175904 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.175904 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.175904 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.175904 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68298.733250 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68298.733250 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68227.312544 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68227.312544 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68272.018349 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68272.018349 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68272.018349 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68272.018349 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 45 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 45 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 45 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 45 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 45 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4731 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4731 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 2854 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 2854 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 7585 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7585 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 7585 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7585 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 264387500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 264387500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 158755250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158755250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 423142750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 423142750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 423142750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 423142750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.116798 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116798 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.994425 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.174866 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.174866 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.174866 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.174866 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55884.062566 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55884.062566 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55625.525578 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55625.525578 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55786.783125 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55786.783125 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55786.783125 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55786.783125 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 40506 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 40505 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1010 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77729 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10032 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 87761 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2487296 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2840640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 44386 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 44386 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 44386 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 23203000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 58996747 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 7500208 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 4731 # Transaction distribution +system.membus.trans_dist::ReadResp 4731 # Transaction distribution +system.membus.trans_dist::ReadExReq 2854 # Transaction distribution +system.membus.trans_dist::ReadExResp 2854 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15170 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15170 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485440 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 485440 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 7585 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 7585 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 7585 # Request fanout histogram +system.membus.reqLayer0.occupancy 8963500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 71030250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index ba9298aae..3373b2092 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -1,65 +1,65 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.555533 # Number of seconds simulated -sim_ticks 555532734000 # Number of ticks simulated -final_tick 555532734000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.559967 # Number of seconds simulated +sim_ticks 559966999500 # Number of ticks simulated +final_tick 559966999500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 316770 # Simulator instruction rate (inst/s) -host_op_rate 316770 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 189468265 # Simulator tick rate (ticks/s) -host_mem_usage 247360 # Number of bytes of host memory used -host_seconds 2932.06 # Real time elapsed on the host +host_inst_rate 393705 # Simulator instruction rate (inst/s) +host_op_rate 393705 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 237364888 # Simulator tick rate (ticks/s) +host_mem_usage 245892 # Number of bytes of host memory used +host_seconds 2359.10 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 18657152 # Number of bytes read from this memory -system.physmem.bytes_read::total 18657152 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 186688 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 186688 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 18657216 # Number of bytes read from this memory +system.physmem.bytes_read::total 18657216 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 186816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 186816 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 291518 # Number of read requests responded to by this memory -system.physmem.num_reads::total 291518 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 291519 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291519 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 33584253 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 33584253 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 336052 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 336052 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7682197 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7682197 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7682197 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 33584253 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 41266450 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 291518 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 33318421 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 33318421 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 333620 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 333620 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7621363 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7621363 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7621363 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 33318421 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40939784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 291519 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted -system.physmem.readBursts 291518 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 291519 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18640064 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 17088 # Total number of bytes read from write queue -system.physmem.bytesWritten 4266624 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18657152 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18639936 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 17280 # Total number of bytes read from write queue +system.physmem.bytesWritten 4266560 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18657216 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 267 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 270 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 17939 # Per bank write bursts -system.physmem.perBankRdBursts::1 18284 # Per bank write bursts -system.physmem.perBankRdBursts::2 18304 # Per bank write bursts -system.physmem.perBankRdBursts::3 18254 # Per bank write bursts +system.physmem.perBankRdBursts::0 17935 # Per bank write bursts +system.physmem.perBankRdBursts::1 18289 # Per bank write bursts +system.physmem.perBankRdBursts::2 18306 # Per bank write bursts +system.physmem.perBankRdBursts::3 18248 # Per bank write bursts system.physmem.perBankRdBursts::4 18163 # Per bank write bursts -system.physmem.perBankRdBursts::5 18248 # Per bank write bursts -system.physmem.perBankRdBursts::6 18324 # Per bank write bursts +system.physmem.perBankRdBursts::5 18239 # Per bank write bursts +system.physmem.perBankRdBursts::6 18320 # Per bank write bursts system.physmem.perBankRdBursts::7 18299 # Per bank write bursts -system.physmem.perBankRdBursts::8 18226 # Per bank write bursts +system.physmem.perBankRdBursts::8 18230 # Per bank write bursts system.physmem.perBankRdBursts::9 18226 # Per bank write bursts -system.physmem.perBankRdBursts::10 18216 # Per bank write bursts -system.physmem.perBankRdBursts::11 18389 # Per bank write bursts -system.physmem.perBankRdBursts::12 18256 # Per bank write bursts -system.physmem.perBankRdBursts::13 18039 # Per bank write bursts -system.physmem.perBankRdBursts::14 17980 # Per bank write bursts -system.physmem.perBankRdBursts::15 18104 # Per bank write bursts +system.physmem.perBankRdBursts::10 18219 # Per bank write bursts +system.physmem.perBankRdBursts::11 18391 # Per bank write bursts +system.physmem.perBankRdBursts::12 18259 # Per bank write bursts +system.physmem.perBankRdBursts::13 18042 # Per bank write bursts +system.physmem.perBankRdBursts::14 17977 # Per bank write bursts +system.physmem.perBankRdBursts::15 18106 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -69,7 +69,7 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4262 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4190 # Per bank write bursts +system.physmem.perBankWrBursts::9 4189 # Per bank write bursts system.physmem.perBankWrBursts::10 4150 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts @@ -78,14 +78,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 555532658500 # Total gap between requests +system.physmem.totGap 559966923500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 291518 # Read request sizes (log2) +system.physmem.readPktSize::6 291519 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -93,9 +93,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 290760 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 465 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 290734 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 487 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -140,24 +140,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4043 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 4045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -189,137 +189,113 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 105079 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 217.968119 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 139.907625 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 270.030152 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 40113 38.17% 38.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 44071 41.94% 80.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8455 8.05% 88.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 717 0.68% 88.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 543 0.52% 89.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 672 0.64% 90.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1241 1.18% 91.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1153 1.10% 92.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8114 7.72% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 105079 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4044 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 71.423096 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.196398 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 785.521839 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 4037 99.83% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-14335 2 0.05% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-16383 3 0.07% 99.95% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 104630 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 218.912664 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 140.833166 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 269.609760 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 39535 37.79% 37.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43904 41.96% 79.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8672 8.29% 88.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 695 0.66% 88.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 728 0.70% 89.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 763 0.73% 90.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1332 1.27% 91.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 808 0.77% 92.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8193 7.83% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 104630 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4042 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 71.196437 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.192949 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 784.958027 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 4035 99.83% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-14335 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-16383 4 0.10% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::16384-18431 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4044 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4044 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.485163 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.463667 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.859123 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3065 75.79% 75.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 975 24.11% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 4 0.10% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4044 # Writes before turning the bus around for reads -system.physmem.totQLat 2419619750 # Total ticks spent queuing -system.physmem.totMemAccLat 7880576000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1456255000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8307.68 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4042 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4042 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.493073 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.471357 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.863386 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3047 75.38% 75.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 992 24.54% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3 0.07% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4042 # Writes before turning the bus around for reads +system.physmem.totQLat 2990654250 # Total ticks spent queuing +system.physmem.totMemAccLat 8451573000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1456245000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10268.38 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27057.68 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 33.55 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 7.68 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 33.58 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 7.68 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29018.38 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 33.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 7.62 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 33.32 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 7.62 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.32 # Data bus utilization in percentage system.physmem.busUtilRead 0.26 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.37 # Average write queue length when enqueuing -system.physmem.readRowHits 202343 # Number of row buffer hits during reads -system.physmem.writeRowHits 50484 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.47 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.71 # Row buffer hit rate for writes -system.physmem.avgGap 1550896.45 # Average gap between requests -system.physmem.pageHitRate 70.64 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 275459224750 # Time in different power states -system.physmem.memoryStateTime::REF 18550220000 # Time in different power states +system.physmem.avgWrQLen 24.50 # Average write queue length when enqueuing +system.physmem.readRowHits 202814 # Number of row buffer hits during reads +system.physmem.writeRowHits 50461 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.64 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.67 # Row buffer hit rate for writes +system.physmem.avgGap 1563271.35 # Average gap between requests +system.physmem.pageHitRate 70.76 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 275670988500 # Time in different power states +system.physmem.memoryStateTime::REF 18698420000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 261516412250 # Time in different power states +system.physmem.memoryStateTime::ACT 265594606500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 396060840 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 398223000 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 216104625 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 217284375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1136803200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1134198000 # Energy for read commands per rank (pJ) +system.physmem.actEnergy::0 393989400 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 396952920 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 214974375 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 216591375 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 1136974800 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 1134400800 # Energy for read commands per rank (pJ) system.physmem.writeEnergy::0 216438480 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 215557200 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 36284230320 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 36284230320 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 106733795895 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 107171521695 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 239689369500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 239305399500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 384672802860 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 384726414090 # Total energy per rank (pJ) -system.physmem.averagePower::0 692.448078 # Core power per rank (mW) -system.physmem.averagePower::1 692.544584 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 224874 # Transaction distribution -system.membus.trans_dist::ReadResp 224874 # Transaction distribution -system.membus.trans_dist::Writeback 66683 # Transaction distribution -system.membus.trans_dist::ReadExReq 66644 # Transaction distribution -system.membus.trans_dist::ReadExResp 66644 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649719 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 649719 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22924864 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22924864 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 358201 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 358201 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 358201 # Request fanout histogram -system.membus.reqLayer0.occupancy 954482500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2723745500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.5 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 125108663 # Number of BP lookups -system.cpu.branchPred.condPredicted 80505376 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12157226 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 103330871 # Number of BTB lookups -system.cpu.branchPred.BTBHits 82874854 # Number of BTB hits +system.physmem.writeEnergy::1 215550720 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 36574109520 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 36574109520 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 108415975050 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 108760602465 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 240876668250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 240574363500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 387829129875 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 387872571300 # Total energy per rank (pJ) +system.physmem.averagePower::0 692.596540 # Core power per rank (mW) +system.physmem.averagePower::1 692.674119 # Core power per rank (mW) +system.cpu.branchPred.lookups 125749069 # Number of BP lookups +system.cpu.branchPred.condPredicted 81144276 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12157130 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 103970439 # Number of BTB lookups +system.cpu.branchPred.BTBHits 83513487 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.203383 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18690215 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 9442 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.324261 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18691097 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 9450 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 237537573 # DTB read hits -system.cpu.dtb.read_misses 198412 # DTB read misses +system.cpu.dtb.read_hits 237537681 # DTB read hits +system.cpu.dtb.read_misses 198468 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 237735985 # DTB read accesses -system.cpu.dtb.write_hits 98305055 # DTB write hits -system.cpu.dtb.write_misses 7206 # DTB write misses +system.cpu.dtb.read_accesses 237736149 # DTB read accesses +system.cpu.dtb.write_hits 98305023 # DTB write hits +system.cpu.dtb.write_misses 7212 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 98312261 # DTB write accesses -system.cpu.dtb.data_hits 335842628 # DTB hits -system.cpu.dtb.data_misses 205618 # DTB misses +system.cpu.dtb.write_accesses 98312235 # DTB write accesses +system.cpu.dtb.data_hits 335842704 # DTB hits +system.cpu.dtb.data_misses 205680 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 336048246 # DTB accesses -system.cpu.itb.fetch_hits 315070347 # ITB hits +system.cpu.dtb.data_accesses 336048384 # DTB accesses +system.cpu.itb.fetch_hits 317138761 # ITB hits system.cpu.itb.fetch_misses 120 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 315070467 # ITB accesses +system.cpu.itb.fetch_accesses 317138881 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -333,71 +309,188 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 1111065468 # number of cpu cycles simulated +system.cpu.numCycles 1119933999 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 928789150 # Number of instructions committed system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed -system.cpu.discardedOps 23870771 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 27043480 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.196252 # CPI: cycles per instruction -system.cpu.ipc 0.835945 # IPC: instructions per cycle -system.cpu.tickCycles 1052548202 # Number of cycles that the object actually ticked -system.cpu.idleCycles 58517266 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 10608 # number of replacements -system.cpu.icache.tags.tagsinuse 1686.446779 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 315057996 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 12350 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 25510.768907 # Average number of references to valid blocks. +system.cpu.cpi 1.205800 # CPI: cycles per instruction +system.cpu.ipc 0.829325 # IPC: instructions per cycle +system.cpu.tickCycles 1060170405 # Number of cycles that the object actually ticked +system.cpu.idleCycles 59763594 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 776532 # number of replacements +system.cpu.dcache.tags.tagsinuse 4092.890193 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 323503178 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 780628 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 414.414008 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 845912250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.890193 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.999241 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999241 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 949 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1244 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1640 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 649485148 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 649485148 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 225339131 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 225339131 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 98164047 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 98164047 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.inst 323503178 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 323503178 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 323503178 # number of overall hits +system.cpu.dcache.overall_hits::total 323503178 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 711929 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 711929 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 137153 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 137153 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 849082 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 849082 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 849082 # number of overall misses +system.cpu.dcache.overall_misses::total 849082 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23415653250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 23415653250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9042894000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9042894000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 32458547250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32458547250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 32458547250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32458547250 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 226051060 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 226051060 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 98301200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 324352260 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 324352260 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 324352260 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 324352260 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.003149 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003149 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.001395 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001395 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.002618 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002618 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.002618 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002618 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32890.433245 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32890.433245 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65932.892463 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65932.892463 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 38227.812214 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38227.812214 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 38227.812214 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38227.812214 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 91489 # number of writebacks +system.cpu.dcache.writebacks::total 91489 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 312 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 312 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 68142 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 68142 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 68454 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 68454 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 68454 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 68454 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 711617 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 711617 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 69011 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 69011 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 780628 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 780628 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 780628 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 780628 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 21914188000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21914188000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4452805750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4452805750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26366993750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26366993750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26366993750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26366993750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.003148 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003148 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002407 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002407 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002407 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002407 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30794.919177 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30794.919177 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 64523.130371 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64523.130371 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33776.643613 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 33776.643613 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33776.643613 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 33776.643613 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 10606 # number of replacements +system.cpu.icache.tags.tagsinuse 1687.447542 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 317126411 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 12349 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 25680.331282 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1686.446779 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.823460 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.823460 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1742 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1687.447542 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.823949 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.823949 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1743 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1572 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.850586 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 630153044 # Number of tag accesses -system.cpu.icache.tags.data_accesses 630153044 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 315057996 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 315057996 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 315057996 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 315057996 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 315057996 # number of overall hits -system.cpu.icache.overall_hits::total 315057996 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12351 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12351 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12351 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12351 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12351 # number of overall misses -system.cpu.icache.overall_misses::total 12351 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 334498250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 334498250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 334498250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 334498250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 334498250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 334498250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 315070347 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 315070347 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 315070347 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 315070347 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 315070347 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 315070347 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::4 1574 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.851074 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 634289871 # Number of tag accesses +system.cpu.icache.tags.data_accesses 634289871 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 317126411 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 317126411 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 317126411 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 317126411 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 317126411 # number of overall hits +system.cpu.icache.overall_hits::total 317126411 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12350 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12350 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12350 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12350 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12350 # number of overall misses +system.cpu.icache.overall_misses::total 12350 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 333735500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 333735500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 333735500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 333735500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 333735500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 333735500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 317138761 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 317138761 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 317138761 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 317138761 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 317138761 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 317138761 # 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average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27082.685613 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27023.117409 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27023.117409 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27023.117409 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27023.117409 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27023.117409 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27023.117409 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -406,132 +499,103 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 308545750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 308545750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12350 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 12350 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 12350 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 12350 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 12350 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 12350 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 307779500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 307779500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 307779500 # 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average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24981.438750 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24981.438750 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 24981.438750 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24981.438750 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 24981.438750 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24921.417004 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24921.417004 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24921.417004 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24921.417004 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24921.417004 # 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Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55815616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56606016 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 884470 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 884470 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # 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Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 29735.546909 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.087461 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.907457 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994917 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32736 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 275 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2681 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29449 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 274 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2658 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29474 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 7436245 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 7436245 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 499096 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 499096 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 7436223 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 7436223 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 499092 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 499092 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 91489 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 91489 # 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number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 792981 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 792981 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 792981 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 792981 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.310613 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.310613 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.965715 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.965715 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.367624 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.367624 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.367624 # 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number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 792978 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 792978 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 792978 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 792978 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.310615 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.310615 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.965716 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.965716 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.367627 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.367627 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.367627 # 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number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -544,153 +608,89 @@ system.cpu.l2cache.writebacks::writebacks 66683 # n system.cpu.l2cache.writebacks::total 66683 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 224875 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 224875 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 66644 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66644 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 291519 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 291519 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 291519 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 291519 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13108086750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13108086750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3516385750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3516385750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16624472500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16624472500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16624472500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16624472500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.310613 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.310613 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.965715 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3526847250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3526847250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17195446750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17195446750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17195446750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17195446750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.310615 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.310615 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.965716 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965716 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.367627 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.367627 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.367627 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.367627 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60783.099500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60783.099500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 52919.907720 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52919.907720 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58985.478698 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58985.478698 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58985.478698 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58985.478698 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 776534 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.879782 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 322859767 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 780630 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 413.588726 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 839965250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.879782 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.999238 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999238 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 950 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1254 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1629 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 648198336 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 648198336 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 224695720 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 224695720 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 98164047 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 98164047 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 322859767 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 322859767 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 322859767 # number of overall hits -system.cpu.dcache.overall_hits::total 322859767 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 711933 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 711933 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 137153 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 137153 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 849086 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 849086 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 849086 # number of overall misses -system.cpu.dcache.overall_misses::total 849086 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 22831828750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 22831828750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9022635000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9022635000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 31854463750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31854463750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 31854463750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31854463750 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 225407653 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 225407653 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 323708853 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 323708853 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 323708853 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 323708853 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.003158 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003158 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.001395 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001395 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.002623 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002623 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.002623 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002623 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32070.193052 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32070.193052 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65785.181513 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65785.181513 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 37516.180634 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37516.180634 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 37516.180634 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37516.180634 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 91489 # number of writebacks -system.cpu.dcache.writebacks::total 91489 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 313 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 313 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 68143 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 68143 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 68456 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 68456 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 68456 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 68456 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 711620 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 711620 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 69010 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 69010 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 780630 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 780630 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 780630 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 780630 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 21330988000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21330988000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4442556750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4442556750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 25773544750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 25773544750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 25773544750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 25773544750 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.003157 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003157 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002412 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002412 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002412 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002412 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 29975.250836 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29975.250836 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 64375.550645 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64375.550645 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33016.339047 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 33016.339047 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33016.339047 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 33016.339047 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 723967 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 723966 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 91489 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 69011 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 69011 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24699 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1652745 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1677444 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 790336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55815488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56605824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 884467 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 884467 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 884467 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 533722500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 19152500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 1222199250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.trans_dist::ReadReq 224874 # Transaction distribution +system.membus.trans_dist::ReadResp 224874 # Transaction distribution +system.membus.trans_dist::Writeback 66683 # Transaction distribution +system.membus.trans_dist::ReadExReq 66645 # Transaction distribution +system.membus.trans_dist::ReadExResp 66645 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649721 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 649721 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22924928 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22924928 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 358202 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 358202 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 358202 # Request fanout histogram +system.membus.reqLayer0.occupancy 975509000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 2745284750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index 12718eef7..531c5ebad 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.537826 # Number of seconds simulated -sim_ticks 537826498500 # Number of ticks simulated -final_tick 537826498500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.541781 # Number of seconds simulated +sim_ticks 541781076000 # Number of ticks simulated +final_tick 541781076000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 182992 # Simulator instruction rate (inst/s) -host_op_rate 225287 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 153620567 # Simulator tick rate (ticks/s) -host_mem_usage 318916 # Number of bytes of host memory used -host_seconds 3501.01 # Real time elapsed on the host +host_inst_rate 140173 # Simulator instruction rate (inst/s) +host_op_rate 172571 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 118539448 # Simulator tick rate (ticks/s) +host_mem_usage 261676 # Number of bytes of host memory used +host_seconds 4570.47 # Real time elapsed on the host sim_insts 640655084 # Number of instructions simulated sim_ops 788730743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 18593984 # Number of bytes read from this memory -system.physmem.bytes_read::total 18593984 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 165056 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 165056 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 18593856 # Number of bytes read from this memory +system.physmem.bytes_read::total 18593856 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 164672 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 164672 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 290531 # Number of read requests responded to by this memory -system.physmem.num_reads::total 290531 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 290529 # Number of read requests responded to by this memory +system.physmem.num_reads::total 290529 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 34572458 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 34572458 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 306895 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 306895 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7865496 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7865496 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7865496 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 34572458 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42437954 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 290531 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 34319870 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 34319870 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 303946 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 303946 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7808084 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7808084 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7808084 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 34319870 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42127954 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 290529 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted -system.physmem.readBursts 290531 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 290529 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18574784 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19200 # Total number of bytes read from write queue -system.physmem.bytesWritten 4228736 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18593984 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18573248 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20608 # Total number of bytes read from write queue +system.physmem.bytesWritten 4228480 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18593856 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 300 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 322 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18291 # Per bank write bursts -system.physmem.perBankRdBursts::1 18140 # Per bank write bursts -system.physmem.perBankRdBursts::2 18223 # Per bank write bursts -system.physmem.perBankRdBursts::3 18183 # Per bank write bursts -system.physmem.perBankRdBursts::4 18268 # Per bank write bursts +system.physmem.perBankRdBursts::0 18288 # Per bank write bursts +system.physmem.perBankRdBursts::1 18139 # Per bank write bursts +system.physmem.perBankRdBursts::2 18224 # Per bank write bursts +system.physmem.perBankRdBursts::3 18182 # Per bank write bursts +system.physmem.perBankRdBursts::4 18264 # Per bank write bursts system.physmem.perBankRdBursts::5 18315 # Per bank write bursts -system.physmem.perBankRdBursts::6 18099 # Per bank write bursts -system.physmem.perBankRdBursts::7 17920 # Per bank write bursts -system.physmem.perBankRdBursts::8 17939 # Per bank write bursts -system.physmem.perBankRdBursts::9 17964 # Per bank write bursts -system.physmem.perBankRdBursts::10 18020 # Per bank write bursts +system.physmem.perBankRdBursts::6 18098 # Per bank write bursts +system.physmem.perBankRdBursts::7 17914 # Per bank write bursts +system.physmem.perBankRdBursts::8 17936 # Per bank write bursts +system.physmem.perBankRdBursts::9 17963 # Per bank write bursts +system.physmem.perBankRdBursts::10 18015 # Per bank write bursts system.physmem.perBankRdBursts::11 18110 # Per bank write bursts -system.physmem.perBankRdBursts::12 18148 # Per bank write bursts -system.physmem.perBankRdBursts::13 18270 # Per bank write bursts -system.physmem.perBankRdBursts::14 18079 # Per bank write bursts -system.physmem.perBankRdBursts::15 18262 # Per bank write bursts +system.physmem.perBankRdBursts::12 18146 # Per bank write bursts +system.physmem.perBankRdBursts::13 18271 # Per bank write bursts +system.physmem.perBankRdBursts::14 18075 # Per bank write bursts +system.physmem.perBankRdBursts::15 18267 # Per bank write bursts system.physmem.perBankWrBursts::0 4174 # Per bank write bursts -system.physmem.perBankWrBursts::1 4102 # Per bank write bursts +system.physmem.perBankWrBursts::1 4101 # Per bank write bursts system.physmem.perBankWrBursts::2 4137 # Per bank write bursts system.physmem.perBankWrBursts::3 4147 # Per bank write bursts system.physmem.perBankWrBursts::4 4225 # Per bank write bursts @@ -70,22 +70,22 @@ system.physmem.perBankWrBursts::6 4171 # Pe system.physmem.perBankWrBursts::7 4096 # Per bank write bursts system.physmem.perBankWrBursts::8 4093 # Per bank write bursts system.physmem.perBankWrBursts::9 4093 # Per bank write bursts -system.physmem.perBankWrBursts::10 4091 # Per bank write bursts +system.physmem.perBankWrBursts::10 4090 # Per bank write bursts system.physmem.perBankWrBursts::11 4094 # Per bank write bursts -system.physmem.perBankWrBursts::12 4098 # Per bank write bursts +system.physmem.perBankWrBursts::12 4096 # Per bank write bursts system.physmem.perBankWrBursts::13 4094 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts system.physmem.perBankWrBursts::15 4138 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 537826410500 # Total gap between requests +system.physmem.totGap 541780987500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 290531 # Read request sizes (log2) +system.physmem.readPktSize::6 290529 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -93,8 +93,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 289832 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 382 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 289809 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 381 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -141,7 +141,7 @@ system.physmem.wrQLenPdf::12 1 # Wh system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 983 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 980 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 4008 # What write queue length does an incoming req see @@ -149,9 +149,9 @@ system.physmem.wrQLenPdf::20 4008 # Wh system.physmem.wrQLenPdf::21 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 4007 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 4007 # What write queue length does an incoming req see @@ -189,117 +189,91 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 111650 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 204.222194 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 132.352958 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 255.940958 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 47308 42.37% 42.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43452 38.92% 81.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8609 7.71% 89.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 837 0.75% 89.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1286 1.15% 90.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1285 1.15% 92.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 530 0.47% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 473 0.42% 92.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7870 7.05% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 111650 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 111520 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 204.445337 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 132.546078 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 256.289579 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 46919 42.07% 42.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43694 39.18% 81.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8696 7.80% 89.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 722 0.65% 89.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1258 1.13% 90.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1255 1.13% 91.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 576 0.52% 92.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 502 0.45% 92.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7898 7.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 111520 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4007 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.550786 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.062915 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 507.683026 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.543798 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.072613 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 507.664819 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 4004 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 4007 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 4007 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.489643 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.468091 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.860070 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3025 75.49% 75.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 3 0.07% 75.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 978 24.41% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.488645 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.467122 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.859477 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3028 75.57% 75.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 979 24.43% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4007 # Writes before turning the bus around for reads -system.physmem.totQLat 3341982750 # Total ticks spent queuing -system.physmem.totMemAccLat 8783814000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1451155000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11514.91 # Average queueing delay per DRAM burst +system.physmem.totQLat 2702187250 # Total ticks spent queuing +system.physmem.totMemAccLat 8143568500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1451035000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9311.24 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30264.91 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 34.54 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 7.86 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 34.57 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 7.87 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28061.24 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 34.28 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 7.80 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 34.32 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 7.81 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.33 # Data bus utilization in percentage system.physmem.busUtilRead 0.27 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.95 # Average write queue length when enqueuing -system.physmem.readRowHits 194589 # Number of row buffer hits during reads -system.physmem.writeRowHits 50052 # Number of row buffer hits during writes -system.physmem.readRowHitRate 67.05 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.72 # Row buffer hit rate for writes -system.physmem.avgGap 1508083.78 # Average gap between requests -system.physmem.pageHitRate 68.66 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 253474796750 # Time in different power states -system.physmem.memoryStateTime::REF 17958980000 # Time in different power states +system.physmem.avgWrQLen 26.42 # Average write queue length when enqueuing +system.physmem.readRowHits 194639 # Number of row buffer hits during reads +system.physmem.writeRowHits 50105 # Number of row buffer hits during writes +system.physmem.readRowHitRate 67.07 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.80 # Row buffer hit rate for writes +system.physmem.avgGap 1519181.07 # Average gap between requests +system.physmem.pageHitRate 68.69 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 263887343000 # Time in different power states +system.physmem.memoryStateTime::REF 18091060000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 266386143250 # Time in different power states +system.physmem.memoryStateTime::ACT 259796939500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 422248680 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 421734600 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 230393625 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 230113125 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1134268200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1129057800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 215634960 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 212524560 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 35127764880 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 35127764880 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 108230961600 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 107988304905 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 227752503750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 227965360500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 373113775695 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 373074860370 # Total energy per rank (pJ) -system.physmem.averagePower::0 693.752260 # Core power per rank (mW) -system.physmem.averagePower::1 693.679903 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 224439 # Transaction distribution -system.membus.trans_dist::ReadResp 224439 # Transaction distribution -system.membus.trans_dist::Writeback 66098 # Transaction distribution -system.membus.trans_dist::ReadExReq 66092 # Transaction distribution -system.membus.trans_dist::ReadExResp 66092 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 647160 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824256 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22824256 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 356629 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 356629 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 356629 # Request fanout histogram -system.membus.reqLayer0.occupancy 974401000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2738560500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.5 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 154837020 # Number of BP lookups -system.cpu.branchPred.condPredicted 104970668 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12892448 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 106220966 # Number of BTB lookups -system.cpu.branchPred.BTBHits 82647169 # Number of BTB hits +system.physmem.actEnergy::0 421530480 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 421462440 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 230001750 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 229964625 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 1134174600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 1128987600 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 215628480 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 212505120 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 35386113360 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 35386113360 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 105979651695 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 105556941405 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 232100586000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 232471384500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 375467686365 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 375407359050 # Total energy per rank (pJ) +system.physmem.averagePower::0 693.032096 # Core power per rank (mW) +system.physmem.averagePower::1 692.920745 # Core power per rank (mW) +system.cpu.branchPred.lookups 156937341 # Number of BP lookups +system.cpu.branchPred.condPredicted 106680042 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12891228 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 97536058 # Number of BTB lookups +system.cpu.branchPred.BTBHits 81874318 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 77.806832 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 19441660 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1323 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 83.942615 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 19487919 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1320 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -385,69 +359,194 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 1075652997 # number of cpu cycles simulated +system.cpu.numCycles 1083562152 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 640655084 # Number of instructions committed system.cpu.committedOps 788730743 # Number of ops (including micro ops) committed -system.cpu.discardedOps 25219021 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 22655429 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.678989 # CPI: cycles per instruction -system.cpu.ipc 0.595596 # IPC: instructions per cycle -system.cpu.tickCycles 1020176456 # Number of cycles that the object actually ticked -system.cpu.idleCycles 55476541 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 23597 # number of replacements -system.cpu.icache.tags.tagsinuse 1711.183580 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 289999264 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 25347 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11441.167160 # Average number of references to valid blocks. +system.cpu.cpi 1.691335 # CPI: cycles per instruction +system.cpu.ipc 0.591249 # IPC: instructions per cycle +system.cpu.tickCycles 1029140125 # Number of cycles that the object actually ticked +system.cpu.idleCycles 54422027 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 778221 # number of replacements +system.cpu.dcache.tags.tagsinuse 4092.644165 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 378457747 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 782317 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 483.765209 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 752182250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.644165 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.999181 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999181 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 962 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1341 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1589 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 759400731 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 759400731 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 249632505 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 249632505 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 128813764 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 128813764 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 5739 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.inst 5739 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.inst 378446269 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 378446269 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 378446269 # number of overall hits +system.cpu.dcache.overall_hits::total 378446269 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 713747 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 713747 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 137713 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 137713 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 851460 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 851460 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 851460 # number of overall misses +system.cpu.dcache.overall_misses::total 851460 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23050728217 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 23050728217 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9196889000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9196889000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 32247617217 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32247617217 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 32247617217 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32247617217 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 250346252 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250346252 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 5739 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 379297729 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 379297729 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 379297729 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 379297729 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002851 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002851 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.001068 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001068 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.002245 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.002245 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32295.376677 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32295.376677 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66783.012497 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66783.012497 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 37873.320199 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37873.320199 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 37873.320199 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37873.320199 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 91420 # number of writebacks +system.cpu.dcache.writebacks::total 91420 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 752 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 752 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 68391 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 68391 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 69143 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 69143 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 69143 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 69143 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 712995 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712995 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 69322 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 69322 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 782317 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 782317 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 782317 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 782317 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 21540338778 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21540338778 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4529678750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4529678750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26070017528 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26070017528 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26070017528 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26070017528 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002848 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000538 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002063 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30211.065685 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30211.065685 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65342.586048 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65342.586048 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33324.109700 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 33324.109700 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33324.109700 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 33324.109700 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 23590 # number of replacements +system.cpu.icache.tags.tagsinuse 1712.180354 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 289921724 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 25341 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 11440.816227 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1711.183580 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.835539 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.835539 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1750 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1598 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.854492 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 580074571 # Number of tag accesses -system.cpu.icache.tags.data_accesses 580074571 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 289999264 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 289999264 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 289999264 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 289999264 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 289999264 # number of overall hits -system.cpu.icache.overall_hits::total 289999264 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 25348 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 25348 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 25348 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 25348 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 25348 # number of overall misses -system.cpu.icache.overall_misses::total 25348 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 480691746 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 480691746 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 480691746 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 480691746 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 480691746 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 480691746 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 290024612 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 290024612 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 290024612 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 290024612 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 290024612 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 290024612 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 1712.180354 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.836026 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.836026 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1602 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 579919473 # Number of tag accesses +system.cpu.icache.tags.data_accesses 579919473 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 289921724 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 289921724 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 289921724 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 289921724 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 289921724 # number of overall hits +system.cpu.icache.overall_hits::total 289921724 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 25342 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 25342 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 25342 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 25342 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 25342 # number of overall misses +system.cpu.icache.overall_misses::total 25342 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 481750746 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 481750746 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 481750746 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 481750746 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 481750746 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 481750746 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 289947066 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 289947066 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 289947066 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 289947066 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 289947066 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 289947066 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000087 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18963.695203 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18963.695203 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18963.695203 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18963.695203 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18963.695203 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18963.695203 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19009.973404 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19009.973404 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19009.973404 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19009.973404 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19009.973404 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19009.973404 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # 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number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 429966254 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 429966254 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 429966254 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 429966254 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 429966254 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 429966254 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # 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average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16966.547786 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16966.547786 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16966.547786 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16966.547786 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 738445 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 738444 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 91420 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50695 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1656260 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1706955 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1622208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55925760 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 57547968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 899188 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 899188 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 899188 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 541014000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # 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number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4422117750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4422117750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21161526500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21161526500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21161526500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21161526500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 738445 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 738445 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_hits::cpu.inst 517097 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 517097 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 517097 # number of overall hits +system.cpu.l2cache.overall_hits::total 517097 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 224471 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 224471 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 66091 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 66091 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 290562 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 290562 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 290562 # number of overall misses +system.cpu.l2cache.overall_misses::total 290562 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16093224000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 16093224000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4428044750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4428044750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20521268750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20521268750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20521268750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20521268750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 738337 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 738337 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 91420 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 91420 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 69323 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 69323 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 807768 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 807768 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 807768 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 807768 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.303975 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.303975 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.953392 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.953392 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.359708 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.359708 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.359708 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.359708 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74573.365364 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74573.365364 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66908.517672 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66908.517672 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72829.892862 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72829.892862 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72829.892862 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72829.892862 # average overall miss latency +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 69322 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 69322 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 807659 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 807659 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 807659 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 807659 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.304022 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.304022 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.953391 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.953391 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.359758 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.359758 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.359758 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.359758 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71694.000561 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71694.000561 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66999.209423 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66999.209423 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70626.127126 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70626.127126 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70626.127126 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70626.127126 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # 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number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13281416250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13281416250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3575940250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3575940250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16857356500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16857356500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16857356500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16857356500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.303979 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.303979 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.953391 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.359719 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.359719 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.359719 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.359719 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59176.062315 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59176.062315 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54106.311752 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54106.311752 # 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number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 379293551 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 379293551 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 379293551 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 379293551 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002851 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002851 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.001067 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001067 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.002245 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.002245 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 33201.094376 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33201.094376 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66750.401573 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66750.401573 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 38622.357658 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38622.357658 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 38622.357658 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38622.357658 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 91420 # number of writebacks -system.cpu.dcache.writebacks::total 91420 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 753 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 753 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 68261 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 68261 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 69014 # 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number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 22188801525 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4523752250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4523752250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26712553775 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26712553775 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26712553775 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26712553775 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002848 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000538 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002063 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 31116.105558 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31116.105558 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65256.152359 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65256.152359 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 34140.939361 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34140.939361 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 34140.939361 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34140.939361 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 738337 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 738336 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 91420 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50683 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1656054 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1706737 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1621824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55919168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 57540992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 899079 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 899079 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 899079 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 540959500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 38562746 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 1224341972 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.trans_dist::ReadReq 224438 # Transaction distribution +system.membus.trans_dist::ReadResp 224438 # Transaction distribution +system.membus.trans_dist::Writeback 66098 # Transaction distribution +system.membus.trans_dist::ReadExReq 66091 # Transaction distribution +system.membus.trans_dist::ReadExResp 66091 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647156 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 647156 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824128 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22824128 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 356627 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 356627 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 356627 # Request fanout histogram +system.membus.reqLayer0.occupancy 983533000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 2738969000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index 2a99c07ac..a69375a69 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -1,100 +1,100 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058385 # Number of seconds simulated -sim_ticks 58384546000 # Number of ticks simulated -final_tick 58384546000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058648 # Number of seconds simulated +sim_ticks 58648243500 # Number of ticks simulated +final_tick 58648243500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 341117 # Simulator instruction rate (inst/s) -host_op_rate 341117 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 225196692 # Simulator tick rate (ticks/s) -host_mem_usage 245432 # Number of bytes of host memory used -host_seconds 259.26 # Real time elapsed on the host +host_inst_rate 296946 # Simulator instruction rate (inst/s) +host_op_rate 296946 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 196921777 # Simulator tick rate (ticks/s) +host_mem_usage 246040 # Number of bytes of host memory used +host_seconds 297.83 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 10663104 # Number of bytes read from this memory -system.physmem.bytes_read::total 10663104 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 515328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 515328 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7299072 # Number of bytes written to this memory -system.physmem.bytes_written::total 7299072 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 166611 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166611 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114048 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114048 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 182635727 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 182635727 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8826445 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8826445 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 125017192 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 125017192 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 125017192 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 182635727 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 307652919 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166611 # Number of read requests accepted -system.physmem.writeReqs 114048 # Number of write requests accepted -system.physmem.readBursts 166611 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114048 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10662592 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 512 # Total number of bytes read from write queue -system.physmem.bytesWritten 7297152 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10663104 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7299072 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 8 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 10664704 # Number of bytes read from this memory +system.physmem.bytes_read::total 10664704 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 516672 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 516672 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7299136 # Number of bytes written to this memory +system.physmem.bytes_written::total 7299136 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 166636 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166636 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114049 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114049 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 181841831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 181841831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8809676 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8809676 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 124456174 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 124456174 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 124456174 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 181841831 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 306298005 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166636 # Number of read requests accepted +system.physmem.writeReqs 114049 # Number of write requests accepted +system.physmem.readBursts 166636 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114049 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10664320 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue +system.physmem.bytesWritten 7297536 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10664704 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7299136 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10468 # Per bank write bursts +system.physmem.perBankRdBursts::0 10467 # Per bank write bursts system.physmem.perBankRdBursts::1 10513 # Per bank write bursts -system.physmem.perBankRdBursts::2 10311 # Per bank write bursts -system.physmem.perBankRdBursts::3 10090 # Per bank write bursts -system.physmem.perBankRdBursts::4 10431 # Per bank write bursts -system.physmem.perBankRdBursts::5 10426 # Per bank write bursts -system.physmem.perBankRdBursts::6 9846 # Per bank write bursts -system.physmem.perBankRdBursts::7 10302 # Per bank write bursts -system.physmem.perBankRdBursts::8 10593 # Per bank write bursts -system.physmem.perBankRdBursts::9 10643 # Per bank write bursts -system.physmem.perBankRdBursts::10 10595 # Per bank write bursts -system.physmem.perBankRdBursts::11 10255 # Per bank write bursts +system.physmem.perBankRdBursts::2 10315 # Per bank write bursts +system.physmem.perBankRdBursts::3 10094 # Per bank write bursts +system.physmem.perBankRdBursts::4 10429 # Per bank write bursts +system.physmem.perBankRdBursts::5 10431 # Per bank write bursts +system.physmem.perBankRdBursts::6 9849 # Per bank write bursts +system.physmem.perBankRdBursts::7 10303 # Per bank write bursts +system.physmem.perBankRdBursts::8 10595 # Per bank write bursts +system.physmem.perBankRdBursts::9 10644 # Per bank write bursts +system.physmem.perBankRdBursts::10 10600 # Per bank write bursts +system.physmem.perBankRdBursts::11 10258 # Per bank write bursts system.physmem.perBankRdBursts::12 10302 # Per bank write bursts -system.physmem.perBankRdBursts::13 10651 # Per bank write bursts -system.physmem.perBankRdBursts::14 10528 # Per bank write bursts -system.physmem.perBankRdBursts::15 10649 # Per bank write bursts +system.physmem.perBankRdBursts::13 10653 # Per bank write bursts +system.physmem.perBankRdBursts::14 10529 # Per bank write bursts +system.physmem.perBankRdBursts::15 10648 # Per bank write bursts system.physmem.perBankWrBursts::0 7087 # Per bank write bursts system.physmem.perBankWrBursts::1 7261 # Per bank write bursts system.physmem.perBankWrBursts::2 7255 # Per bank write bursts system.physmem.perBankWrBursts::3 6999 # Per bank write bursts system.physmem.perBankWrBursts::4 7126 # Per bank write bursts -system.physmem.perBankWrBursts::5 7178 # Per bank write bursts +system.physmem.perBankWrBursts::5 7180 # Per bank write bursts system.physmem.perBankWrBursts::6 6771 # Per bank write bursts -system.physmem.perBankWrBursts::7 7079 # Per bank write bursts -system.physmem.perBankWrBursts::8 7222 # Per bank write bursts -system.physmem.perBankWrBursts::9 6940 # Per bank write bursts -system.physmem.perBankWrBursts::10 7097 # Per bank write bursts +system.physmem.perBankWrBursts::7 7094 # Per bank write bursts +system.physmem.perBankWrBursts::8 7220 # Per bank write bursts +system.physmem.perBankWrBursts::9 6938 # Per bank write bursts +system.physmem.perBankWrBursts::10 7094 # Per bank write bursts system.physmem.perBankWrBursts::11 6991 # Per bank write bursts -system.physmem.perBankWrBursts::12 6967 # Per bank write bursts +system.physmem.perBankWrBursts::12 6965 # Per bank write bursts system.physmem.perBankWrBursts::13 7289 # Per bank write bursts -system.physmem.perBankWrBursts::14 7284 # Per bank write bursts +system.physmem.perBankWrBursts::14 7282 # Per bank write bursts system.physmem.perBankWrBursts::15 7472 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58384519500 # Total gap between requests +system.physmem.totGap 58648216500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166611 # Read request sizes (log2) +system.physmem.readPktSize::6 166636 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114048 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 164957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1618 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114049 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 165019 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1583 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -140,29 +140,29 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6978 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7028 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7031 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7036 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7068 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7078 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7083 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7023 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 758 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 777 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7026 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7035 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7039 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7066 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7087 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see @@ -189,140 +189,115 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 54365 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 330.333707 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 195.729973 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 332.976327 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19356 35.60% 35.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11696 21.51% 57.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5632 10.36% 67.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3623 6.66% 74.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2688 4.94% 79.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2044 3.76% 82.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1686 3.10% 85.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1497 2.75% 88.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6143 11.30% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 54365 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7019 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.733295 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 348.126500 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 7017 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 54349 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 330.476881 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 195.680943 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 333.305827 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19373 35.65% 35.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11674 21.48% 57.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5602 10.31% 67.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3597 6.62% 74.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2712 4.99% 79.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2058 3.79% 82.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1657 3.05% 85.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1528 2.81% 88.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6148 11.31% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 54349 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7016 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.748575 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 348.190330 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7015 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7019 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7019 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.244194 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.228515 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.751123 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6265 89.26% 89.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 18 0.26% 89.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 572 8.15% 97.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 131 1.87% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 24 0.34% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 4 0.06% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 2 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7019 # Writes before turning the bus around for reads -system.physmem.totQLat 2006026500 # Total ticks spent queuing -system.physmem.totMemAccLat 5129832750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 833015000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12040.76 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7016 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7016 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.251995 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.236052 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.756108 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6236 88.88% 88.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 15 0.21% 89.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 602 8.58% 97.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 126 1.80% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 27 0.38% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 6 0.09% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7016 # Writes before turning the bus around for reads +system.physmem.totQLat 2009240500 # Total ticks spent queuing +system.physmem.totMemAccLat 5133553000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 833150000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12058.10 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30790.76 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 182.63 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 124.98 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 182.64 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 125.02 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30808.10 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 181.84 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 124.43 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 181.84 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 124.46 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.40 # Data bus utilization in percentage -system.physmem.busUtilRead 1.43 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.98 # Data bus utilization in percentage for writes +system.physmem.busUtil 2.39 # Data bus utilization in percentage +system.physmem.busUtilRead 1.42 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.97 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.87 # Average write queue length when enqueuing -system.physmem.readRowHits 144815 # Number of row buffer hits during reads -system.physmem.writeRowHits 81433 # Number of row buffer hits during writes +system.physmem.avgWrQLen 24.05 # Average write queue length when enqueuing +system.physmem.readRowHits 144828 # Number of row buffer hits during reads +system.physmem.writeRowHits 81470 # Number of row buffer hits during writes system.physmem.readRowHitRate 86.92 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.40 # Row buffer hit rate for writes -system.physmem.avgGap 208026.54 # Average gap between requests -system.physmem.pageHitRate 80.62 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 31935315750 # Time in different power states -system.physmem.memoryStateTime::REF 1949480000 # Time in different power states +system.physmem.writeRowHitRate 71.43 # Row buffer hit rate for writes +system.physmem.avgGap 208946.74 # Average gap between requests +system.physmem.pageHitRate 80.63 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 32158270750 # Time in different power states +system.physmem.memoryStateTime::REF 1958320000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 24496780500 # Time in different power states +system.physmem.memoryStateTime::ACT 24529718750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 198434880 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 212398200 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 108273000 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 115891875 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 642478200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 656705400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 367733520 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 370876320 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3813182880 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3813182880 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 12240327915 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 12673025460 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 24291807750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 23912248500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 41662238145 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 41754328635 # Total energy per rank (pJ) -system.physmem.averagePower::0 713.619786 # Core power per rank (mW) -system.physmem.averagePower::1 715.197176 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 35730 # Transaction distribution -system.membus.trans_dist::ReadResp 35730 # Transaction distribution -system.membus.trans_dist::Writeback 114048 # Transaction distribution -system.membus.trans_dist::ReadExReq 130881 # Transaction distribution -system.membus.trans_dist::ReadExResp 130881 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447270 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 447270 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17962176 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17962176 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 280659 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 280659 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 280659 # Request fanout histogram -system.membus.reqLayer0.occupancy 1302108500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1600532000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.7 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 14593516 # Number of BP lookups -system.cpu.branchPred.condPredicted 9448617 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 379109 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10302575 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6369350 # Number of BTB hits +system.physmem.actEnergy::0 198298800 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 212481360 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 108198750 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 115937250 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 642673200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 656838000 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 367811280 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 370960560 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 3830473920 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 3830473920 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 12291718545 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 12736700730 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 24405568500 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 24015233250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 41844742995 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 41938625070 # Total energy per rank (pJ) +system.physmem.averagePower::0 713.510412 # Core power per rank (mW) +system.physmem.averagePower::1 715.111230 # Core power per rank (mW) +system.cpu.branchPred.lookups 14678284 # Number of BP lookups +system.cpu.branchPred.condPredicted 9497966 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 389718 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9980180 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6390464 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.822894 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1700742 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 73233 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 64.031551 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1709614 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 85893 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20554145 # DTB read hits -system.cpu.dtb.read_misses 96857 # DTB read misses -system.cpu.dtb.read_acv 9 # DTB read access violations -system.cpu.dtb.read_accesses 20651002 # DTB read accesses -system.cpu.dtb.write_hits 14666071 # DTB write hits -system.cpu.dtb.write_misses 9396 # DTB write misses +system.cpu.dtb.read_hits 20567325 # DTB read hits +system.cpu.dtb.read_misses 96876 # DTB read misses +system.cpu.dtb.read_acv 11 # DTB read access violations +system.cpu.dtb.read_accesses 20664201 # DTB read accesses +system.cpu.dtb.write_hits 14665780 # DTB write hits +system.cpu.dtb.write_misses 9406 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14675467 # DTB write accesses -system.cpu.dtb.data_hits 35220216 # DTB hits -system.cpu.dtb.data_misses 106253 # DTB misses -system.cpu.dtb.data_acv 9 # DTB access violations -system.cpu.dtb.data_accesses 35326469 # DTB accesses -system.cpu.itb.fetch_hits 25540027 # ITB hits -system.cpu.itb.fetch_misses 5176 # ITB misses +system.cpu.dtb.write_accesses 14675186 # DTB write accesses +system.cpu.dtb.data_hits 35233105 # DTB hits +system.cpu.dtb.data_misses 106282 # DTB misses +system.cpu.dtb.data_acv 11 # DTB access violations +system.cpu.dtb.data_accesses 35339387 # DTB accesses +system.cpu.itb.fetch_hits 25627874 # ITB hits +system.cpu.itb.fetch_misses 5262 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25545203 # ITB accesses +system.cpu.itb.fetch_accesses 25633136 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -336,70 +311,185 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 116769092 # number of cpu cycles simulated +system.cpu.numCycles 117296487 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88438073 # Number of instructions committed system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1185538 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1098513 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.320349 # CPI: cycles per instruction -system.cpu.ipc 0.757376 # IPC: instructions per cycle -system.cpu.tickCycles 90792552 # Number of cycles that the object actually ticked -system.cpu.idleCycles 25976540 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 153164 # number of replacements -system.cpu.icache.tags.tagsinuse 1933.730829 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25384814 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 155212 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 163.549300 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 41528149250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1933.730829 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.944205 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.944205 # Average percentage of cache occupancy +system.cpu.cpi 1.326312 # CPI: cycles per instruction +system.cpu.ipc 0.753970 # IPC: instructions per cycle +system.cpu.tickCycles 91572461 # Number of cycles that the object actually ticked +system.cpu.idleCycles 25724026 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 200783 # number of replacements +system.cpu.dcache.tags.tagsinuse 4071.549742 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34616444 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204879 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 168.960430 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 644809250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.549742 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.994031 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.994031 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 740 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3305 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 70176773 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70176773 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 20283132 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20283132 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 14333312 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 14333312 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.inst 34616444 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34616444 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 34616444 # number of overall hits +system.cpu.dcache.overall_hits::total 34616444 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 89438 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89438 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 280065 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 280065 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 369503 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 369503 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 369503 # number of overall misses +system.cpu.dcache.overall_misses::total 369503 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 4420798500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4420798500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20106086500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20106086500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 24526885000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24526885000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 24526885000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24526885000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 20372570 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20372570 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 34985947 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34985947 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 34985947 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34985947 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.004390 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004390 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.019165 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.019165 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.010561 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010561 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.010561 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010561 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 49428.637716 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49428.637716 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 71790.786068 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 71790.786068 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66378.040232 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66378.040232 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66378.040232 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66378.040232 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 168546 # number of writebacks +system.cpu.dcache.writebacks::total 168546 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 28119 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 28119 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 136505 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 136505 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 164624 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 164624 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 164624 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 164624 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 61319 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 61319 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 143560 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143560 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 204879 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 204879 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 204879 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204879 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 2428683000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2428683000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 9985116500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9985116500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12413799500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12413799500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12413799500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12413799500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.003010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009824 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009824 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.005856 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005856 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.005856 # 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number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 166637 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 166637 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 166637 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2156394000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2156394000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 8029638750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8029638750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10186032750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10186032750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10186032750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10186032750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.164641 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.164641 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.911682 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911682 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461944 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.461944 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461944 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.461944 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60310.278283 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60310.278283 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 61350.214315 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61350.214315 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61127.077120 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61127.077120 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61127.077120 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61127.077120 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 217169 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 217168 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168546 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 143561 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 143561 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 310425 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 578271 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 888696 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9933568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23897664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 33831232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 311701 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 578304 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 890005 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9974400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23899200 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 33873600 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 528614 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 529276 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 528614 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 529276 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 528614 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 432838000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 529276 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 433184000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 234362497 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 235328991 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 343210750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 343237000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 132688 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30473.454944 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 220028 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 164763 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.335421 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26247.246790 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4226.208154 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.801002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.128974 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.929976 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32075 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1029 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11968 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 18838 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 112 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978851 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4537236 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4537236 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 180791 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 180791 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 168531 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 168531 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 12680 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12680 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 193471 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 193471 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 193471 # number of overall hits -system.cpu.l2cache.overall_hits::total 193471 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 35731 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 35731 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 130881 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130881 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 166612 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 166612 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 166612 # number of overall misses -system.cpu.l2cache.overall_misses::total 166612 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 2608794250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2608794250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 9709899750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9709899750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 12318694000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 12318694000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 12318694000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 12318694000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 216522 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 216522 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 168531 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 168531 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 143561 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 143561 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 360083 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 360083 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 360083 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 360083 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.165022 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.165022 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.911675 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.911675 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.462704 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.462704 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.462704 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.462704 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73012.069352 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73012.069352 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 74188.764985 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74188.764985 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73936.415144 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73936.415144 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73936.415144 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73936.415144 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 114048 # number of writebacks -system.cpu.l2cache.writebacks::total 114048 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 35731 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 35731 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 130881 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130881 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 166612 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 166612 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 166612 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 166612 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2155637750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2155637750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 8025242250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8025242250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10180880000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 10180880000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10180880000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 10180880000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.165022 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.165022 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.911675 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911675 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.462704 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.462704 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.462704 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.462704 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60329.622737 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60329.622737 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 61317.091480 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61317.091480 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61105.322546 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61105.322546 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61105.322546 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61105.322546 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 200774 # number of replacements -system.cpu.dcache.tags.tagsinuse 4071.445438 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34597334 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204870 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 168.874574 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 644670250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.445438 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.994005 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.994005 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 755 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3288 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70138572 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70138572 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 20264067 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20264067 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 14333267 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14333267 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 34597334 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34597334 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 34597334 # number of overall hits -system.cpu.dcache.overall_hits::total 34597334 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 89407 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89407 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 280110 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 280110 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 369517 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 369517 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 369517 # number of overall misses -system.cpu.dcache.overall_misses::total 369517 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 4423552750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4423552750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20095524250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20095524250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 24519077000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24519077000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 24519077000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24519077000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 20353474 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20353474 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 34966851 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34966851 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 34966851 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34966851 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.004393 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004393 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.019168 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.019168 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.010568 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.010568 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.010568 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.010568 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 49476.581811 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 49476.581811 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 71741.545286 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 71741.545286 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66354.395062 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66354.395062 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66354.395062 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66354.395062 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168531 # number of writebacks -system.cpu.dcache.writebacks::total 168531 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 28097 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 28097 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 136550 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 136550 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 164647 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 164647 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 164647 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 164647 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 61310 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61310 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 143560 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143560 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 204870 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204870 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 204870 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204870 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 2430963250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2430963250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 9980296000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9980296000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12411259250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12411259250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12411259250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12411259250 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.003012 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003012 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009824 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009824 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.005859 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005859 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.005859 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005859 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 39650.354755 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39650.354755 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 69520.033435 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69520.033435 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 60581.145360 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 60581.145360 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 60581.145360 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 60581.145360 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 35754 # Transaction distribution +system.membus.trans_dist::ReadResp 35754 # Transaction distribution +system.membus.trans_dist::Writeback 114049 # Transaction distribution +system.membus.trans_dist::ReadExReq 130882 # Transaction distribution +system.membus.trans_dist::ReadExResp 130882 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447321 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 447321 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17963840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17963840 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 280685 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 280685 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 280685 # Request fanout histogram +system.membus.reqLayer0.occupancy 1304586000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 1602413250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index 92998cd4b..c949b9a6e 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,91 +1,91 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.056374 # Number of seconds simulated -sim_ticks 56374399500 # Number of ticks simulated -final_tick 56374399500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.057847 # Number of seconds simulated +sim_ticks 57847312000 # Number of ticks simulated +final_tick 57847312000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 200830 # Simulator instruction rate (inst/s) -host_op_rate 256832 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 159651052 # Simulator tick rate (ticks/s) -host_mem_usage 319716 # Number of bytes of host memory used -host_seconds 353.11 # Real time elapsed on the host +host_inst_rate 186854 # Simulator instruction rate (inst/s) +host_op_rate 238959 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 152421830 # Simulator tick rate (ticks/s) +host_mem_usage 261476 # Number of bytes of host memory used +host_seconds 379.52 # Real time elapsed on the host sim_insts 70915127 # Number of instructions simulated sim_ops 90690083 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 8247168 # Number of bytes read from this memory -system.physmem.bytes_read::total 8247168 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 323904 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 323904 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 8247680 # Number of bytes read from this memory +system.physmem.bytes_read::total 8247680 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 324352 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 324352 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 5372864 # Number of bytes written to this memory system.physmem.bytes_written::total 5372864 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 128862 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128862 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 128870 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128870 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 83951 # Number of write requests responded to by this memory system.physmem.num_writes::total 83951 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 146292787 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 146292787 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5745587 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5745587 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 95306807 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 95306807 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 95306807 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 146292787 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 241599593 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128862 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 142576720 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 142576720 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5607037 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5607037 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 92880098 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 92880098 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 92880098 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 142576720 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 235456818 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128870 # Number of read requests accepted system.physmem.writeReqs 83951 # Number of write requests accepted -system.physmem.readBursts 128862 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 128870 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 83951 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8246784 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue -system.physmem.bytesWritten 5371136 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8247168 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 8247360 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue +system.physmem.bytesWritten 5370944 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8247680 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 5372864 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 8164 # Per bank write bursts -system.physmem.perBankRdBursts::1 8373 # Per bank write bursts -system.physmem.perBankRdBursts::2 8238 # Per bank write bursts -system.physmem.perBankRdBursts::3 8169 # Per bank write bursts -system.physmem.perBankRdBursts::4 8316 # Per bank write bursts -system.physmem.perBankRdBursts::5 8449 # Per bank write bursts +system.physmem.perBankRdBursts::0 8158 # Per bank write bursts +system.physmem.perBankRdBursts::1 8375 # Per bank write bursts +system.physmem.perBankRdBursts::2 8229 # Per bank write bursts +system.physmem.perBankRdBursts::3 8171 # Per bank write bursts +system.physmem.perBankRdBursts::4 8319 # Per bank write bursts +system.physmem.perBankRdBursts::5 8450 # Per bank write bursts system.physmem.perBankRdBursts::6 8089 # Per bank write bursts -system.physmem.perBankRdBursts::7 7969 # Per bank write bursts +system.physmem.perBankRdBursts::7 7970 # Per bank write bursts system.physmem.perBankRdBursts::8 8071 # Per bank write bursts -system.physmem.perBankRdBursts::9 7635 # Per bank write bursts -system.physmem.perBankRdBursts::10 7816 # Per bank write bursts +system.physmem.perBankRdBursts::9 7641 # Per bank write bursts +system.physmem.perBankRdBursts::10 7819 # Per bank write bursts system.physmem.perBankRdBursts::11 7830 # Per bank write bursts system.physmem.perBankRdBursts::12 7881 # Per bank write bursts -system.physmem.perBankRdBursts::13 7876 # Per bank write bursts -system.physmem.perBankRdBursts::14 7976 # Per bank write bursts -system.physmem.perBankRdBursts::15 8004 # Per bank write bursts -system.physmem.perBankWrBursts::0 5186 # Per bank write bursts +system.physmem.perBankRdBursts::13 7879 # Per bank write bursts +system.physmem.perBankRdBursts::14 7977 # Per bank write bursts +system.physmem.perBankRdBursts::15 8006 # Per bank write bursts +system.physmem.perBankWrBursts::0 5181 # Per bank write bursts system.physmem.perBankWrBursts::1 5376 # Per bank write bursts system.physmem.perBankWrBursts::2 5285 # Per bank write bursts system.physmem.perBankWrBursts::3 5155 # Per bank write bursts -system.physmem.perBankWrBursts::4 5265 # Per bank write bursts +system.physmem.perBankWrBursts::4 5266 # Per bank write bursts system.physmem.perBankWrBursts::5 5517 # Per bank write bursts -system.physmem.perBankWrBursts::6 5196 # Per bank write bursts -system.physmem.perBankWrBursts::7 5049 # Per bank write bursts +system.physmem.perBankWrBursts::6 5198 # Per bank write bursts +system.physmem.perBankWrBursts::7 5047 # Per bank write bursts system.physmem.perBankWrBursts::8 5033 # Per bank write bursts -system.physmem.perBankWrBursts::9 5086 # Per bank write bursts -system.physmem.perBankWrBursts::10 5252 # Per bank write bursts +system.physmem.perBankWrBursts::9 5087 # Per bank write bursts +system.physmem.perBankWrBursts::10 5251 # Per bank write bursts system.physmem.perBankWrBursts::11 5143 # Per bank write bursts system.physmem.perBankWrBursts::12 5343 # Per bank write bursts system.physmem.perBankWrBursts::13 5363 # Per bank write bursts system.physmem.perBankWrBursts::14 5451 # Per bank write bursts -system.physmem.perBankWrBursts::15 5224 # Per bank write bursts +system.physmem.perBankWrBursts::15 5225 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 56374368000 # Total gap between requests +system.physmem.totGap 57847280000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128862 # Read request sizes (log2) +system.physmem.readPktSize::6 128870 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -93,8 +93,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 83951 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 126558 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 126560 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2283 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -140,27 +140,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 651 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 620 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5165 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 5166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5740 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -189,120 +189,97 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38259 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 355.901827 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 215.943020 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 337.187447 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12097 31.62% 31.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8058 21.06% 52.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4075 10.65% 63.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2806 7.33% 70.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2532 6.62% 77.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1601 4.18% 81.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1324 3.46% 84.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1160 3.03% 87.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4606 12.04% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38259 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5153 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.995537 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 361.849882 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5150 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 38379 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 354.780687 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 215.561409 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 335.824723 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12139 31.63% 31.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8088 21.07% 52.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4086 10.65% 63.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2872 7.48% 70.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2530 6.59% 77.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1664 4.34% 81.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1273 3.32% 85.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1227 3.20% 88.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4500 11.73% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38379 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5156 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.981187 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 361.178240 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5153 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5153 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5153 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.286435 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.268739 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.792681 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4505 87.42% 87.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 6 0.12% 87.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 503 9.76% 97.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 112 2.17% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 16 0.31% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 4 0.08% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 5 0.10% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 2 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5153 # Writes before turning the bus around for reads -system.physmem.totQLat 1533288750 # Total ticks spent queuing -system.physmem.totMemAccLat 3949338750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 644280000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11899.24 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5156 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5156 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.276377 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.259366 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.777117 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4528 87.82% 87.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 7 0.14% 87.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 480 9.31% 97.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 121 2.35% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 14 0.27% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 2 0.04% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 2 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5156 # Writes before turning the bus around for reads +system.physmem.totQLat 1539171500 # Total ticks spent queuing +system.physmem.totMemAccLat 3955390250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 644325000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11944.06 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30649.24 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 146.29 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 95.28 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 146.29 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 95.31 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30694.06 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 142.57 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 92.85 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 142.58 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 92.88 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.89 # Data bus utilization in percentage -system.physmem.busUtilRead 1.14 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.74 # Data bus utilization in percentage for writes +system.physmem.busUtil 1.84 # Data bus utilization in percentage +system.physmem.busUtilRead 1.11 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.73 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.42 # Average write queue length when enqueuing -system.physmem.readRowHits 112227 # Number of row buffer hits during reads -system.physmem.writeRowHits 62289 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.09 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.20 # Row buffer hit rate for writes -system.physmem.avgGap 264900.96 # Average gap between requests -system.physmem.pageHitRate 82.01 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 30998356250 # Time in different power states -system.physmem.memoryStateTime::REF 1882400000 # Time in different power states +system.physmem.avgWrQLen 23.48 # Average write queue length when enqueuing +system.physmem.readRowHits 112176 # Number of row buffer hits during reads +system.physmem.writeRowHits 62224 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.12 # Row buffer hit rate for writes +system.physmem.avgGap 271811.90 # Average gap between requests +system.physmem.pageHitRate 81.95 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 32236826000 # Time in different power states +system.physmem.memoryStateTime::REF 1931540000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 23491967500 # Time in different power states +system.physmem.memoryStateTime::ACT 23675959000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 150716160 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 138521880 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 82236000 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 75582375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 512857800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 492039600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 272347920 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 271479600 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3681974400 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3681974400 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 11715197175 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 11107328085 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 23547137250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 24080355750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 39962466705 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 39847281690 # Total energy per rank (pJ) -system.physmem.averagePower::0 708.897385 # Core power per rank (mW) -system.physmem.averagePower::1 706.854109 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 26583 # Transaction distribution -system.membus.trans_dist::ReadResp 26583 # Transaction distribution -system.membus.trans_dist::Writeback 83951 # Transaction distribution -system.membus.trans_dist::ReadExReq 102279 # Transaction distribution -system.membus.trans_dist::ReadExResp 102279 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341675 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 341675 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620032 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13620032 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 212813 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 212813 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 212813 # Request fanout histogram -system.membus.reqLayer0.occupancy 942245500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 1221409750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.2 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 14808790 # Number of BP lookups -system.cpu.branchPred.condPredicted 9910130 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 393084 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9534894 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6736290 # Number of BTB hits +system.physmem.actEnergy::0 151237800 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 138899880 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 82520625 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 75788625 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 512678400 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 492078600 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 272322000 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 271486080 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 3778092240 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 3778092240 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 11712850200 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 11277598770 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 24432156750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 24813956250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 40941858015 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 40847900445 # Total energy per rank (pJ) +system.physmem.averagePower::0 707.794027 # Core power per rank (mW) +system.physmem.averagePower::1 706.169709 # Core power per rank (mW) +system.cpu.branchPred.lookups 14825675 # Number of BP lookups +system.cpu.branchPred.condPredicted 9917897 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 395023 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9456669 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6745546 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.648819 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1716012 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 71.331100 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1719567 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -388,329 +365,89 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 112748799 # number of cpu cycles simulated +system.cpu.numCycles 115694624 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915127 # Number of instructions committed system.cpu.committedOps 90690083 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1227279 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1146301 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.589912 # CPI: cycles per instruction -system.cpu.ipc 0.628966 # IPC: instructions per cycle -system.cpu.tickCycles 93715149 # Number of cycles that the object actually ticked -system.cpu.idleCycles 19033650 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 42434 # number of replacements -system.cpu.icache.tags.tagsinuse 1857.503994 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 24948244 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 44476 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 560.937225 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1857.503994 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.906984 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.906984 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 846 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1075 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 50029918 # Number of tag accesses -system.cpu.icache.tags.data_accesses 50029918 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 24948244 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 24948244 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 24948244 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 24948244 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 24948244 # number of overall hits -system.cpu.icache.overall_hits::total 24948244 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 44477 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 44477 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 44477 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 44477 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 44477 # number of overall misses -system.cpu.icache.overall_misses::total 44477 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 894634739 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 894634739 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 894634739 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 894634739 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 894634739 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 894634739 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 24992721 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 24992721 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 24992721 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 24992721 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 24992721 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 24992721 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001780 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001780 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001780 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001780 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001780 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001780 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20114.547721 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20114.547721 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20114.547721 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20114.547721 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20114.547721 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20114.547721 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44477 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 44477 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 44477 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 44477 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 44477 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 44477 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 803759261 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 803759261 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 803759261 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 803759261 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 803759261 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 803759261 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001780 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001780 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001780 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18071.346111 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18071.346111 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18071.346111 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18071.346111 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18071.346111 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18071.346111 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 97959 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 97958 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 128423 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107038 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107038 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 88953 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449463 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 538416 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2846464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18492352 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 21338816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 333420 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 333420 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 333420 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 295133000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 67675739 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 268453439 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 95725 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29925.727358 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 99436 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 126843 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.783930 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26686.334760 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3239.392599 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.814402 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.098858 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.913261 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31118 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1141 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9850 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19418 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 583 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949646 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 2901241 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 2901241 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 71304 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 71304 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 128423 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 128423 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 4759 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4759 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 76063 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 76063 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 76063 # number of overall hits -system.cpu.l2cache.overall_hits::total 76063 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 26655 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 26655 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 102279 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 102279 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 128934 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 128934 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 128934 # number of overall misses -system.cpu.l2cache.overall_misses::total 128934 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1985312250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1985312250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7483113000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7483113000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 9468425250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 9468425250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 9468425250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 9468425250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 97959 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 97959 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 128423 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 128423 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 107038 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 107038 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 204997 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 204997 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 204997 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 204997 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.272104 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.272104 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.955539 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.955539 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.628956 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.628956 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.628956 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.628956 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74481.795160 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74481.795160 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 73163.728625 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73163.728625 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73436.217367 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73436.217367 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73436.217367 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73436.217367 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 83951 # number of writebacks -system.cpu.l2cache.writebacks::total 83951 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 71 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 71 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 71 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 71 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 26584 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 26584 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 102279 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102279 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 128863 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 128863 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 128863 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 128863 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1642872250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1642872250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6184053500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6184053500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7826925750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 7826925750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7826925750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 7826925750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.271379 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.271379 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.955539 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955539 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.628609 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.628609 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.628609 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.628609 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61799.287165 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61799.287165 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60462.592517 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60462.592517 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60738.348091 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60738.348091 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60738.348091 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60738.348091 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 156424 # number of replacements -system.cpu.dcache.tags.tagsinuse 4068.200974 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42664255 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 160520 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 265.787783 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 770315250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4068.200974 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.993213 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993213 # Average percentage of cache occupancy +system.cpu.cpi 1.631452 # CPI: cycles per instruction +system.cpu.ipc 0.612951 # IPC: instructions per cycle +system.cpu.tickCycles 96938261 # Number of cycles that the object actually ticked +system.cpu.idleCycles 18756363 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 156422 # number of replacements +system.cpu.dcache.tags.tagsinuse 4068.596798 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42665450 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 160518 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 265.798540 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 784159000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 4068.596798 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.993310 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993310 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 752 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 750 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 3296 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 86013136 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 86013136 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 22988554 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22988554 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 19643863 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19643863 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 86015580 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86015580 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 22989734 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22989734 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 19643878 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19643878 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.inst 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.inst 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 42632417 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42632417 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 42632417 # 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average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73981.389214 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66383.888710 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66383.888710 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66383.888710 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66383.888710 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -719,32 +456,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # 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number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001781 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001781 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001781 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001781 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001781 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001781 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18018.666741 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18018.666741 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18018.666741 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18018.666741 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18018.666741 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18018.666741 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.tags.replacements 95732 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29937.969910 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 99708 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 126850 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.786031 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 26706.762922 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3231.206988 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.815026 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.098609 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.913634 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 31118 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1136 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9726 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19542 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 583 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949646 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 2903460 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 2903460 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 71567 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 71567 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 128433 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 128433 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 4753 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4753 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 76320 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 76320 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 76320 # number of overall hits +system.cpu.l2cache.overall_hits::total 76320 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 26663 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 26663 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 102281 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 102281 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 128944 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 128944 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 128944 # number of overall misses +system.cpu.l2cache.overall_misses::total 128944 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1987300500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1987300500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7479393750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7479393750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9466694250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 9466694250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9466694250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 9466694250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 98230 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 98230 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 128433 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 128433 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 107034 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 107034 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 205264 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 205264 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 205264 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 205264 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.271434 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.271434 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.955594 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.955594 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.628186 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.628186 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.628186 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.628186 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74534.017177 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74534.017177 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 73125.934924 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73125.934924 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73417.097732 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73417.097732 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73417.097732 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73417.097732 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 83951 # number of writebacks +system.cpu.l2cache.writebacks::total 83951 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 73 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 73 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 26590 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 26590 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 102281 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102281 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 128871 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128871 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 128871 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128871 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1644904750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1644904750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6188348750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6188348750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7833253500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7833253500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7833253500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 7833253500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.270691 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.270691 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.955594 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955594 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.627831 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.627831 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.627831 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.627831 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61861.780745 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61861.780745 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60503.404836 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60503.404836 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60783.679028 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60783.679028 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60783.679028 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60783.679028 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 98230 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 98229 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 128433 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107034 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107034 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89491 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449469 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 538960 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2863680 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18492864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 21356544 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 333697 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 333697 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 333697 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 295281500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 68080238 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 268447937 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.membus.trans_dist::ReadReq 26589 # Transaction distribution +system.membus.trans_dist::ReadResp 26589 # Transaction distribution +system.membus.trans_dist::Writeback 83951 # Transaction distribution +system.membus.trans_dist::ReadExReq 102281 # Transaction distribution +system.membus.trans_dist::ReadExResp 102281 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341691 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 341691 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620544 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13620544 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 212821 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 212821 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 212821 # Request fanout histogram +system.membus.reqLayer0.occupancy 929388500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 1213397000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index 3052ca460..38d19f012 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -1,100 +1,100 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.182263 # Number of seconds simulated -sim_ticks 1182263011500 # Number of ticks simulated -final_tick 1182263011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.200149 # Number of seconds simulated +sim_ticks 1200148658000 # Number of ticks simulated +final_tick 1200148658000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 317111 # Simulator instruction rate (inst/s) -host_op_rate 317111 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 205274325 # Simulator tick rate (ticks/s) -host_mem_usage 237352 # Number of bytes of host memory used -host_seconds 5759.43 # Real time elapsed on the host +host_inst_rate 401299 # Simulator instruction rate (inst/s) +host_op_rate 401299 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 263701147 # Simulator tick rate (ticks/s) +host_mem_usage 236908 # Number of bytes of host memory used +host_seconds 4551.17 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 125507520 # Number of bytes read from this memory -system.physmem.bytes_read::total 125507520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61184 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61184 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65168128 # Number of bytes written to this memory -system.physmem.bytes_written::total 65168128 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1961055 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1961055 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1018252 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1018252 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 106158713 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 106158713 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 51752 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 51752 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 55121515 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 55121515 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 55121515 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 106158713 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 161280228 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1961055 # Number of read requests accepted -system.physmem.writeReqs 1018252 # Number of write requests accepted -system.physmem.readBursts 1961055 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1018252 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125426368 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 81152 # Total number of bytes read from write queue -system.physmem.bytesWritten 65166528 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 125507520 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65168128 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1268 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 125506304 # Number of bytes read from this memory +system.physmem.bytes_read::total 125506304 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61312 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65167488 # Number of bytes written to this memory +system.physmem.bytes_written::total 65167488 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1961036 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1961036 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1018242 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1018242 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 104575632 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 104575632 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 51087 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 51087 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 54299513 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 54299513 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 54299513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 104575632 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 158875145 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1961036 # Number of read requests accepted +system.physmem.writeReqs 1018242 # Number of write requests accepted +system.physmem.readBursts 1961036 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1018242 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125423936 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 82368 # Total number of bytes read from write queue +system.physmem.bytesWritten 65165888 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125506304 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65167488 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1287 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 118756 # Per bank write bursts -system.physmem.perBankRdBursts::1 114094 # Per bank write bursts -system.physmem.perBankRdBursts::2 116231 # Per bank write bursts -system.physmem.perBankRdBursts::3 117777 # Per bank write bursts -system.physmem.perBankRdBursts::4 117824 # Per bank write bursts -system.physmem.perBankRdBursts::5 117524 # Per bank write bursts -system.physmem.perBankRdBursts::6 119883 # Per bank write bursts +system.physmem.perBankRdBursts::0 118759 # Per bank write bursts +system.physmem.perBankRdBursts::1 114099 # Per bank write bursts +system.physmem.perBankRdBursts::2 116224 # Per bank write bursts +system.physmem.perBankRdBursts::3 117761 # Per bank write bursts +system.physmem.perBankRdBursts::4 117826 # Per bank write bursts +system.physmem.perBankRdBursts::5 117519 # Per bank write bursts +system.physmem.perBankRdBursts::6 119878 # Per bank write bursts system.physmem.perBankRdBursts::7 124524 # Per bank write bursts -system.physmem.perBankRdBursts::8 126980 # Per bank write bursts -system.physmem.perBankRdBursts::9 130091 # Per bank write bursts -system.physmem.perBankRdBursts::10 128645 # Per bank write bursts -system.physmem.perBankRdBursts::11 130349 # Per bank write bursts -system.physmem.perBankRdBursts::12 126066 # Per bank write bursts -system.physmem.perBankRdBursts::13 125260 # Per bank write bursts -system.physmem.perBankRdBursts::14 122596 # Per bank write bursts -system.physmem.perBankRdBursts::15 123187 # Per bank write bursts -system.physmem.perBankWrBursts::0 61220 # Per bank write bursts +system.physmem.perBankRdBursts::8 126972 # Per bank write bursts +system.physmem.perBankRdBursts::9 130092 # Per bank write bursts +system.physmem.perBankRdBursts::10 128660 # Per bank write bursts +system.physmem.perBankRdBursts::11 130342 # Per bank write bursts +system.physmem.perBankRdBursts::12 126055 # Per bank write bursts +system.physmem.perBankRdBursts::13 125250 # Per bank write bursts +system.physmem.perBankRdBursts::14 122599 # Per bank write bursts +system.physmem.perBankRdBursts::15 123189 # Per bank write bursts +system.physmem.perBankWrBursts::0 61222 # Per bank write bursts system.physmem.perBankWrBursts::1 61486 # Per bank write bursts -system.physmem.perBankWrBursts::2 60567 # Per bank write bursts -system.physmem.perBankWrBursts::3 61241 # Per bank write bursts -system.physmem.perBankWrBursts::4 61658 # Per bank write bursts -system.physmem.perBankWrBursts::5 63102 # Per bank write bursts -system.physmem.perBankWrBursts::6 64150 # Per bank write bursts -system.physmem.perBankWrBursts::7 65615 # Per bank write bursts -system.physmem.perBankWrBursts::8 65332 # Per bank write bursts +system.physmem.perBankWrBursts::2 60565 # Per bank write bursts +system.physmem.perBankWrBursts::3 61239 # Per bank write bursts +system.physmem.perBankWrBursts::4 61662 # Per bank write bursts +system.physmem.perBankWrBursts::5 63103 # Per bank write bursts +system.physmem.perBankWrBursts::6 64148 # Per bank write bursts +system.physmem.perBankWrBursts::7 65614 # Per bank write bursts +system.physmem.perBankWrBursts::8 65330 # Per bank write bursts system.physmem.perBankWrBursts::9 65779 # Per bank write bursts -system.physmem.perBankWrBursts::10 65299 # Per bank write bursts -system.physmem.perBankWrBursts::11 65643 # Per bank write bursts -system.physmem.perBankWrBursts::12 64166 # Per bank write bursts -system.physmem.perBankWrBursts::13 64211 # Per bank write bursts -system.physmem.perBankWrBursts::14 64571 # Per bank write bursts -system.physmem.perBankWrBursts::15 64187 # Per bank write bursts +system.physmem.perBankWrBursts::10 65300 # Per bank write bursts +system.physmem.perBankWrBursts::11 65644 # Per bank write bursts +system.physmem.perBankWrBursts::12 64162 # Per bank write bursts +system.physmem.perBankWrBursts::13 64212 # Per bank write bursts +system.physmem.perBankWrBursts::14 64570 # Per bank write bursts +system.physmem.perBankWrBursts::15 64181 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1182262901500 # Total gap between requests +system.physmem.totGap 1200148547500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1961055 # Read request sizes (log2) +system.physmem.readPktSize::6 1961036 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1018252 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1833329 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 126440 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1018242 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1833978 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 125753 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -140,30 +140,30 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 29905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 31308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 59278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 29968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 31481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 59260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 59828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60000 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 60083 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 60071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 59993 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 60069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 60024 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 60155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 60608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 60785 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 60198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 61396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 59839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 59485 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 60033 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 59975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 60058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 60092 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 60131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 60560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 60789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 60110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 61326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 59818 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 59467 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see @@ -189,149 +189,128 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1836557 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.775367 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.104101 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 130.072591 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1457072 79.34% 79.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 262826 14.31% 93.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 49283 2.68% 96.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20722 1.13% 97.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12908 0.70% 98.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7083 0.39% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5369 0.29% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4081 0.22% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 17213 0.94% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1836557 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59478 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.947897 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 162.231607 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 59437 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 16 0.03% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 8 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1837714 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.708116 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.073776 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 129.879385 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1458610 79.37% 79.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 262385 14.28% 93.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 49383 2.69% 96.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20628 1.12% 97.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12966 0.71% 98.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7221 0.39% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5354 0.29% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4357 0.24% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16810 0.91% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1837714 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59460 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.957232 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 160.327917 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 59419 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 13 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 12 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59478 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59478 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.119389 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.083537 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.112675 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 28008 47.09% 47.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1262 2.12% 49.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 25918 43.58% 92.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3789 6.37% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 422 0.71% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 60 0.10% 99.97% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 59460 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59460 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.124403 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.088362 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.116973 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 27861 46.86% 46.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1344 2.26% 49.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 25901 43.56% 92.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3838 6.45% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 438 0.74% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 56 0.09% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::22 14 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 3 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 3 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 2 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59478 # Writes before turning the bus around for reads -system.physmem.totQLat 36992521000 # Total ticks spent queuing -system.physmem.totMemAccLat 73738527250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9798935000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18875.79 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::36 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59460 # Writes before turning the bus around for reads +system.physmem.totQLat 37078229500 # Total ticks spent queuing +system.physmem.totMemAccLat 73823523250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9798745000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18919.89 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37625.79 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 106.09 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 55.12 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 106.16 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 55.12 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37669.89 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 104.51 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 54.30 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 104.58 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 54.30 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.26 # Data bus utilization in percentage -system.physmem.busUtilRead 0.83 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.43 # Data bus utilization in percentage for writes +system.physmem.busUtil 1.24 # Data bus utilization in percentage +system.physmem.busUtilRead 0.82 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.42 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing system.physmem.avgWrQLen 24.57 # Average write queue length when enqueuing -system.physmem.readRowHits 727653 # Number of row buffer hits during reads -system.physmem.writeRowHits 413795 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.13 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.64 # Row buffer hit rate for writes -system.physmem.avgGap 396824.80 # Average gap between requests -system.physmem.pageHitRate 38.33 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 385836572500 # Time in different power states -system.physmem.memoryStateTime::REF 39478140000 # Time in different power states +system.physmem.readRowHits 726316 # Number of row buffer hits during reads +system.physmem.writeRowHits 413927 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.06 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 40.65 # Row buffer hit rate for writes +system.physmem.avgGap 402832.01 # Average gap between requests +system.physmem.pageHitRate 38.29 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 393584177750 # Time in different power states +system.physmem.memoryStateTime::REF 40075360000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 756941975000 # Time in different power states +system.physmem.memoryStateTime::ACT 766482185250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 6738530400 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 7145810280 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 3676777500 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 3899003625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 7383534600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 7902102000 # Energy for read commands per rank (pJ) +system.physmem.actEnergy::0 6742219680 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 7150867920 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 3678790500 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 3901763250 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 7383355200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 7901907000 # Energy for read commands per rank (pJ) system.physmem.writeEnergy::0 3233772720 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 3364338240 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 77219241840 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 77219241840 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 405130664925 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 418464065025 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 353976228000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 342280263000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 857358749985 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 860274824010 # Total energy per rank (pJ) -system.physmem.averagePower::0 725.188336 # Core power per rank (mW) -system.physmem.averagePower::1 727.654868 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 1181608 # Transaction distribution -system.membus.trans_dist::ReadResp 1181608 # Transaction distribution -system.membus.trans_dist::Writeback 1018252 # Transaction distribution -system.membus.trans_dist::ReadExReq 779447 # Transaction distribution -system.membus.trans_dist::ReadExResp 779447 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940362 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4940362 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190675648 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190675648 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2979307 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2979307 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2979307 # Request fanout histogram -system.membus.reqLayer0.occupancy 11933178500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 18493465250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.6 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 244422779 # Number of BP lookups -system.cpu.branchPred.condPredicted 184893031 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15656805 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 166159806 # Number of BTB lookups -system.cpu.branchPred.BTBHits 163963467 # Number of BTB hits +system.physmem.writeEnergy::1 3364273440 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 78387404160 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 78387404160 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 410122352430 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 423496116225 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 360328576500 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 348597204750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 869876471190 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 872799536745 # Total energy per rank (pJ) +system.physmem.averagePower::0 724.811465 # Core power per rank (mW) +system.physmem.averagePower::1 727.247065 # Core power per rank (mW) +system.cpu.branchPred.lookups 246247636 # Number of BP lookups +system.cpu.branchPred.condPredicted 186450048 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15699340 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 168260719 # Number of BTB lookups +system.cpu.branchPred.BTBHits 165258168 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.678177 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18313255 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 100190 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.215537 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18428845 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104881 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 452570621 # DTB read hits -system.cpu.dtb.read_misses 4982980 # DTB read misses +system.cpu.dtb.read_hits 452532318 # DTB read hits +system.cpu.dtb.read_misses 4979776 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 457553601 # DTB read accesses -system.cpu.dtb.write_hits 161352620 # DTB write hits -system.cpu.dtb.write_misses 1708824 # DTB write misses +system.cpu.dtb.read_accesses 457512094 # DTB read accesses +system.cpu.dtb.write_hits 161379130 # DTB write hits +system.cpu.dtb.write_misses 1710165 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 163061444 # DTB write accesses -system.cpu.dtb.data_hits 613923241 # DTB hits -system.cpu.dtb.data_misses 6691804 # DTB misses +system.cpu.dtb.write_accesses 163089295 # DTB write accesses +system.cpu.dtb.data_hits 613911448 # DTB hits +system.cpu.dtb.data_misses 6689941 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 620615045 # DTB accesses -system.cpu.itb.fetch_hits 591467838 # ITB hits +system.cpu.dtb.data_accesses 620601389 # DTB accesses +system.cpu.itb.fetch_hits 598579568 # ITB hits system.cpu.itb.fetch_misses 19 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 591467857 # ITB accesses +system.cpu.itb.fetch_accesses 598579587 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -345,68 +324,184 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 2364526023 # number of cpu cycles simulated +system.cpu.numCycles 2400297316 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1826378509 # Number of instructions committed system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed -system.cpu.discardedOps 49659953 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 52410829 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.294653 # CPI: cycles per instruction -system.cpu.ipc 0.772408 # IPC: instructions per cycle -system.cpu.tickCycles 2043503290 # Number of cycles that the object actually ticked -system.cpu.idleCycles 321022733 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.314239 # CPI: cycles per instruction +system.cpu.ipc 0.760897 # IPC: instructions per cycle +system.cpu.tickCycles 2077436531 # Number of cycles that the object actually ticked +system.cpu.idleCycles 322860785 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 9121980 # number of replacements +system.cpu.dcache.tags.tagsinuse 4080.680046 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 601827690 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9126076 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.945943 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 16791074000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 4080.680046 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.996260 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.996260 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1617 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2306 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 65 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1231838176 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1231838176 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 443337984 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 443337984 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 158489706 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 158489706 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.inst 601827690 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 601827690 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 601827690 # number of overall hits +system.cpu.dcache.overall_hits::total 601827690 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 7289564 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7289564 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 2238796 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2238796 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 9528360 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9528360 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 9528360 # number of overall misses +system.cpu.dcache.overall_misses::total 9528360 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 178244544500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 178244544500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101115441000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 101115441000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 279359985500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 279359985500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 279359985500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 279359985500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 450627548 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 450627548 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 611356050 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 611356050 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 611356050 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 611356050 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.016176 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.016176 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.013929 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013929 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.015586 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015586 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.015586 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015586 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24452.017226 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24452.017226 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45165.098115 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45165.098115 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29318.789960 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29318.789960 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29318.789960 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29318.789960 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 3700593 # number of writebacks +system.cpu.dcache.writebacks::total 3700593 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 50804 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 50804 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 351480 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 351480 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 402284 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 402284 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 402284 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 402284 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7238760 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7238760 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1887316 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1887316 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 9126076 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9126076 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 9126076 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9126076 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 162288114750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 162288114750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 76072677250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 76072677250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 238360792000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 238360792000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 238360792000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 238360792000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.016064 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016064 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.011742 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011742 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014928 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014928 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014928 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014928 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22419.325237 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22419.325237 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40307.334463 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40307.334463 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26118.650776 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26118.650776 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26118.650776 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26118.650776 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 749.760915 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 591466882 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 956 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 618689.207113 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 751.335570 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 598578610 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 958 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 624821.096033 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 749.760915 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.366094 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.366094 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 953 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 751.335570 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.366863 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.366863 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 955 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 872 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.465332 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1182936632 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1182936632 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 591466882 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 591466882 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 591466882 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 591466882 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 591466882 # number of overall hits -system.cpu.icache.overall_hits::total 591466882 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 956 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 956 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 956 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 956 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 956 # number of overall misses -system.cpu.icache.overall_misses::total 956 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 70103250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 70103250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 70103250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 70103250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 70103250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 70103250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 591467838 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 591467838 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 591467838 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 591467838 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 591467838 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 591467838 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::4 874 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.466309 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1197160094 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1197160094 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 598578610 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 598578610 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 598578610 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 598578610 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 598578610 # number of overall hits +system.cpu.icache.overall_hits::total 598578610 # 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average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80901.396380 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80353.731395 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80353.731395 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80353.731395 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80353.731395 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -549,156 +615,93 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67740.291450 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67740.291450 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 1018242 # number of writebacks +system.cpu.l2cache.writebacks::total 1018242 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1181592 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1181592 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 779444 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 779444 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1961036 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1961036 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1961036 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163210 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.412991 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.412991 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.214860 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214860 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.214860 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214860 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67431.741244 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67431.741244 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68314.655062 # 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Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 16715078000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4080.554959 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.996229 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.996229 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1616 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2312 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 64 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1227940890 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1227940890 # 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average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29317.336311 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29317.336311 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3700618 # number of writebacks -system.cpu.dcache.writebacks::total 3700618 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 50811 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 50811 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 350963 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 350963 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 401774 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 401774 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 401774 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 401774 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7238754 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7238754 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1887318 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1887318 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 9126072 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9126072 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 9126072 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9126072 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 162228644750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 162228644750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 76111394500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 76111394500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 238340039250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 238340039250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 238340039250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 238340039250 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.016133 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016133 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.011742 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011742 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014975 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014975 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014975 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014975 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22411.128317 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22411.128317 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40327.806178 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40327.806178 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26116.388217 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26116.388217 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26116.388217 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26116.388217 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 7239718 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7239718 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3700593 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1887316 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1887316 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1916 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21952745 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 21954661 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820906816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 820968128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 12827627 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12827627 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 12827627 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10114406500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1631750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 14010883500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) +system.membus.trans_dist::ReadReq 1181592 # Transaction distribution +system.membus.trans_dist::ReadResp 1181592 # Transaction distribution +system.membus.trans_dist::Writeback 1018242 # Transaction distribution +system.membus.trans_dist::ReadExReq 779444 # Transaction distribution +system.membus.trans_dist::ReadExResp 779444 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940314 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4940314 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190673792 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190673792 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 2979278 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2979278 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 2979278 # Request fanout histogram +system.membus.reqLayer0.occupancy 11833253000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 18446066000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index 9172e88dd..b905eb22a 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,100 +1,100 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.096187 # Number of seconds simulated -sim_ticks 1096186990500 # Number of ticks simulated -final_tick 1096186990500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.108945 # Number of seconds simulated +sim_ticks 1108944740000 # Number of ticks simulated +final_tick 1108944740000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 245276 # Simulator instruction rate (inst/s) -host_op_rate 264248 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 174074375 # Simulator tick rate (ticks/s) -host_mem_usage 310916 # Number of bytes of host memory used -host_seconds 6297.23 # Real time elapsed on the host +host_inst_rate 239014 # Simulator instruction rate (inst/s) +host_op_rate 257501 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 171603826 # Simulator tick rate (ticks/s) +host_mem_usage 253696 # Number of bytes of host memory used +host_seconds 6462.24 # Real time elapsed on the host sim_insts 1544563087 # Number of instructions simulated sim_ops 1664032480 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 131551936 # Number of bytes read from this memory -system.physmem.bytes_read::total 131551936 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 50432 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 50432 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 66968384 # Number of bytes written to this memory -system.physmem.bytes_written::total 66968384 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2055499 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2055499 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1046381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1046381 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 120008664 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 120008664 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 46007 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 46007 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 61092117 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 61092117 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 61092117 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 120008664 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 181100781 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2055499 # Number of read requests accepted -system.physmem.writeReqs 1046381 # Number of write requests accepted -system.physmem.readBursts 2055499 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1046381 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 131465088 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 86848 # Total number of bytes read from write queue -system.physmem.bytesWritten 66966784 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131551936 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 66968384 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1357 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 131625408 # Number of bytes read from this memory +system.physmem.bytes_read::total 131625408 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 50368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 50368 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 66989632 # Number of bytes written to this memory +system.physmem.bytes_written::total 66989632 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2056647 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2056647 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1046713 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1046713 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 118694289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 118694289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 45420 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 45420 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 60408449 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 60408449 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 60408449 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 118694289 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 179102739 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2056647 # Number of read requests accepted +system.physmem.writeReqs 1046713 # Number of write requests accepted +system.physmem.readBursts 2056647 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1046713 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 131542016 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 83392 # Total number of bytes read from write queue +system.physmem.bytesWritten 66988032 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131625408 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 66989632 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1303 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 127914 # Per bank write bursts -system.physmem.perBankRdBursts::1 125107 # Per bank write bursts -system.physmem.perBankRdBursts::2 122280 # Per bank write bursts -system.physmem.perBankRdBursts::3 124254 # Per bank write bursts -system.physmem.perBankRdBursts::4 123262 # Per bank write bursts +system.physmem.perBankRdBursts::0 128036 # Per bank write bursts +system.physmem.perBankRdBursts::1 125234 # Per bank write bursts +system.physmem.perBankRdBursts::2 122300 # Per bank write bursts +system.physmem.perBankRdBursts::3 124230 # Per bank write bursts +system.physmem.perBankRdBursts::4 123415 # Per bank write bursts system.physmem.perBankRdBursts::5 123345 # Per bank write bursts -system.physmem.perBankRdBursts::6 123865 # Per bank write bursts -system.physmem.perBankRdBursts::7 124190 # Per bank write bursts -system.physmem.perBankRdBursts::8 131999 # Per bank write bursts -system.physmem.perBankRdBursts::9 134064 # Per bank write bursts -system.physmem.perBankRdBursts::10 132428 # Per bank write bursts -system.physmem.perBankRdBursts::11 133673 # Per bank write bursts -system.physmem.perBankRdBursts::12 133725 # Per bank write bursts -system.physmem.perBankRdBursts::13 133862 # Per bank write bursts -system.physmem.perBankRdBursts::14 129895 # Per bank write bursts -system.physmem.perBankRdBursts::15 130279 # Per bank write bursts -system.physmem.perBankWrBursts::0 65789 # Per bank write bursts -system.physmem.perBankWrBursts::1 64087 # Per bank write bursts -system.physmem.perBankWrBursts::2 62403 # Per bank write bursts -system.physmem.perBankWrBursts::3 62885 # Per bank write bursts -system.physmem.perBankWrBursts::4 62820 # Per bank write bursts -system.physmem.perBankWrBursts::5 62979 # Per bank write bursts -system.physmem.perBankWrBursts::6 64285 # Per bank write bursts -system.physmem.perBankWrBursts::7 65232 # Per bank write bursts -system.physmem.perBankWrBursts::8 67082 # Per bank write bursts -system.physmem.perBankWrBursts::9 67588 # Per bank write bursts -system.physmem.perBankWrBursts::10 67303 # Per bank write bursts -system.physmem.perBankWrBursts::11 67613 # Per bank write bursts -system.physmem.perBankWrBursts::12 67020 # Per bank write bursts -system.physmem.perBankWrBursts::13 67468 # Per bank write bursts -system.physmem.perBankWrBursts::14 66169 # Per bank write bursts -system.physmem.perBankWrBursts::15 65633 # Per bank write bursts +system.physmem.perBankRdBursts::6 123964 # Per bank write bursts +system.physmem.perBankRdBursts::7 124409 # Per bank write bursts +system.physmem.perBankRdBursts::8 131872 # Per bank write bursts +system.physmem.perBankRdBursts::9 134140 # Per bank write bursts +system.physmem.perBankRdBursts::10 132473 # Per bank write bursts +system.physmem.perBankRdBursts::11 133756 # Per bank write bursts +system.physmem.perBankRdBursts::12 133901 # Per bank write bursts +system.physmem.perBankRdBursts::13 134102 # Per bank write bursts +system.physmem.perBankRdBursts::14 129958 # Per bank write bursts +system.physmem.perBankRdBursts::15 130209 # Per bank write bursts +system.physmem.perBankWrBursts::0 65849 # Per bank write bursts +system.physmem.perBankWrBursts::1 64131 # Per bank write bursts +system.physmem.perBankWrBursts::2 62381 # Per bank write bursts +system.physmem.perBankWrBursts::3 62840 # Per bank write bursts +system.physmem.perBankWrBursts::4 62871 # Per bank write bursts +system.physmem.perBankWrBursts::5 62990 # Per bank write bursts +system.physmem.perBankWrBursts::6 64312 # Per bank write bursts +system.physmem.perBankWrBursts::7 65310 # Per bank write bursts +system.physmem.perBankWrBursts::8 67027 # Per bank write bursts +system.physmem.perBankWrBursts::9 67624 # Per bank write bursts +system.physmem.perBankWrBursts::10 67292 # Per bank write bursts +system.physmem.perBankWrBursts::11 67645 # Per bank write bursts +system.physmem.perBankWrBursts::12 67063 # Per bank write bursts +system.physmem.perBankWrBursts::13 67560 # Per bank write bursts +system.physmem.perBankWrBursts::14 66200 # Per bank write bursts +system.physmem.perBankWrBursts::15 65593 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1096186902500 # Total gap between requests +system.physmem.totGap 1108944651500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2055499 # Read request sizes (log2) +system.physmem.readPktSize::6 2056647 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1046381 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1922421 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 131703 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1046713 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1923205 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 132121 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -140,30 +140,30 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 31796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 33166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 57030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 60853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61606 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61519 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 61936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 62305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 61675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62790 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 61028 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 31987 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 33324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 57104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 60908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61572 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61602 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62038 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 62277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 61631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 61027 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see @@ -189,126 +189,104 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1916158 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.556187 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.764224 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 125.552714 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1491113 77.82% 77.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 305811 15.96% 93.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52727 2.75% 96.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21051 1.10% 97.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13077 0.68% 98.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6875 0.36% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5570 0.29% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4107 0.21% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 15827 0.83% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1916158 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 61021 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.615247 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 160.737468 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 60978 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 19 0.03% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 9 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1918209 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.496643 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.775288 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 125.095886 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1492147 77.79% 77.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 306422 15.97% 93.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52965 2.76% 96.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21185 1.10% 97.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13242 0.69% 98.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7471 0.39% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5204 0.27% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3914 0.20% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 15659 0.82% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1918209 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 61025 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.632724 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 160.189303 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 60982 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 18 0.03% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 61021 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 61021 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.147474 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.112394 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.099372 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 27727 45.44% 45.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1223 2.00% 47.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 27936 45.78% 93.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3708 6.08% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 355 0.58% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 59 0.10% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 10 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 61021 # Writes before turning the bus around for reads -system.physmem.totQLat 38533876500 # Total ticks spent queuing -system.physmem.totMemAccLat 77049039000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 10270710000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18759.11 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 61025 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 61025 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.151790 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.116821 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.097688 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 27581 45.20% 45.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1180 1.93% 47.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 28172 46.16% 93.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3706 6.07% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 317 0.52% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 54 0.09% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 9 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 61025 # Writes before turning the bus around for reads +system.physmem.totQLat 38537340500 # Total ticks spent queuing +system.physmem.totMemAccLat 77075040500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10276720000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18749.83 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37509.11 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 119.93 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 61.09 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 120.01 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 61.09 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37499.83 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 118.62 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 60.41 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 118.69 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 60.41 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.41 # Data bus utilization in percentage -system.physmem.busUtilRead 0.94 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.48 # Data bus utilization in percentage for writes +system.physmem.busUtil 1.40 # Data bus utilization in percentage +system.physmem.busUtilRead 0.93 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.88 # Average write queue length when enqueuing -system.physmem.readRowHits 777772 # Number of row buffer hits during reads -system.physmem.writeRowHits 406558 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.86 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 38.85 # Row buffer hit rate for writes -system.physmem.avgGap 353394.36 # Average gap between requests -system.physmem.pageHitRate 38.20 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 306608104500 # Time in different power states -system.physmem.memoryStateTime::REF 36603840000 # Time in different power states +system.physmem.avgWrQLen 25.09 # Average write queue length when enqueuing +system.physmem.readRowHits 777039 # Number of row buffer hits during reads +system.physmem.writeRowHits 406774 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.81 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 38.86 # Row buffer hit rate for writes +system.physmem.avgGap 357336.77 # Average gap between requests +system.physmem.pageHitRate 38.16 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 313164826000 # Time in different power states +system.physmem.memoryStateTime::REF 37029980000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 752971887000 # Time in different power states +system.physmem.memoryStateTime::ACT 758746776000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 7068978000 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 7417161360 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 3857081250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 4047062250 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 7754580600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 8267360400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 3307910400 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 3472476480 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 71597111040 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 71597111040 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 413628192720 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 422690389875 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 294876051750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 286926756000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 802089905760 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 804418317405 # Total energy per rank (pJ) -system.physmem.averagePower::0 731.713906 # Core power per rank (mW) -system.physmem.averagePower::1 733.838021 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 1255486 # Transaction distribution -system.membus.trans_dist::ReadResp 1255486 # Transaction distribution -system.membus.trans_dist::Writeback 1046381 # Transaction distribution -system.membus.trans_dist::ReadExReq 800013 # Transaction distribution -system.membus.trans_dist::ReadExResp 800013 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5157379 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5157379 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198520320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 198520320 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3101880 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3101880 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3101880 # Request fanout histogram -system.membus.reqLayer0.occupancy 12229457500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 19361348500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.8 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 239650352 # Number of BP lookups -system.cpu.branchPred.condPredicted 186306880 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14598405 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 131764254 # Number of BTB lookups -system.cpu.branchPred.BTBHits 121991524 # Number of BTB hits +system.physmem.actEnergy::0 7075638360 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 7426006560 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 3860715375 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 4051888500 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 7760165400 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 8271151200 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 3309232320 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 3473305920 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 72430640880 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 72430640880 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 416866648005 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 425333204280 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 299692308000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 292265504250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 810995348340 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 813251701590 # Total energy per rank (pJ) +system.physmem.averagePower::0 731.323936 # Core power per rank (mW) +system.physmem.averagePower::1 733.358627 # Core power per rank (mW) +system.cpu.branchPred.lookups 240152510 # Number of BP lookups +system.cpu.branchPred.condPredicted 186756179 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14598640 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 131763268 # Number of BTB lookups +system.cpu.branchPred.BTBHits 122287171 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.583171 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15654227 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 92.808241 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15660181 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -394,69 +372,193 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 2192373981 # number of cpu cycles simulated +system.cpu.numCycles 2217889480 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563087 # Number of instructions committed system.cpu.committedOps 1664032480 # Number of ops (including micro ops) committed -system.cpu.discardedOps 42081657 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 40077128 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.419414 # CPI: cycles per instruction -system.cpu.ipc 0.704516 # IPC: instructions per cycle -system.cpu.tickCycles 1808241834 # Number of cycles that the object actually ticked -system.cpu.idleCycles 384132147 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.435933 # CPI: cycles per instruction +system.cpu.ipc 0.696411 # IPC: instructions per cycle +system.cpu.tickCycles 1838736315 # Number of cycles that the object actually ticked +system.cpu.idleCycles 379153165 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 9224311 # number of replacements +system.cpu.dcache.tags.tagsinuse 4085.608602 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624084220 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9228407 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.626430 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 9776044000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 4085.608602 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.997463 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997463 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 259 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1292 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2484 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1276551305 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1276551305 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 453737568 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 453737568 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 170346530 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170346530 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 61 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.inst 61 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.inst 624084098 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624084098 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 624084098 # number of overall hits +system.cpu.dcache.overall_hits::total 624084098 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 7337712 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7337712 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 2239517 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2239517 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 9577229 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9577229 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 9577229 # number of overall misses +system.cpu.dcache.overall_misses::total 9577229 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 183598363496 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 183598363496 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101566510500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 101566510500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 285164873996 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 285164873996 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 285164873996 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 285164873996 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 461075280 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 461075280 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 61 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 633661327 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 633661327 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 633661327 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 633661327 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.015914 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.015914 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012976 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.012976 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.015114 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015114 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.015114 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015114 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25021.200545 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25021.200545 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45351.971206 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45351.971206 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29775.300768 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29775.300768 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29775.300768 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29775.300768 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 3700618 # number of writebacks +system.cpu.dcache.writebacks::total 3700618 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 213 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 213 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 348609 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 348609 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 348822 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 348822 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 348822 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 348822 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7337499 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7337499 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1890908 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1890908 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 9228407 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9228407 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 9228407 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9228407 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168505826254 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 168505826254 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77457723500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 77457723500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245963549754 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 245963549754 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245963549754 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 245963549754 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.015914 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015914 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.010956 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 139048350000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 139048350000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139048350000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 139048350000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171200 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171200 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.423249 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423249 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.222841 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.222841 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.222841 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.222841 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67276.582734 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67276.582734 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68131.446452 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68131.446452 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67609.244562 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67609.244562 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67609.244562 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67609.244562 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 7338319 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7338319 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3700618 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1890908 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1890908 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22154304 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22155944 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22157432 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22159072 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827358208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 827410688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827457600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 827510080 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 12928292 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 12929845 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -511,262 +734,41 @@ system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Re system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 12928292 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 12929845 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 12928292 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10164786000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 12929845 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10165540500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1391749 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1391499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14185031745 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14187091746 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 2022796 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31252.383158 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8984119 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2052571 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.377008 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 58953869250 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14967.342328 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 16285.040830 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.456767 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.496980 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.953747 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29775 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1248 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12849 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15556 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908661 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 107369776 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 107369776 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 6081291 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6081291 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3700640 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3700640 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 1090856 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1090856 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 7172147 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7172147 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 7172147 # number of overall hits -system.cpu.l2cache.overall_hits::total 7172147 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1255492 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1255492 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 800013 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 800013 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2055505 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2055505 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2055505 # number of overall misses -system.cpu.l2cache.overall_misses::total 2055505 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100333400500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 100333400500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 64526294750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 64526294750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 164859695250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 164859695250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 164859695250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 164859695250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 7336783 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7336783 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3700640 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3700640 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1890869 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1890869 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 9227652 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9227652 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 9227652 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9227652 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.171123 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.171123 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.423093 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.423093 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.222755 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.222755 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.222755 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.222755 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79915.603206 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 79915.603206 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80656.557768 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80656.557768 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80203.986490 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 80203.986490 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80203.986490 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 80203.986490 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1046381 # number of writebacks -system.cpu.l2cache.writebacks::total 1046381 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 6 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 6 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1255486 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1255486 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 800013 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 800013 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2055499 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2055499 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2055499 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2055499 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 84544683250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84544683250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 54440940250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54440940250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138985623500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 138985623500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138985623500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 138985623500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171122 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171122 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.423093 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423093 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.222754 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.222754 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.222754 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.222754 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67340.203913 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67340.203913 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68050.069499 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68050.069499 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67616.488016 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67616.488016 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67616.488016 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67616.488016 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9222736 # number of replacements -system.cpu.dcache.tags.tagsinuse 4085.561884 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 624006676 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9226832 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.629569 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 9704965000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4085.561884 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.997452 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997452 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 280 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1316 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2439 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1276393554 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1276393554 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 453661018 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 453661018 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 170345536 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170345536 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 61 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 61 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 624006554 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 624006554 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 624006554 # number of overall hits -system.cpu.dcache.overall_hits::total 624006554 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 7336174 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7336174 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 2240511 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2240511 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 9576685 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9576685 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 9576685 # number of overall misses -system.cpu.dcache.overall_misses::total 9576685 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 183520141245 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 183520141245 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101423015250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 101423015250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 284943156495 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 284943156495 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 284943156495 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 284943156495 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 460997192 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 460997192 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 633583239 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 633583239 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 633583239 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 633583239 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.015914 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.015914 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012982 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.012982 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.015115 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015115 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.015115 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015115 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25015.783601 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25015.783601 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45267.805090 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45267.805090 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29753.840342 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29753.840342 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29753.840342 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29753.840342 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3700640 # number of writebacks -system.cpu.dcache.writebacks::total 3700640 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 211 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 211 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 349642 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 349642 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 349853 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 349853 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 349853 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 349853 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7335963 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7335963 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1890869 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1890869 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 9226832 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9226832 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 9226832 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9226832 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168431190255 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 168431190255 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77354259500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 77354259500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245785449755 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 245785449755 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245785449755 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 245785449755 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.015913 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015913 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.010956 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014563 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014563 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014563 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014563 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22959.656456 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22959.656456 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40909.369978 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40909.369978 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26638.119103 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26638.119103 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26638.119103 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26638.119103 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 1256323 # Transaction distribution +system.membus.trans_dist::ReadResp 1256323 # Transaction distribution +system.membus.trans_dist::Writeback 1046713 # Transaction distribution +system.membus.trans_dist::ReadExReq 800324 # Transaction distribution +system.membus.trans_dist::ReadExResp 800324 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5160007 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5160007 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198615040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 198615040 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 3103360 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 3103360 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 3103360 # Request fanout histogram +system.membus.reqLayer0.occupancy 12130659500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 19439818500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index d4fe531fc..38e101aaf 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.051523 # Number of seconds simulated -sim_ticks 51522973500 # Number of ticks simulated -final_tick 51522973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.052167 # Number of seconds simulated +sim_ticks 52167245000 # Number of ticks simulated +final_tick 52167245000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 234694 # Simulator instruction rate (inst/s) -host_op_rate 234694 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 131574801 # Simulator tick rate (ticks/s) -host_mem_usage 241032 # Number of bytes of host memory used -host_seconds 391.59 # Real time elapsed on the host +host_inst_rate 231551 # Simulator instruction rate (inst/s) +host_op_rate 231551 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 131435822 # Simulator tick rate (ticks/s) +host_mem_usage 240584 # Number of bytes of host memory used +host_seconds 396.90 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 340096 # Number of bytes read from this memory -system.physmem.bytes_read::total 340096 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 202432 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 202432 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 5314 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5314 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 6600861 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6600861 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3928966 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3928966 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6600861 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6600861 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5314 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 340352 # Number of bytes read from this memory +system.physmem.bytes_read::total 340352 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 202688 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 202688 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 5318 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5318 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 6524247 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6524247 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3885350 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3885350 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6524247 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6524247 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5318 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5314 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5318 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 340096 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 340352 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 340096 # Total read bytes from the system interface side +system.physmem.bytesReadSys 340352 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 468 # Per bank write bursts +system.physmem.perBankRdBursts::0 469 # Per bank write bursts system.physmem.perBankRdBursts::1 295 # Per bank write bursts system.physmem.perBankRdBursts::2 307 # Per bank write bursts -system.physmem.perBankRdBursts::3 523 # Per bank write bursts +system.physmem.perBankRdBursts::3 524 # Per bank write bursts system.physmem.perBankRdBursts::4 224 # Per bank write bursts system.physmem.perBankRdBursts::5 238 # Per bank write bursts system.physmem.perBankRdBursts::6 222 # Per bank write bursts @@ -48,8 +48,8 @@ system.physmem.perBankRdBursts::7 289 # Pe system.physmem.perBankRdBursts::8 251 # Per bank write bursts system.physmem.perBankRdBursts::9 282 # Per bank write bursts system.physmem.perBankRdBursts::10 255 # Per bank write bursts -system.physmem.perBankRdBursts::11 260 # Per bank write bursts -system.physmem.perBankRdBursts::12 408 # Per bank write bursts +system.physmem.perBankRdBursts::11 261 # Per bank write bursts +system.physmem.perBankRdBursts::12 409 # Per bank write bursts system.physmem.perBankRdBursts::13 344 # Per bank write bursts system.physmem.perBankRdBursts::14 500 # Per bank write bursts system.physmem.perBankRdBursts::15 448 # Per bank write bursts @@ -71,14 +71,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 51522892000 # Total gap between requests +system.physmem.totGap 52167163500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5314 # Read request sizes (log2) +system.physmem.readPktSize::6 5318 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -86,8 +86,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4906 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 389 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4912 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 387 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -182,29 +182,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 963 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 352.232606 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 215.271932 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 332.609683 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 308 31.98% 31.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 198 20.56% 52.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 99 10.28% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 77 8.00% 70.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 83 8.62% 79.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 29 3.01% 82.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 26 2.70% 85.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 28 2.91% 88.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 115 11.94% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 963 # Bytes accessed per row activation -system.physmem.totQLat 35638500 # Total ticks spent queuing -system.physmem.totMemAccLat 135276000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26570000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6706.53 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 974 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 348.254620 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 211.254822 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 332.143137 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 322 33.06% 33.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 190 19.51% 52.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 96 9.86% 62.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 102 10.47% 72.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 61 6.26% 79.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 36 3.70% 82.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 25 2.57% 85.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 25 2.57% 87.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 117 12.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 974 # Bytes accessed per row activation +system.physmem.totQLat 31955000 # Total ticks spent queuing +system.physmem.totMemAccLat 131667500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26590000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6008.84 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25456.53 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 6.60 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24758.84 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 6.52 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 6.60 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.52 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage @@ -212,88 +212,65 @@ system.physmem.busUtilRead 0.05 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4346 # Number of row buffer hits during reads +system.physmem.readRowHits 4336 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.78 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.53 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9695689.12 # Average gap between requests -system.physmem.pageHitRate 81.78 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 48467499750 # Time in different power states -system.physmem.memoryStateTime::REF 1720420000 # Time in different power states +system.physmem.avgGap 9809545.60 # Average gap between requests +system.physmem.pageHitRate 81.53 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 49062382500 # Time in different power states +system.physmem.memoryStateTime::REF 1741740000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1333970250 # Time in different power states +system.physmem.memoryStateTime::ACT 1356240000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 3470040 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3810240 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1893375 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 2079000 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 19999200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 21340800 # Energy for read commands per rank (pJ) +system.physmem.actEnergy::0 3530520 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 3787560 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 1926375 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 2066625 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 19827600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 21216000 # Energy for read commands per rank (pJ) system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3365141520 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3365141520 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1727742960 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1771093170 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 29397561750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 29359535250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 34515808845 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 34522999980 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.925309 # Core power per rank (mW) -system.physmem.averagePower::1 670.064883 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 3595 # Transaction distribution -system.membus.trans_dist::ReadResp 3595 # Transaction distribution -system.membus.trans_dist::ReadExReq 1719 # Transaction distribution -system.membus.trans_dist::ReadExResp 1719 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10628 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10628 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 340096 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5314 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5314 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5314 # Request fanout histogram -system.membus.reqLayer0.occupancy 6106500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 49715250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 11407319 # Number of BP lookups -system.cpu.branchPred.condPredicted 8177175 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 788662 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 6672694 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5348459 # Number of BTB hits +system.physmem.refreshEnergy::0 3406843440 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 3406843440 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 1740241350 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 1807017705 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 29769681750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 29711106000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 34942051035 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 34952037330 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.896806 # Core power per rank (mW) +system.physmem.averagePower::1 670.088260 # Core power per rank (mW) +system.cpu.branchPred.lookups 11476347 # Number of BP lookups +system.cpu.branchPred.condPredicted 8235349 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 785844 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 6672654 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5371509 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.154417 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1172952 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 80.500338 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1176736 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20390003 # DTB read hits -system.cpu.dtb.read_misses 46972 # DTB read misses +system.cpu.dtb.read_hits 20396755 # DTB read hits +system.cpu.dtb.read_misses 47141 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20436975 # DTB read accesses -system.cpu.dtb.write_hits 6579991 # DTB write hits -system.cpu.dtb.write_misses 273 # DTB write misses +system.cpu.dtb.read_accesses 20443896 # DTB read accesses +system.cpu.dtb.write_hits 6580249 # DTB write hits +system.cpu.dtb.write_misses 266 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6580264 # DTB write accesses -system.cpu.dtb.data_hits 26969994 # DTB hits -system.cpu.dtb.data_misses 47245 # DTB misses +system.cpu.dtb.write_accesses 6580515 # DTB write accesses +system.cpu.dtb.data_hits 26977004 # DTB hits +system.cpu.dtb.data_misses 47407 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 27017239 # DTB accesses -system.cpu.itb.fetch_hits 22956157 # ITB hits +system.cpu.dtb.data_accesses 27024411 # DTB accesses +system.cpu.itb.fetch_hits 23068125 # ITB hits system.cpu.itb.fetch_misses 88 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 22956245 # ITB accesses +system.cpu.itb.fetch_accesses 23068213 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -307,255 +284,26 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 103045947 # number of cpu cycles simulated +system.cpu.numCycles 104334490 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 91903089 # Number of instructions committed system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2250214 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2153944 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.121246 # CPI: cycles per instruction -system.cpu.ipc 0.891865 # IPC: instructions per cycle -system.cpu.tickCycles 100852672 # Number of cycles that the object actually ticked -system.cpu.idleCycles 2193275 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 13697 # number of replacements -system.cpu.icache.tags.tagsinuse 1640.302767 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22940496 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15661 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1464.816806 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1640.302767 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.800929 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.800929 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1964 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 670 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 149 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 947 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.958984 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45927975 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45927975 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 22940496 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22940496 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22940496 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22940496 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22940496 # number of overall hits -system.cpu.icache.overall_hits::total 22940496 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 15661 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 15661 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 15661 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 15661 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 15661 # number of overall misses -system.cpu.icache.overall_misses::total 15661 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 386976750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 386976750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 386976750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 386976750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 386976750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 386976750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22956157 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22956157 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22956157 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22956157 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22956157 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22956157 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000682 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000682 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000682 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000682 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000682 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000682 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24709.581125 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 24709.581125 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 24709.581125 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 24709.581125 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 24709.581125 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 24709.581125 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15661 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15661 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15661 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15661 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15661 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15661 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 354287250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 354287250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 354287250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 354287250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 354287250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 354287250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000682 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000682 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000682 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22622.262308 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22622.262308 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22622.262308 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22622.262308 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22622.262308 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22622.262308 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 16146 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 16146 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1745 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1745 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31322 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4567 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 35889 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1002304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1151872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 17998 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 17998 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 17998 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 9106000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 24175250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3734000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2477.584038 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 12565 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3661 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 3.432122 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.790277 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2459.793761 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.075067 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.075610 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3661 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 181 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2504 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.111725 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 149390 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 149390 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 12551 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 12551 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 26 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 12577 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 12577 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 12577 # number of overall hits -system.cpu.l2cache.overall_hits::total 12577 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3595 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 3595 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 1719 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1719 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 5314 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 5314 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 5314 # number of overall misses -system.cpu.l2cache.overall_misses::total 5314 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 246128750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 246128750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 116497000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 116497000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 362625750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 362625750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 362625750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 362625750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 16146 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 16146 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1745 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1745 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 17891 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 17891 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 17891 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 17891 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.222656 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.222656 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.985100 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.985100 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.297021 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.297021 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.297021 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.297021 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68464.186370 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68464.186370 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67770.215241 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67770.215241 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68239.697027 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68239.697027 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68239.697027 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68239.697027 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3595 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3595 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 1719 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1719 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 5314 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5314 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 5314 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5314 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 200952250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 200952250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 94943500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 94943500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 295895750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 295895750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 295895750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 295895750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.222656 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.222656 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.985100 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985100 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.297021 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.297021 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.297021 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.297021 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55897.705146 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55897.705146 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55231.820826 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55231.820826 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55682.301468 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55682.301468 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55682.301468 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55682.301468 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.cpi 1.135266 # CPI: cycles per instruction +system.cpu.ipc 0.880851 # IPC: instructions per cycle +system.cpu.tickCycles 102681426 # Number of cycles that the object actually ticked +system.cpu.idleCycles 1653064 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1448.555792 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26545428 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1448.700924 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26568138 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11903.779372 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11913.963229 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 1448.555792 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.353651 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.353651 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.inst 1448.700924 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.353687 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.353687 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id @@ -563,16 +311,16 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 226 system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1380 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 53099946 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 53099946 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 20047236 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20047236 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 53145366 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 53145366 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 20069946 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20069946 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.inst 6498192 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 6498192 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 26545428 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26545428 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 26545428 # number of overall hits -system.cpu.dcache.overall_hits::total 26545428 # number of overall hits +system.cpu.dcache.demand_hits::cpu.inst 26568138 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26568138 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 26568138 # number of overall hits +system.cpu.dcache.overall_hits::total 26568138 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.inst 519 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 519 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.inst 2911 # number of WriteReq misses @@ -581,22 +329,22 @@ system.cpu.dcache.demand_misses::cpu.inst 3430 # n system.cpu.dcache.demand_misses::total 3430 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 3430 # number of overall misses system.cpu.dcache.overall_misses::total 3430 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 37054000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 37054000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 196991000 # 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number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 232300250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 232300250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 232300250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 232300250 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 20070465 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20070465 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 26548858 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 26548858 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 26548858 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 26548858 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.inst 26571568 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26571568 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 26571568 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26571568 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000448 # miss rate for WriteReq accesses @@ -605,14 +353,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.000129 system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.000129 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 71394.990366 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 71394.990366 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 67671.246994 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 67671.246994 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 68234.693878 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 68234.693878 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 68234.693878 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 68234.693878 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 72664.258189 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72664.258189 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66845.585709 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66845.585709 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 67726.020408 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67726.020408 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 67726.020408 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67726.020408 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -639,14 +387,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 2230 system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 2230 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 33506000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33506000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 118502500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 118502500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 152008500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 152008500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 152008500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 152008500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 34134000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 34134000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 117191500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 117191500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 151325500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 151325500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 151325500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 151325500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000268 # mshr miss rate for WriteReq accesses @@ -655,14 +403,266 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 69084.536082 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69084.536082 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67909.742120 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67909.742120 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68165.246637 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68165.246637 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68165.246637 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68165.246637 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 70379.381443 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70379.381443 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67158.452722 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67158.452722 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 67858.968610 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67858.968610 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 67858.968610 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67858.968610 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 13871 # number of replacements +system.cpu.icache.tags.tagsinuse 1640.666168 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 23052289 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15835 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1455.780802 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1640.666168 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.801107 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.801107 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1964 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 669 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 148 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 948 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.958984 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 46152085 # Number of tag accesses +system.cpu.icache.tags.data_accesses 46152085 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 23052289 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 23052289 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 23052289 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 23052289 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 23052289 # number of overall hits +system.cpu.icache.overall_hits::total 23052289 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 15836 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 15836 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 15836 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 15836 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 15836 # number of overall misses +system.cpu.icache.overall_misses::total 15836 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 386603500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 386603500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 386603500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 386603500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 386603500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 386603500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 23068125 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 23068125 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 23068125 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 23068125 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 23068125 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 23068125 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000686 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000686 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000686 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000686 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000686 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000686 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24412.951503 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 24412.951503 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 24412.951503 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 24412.951503 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 24412.951503 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 24412.951503 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15836 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15836 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15836 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15836 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15836 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15836 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 353567500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 353567500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 353567500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 353567500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 353567500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 353567500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000686 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000686 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000686 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22326.818641 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22326.818641 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22326.818641 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22326.818641 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22326.818641 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22326.818641 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2479.834280 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 12735 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3665 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 3.474761 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 17.780071 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2462.054210 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.075136 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.075679 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3665 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 768 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 182 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2506 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.111847 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 150786 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 150786 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 12721 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 12721 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 26 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 12747 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 12747 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 12747 # number of overall hits +system.cpu.l2cache.overall_hits::total 12747 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3599 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 3599 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 1719 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1719 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 5318 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 5318 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 5318 # number of overall misses +system.cpu.l2cache.overall_misses::total 5318 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 244164500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 244164500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 115186000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 115186000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 359350500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 359350500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 359350500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 359350500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 16320 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 16320 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1745 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1745 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 18065 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 18065 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 18065 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 18065 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.220527 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.220527 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.985100 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.985100 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.294381 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.294381 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.294381 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.294381 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67842.317310 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67842.317310 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67007.562536 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67007.562536 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67572.489658 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 67572.489658 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67572.489658 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 67572.489658 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3599 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3599 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 1719 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1719 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 5318 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5318 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 5318 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5318 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 198927000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 198927000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 93369000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 93369000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 292296000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 292296000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 292296000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 292296000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.220527 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.220527 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.985100 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985100 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.294381 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.294381 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.294381 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.294381 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55272.853570 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55272.853570 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54315.881326 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54315.881326 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54963.520120 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54963.520120 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54963.520120 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54963.520120 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 16320 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 16320 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1745 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1745 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31670 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4567 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 36237 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1013440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1163008 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 18172 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 18172 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 18172 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 9193000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 24435500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3734500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 3599 # Transaction distribution +system.membus.trans_dist::ReadResp 3599 # Transaction distribution +system.membus.trans_dist::ReadExReq 1719 # Transaction distribution +system.membus.trans_dist::ReadExResp 1719 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10636 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10636 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340352 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 340352 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 5318 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 5318 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 5318 # Request fanout histogram +system.membus.reqLayer0.occupancy 6477500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 50028000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index 5a483b5e7..be651ff21 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.131652 # Number of seconds simulated -sim_ticks 131652469500 # Number of ticks simulated -final_tick 131652469500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.131746 # Number of seconds simulated +sim_ticks 131745950000 # Number of ticks simulated +final_tick 131745950000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 162179 # Simulator instruction rate (inst/s) -host_op_rate 170963 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 123906567 # Simulator tick rate (ticks/s) -host_mem_usage 259776 # Number of bytes of host memory used -host_seconds 1062.51 # Real time elapsed on the host +host_inst_rate 190259 # Simulator instruction rate (inst/s) +host_op_rate 200564 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 145463120 # Simulator tick rate (ticks/s) +host_mem_usage 256996 # Number of bytes of host memory used +host_seconds 905.70 # Real time elapsed on the host sim_insts 172317809 # Number of instructions simulated sim_ops 181650742 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 247616 # Number of bytes read from this memory -system.physmem.bytes_read::total 247616 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 138304 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 138304 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3869 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3869 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1880831 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1880831 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1050523 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1050523 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1880831 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1880831 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3869 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 247488 # Number of bytes read from this memory +system.physmem.bytes_read::total 247488 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 138176 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 138176 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3867 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3867 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1878525 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1878525 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1048806 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1048806 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1878525 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1878525 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3867 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 3869 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 3867 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 247616 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 247488 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 247616 # Total read bytes from the system interface side +system.physmem.bytesReadSys 247488 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -42,14 +42,14 @@ system.physmem.perBankRdBursts::1 217 # Pe system.physmem.perBankRdBursts::2 135 # Per bank write bursts system.physmem.perBankRdBursts::3 313 # Per bank write bursts system.physmem.perBankRdBursts::4 308 # Per bank write bursts -system.physmem.perBankRdBursts::5 306 # Per bank write bursts +system.physmem.perBankRdBursts::5 305 # Per bank write bursts system.physmem.perBankRdBursts::6 273 # Per bank write bursts system.physmem.perBankRdBursts::7 222 # Per bank write bursts system.physmem.perBankRdBursts::8 249 # Per bank write bursts system.physmem.perBankRdBursts::9 218 # Per bank write bursts system.physmem.perBankRdBursts::10 295 # Per bank write bursts -system.physmem.perBankRdBursts::11 201 # Per bank write bursts -system.physmem.perBankRdBursts::12 182 # Per bank write bursts +system.physmem.perBankRdBursts::11 199 # Per bank write bursts +system.physmem.perBankRdBursts::12 183 # Per bank write bursts system.physmem.perBankRdBursts::13 218 # Per bank write bursts system.physmem.perBankRdBursts::14 224 # Per bank write bursts system.physmem.perBankRdBursts::15 203 # Per bank write bursts @@ -71,14 +71,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 131652381500 # Total gap between requests +system.physmem.totGap 131745861500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 3869 # Read request sizes (log2) +system.physmem.readPktSize::6 3867 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -87,8 +87,8 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 3616 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 241 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 238 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -182,26 +182,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 904 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 272.070796 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 178.793599 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 280.048713 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 264 29.20% 29.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 351 38.83% 68.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 86 9.51% 77.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 48 5.31% 82.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 35 3.87% 86.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 23 2.54% 89.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 17 1.88% 91.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 16 1.77% 92.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 64 7.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 904 # Bytes accessed per row activation -system.physmem.totQLat 27698500 # Total ticks spent queuing -system.physmem.totMemAccLat 100242250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 19345000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7159.09 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 912 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 269.543860 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.691365 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 273.658023 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 266 29.17% 29.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 353 38.71% 67.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 82 8.99% 76.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 61 6.69% 83.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 33 3.62% 87.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 27 2.96% 90.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 14 1.54% 91.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 19 2.08% 93.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 57 6.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 912 # Bytes accessed per row activation +system.physmem.totQLat 28129500 # Total ticks spent queuing +system.physmem.totMemAccLat 100635750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 19335000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7274.24 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25909.09 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26024.24 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s @@ -212,68 +212,45 @@ system.physmem.busUtilRead 0.01 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 2960 # Number of row buffer hits during reads +system.physmem.readRowHits 2950 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.51 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.29 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34027495.86 # Average gap between requests -system.physmem.pageHitRate 76.51 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 125800686500 # Time in different power states -system.physmem.memoryStateTime::REF 4396080000 # Time in different power states +system.physmem.avgGap 34069268.55 # Average gap between requests +system.physmem.pageHitRate 76.29 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 125856871250 # Time in different power states +system.physmem.memoryStateTime::REF 4399200000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1453435500 # Time in different power states +system.physmem.memoryStateTime::ACT 1487617250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 3039120 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3780000 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1658250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 2062500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 16185000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 13774800 # Energy for read commands per rank (pJ) +system.physmem.actEnergy::0 3092040 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 3787560 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 1687125 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 2066625 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 16177200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 13767000 # Energy for read commands per rank (pJ) system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 8598732480 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 8598732480 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 3574139400 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 3578406705 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 75854895000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 75851151750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 88048649250 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 88047908235 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.807689 # Core power per rank (mW) -system.physmem.averagePower::1 668.802060 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 2779 # Transaction distribution -system.membus.trans_dist::ReadResp 2779 # Transaction distribution -system.membus.trans_dist::ReadExReq 1090 # Transaction distribution -system.membus.trans_dist::ReadExResp 1090 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7738 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7738 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247616 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 247616 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3869 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3869 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3869 # Request fanout histogram -system.membus.reqLayer0.occupancy 4528000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 36225250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 49915423 # Number of BP lookups -system.cpu.branchPred.condPredicted 39661220 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5747038 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24423675 # Number of BTB lookups -system.cpu.branchPred.BTBHits 23301282 # Number of BTB hits +system.physmem.refreshEnergy::0 8604835200 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 8604835200 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 3575888730 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 3595740120 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 75909421500 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 75892008000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 88111101795 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 88112204505 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.807404 # Core power per rank (mW) +system.physmem.averagePower::1 668.815774 # Core power per rank (mW) +system.cpu.branchPred.lookups 49935043 # Number of BP lookups +system.cpu.branchPred.condPredicted 39664695 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5744224 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 24405530 # Number of BTB lookups +system.cpu.branchPred.BTBHits 23309445 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.404488 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1905800 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 95.508866 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1908457 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 139 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -359,330 +336,91 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 263304939 # number of cpu cycles simulated +system.cpu.numCycles 263491900 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 172317809 # Number of instructions committed system.cpu.committedOps 181650742 # Number of ops (including micro ops) committed -system.cpu.discardedOps 11787313 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 11758002 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.528019 # CPI: cycles per instruction -system.cpu.ipc 0.654442 # IPC: instructions per cycle -system.cpu.tickCycles 255940225 # Number of cycles that the object actually ticked -system.cpu.idleCycles 7364714 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 2881 # number of replacements -system.cpu.icache.tags.tagsinuse 1424.983856 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 71509873 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4678 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 15286.420051 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1424.983856 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.695793 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.695793 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 503 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 114 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1069 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.877441 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 143033782 # Number of tag accesses -system.cpu.icache.tags.data_accesses 143033782 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 71509873 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 71509873 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 71509873 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 71509873 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 71509873 # number of overall hits -system.cpu.icache.overall_hits::total 71509873 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4679 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4679 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4679 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4679 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4679 # number of overall misses -system.cpu.icache.overall_misses::total 4679 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 184816496 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 184816496 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 184816496 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 184816496 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 184816496 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 184816496 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 71514552 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 71514552 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 71514552 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 71514552 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 71514552 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 71514552 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000065 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000065 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000065 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000065 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000065 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000065 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39499.144262 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 39499.144262 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 39499.144262 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 39499.144262 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 39499.144262 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 39499.144262 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4679 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4679 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4679 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4679 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4679 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4679 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 174539504 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 174539504 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 174539504 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 174539504 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 174539504 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 174539504 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000065 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000065 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000065 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37302.736482 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37302.736482 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37302.736482 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37302.736482 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37302.736482 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37302.736482 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 5390 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5389 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9357 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3634 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 12991 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 299392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116800 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 416192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6504 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 6504 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6504 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3268000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7477496 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2996735 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2001.642948 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2592 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2787 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.930032 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 3.028976 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1998.613972 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.060993 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.061085 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 2787 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 535 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 142 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2005 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.085052 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 55917 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 55917 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2591 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2591 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 8 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2599 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2599 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2599 # number of overall hits -system.cpu.l2cache.overall_hits::total 2599 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2799 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 2799 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 1090 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1090 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3889 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 3889 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3889 # number of overall misses -system.cpu.l2cache.overall_misses::total 3889 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 190706250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 190706250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 75951500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 75951500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 266657750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 266657750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 266657750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 266657750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 5390 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 5390 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1098 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1098 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 6488 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 6488 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 6488 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 6488 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.519295 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.519295 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.992714 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.992714 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.599414 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.599414 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.599414 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.599414 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68133.708467 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68133.708467 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69680.275229 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69680.275229 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68567.176652 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68567.176652 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68567.176652 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68567.176652 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 19 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 19 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 19 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 19 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 19 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 19 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2780 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2780 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 1090 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1090 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3870 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3870 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3870 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 3870 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 154681250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 154681250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 62286000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62286000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 216967250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 216967250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 216967250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 216967250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.515770 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.515770 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.992714 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.596486 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.596486 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.596486 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.596486 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55640.737410 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55640.737410 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57143.119266 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57143.119266 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56063.888889 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56063.888889 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56063.888889 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56063.888889 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.cpi 1.529104 # CPI: cycles per instruction +system.cpu.ipc 0.653978 # IPC: instructions per cycle +system.cpu.tickCycles 257145198 # Number of cycles that the object actually ticked +system.cpu.idleCycles 6346702 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1376.810186 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40745471 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1809 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22523.754008 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1377.772721 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40762987 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22520.987293 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 1376.810186 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.336135 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.336135 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1767 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.inst 1377.772721 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.336370 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.336370 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 269 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1357 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.431396 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 81497573 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 81497573 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 28338014 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28338014 # number of ReadReq hits +system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1358 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.431641 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 81532656 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 81532656 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 28355530 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28355530 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.inst 12362643 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 12362643 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.inst 22407 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.inst 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 40700657 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40700657 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 40700657 # number of overall hits -system.cpu.dcache.overall_hits::total 40700657 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 767 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 767 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.inst 40718173 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40718173 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 40718173 # number of overall hits +system.cpu.dcache.overall_hits::total 40718173 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 792 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 792 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.inst 1644 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 1644 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 2411 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2411 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 2411 # number of overall misses -system.cpu.dcache.overall_misses::total 2411 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 52005983 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 52005983 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 115743750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 115743750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 167749733 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 167749733 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 167749733 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 167749733 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 28338781 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28338781 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.inst 2436 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2436 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 2436 # number of overall misses +system.cpu.dcache.overall_misses::total 2436 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 54011984 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 54011984 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 115580250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 115580250 # 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number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 40703068 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 40703068 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 40703068 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 40703068 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000027 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.inst 40720609 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 40720609 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 40720609 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 40720609 # 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average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70304.288321 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70304.288321 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69619.143678 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69619.143678 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69619.143678 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69619.143678 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -693,30 +431,30 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 16 # 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Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.942190 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 3.029184 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1998.491284 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.060989 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.061082 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 2785 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 522 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 153 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2005 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084991 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 56139 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 56139 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 2623 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2623 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 8 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2631 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2631 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2631 # number of overall hits +system.cpu.l2cache.overall_hits::total 2631 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2795 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 2795 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 1090 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1090 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3885 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 3885 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3885 # number of overall misses +system.cpu.l2cache.overall_misses::total 3885 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 191698500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 191698500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 75314000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 75314000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 267012500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 267012500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 267012500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 267012500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 5418 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 5418 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1098 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1098 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 6516 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 6516 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 6516 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 6516 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.515873 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.515873 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.992714 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.992714 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.596225 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.596225 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.596225 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.596225 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68586.225403 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68586.225403 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69095.412844 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69095.412844 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68729.086229 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68729.086229 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68729.086229 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68729.086229 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 17 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 17 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 17 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2778 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2778 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 1090 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1090 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3868 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3868 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3868 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 3868 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 155803750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 155803750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 61486500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61486500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 217290250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 217290250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 217290250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 217290250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.512735 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.512735 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.992714 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.593616 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.593616 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.593616 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.593616 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56084.863211 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56084.863211 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56409.633028 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56409.633028 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56176.383144 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56176.383144 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56176.383144 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56176.383144 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 5418 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5417 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9411 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3636 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 13047 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 301120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 417984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 6532 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 6532 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 6532 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3282000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 7517747 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2996736 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 2777 # Transaction distribution +system.membus.trans_dist::ReadResp 2777 # Transaction distribution +system.membus.trans_dist::ReadExReq 1090 # Transaction distribution +system.membus.trans_dist::ReadExResp 1090 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7734 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7734 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247488 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 247488 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 3867 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 3867 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 3867 # Request fanout histogram +system.membus.reqLayer0.occupancy 4723500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 36361250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |