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-rw-r--r--tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini391
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/o3-timing/config.out366
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt423
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr6
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout44
-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini4
-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.out2
-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt22
-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out3075
-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout28
-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini13
-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out8
-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt288
-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out3075
-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout28
15 files changed, 2404 insertions, 5369 deletions
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
new file mode 100644
index 000000000..585239418
--- /dev/null
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
@@ -0,0 +1,391 @@
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache fuPool icache l2cache toL2Bus workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+system=system
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+adaptive_compression=false
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+latency=1000
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=262144
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList0
+count=6
+opList=system.cpu.fuPool.FUList0.opList0
+
+[system.cpu.fuPool.FUList0.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList0
+count=0
+opList=system.cpu.fuPool.FUList4.opList0
+
+[system.cpu.fuPool.FUList4.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList0
+count=0
+opList=system.cpu.fuPool.FUList5.opList0
+
+[system.cpu.fuPool.FUList5.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
+
+[system.cpu.fuPool.FUList6.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList6.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0
+count=1
+opList=system.cpu.fuPool.FUList7.opList0
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+adaptive_compression=false
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+latency=1000
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=131072
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.l2cache]
+type=BaseCache
+adaptive_compression=false
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+latency=1000
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=2097152
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=gzip input.log 1
+cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
+egid=100
+env=
+euid=100
+executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
+gid=100
+input=cin
+output=cout
+pid=100
+ppid=99
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.out b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.out
new file mode 100644
index 000000000..b8a2728b3
--- /dev/null
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.out
@@ -0,0 +1,366 @@
+[root]
+type=Root
+dummy=0
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+zero=false
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+block_size=64
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=gzip input.log 1
+executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
+input=cin
+output=cout
+env=
+cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
+system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
+
+[system.cpu.fuPool.FUList0.opList0]
+type=OpDesc
+opClass=IntAlu
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+opList=system.cpu.fuPool.FUList0.opList0
+count=6
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+opClass=IntMult
+opLat=3
+issueLat=1
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+opClass=IntDiv
+opLat=20
+issueLat=19
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+count=2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+opClass=FloatAdd
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+opClass=FloatCmp
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+opClass=FloatCvt
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+count=4
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+opClass=FloatMult
+opLat=4
+issueLat=1
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+opClass=FloatDiv
+opLat=12
+issueLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+opClass=FloatSqrt
+opLat=24
+issueLat=24
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+count=2
+
+[system.cpu.fuPool.FUList4.opList0]
+type=OpDesc
+opClass=MemRead
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+opList=system.cpu.fuPool.FUList4.opList0
+count=0
+
+[system.cpu.fuPool.FUList5.opList0]
+type=OpDesc
+opClass=MemWrite
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+opList=system.cpu.fuPool.FUList5.opList0
+count=0
+
+[system.cpu.fuPool.FUList6.opList0]
+type=OpDesc
+opClass=MemRead
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList6.opList1]
+type=OpDesc
+opClass=MemWrite
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
+count=4
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+opClass=IprAccess
+opLat=3
+issueLat=3
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+opList=system.cpu.fuPool.FUList7.opList0
+count=1
+
+[system.cpu.fuPool]
+type=FUPool
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
+
+[system.cpu]
+type=DerivO3CPU
+clock=500
+phase=0
+numThreads=1
+cpu_id=0
+activity=0
+workload=system.cpu.workload
+checker=null
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+cachePorts=200
+decodeToFetchDelay=1
+renameToFetchDelay=1
+iewToFetchDelay=1
+commitToFetchDelay=1
+fetchWidth=8
+renameToDecodeDelay=1
+iewToDecodeDelay=1
+commitToDecodeDelay=1
+fetchToDecodeDelay=1
+decodeWidth=8
+iewToRenameDelay=1
+commitToRenameDelay=1
+decodeToRenameDelay=1
+renameWidth=8
+commitToIEWDelay=1
+renameToIEWDelay=2
+issueToExecuteDelay=1
+dispatchWidth=8
+issueWidth=8
+wbWidth=8
+wbDepth=1
+fuPool=system.cpu.fuPool
+iewToCommitDelay=1
+renameToROBDelay=1
+commitWidth=8
+squashWidth=8
+trapLatency=13
+backComSize=5
+forwardComSize=5
+predType=tournament
+localPredictorSize=2048
+localCtrBits=2
+localHistoryTableSize=2048
+localHistoryBits=11
+globalPredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+choicePredictorSize=8192
+choiceCtrBits=2
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+LQEntries=32
+SQEntries=32
+LFSTSize=1024
+SSITSize=1024
+numPhysIntRegs=256
+numPhysFloatRegs=256
+numIQEntries=64
+numROBEntries=192
+smtNumFetchingThreads=1
+smtFetchPolicy=SingleThread
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+smtCommitPolicy=RoundRobin
+instShiftAmt=2
+defer_registration=false
+function_trace=false
+function_trace_start=0
+
+[system.cpu.icache]
+type=BaseCache
+size=131072
+assoc=2
+block_size=64
+latency=1000
+mshrs=10
+tgts_per_mshr=20
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10000
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1000
+mshrs=10
+tgts_per_mshr=20
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10000
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+
+[system.cpu.l2cache]
+type=BaseCache
+size=2097152
+assoc=2
+block_size=64
+latency=1000
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10000
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+block_size=64
+
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt
new file mode 100644
index 000000000..929354b82
--- /dev/null
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt
@@ -0,0 +1,423 @@
+
+---------- Begin Simulation Statistics ----------
+global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+global.BPredUnit.BTBHits 155497873 # Number of BTB hits
+global.BPredUnit.BTBLookups 176569029 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 90327270 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 223339092 # Number of conditional branches predicted
+global.BPredUnit.lookups 223339092 # Number of BP lookups
+global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
+host_inst_rate 54106 # Simulator instruction rate (inst/s)
+host_mem_usage 156124 # Number of bytes of host memory used
+host_seconds 27529.37 # Real time elapsed on the host
+host_tick_rate 45674334 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 464625781 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 155659586 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 751805606 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 305482201 # Number of stores inserted to the mem dependence unit.
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 1489514762 # Number of instructions simulated
+sim_seconds 1.257386 # Number of seconds simulated
+sim_ticks 1257385552000 # Number of ticks simulated
+system.cpu.commit.COM:branches 86246390 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 9313657 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle.samples 2273477268
+system.cpu.commit.COM:committed_per_cycle.min_value 0
+ 0 1413600532 6217.79%
+ 1 557883273 2453.88%
+ 2 123364539 542.62%
+ 3 120963543 532.06%
+ 4 18884040 83.06%
+ 5 12171132 53.54%
+ 6 9965158 43.83%
+ 7 7331394 32.25%
+ 8 9313657 40.97%
+system.cpu.commit.COM:committed_per_cycle.max_value 8
+system.cpu.commit.COM:committed_per_cycle.end_dist
+
+system.cpu.commit.COM:count 1489514762 # Number of instructions committed
+system.cpu.commit.COM:loads 402511689 # Number of loads committed
+system.cpu.commit.COM:membars 51356 # Number of memory barriers committed
+system.cpu.commit.COM:refs 569359657 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 90327270 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 1489514762 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 2243499 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 1399513618 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 1489514762 # Number of Instructions Simulated
+system.cpu.committedInsts_total 1489514762 # Number of Instructions Simulated
+system.cpu.cpi 1.688316 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.688316 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 431095835 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 2842.252413 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2392.500580 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 430168385 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 2636047000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.002151 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 927450 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 694672 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 556921500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.000540 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 232778 # number of ReadReq MSHR misses
+system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_avg_miss_latency 3500 # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2500 # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits
+system.cpu.dcache.SwapReq_miss_latency 24500 # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses
+system.cpu.dcache.SwapReq_mshr_miss_latency 17500 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 166846642 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 3889.592412 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3171.120393 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 165155866 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 6576429500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.010134 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1690776 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 1420478 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 857147500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.001620 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 270298 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 1183.354576 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 597942477 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 3518.594842 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 2810.845677 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 595324251 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 9212476500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.004379 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 2618226 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 2115150 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 1414069000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.000841 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 503076 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 597942477 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 3518.594842 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 2810.845677 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 595324251 # number of overall hits
+system.cpu.dcache.overall_miss_latency 9212476500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.004379 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 2618226 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 2115150 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 1414069000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.000841 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 503076 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 498987 # number of replacements
+system.cpu.dcache.sampled_refs 503083 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 4095.797134 # Cycle average of tags in use
+system.cpu.dcache.total_refs 595325570 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 77974000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 335737 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 435745843 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 3276032607 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 1073744654 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 761619600 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 241293837 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles 2367171 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 223339092 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 355860305 # Number of cache lines fetched
+system.cpu.fetch.Cycles 1166695920 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 14770227 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 3591774268 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 93734364 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.088811 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 355860305 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 155497873 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.428271 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist.samples 2514771105
+system.cpu.fetch.rateDist.min_value 0
+ 0 1703935491 6775.71%
+ 1 252157679 1002.71%
+ 2 75632424 300.75%
+ 3 38096592 151.49%
+ 4 76680653 304.92%
+ 5 30840750 122.64%
+ 6 33076966 131.53%
+ 7 20130593 80.05%
+ 8 284219957 1130.20%
+system.cpu.fetch.rateDist.max_value 8
+system.cpu.fetch.rateDist.end_dist
+
+system.cpu.icache.ReadReq_accesses 355860305 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 5111.111111 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 4198.640483 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 355858946 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 6946000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 1359 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 5559000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 1324 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 268775.638973 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 355860305 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 5111.111111 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 4198.640483 # average overall mshr miss latency
+system.cpu.icache.demand_hits 355858946 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 6946000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
+system.cpu.icache.demand_misses 1359 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 35 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 5559000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 1324 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 355860305 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 5111.111111 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 4198.640483 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 355858946 # number of overall hits
+system.cpu.icache.overall_miss_latency 6946000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
+system.cpu.icache.overall_misses 1359 # number of overall misses
+system.cpu.icache.overall_mshr_hits 35 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 5559000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 1324 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 198 # number of replacements
+system.cpu.icache.sampled_refs 1324 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 1026.431065 # Cycle average of tags in use
+system.cpu.icache.total_refs 355858946 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idleCycles 1497 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 128998684 # Number of branches executed
+system.cpu.iew.EXEC:nop 0 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.879999 # Inst execution rate
+system.cpu.iew.EXEC:refs 756340485 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 208683785 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 1511846593 # num instructions consuming a value
+system.cpu.iew.WB:count 2184193190 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.964010 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 1457435157 # num instructions producing a value
+system.cpu.iew.WB:rate 0.868546 # insts written-back per cycle
+system.cpu.iew.WB:sent 2194556483 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 93921260 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 242324 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 751805606 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 21112863 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 6967923 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 305482201 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 2889028359 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 547656700 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 155922171 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 2212995141 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 241293837 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 1173 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 116560202 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 586068 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.memOrderViolation 3827981 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 59 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 349293917 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 138634233 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 3827981 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 1127857 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 92793403 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.592306 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.592306 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 2368917312 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.start_dist
+ No_OpClass 351375247 14.83% # Type of FU issued
+ IntAlu 1188705257 50.18% # Type of FU issued
+ IntMult 0 0.00% # Type of FU issued
+ IntDiv 0 0.00% # Type of FU issued
+ FloatAdd 2951238 0.12% # Type of FU issued
+ FloatCmp 0 0.00% # Type of FU issued
+ FloatCvt 0 0.00% # Type of FU issued
+ FloatMult 0 0.00% # Type of FU issued
+ FloatDiv 0 0.00% # Type of FU issued
+ FloatSqrt 0 0.00% # Type of FU issued
+ MemRead 592531661 25.01% # Type of FU issued
+ MemWrite 233353909 9.85% # Type of FU issued
+ IprAccess 0 0.00% # Type of FU issued
+ InstPrefetch 0 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.end_dist
+system.cpu.iq.ISSUE:fu_busy_cnt 6622922 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.002796 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full.start_dist
+ No_OpClass 0 0.00% # attempts to use FU when none available
+ IntAlu 3150287 47.57% # attempts to use FU when none available
+ IntMult 0 0.00% # attempts to use FU when none available
+ IntDiv 0 0.00% # attempts to use FU when none available
+ FloatAdd 202242 3.05% # attempts to use FU when none available
+ FloatCmp 0 0.00% # attempts to use FU when none available
+ FloatCvt 0 0.00% # attempts to use FU when none available
+ FloatMult 0 0.00% # attempts to use FU when none available
+ FloatDiv 0 0.00% # attempts to use FU when none available
+ FloatSqrt 0 0.00% # attempts to use FU when none available
+ MemRead 2975364 44.93% # attempts to use FU when none available
+ MemWrite 295029 4.45% # attempts to use FU when none available
+ IprAccess 0 0.00% # attempts to use FU when none available
+ InstPrefetch 0 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full.end_dist
+system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle.samples 2514771105
+system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
+ 0 1264571415 5028.57%
+ 1 618163663 2458.13%
+ 2 318214573 1265.38%
+ 3 195947630 779.19%
+ 4 78232851 311.09%
+ 5 28085074 111.68%
+ 6 8167595 32.48%
+ 7 2987163 11.88%
+ 8 401141 1.60%
+system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
+system.cpu.iq.ISSUE:issued_per_cycle.end_dist
+
+system.cpu.iq.ISSUE:rate 0.942001 # Inst issue rate
+system.cpu.iq.iqInstsAdded 2867645475 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 2368917312 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 21382884 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 1368214032 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 461256 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 19139385 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 1296493196 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadReq_accesses 504406 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 4393.799833 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2267.430007 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 476939 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 120684500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.054454 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 27467 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 62279500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.054454 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 27467 # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 335737 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 335720 # number of Writeback hits
+system.cpu.l2cache.Writeback_miss_rate 0.000051 # miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_misses 17 # number of Writeback misses
+system.cpu.l2cache.Writeback_mshr_miss_rate 0.000051 # mshr miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_mshr_misses 17 # number of Writeback MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 29.586740 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 504406 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 4393.799833 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 2267.430007 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 476939 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 120684500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.054454 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 27467 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 62279500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.054454 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 27467 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 840143 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 4391.082084 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 2267.430007 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 812659 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 120684500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.032713 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 27484 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 62279500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.032693 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 27467 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 2692 # number of replacements
+system.cpu.l2cache.sampled_refs 27467 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 24466.224839 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 812659 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 2555 # number of writebacks
+system.cpu.numCycles 2514771105 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 14153952 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 1244762263 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 845 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 1122858502 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 18964355 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups 4974059876 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 3105364972 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 2435580679 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 713636177 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 241293837 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 24303898 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 1190818416 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 398524739 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 21495577 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 149561373 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 21338548 # count of temporary serializing insts renamed
+system.cpu.timesIdled 3 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls 19 # Number of system calls
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr
new file mode 100644
index 000000000..6fe2fe04f
--- /dev/null
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr
@@ -0,0 +1,6 @@
+warn: More than two loadable segments in ELF object.
+warn: Ignoring segment @ 0xb4000 length 0x10.
+warn: More than two loadable segments in ELF object.
+warn: Ignoring segment @ 0x0 length 0x0.
+warn: Entering event queue @ 0. Starting simulation...
+warn: Ignoring request to flush register windows.
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout
new file mode 100644
index 000000000..c0d965c7b
--- /dev/null
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout
@@ -0,0 +1,44 @@
+spec_init
+Loading Input Data
+Duplicating 262144 bytes
+Duplicating 524288 bytes
+Input data 1048576 bytes in length
+Compressing Input Data, level 1
+Compressed data 108074 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 3
+Compressed data 97831 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 5
+Compressed data 83382 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 7
+Compressed data 76606 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 73189 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+M5 Simulator System
+
+Copyright (c) 2001-2006
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jun 21 2007 21:15:48
+M5 started Fri Jun 22 01:01:27 2007
+M5 executing on zizzer.eecs.umich.edu
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing tests/run.py long/00.gzip/sparc/linux/o3-timing
+Global frequency set at 1000000000000 ticks per second
+Exiting @ tick 1257385552000 because target called exit()
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
index 9b8d69888..9cdc13914 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
@@ -39,7 +39,7 @@ env=
euid=100
executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
gid=100
-input=/dist/m5/cpu2000/data/mcf/lgred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
output=cout
pid=100
ppid=99
@@ -53,7 +53,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
-port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
+port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.out b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.out
index 8a5c9fd62..b84a9d780 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.out
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.out
@@ -26,7 +26,7 @@ block_size=64
type=LiveProcess
cmd=mcf mcf.in
executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
-input=/dist/m5/cpu2000/data/mcf/lgred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
output=cout
env=
cwd=build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt
index 530572b5d..ed8482fb4 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt
@@ -1,18 +1,18 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 686638 # Simulator instruction rate (inst/s)
-host_mem_usage 149820 # Number of bytes of host memory used
-host_seconds 2504.37 # Real time elapsed on the host
-host_tick_rate 343319148 # Simulator tick rate (ticks/s)
+host_inst_rate 1151751 # Simulator instruction rate (inst/s)
+host_mem_usage 150484 # Number of bytes of host memory used
+host_seconds 211.71 # Real time elapsed on the host
+host_tick_rate 575874246 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1719594534 # Number of instructions simulated
-sim_seconds 0.859797 # Number of seconds simulated
-sim_ticks 859797266500 # Number of ticks simulated
+sim_insts 243840172 # Number of instructions simulated
+sim_seconds 0.121920 # Number of seconds simulated
+sim_ticks 121920085500 # Number of ticks simulated
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 1719594534 # number of cpu cycles simulated
-system.cpu.num_insts 1719594534 # Number of instructions executed
-system.cpu.num_refs 774793634 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 632 # Number of system calls
+system.cpu.numCycles 243840172 # number of cpu cycles simulated
+system.cpu.num_insts 243840172 # Number of instructions executed
+system.cpu.num_refs 105125191 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 428 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out
index 6bbb02cf0..095132477 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out
@@ -1,3092 +1,999 @@
()
-1642
-***
-1759
-()
-1641
-***
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-()
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-1500
-()
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-1483
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()
-1388
-***
-1570
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()
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-1543
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()
-1386
-***
-1558
+496
()
-1385
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()
-1384
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()
-1382
-***
-1439
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()
-1381
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-1677
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()
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()
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-***
-1397
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()
-1377
-***
-1787
+489
()
-1376
-***
-1408
+488
()
-1375
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()
-1374
+486
()
-1373
-***
-1671
+484
()
-1372
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()
-1370
-***
-1793
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()
-1369
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()
-1365
-***
-1762
+479
()
-1346
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()
-1345
-***
-1566
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()
-1344
-***
-1520
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()
-1343
-***
-1492
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()
-1342
-***
-1576
-***
-1656
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()
-1341
-***
-1447
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()
-1340
-***
-1550
+472
()
-1339
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()
-1338
+469
()
-1337
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()
-1329
-***
-1336
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()
-1328
-***
-1446
+466
()
-1327
-***
-1607
+465
()
-1325
+464
()
-1324
+463
()
-1323
+462
()
-1317
+461
()
-1315
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()
-1311
-***
-1450
-***
-1720
+459
()
-1310
-***
-1619
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()
-1309
-***
-1458
+457
()
-1308
+455
()
-1307
-***
-1427
+454
()
-1306
-***
-1364
-***
-1696
+452
()
-1299
+451
()
-1297
-***
-1395
+450
()
-1296
+449
()
-1295
-***
-1326
+448
()
-1294
-***
-1371
+446
()
-1293
-***
-1456
+445
()
-1292
-***
-1312
+444
()
-1291
+443
()
-1290
-***
-1363
+442
()
-1282
-***
-1592
+440
()
-1281
-***
-1379
+439
()
-1280
-***
-1478
+438
()
-1279
-***
-1436
+436
()
-1278
-***
-1620
+435
()
-1277
-***
-1487
+433
()
-1276
-***
-1288
+432
()
-1275
-***
-1596
+431
()
-1274
-***
-1322
+428
()
-1273
-***
-1305
-***
-1699
+427
()
-1272
+425
()
-1271
-***
-1484
+424
()
-1270
-***
-1518
+423
()
-1269
-***
-1289
+420
()
-1268
-***
-1443
-***
-1786
+419
()
-1265
+416
()
-1243
-***
-1368
+414
()
-1242
+413
()
-1241
-***
-1421
-***
-1749
+412
()
-1240
-***
-1260
-***
-1678
+407
()
-1239
+406
()
-1238
+405
()
-1236
-***
-1263
-***
-1767
+404
()
-1235
+403
()
-1234
+402
()
-1233
+401
()
-1232
-***
-1752
+400
()
-1231
-***
-1791
+399
()
-1230
+398
()
-1229
+396
()
-1228
-***
-1702
+395
()
-1227
+393
()
-1226
+392
()
-1225
+390
()
-1224
+389
()
-1223
+388
()
-1216
-***
-1531
+387
()
-1215
-***
-1530
-***
-1797
+386
()
-1214
-***
-1474
-***
-1742
+385
()
-1213
-***
-1488
+384
()
-1212
-***
-1298
-***
-1789
+383
()
-1211
-***
-1491
+382
()
-1210
-***
-1600
+381
()
-1209
-***
-1244
+380
()
-1208
-***
-1609
-***
-1704
+379
()
-1207
-***
-1237
+377
()
-1206
-***
-1468
+375
()
-1205
-***
-1547
+374
()
-1204
-***
-1246
+373
()
-1203
-***
-1593
-***
-1734
+372
()
-1202
-***
-1535
+371
()
-1200
+370
()
-1198
+369
()
-1196
+368
()
-1195
+366
()
-1194
-***
-1302
+365
()
-1192
+364
()
-1191
+362
()
-1189
+361
()
-1188
+360
()
-1187
+359
()
-1186
+358
()
-1183
+357
()
-1181
-***
-1778
+356
()
-1179
+355
()
-1178
+354
()
-1177
-***
-1645
+352
()
-1176
+350
()
-1175
-***
-1318
-***
-1649
+347
()
-1173
+344
()
-1172
+342
()
-1171
+341
()
-1169
-***
-1654
+340
()
-1168
-***
-1692
+339
()
-1167
+338
()
-1164
+332
()
-1163
+325
()
-1162
+320
***
-1716
-()
-1160
+345
()
-1159
+319
***
-1663
-()
-1157
-()
-1156
-()
-1155
-()
-1154
-()
-1153
-()
-1152
-()
-1150
-()
-1149
-()
-1147
-()
-1145
+497
()
-1143
+318
***
-1711
-()
-1142
-()
-1141
-()
-1140
+349
()
-1139
+317
***
-1755
-()
-1138
+408
()
-1137
+316
***
-1218
+324
()
-1136
-***
-1248
+315
***
-1670
-()
-1135
-()
-1134
+328
()
-1133
+314
***
-1662
-()
-1132
-()
-1131
-()
-1129
-()
-1128
-()
-1127
+335
()
-1126
+313
***
-1301
-()
-1125
-()
-1124
-()
-1123
-()
-1122
+378
()
-1120
+312
***
-1332
+426
()
-1119
+311
***
-1737
+411
()
-1118
+304
***
-1718
+343
()
-1117
-***
-1250
+303
***
-1658
-()
-1116
-()
-1114
-()
-1113
-()
-1112
+417
()
-1111
+302
***
-1772
+485
()
-1110
+301
***
-1359
-()
-1109
+363
()
-1108
+300
***
-1251
-()
-1106
+376
()
-1105
+299
***
-1771
-()
-1104
-()
-1102
-()
-1101
-()
-1100
+333
()
-1099
+292
***
-1689
-()
-1098
+337
()
-1097
+291
***
-1785
+409
()
-1096
+290
***
-1685
-()
-1095
-()
-1094
-()
-1093
-()
-1092
-()
-1091
-()
-1090
-()
-1089
-()
-1088
-()
-1087
-()
-1086
-()
-1085
+421
()
-1084
+289
***
-1739
+437
()
-1083
+288
***
-1405
-()
-1082
-()
-1081
-()
-1080
-()
-1078
-()
-1077
-()
-1076
-()
-1075
-()
-1074
-()
-1073
-()
-1072
-()
-1071
+430
()
-1070
+287
***
-1707
+348
()
-1069
+286
***
-1334
-()
-1068
-()
-1066
-()
-1065
-()
-1064
-()
-1063
-()
-1062
-()
-1061
-()
-1060
-()
-1059
+326
()
-1058
+284
()
-1057
+282
***
-1744
-()
-1056
-()
-1055
+308
()
-1054
+279
***
-1335
-()
-1052
+297
***
-1660
-()
-1051
-()
-1050
-()
-1049
-()
-1048
-()
-1047
+305
()
-1046
+278
()
-1045
+277
***
-1357
+307
()
-1044
+276
***
-1659
-()
-1043
-()
-1041
-()
-1040
-()
-1039
-()
-1038
-()
-1037
+296
()
-1036
+273
()
-1035
+271
()
-1034
+265
()
-1033
+246
***
-1690
-()
-1031
-()
-1030
-()
-1029
+267
()
-1028
+245
***
-1675
-()
-1027
-()
-1026
+280
()
-1025
+244
***
-1257
-()
-1024
-()
-1023
-()
-1022
-()
-1021
-()
-1020
+391
()
-1019
+243
***
-1284
-()
-1018
+330
()
-1017
+242
***
-1754
-()
-1016
+456
()
-1015
+241
***
-1247
-()
-1014
-()
-1013
+346
()
-1012
+240
***
-1319
+483
()
-1011
-***
-1352
+239
***
-1651
-()
-1010
+260
()
-1009
+238
***
-1705
-()
-1008
-()
-1007
-()
-1006
+261
()
-1005
+237
***
-1679
-()
-1004
-()
-1003
-()
-1002
-()
-1001
-()
-1000
+262
***
-1731
-()
-999
-()
-998
-()
-996
-()
-995
-()
-994
-()
-993
+294
()
-991
+236
***
-1799
-()
-990
-()
-989
-()
-987
-()
-986
-()
-985
-()
-984
+253
()
-983
+229
***
-1745
-()
-982
+397
()
-981
+228
***
-1644
-()
-980
-()
-979
-()
-978
-()
-977
-()
-976
-()
-975
+298
()
-974
+227
***
-1222
-()
-973
-()
-972
-()
-971
-()
-970
-()
-968
-()
-967
-()
-966
+415
()
-965
+226
***
-1347
-()
-964
-()
-963
+264
()
-962
+224
***
-1743
+232
()
-961
+222
***
-1719
+233
()
-960
+217
***
-1758
-()
-959
+250
()
-958
+211
***
-1733
+331
()
-957
+210
***
-1775
-()
-956
-()
-955
-()
-954
-()
-953
+394
()
-952
+209
***
-1393
-()
-951
-()
-950
+410
()
-949
+208
***
-1669
-()
-948
-()
-947
+321
()
-946
+207
***
-1681
+327
()
-944
+206
***
-1686
-()
-943
-()
-942
+309
()
-940
+199
***
-1783
-()
-939
-()
-938
-()
-937
-()
-936
-()
-934
-()
-933
-()
-932
-()
-931
-()
-930
+259
()
-929
+198
***
-1713
+219
()
-928
+197
***
-1725
-()
-927
-()
-926
-()
-925
-()
-924
-()
-923
-()
-922
+220
()
-921
+195
***
-1394
+429
()
-920
+194
***
-1741
+470
()
-919
+193
***
-1708
-()
-918
-()
-917
+274
()
-916
+191
***
-1723
-()
-915
-()
-914
-()
-913
-()
-912
-()
-911
-()
-910
+203
()
-909
+190
***
-1795
-()
-908
-()
-907
-()
-906
-()
-905
-()
-904
+263
()
-903
+189
+215
***
-1330
-()
-902
-()
-901
-()
-900
-()
-899
-()
-898
+230
()
-897
+188
***
-1790
-()
-896
+266
***
-1652
+295
()
-895
+182
***
-1761
-()
-894
-()
-893
-()
-892
-()
-891
+329
()
-890
+181
***
-1253
+351
()
-889
+180
***
-1698
-()
-888
-()
-887
-()
-885
+441
()
-884
+179
***
-1703
-()
-883
-()
-882
+453
()
-881
+178
***
-1747
-()
-880
+418
()
-879
+177
***
-1647
+353
()
-878
+176
***
-1358
+422
()
-877
+175
***
-1407
-()
-876
-()
-875
-()
-874
+225
***
-1283
+255
()
-873
+174
***
-1682
-()
-872
-()
-871
-()
-870
-()
-869
-()
-868
+269
()
-867
+173
***
-1751
-()
-866
-()
-865
-()
-864
-()
-863
+214
()
-862
+172
***
-1753
-()
-861
-()
-860
-()
-859
+186
()
-858
+171
***
-1348
-()
-857
+447
()
-856
+170
***
-1350
-()
-855
+270
***
-1252
-()
-854
+306
()
-853
+169
***
-1201
-()
-852
-()
-851
+336
()
-850
+168
***
-1361
-()
-849
-()
-848
-()
-847
-()
-846
-()
-845
-()
-844
-()
-843
-()
-842
-()
-841
-()
-840
+285
()
-839
+165
***
-1360
-()
-838
-()
-837
-()
-836
-()
-835
-()
-834
+249
()
-833
+146
***
-1406
-()
-832
-()
-831
-()
-830
-()
-829
-()
-827
-()
-826
-()
-825
-()
-824
-()
-823
-()
-822
+154
()
-821
+143
***
-1683
+334
()
-820
+142
***
-1672
-()
-819
-()
-818
+216
***
-1693
-()
-816
+257
()
-815
+141
***
-1313
-()
-814
-()
-813
-()
-812
+167
***
-1727
-()
-811
-()
-810
-()
-809
-()
-808
-()
-806
+251
()
-805
+140
***
-1217
-()
-804
-()
-803
-()
-802
-()
-801
-()
-800
-()
-799
-()
-798
-()
-797
+162
***
-1220
+293
()
-796
+139
***
-1788
-()
-795
+158
()
-794
-***
-1255
+137
***
-1674
-()
-793
+166
***
-1740
-()
-792
+201
()
-791
+136
***
-1349
-()
-790
-()
-789
-()
-788
+160
()
-787
+134
***
-1800
-()
-786
-()
-785
-()
-784
-()
-783
-()
-782
-()
-781
-()
-780
-()
-779
-()
-778
-()
-777
-()
-776
-()
-775
+221
()
-774
+132
***
-1331
-()
-773
+213
()
-772
+131
***
-1256
-()
-771
-()
-770
-()
-769
-()
-768
-()
-767
-()
-766
-()
-765
-()
-764
-()
-763
-()
-762
-()
-761
-()
-759
+187
()
-758
+129
***
-1655
-()
-757
-()
-756
+235
()
-755
+128
***
-1760
-()
-754
-()
-753
-()
-752
+153
()
-751
-***
-1285
+127
***
-1680
+156
()
-750
+126
***
-1261
-()
-749
-()
-748
-()
-747
-()
-746
-()
-745
+159
***
-1362
-()
-744
-()
-743
-()
-742
-()
-741
-()
-740
-()
-739
-()
-738
-()
-737
+218
()
-736
+125
***
-1729
+155
()
-735
+124
***
-1769
-()
-734
-()
-733
+157
()
-732
+123
***
-1715
-()
-731
-()
-730
-()
-729
-()
-728
+152
()
-727
+116
***
-1721
-()
-726
-()
-725
-()
-724
-()
-723
-()
-722
-()
-721
-()
-720
-()
-719
+135
***
-1770
-()
-718
-()
-717
-()
-716
-()
-715
-()
-714
-()
-713
-()
-712
+163
()
-711
+115
***
-1779
-()
-710
+133
***
-1221
-()
-709
-()
-708
-()
-707
-()
-706
-()
-705
+204
***
-1661
-()
-704
-()
-703
-()
-702
+248
()
-701
+114
***
-1722
-()
-700
-()
-699
-()
-698
-()
-697
-()
-696
-()
-695
-()
-694
-()
-693
-()
-692
+192
***
-1776
+212
()
-690
+113
***
-1254
+268
()
-689
+112
***
-1738
-()
-688
-()
-687
+367
()
-686
+111
***
-1287
-()
-685
-()
-684
-()
-683
-()
-682
+272
()
-681
+110
***
-1666
-()
-680
-()
-679
-()
-678
-()
-677
-()
-676
-()
-675
+434
()
-674
+109
***
-1695
+323
()
-673
+108
***
-1709
-()
-672
-()
-671
-()
-670
-()
-669
-()
-667
-()
-666
-()
-665
-()
-664
-()
-663
-()
-662
+281
()
-661
+107
***
-1730
-()
-660
-()
-659
-()
-658
-()
-657
-()
-656
-()
-655
-()
-654
-()
-653
-()
-652
-()
-651
-()
-650
-()
-649
-()
-648
-()
-647
-()
-594
-610
-622
-()
-588
-()
-584
-601
-615
+144
***
-1266
-()
-578
-590
-603
+148
()
-574
-592
-607
+106
***
-1646
-()
-568
-()
-564
-582
-598
+275
()
-558
-570
-***
-1351
+105
***
-1712
-()
-554
-572
-()
-547
-560
-580
-()
-543
-562
-()
-536
-549
-()
-533
-551
+196
***
-1356
-()
-527
-539
-()
-524
-541
-()
-518
-530
-()
-514
-531
+254
()
-508
-521
+104
***
-1657
-()
-503
-523
-()
-498
+138
***
-1383
+161
()
-493
-512
+103
***
-1422
-()
-487
-501
+310
()
-484
-515
+102
***
-1354
+223
***
-1701
-()
-481
-502
-()
-475
-490
-511
-()
-472
-504
-538
-566
-589
-613
-629
+252
()
-470
-491
-***
-1303
+80
()
-464
+70
()
-461
-494
-526
-556
-579
-605
-623
-639
+69
()
-450
-***
-1355
+68
()
-438
-483
-516
-545
-569
-596
-616
-633
+66
()
-426
-471
-506
-535
-559
-586
-608
-627
-643
-***
-1259
+64
()
-414
-459
-495
-525
-548
-576
-599
-620
-635
+62
***
-1765
-()
-402
-449
-500
+256
()
-401
-446
-482
+61
***
-1258
-()
-391
-418
-434
-455
-()
-388
-435
-469
-()
-384
-407
-429
-454
-()
-378
-406
-447
-467
+93
()
-376
-423
-457
+59
***
-1316
-()
-373
-394
-416
-442
-()
-367
-393
-410
-431
-452
-478
+120
()
-366
-413
-465
-513
-550
-585
-617
-638
+58
()
-364
-***
-1146
+57
***
-1750
+183
()
-363
-411
-445
+55
()
-359
-396
-***
-1396
-***
-1756
+54
()
-357
-381
-405
-430
-458
-479
+52
***
-1353
-()
-351
-368
+147
()
-350
-389
+51
***
-1103
-()
-349
-397
-433
-()
-344
-369
-422
-443
-()
-338
-354
-380
-398
-419
-441
-466
-()
-335
-385
-421
+118
()
-332
-355
+50
***
-1320
+83
()
-327
-375
-428
-505
-540
-575
-609
-632
+49
***
-1321
+98
()
-326
-341
+48
***
-1182
-()
-323
-372
-409
-()
-319
-342
-()
-318
-331
-343
-356
-370
-382
-395
-408
-420
-432
-444
-456
-468
-480
-492
+99
()
-312
-***
-1161
+47
()
-309
-346
-383
+46
***
-1366
+184
()
-308
+45
***
-1262
+121
()
-305
-330
+44
()
-299
-315
-***
-1333
+43
***
-1676
-()
-293
-317
+88
()
-289
-296
-334
-371
+42
***
-1158
-()
-286
-302
-329
+122
()
-281
-303
+41
***
-1219
+91
()
-280
-292
-304
-316
+40
***
-1264
-()
-275
-290
-()
-270
-291
+96
()
-265
-278
+38
***
-1184
-()
-260
-279
+100
()
-255
-268
+37
***
-1367
+149
()
-250
-269
+36
***
-1165
+74
()
-245
+35
***
-1115
+258
()
-240
-259
+34
***
-1067
+151
()
-235
-248
-***
-1199
+33
***
-1717
+85
()
-230
-249
+32
()
-225
-238
+31
***
-1197
-()
-220
-239
+94
()
-215
+30
***
-935
+97
()
-210
-229
-258
+29
***
-1193
+90
()
-205
+28
***
-988
-()
-200
-219
+89
()
-195
-***
-1166
+27
***
-1667
+92
()
-190
-209
-***
-1079
+26
***
-1249
-()
-185
-198
+72
***
-1180
-()
-131
-161
-192
-221
-252
-282
-320
+247
()
-118
-151
-182
-211
-242
-271
-306
+25
***
-1398
+86
()
-112
-127
-140
+24
***
-1148
-()
-105
-141
-172
-201
-232
-261
-294
+82
()
-103
+23
***
-1144
-()
-92
-130
-162
-191
-222
-251
-283
-321
-358
-()
-91
+87
***
-886
-()
-80
-136
-174
-216
-254
-301
-348
-404
-473
-520
-555
-591
-619
-()
-79
117
-152
-181
-212
-241
-272
-307
-345
-***
-1267
()
-78
-116
-***
-1042
+22
***
-1764
-()
-74
-87
-100
-114
-126
-()
-73
-95
-111
-128
-149
-165
-178
+76
***
-997
-()
-70
119
-166
-204
-246
-285
-339
-386
-439
-485
-532
-557
-583
-606
-625
-640
-646
-()
-66
-104
-142
-171
-202
-231
-262
-295
-333
-***
-1286
()
-62
-86
-108
-124
-139
-159
-175
-188
+21
***
-1130
+84
()
-61
-72
-88
-113
-134
-148
-160
-179
-208
-228
+20
***
-1245
-()
-57
-106
-157
-193
-236
-273
-328
-374
-427
-474
-519
-552
+78
()
-56
+19
***
-969
-()
-55
-109
-153
-197
-233
-277
-325
-377
-424
-476
-517
-553
-577
-602
-621
-637
-645
-()
-54
-110
-154
-196
-234
-276
-324
-379
-425
-477
-522
-561
-595
-624
-642
+73
()
-53
-90
-129
+18
***
-1190
+81
()
-52
+17
***
-941
+65
()
-50
-59
-75
-99
-121
-137
-150
-169
+16
***
-945
+63
***
-1706
-()
-49
-69
-85
101
-125
-145
-158
-170
-189
-218
-***
-992
-***
-1781
-()
-48
-68
-122
-163
-207
-244
-288
-336
-390
-436
-489
-529
-()
-45
-96
-143
-187
-223
-267
-310
-360
-***
-1409
-()
-41
-60
-82
-98
-115
-138
-155
-168
-180
-199
()
-39
-67
-123
-164
-206
-243
-287
-337
-392
-437
-488
-534
-571
-604
-630
-()
-36
-43
-***
-1170
-()
-26
-***
-1107
-()
-24
-40
-***
-817
-()
-20
-46
-97
-144
-186
-224
-266
-311
-365
-412
-463
-507
-542
-567
-593
-614
-631
-()
-19
-33
-***
-1185
-***
-1694
-()
-18
-44
-94
-146
-184
-226
-263
-314
-361
-415
-460
-509
-546
-573
-597
-618
-634
-644
-()
-17
-31
-65
-102
+15
***
-807
-()
-16
-34
-84
-133
-177
-213
-256
-298
-352
-400
-453
-496
+71
()
14
-37
-81
-135
-173
-217
-253
-300
-347
-403
-448
-499
-537
-563
-587
-611
-628
-641
+***
+75
()
13
-22
-42
***
-691
+322
()
12
-47
-93
-147
-183
-227
-264
-313
-362
-417
-462
-510
-544
-581
-612
-636
+***
+77
()
11
-29
***
-760
+283
()
10
-30
-63
***
-1121
+79
()
9
-35
-83
-132
-176
-214
-257
-297
-353
-399
-451
-497
***
-1304
+145
+***
+150
()
8
-25
-64
***
-828
+67
()
7
-23
-51
-89
***
-1174
+60
***
-1300
+231
()
6
-28
-71
-120
-167
-203
-247
-284
-340
-387
-440
-486
-528
-565
-600
-626
+***
+56
+***
+234
()
5
***
-668
+164
+***
+202
()
4
-32
-77
***
-1032
+53
()
3
-15
-38
-76
***
-1314
+130
+***
+185
+***
+200
()
2
-27
***
-1053
+205
()
1
-21
-58
-107
-156
-194
-237
-274
-322
***
-1151
+39
***
-1777
+95
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout
index bd861b307..448df62f5 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout
@@ -4,19 +4,15 @@ by Andreas Loebel
Copyright (c) 1998,1999 ZIB Berlin
All Rights Reserved.
-nodes : 1800
-active arcs : 8190
-simplex iterations : 6837
-flow value : 12860044181
-new implicit arcs : 300000
-active arcs : 308190
-simplex iterations : 11843
-flow value : 9360043604
-new implicit arcs : 22787
-active arcs : 330977
-simplex iterations : 11931
-flow value : 9360043512
-checksum : 798014
+nodes : 500
+active arcs : 1905
+simplex iterations : 1502
+flow value : 4990014995
+new implicit arcs : 23867
+active arcs : 25772
+simplex iterations : 2663
+flow value : 3080014995
+checksum : 68389
optimal
M5 Simulator System
@@ -25,9 +21,9 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled May 15 2007 13:02:31
-M5 started Tue May 15 14:23:47 2007
+M5 compiled Jun 21 2007 21:15:48
+M5 started Fri Jun 22 01:58:18 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic tests/run.py long/10.mcf/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 859797266500 because target called exit()
+Exiting @ tick 121920085500 because target called exit()
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
index 9beb527ea..fe99eeeb9 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
@@ -31,6 +31,7 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
@@ -44,7 +45,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@@ -69,6 +70,7 @@ mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.icache]
type=BaseCache
adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
@@ -82,7 +84,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@@ -107,6 +109,7 @@ mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
@@ -120,7 +123,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=100000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@@ -160,7 +163,7 @@ env=
euid=100
executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
gid=100
-input=/dist/m5/cpu2000/data/mcf/lgred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
output=cout
pid=100
ppid=99
@@ -174,7 +177,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
-port=system.physmem.port system.cpu.l2cache.mem_side
+port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out
index 5d5cc71c1..81e06c995 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out
@@ -26,7 +26,7 @@ block_size=64
type=LiveProcess
cmd=mcf mcf.in
executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
-input=/dist/m5/cpu2000/data/mcf/lgred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
output=cout
env=
cwd=build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing
@@ -94,7 +94,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
-prefetch_latency=10
+prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@@ -131,7 +131,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
-prefetch_latency=10
+prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@@ -168,7 +168,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
-prefetch_latency=10
+prefetch_latency=100000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt
index c95331047..56d2d33b9 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt
@@ -1,77 +1,77 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 480485 # Simulator instruction rate (inst/s)
-host_mem_usage 155316 # Number of bytes of host memory used
-host_seconds 3578.87 # Real time elapsed on the host
-host_tick_rate 745845171 # Simulator tick rate (ticks/s)
+host_inst_rate 697152 # Simulator instruction rate (inst/s)
+host_mem_usage 155896 # Number of bytes of host memory used
+host_seconds 349.77 # Real time elapsed on the host
+host_tick_rate 1027373651 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1719594534 # Number of instructions simulated
-sim_seconds 2.669285 # Number of seconds simulated
-sim_ticks 2669284585000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 607807189 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 12893.226605 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11893.226605 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 594739458 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 168485217000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.021500 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 13067731 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 155417486000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.021500 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 13067731 # number of ReadReq MSHR misses
-system.cpu.dcache.SwapReq_accesses 15448 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_avg_miss_latency 13090.909091 # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency 12090.909091 # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_hits 15437 # number of SwapReq hits
-system.cpu.dcache.SwapReq_miss_latency 144000 # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_rate 0.000712 # miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_misses 11 # number of SwapReq misses
-system.cpu.dcache.SwapReq_mshr_miss_latency 133000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_rate 0.000712 # mshr miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_mshr_misses 11 # number of SwapReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 166970997 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 12404.292450 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11404.292450 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 165264000 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 21174090000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.010223 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 1706997 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 19467093000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.010223 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 1706997 # number of WriteReq MSHR misses
+sim_insts 243840172 # Number of instructions simulated
+sim_seconds 0.359341 # Number of seconds simulated
+sim_ticks 359340764000 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 82219469 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 12000.343864 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11000.343864 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 81326673 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 10713859000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.010859 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 892796 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 9821063000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.010859 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 892796 # number of ReadReq MSHR misses
+system.cpu.dcache.SwapReq_accesses 3886 # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_avg_miss_latency 12500 # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency 11500 # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_hits 3882 # number of SwapReq hits
+system.cpu.dcache.SwapReq_miss_latency 50000 # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_rate 0.001029 # miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_misses 4 # number of SwapReq misses
+system.cpu.dcache.SwapReq_mshr_miss_latency 46000 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_rate 0.001029 # mshr miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_mshr_misses 4 # number of SwapReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 22901836 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 12623.899964 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11623.899964 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 22855133 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 589574000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.002039 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 46703 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 542871000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.002039 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 46703 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 51.440428 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 110.894471 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 774778186 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 12836.737637 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 11836.737637 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 760003458 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 189659307000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.019070 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 14774728 # number of demand (read+write) misses
+system.cpu.dcache.demand_accesses 105121305 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 12031.341172 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 11031.341172 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 104181806 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 11303433000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.008937 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 939499 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 174884579000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.019070 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 14774728 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 10363934000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.008937 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 939499 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 774778186 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 12836.737637 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 11836.737637 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 105121305 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 12031.341172 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 11031.341172 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 760003458 # number of overall hits
-system.cpu.dcache.overall_miss_latency 189659307000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.019070 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 14774728 # number of overall misses
+system.cpu.dcache.overall_hits 104181806 # number of overall hits
+system.cpu.dcache.overall_miss_latency 11303433000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.008937 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 939499 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 174884579000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.019070 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 14774728 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 10363934000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.008937 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 939499 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -83,57 +83,57 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 14770643 # number of replacements
-system.cpu.dcache.sampled_refs 14774739 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 935407 # number of replacements
+system.cpu.dcache.sampled_refs 939503 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4094.628585 # Cycle average of tags in use
-system.cpu.dcache.total_refs 760018895 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 3913237000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 4191356 # number of writebacks
-system.cpu.icache.ReadReq_accesses 1719594535 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 13991.120977 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 12991.120977 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1719593634 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 12606000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 901 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 11705000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 901 # number of ReadReq MSHR misses
+system.cpu.dcache.tagsinuse 3560.887601 # Cycle average of tags in use
+system.cpu.dcache.total_refs 104185688 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 134116230000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 94807 # number of writebacks
+system.cpu.icache.ReadReq_accesses 243840173 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 13993.174061 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 12993.174061 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 243839294 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 12300000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 879 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 11421000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 879 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 1908538.994451 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 277405.340159 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1719594535 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 13991.120977 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 12991.120977 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1719593634 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 12606000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
-system.cpu.icache.demand_misses 901 # number of demand (read+write) misses
+system.cpu.icache.demand_accesses 243840173 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 13993.174061 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 12993.174061 # average overall mshr miss latency
+system.cpu.icache.demand_hits 243839294 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 12300000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
+system.cpu.icache.demand_misses 879 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 11705000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 901 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_miss_latency 11421000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 879 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1719594535 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 13991.120977 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 12991.120977 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 243840173 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 13993.174061 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 12993.174061 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1719593634 # number of overall hits
-system.cpu.icache.overall_miss_latency 12606000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
-system.cpu.icache.overall_misses 901 # number of overall misses
+system.cpu.icache.overall_hits 243839294 # number of overall hits
+system.cpu.icache.overall_miss_latency 12300000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
+system.cpu.icache.overall_misses 879 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 11705000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 901 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_miss_latency 11421000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 879 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -145,64 +145,60 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 31 # number of replacements
-system.cpu.icache.sampled_refs 901 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 25 # number of replacements
+system.cpu.icache.sampled_refs 879 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 737.715884 # Cycle average of tags in use
-system.cpu.icache.total_refs 1719593634 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 716.200092 # Cycle average of tags in use
+system.cpu.icache.total_refs 243839294 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.l2cache.ReadReq_accesses 14775639 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 12999.785859 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 10999.785859 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 8592784 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 80375791000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.418449 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 6182855 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 68010081000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.418449 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 6182855 # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 4191356 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 4164131 # number of Writeback hits
-system.cpu.l2cache.Writeback_miss_rate 0.006496 # miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_misses 27225 # number of Writeback misses
-system.cpu.l2cache.Writeback_mshr_miss_rate 0.006496 # mshr miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_mshr_misses 27225 # number of Writeback MSHR misses
+system.cpu.l2cache.ReadReq_accesses 940381 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 924777 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 202852000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.016593 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 15604 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 171644000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.016593 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 15604 # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 94807 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 94807 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 2.063273 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 65.341195 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 14775639 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 12999.785859 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 10999.785859 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 8592784 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 80375791000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.418449 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 6182855 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 940381 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 924777 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 202852000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.016593 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 15604 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 68010081000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.418449 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 6182855 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 171644000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.016593 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 15604 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 18966995 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 12942.794779 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 10999.785859 # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses 1035188 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 12756915 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 80375791000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.327415 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 6210080 # number of overall misses
+system.cpu.l2cache.overall_hits 1019584 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 202852000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.015074 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 15604 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 68010081000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.325980 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 6182855 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 171644000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.015074 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 15604 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -214,17 +210,17 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 6150087 # number of replacements
-system.cpu.l2cache.sampled_refs 6182855 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.sampled_refs 15604 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 26129.060966 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 12756915 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 806915893000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 1069081 # number of writebacks
+system.cpu.l2cache.tagsinuse 10833.027960 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1019584 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 2669284585000 # number of cpu cycles simulated
-system.cpu.num_insts 1719594534 # Number of instructions executed
-system.cpu.num_refs 774793634 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 632 # Number of system calls
+system.cpu.numCycles 359340764000 # number of cpu cycles simulated
+system.cpu.num_insts 243840172 # Number of instructions executed
+system.cpu.num_refs 105125191 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 428 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out b/tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out
index 6bbb02cf0..095132477 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out
@@ -1,3092 +1,999 @@
()
-1642
-***
-1759
-()
-1641
-***
-1691
-()
-1640
-()
-1639
-()
-1638
-()
-1637
-()
-1636
-()
-1635
-()
-1634
-()
-1633
-()
-1632
-()
-1631
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-1630
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-1629
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-1628
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-1627
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-1626
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-***
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-1622
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-1688
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-1796
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-***
-1700
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-1773
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-1710
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-1748
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-***
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-1726
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-***
-1763
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-1567
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-1565
-***
-1643
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-1563
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-1562
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-1774
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-1472
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-1471
-***
-1728
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-1470
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-1469
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-1467
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-1466
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-1464
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-1463
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-1462
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-1461
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-1460
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-1782
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-***
-1732
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-1432
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-1665
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-1431
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-1426
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-1425
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-1423
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-1420
-***
-1499
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-1419
-***
-1457
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-1653
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-1418
-***
-1577
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-1664
-()
-1417
-***
-1489
-()
-1416
-***
-1545
-()
-1415
-***
-1430
-()
-1414
-***
-1434
-()
-1413
-***
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-1735
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-1412
-***
-1560
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-1724
-()
-1411
-***
-1428
-()
-1404
-***
-1496
-***
-1780
-()
-1403
-***
-1561
-()
-1402
-***
-1548
-()
-1401
-***
-1569
-***
-1792
-()
-1400
-***
-1537
-()
-1399
-***
-1429
-()
-1392
-***
-1580
-()
-1391
-***
-1410
-()
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-***
-1500
-()
-1389
-***
-1483
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()
-1388
-***
-1570
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()
-1387
-***
-1543
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()
-1386
-***
-1558
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()
-1385
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()
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()
-1382
-***
-1439
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()
-1381
-***
-1677
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()
-1380
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()
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-***
-1397
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()
-1377
-***
-1787
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()
-1376
-***
-1408
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()
-1375
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()
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()
-1373
-***
-1671
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()
-1372
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()
-1370
-***
-1793
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()
-1369
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()
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-***
-1762
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()
-1346
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()
-1345
-***
-1566
+477
()
-1344
-***
-1520
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()
-1343
-***
-1492
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()
-1342
-***
-1576
-***
-1656
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()
-1341
-***
-1447
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()
-1340
-***
-1550
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()
-1339
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()
-1338
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()
-1337
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()
-1329
-***
-1336
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()
-1328
-***
-1446
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()
-1327
-***
-1607
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()
-1325
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()
-1324
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()
-1323
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()
-1317
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()
-1315
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()
-1311
-***
-1450
-***
-1720
+459
()
-1310
-***
-1619
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()
-1309
-***
-1458
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()
-1308
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()
-1307
-***
-1427
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()
-1306
-***
-1364
-***
-1696
+452
()
-1299
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()
-1297
-***
-1395
+450
()
-1296
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()
-1295
-***
-1326
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()
-1294
-***
-1371
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()
-1293
-***
-1456
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()
-1292
-***
-1312
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()
-1291
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()
-1290
-***
-1363
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()
-1282
-***
-1592
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()
-1281
-***
-1379
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()
-1280
-***
-1478
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()
-1279
-***
-1436
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()
-1278
-***
-1620
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()
-1277
-***
-1487
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()
-1276
-***
-1288
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()
-1275
-***
-1596
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()
-1274
-***
-1322
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()
-1273
-***
-1305
-***
-1699
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()
-1272
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()
-1271
-***
-1484
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()
-1270
-***
-1518
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()
-1269
-***
-1289
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()
-1268
-***
-1443
-***
-1786
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()
-1265
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()
-1243
-***
-1368
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()
-1242
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()
-1241
-***
-1421
-***
-1749
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()
-1240
-***
-1260
-***
-1678
+407
()
-1239
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()
-1238
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()
-1236
-***
-1263
-***
-1767
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()
-1235
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()
-1234
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()
-1233
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()
-1232
-***
-1752
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()
-1231
-***
-1791
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()
-1230
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()
-1229
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()
-1228
-***
-1702
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()
-1227
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()
-1226
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()
-1225
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()
-1224
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()
-1223
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()
-1216
-***
-1531
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()
-1215
-***
-1530
-***
-1797
+386
()
-1214
-***
-1474
-***
-1742
+385
()
-1213
-***
-1488
+384
()
-1212
-***
-1298
-***
-1789
+383
()
-1211
-***
-1491
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()
-1210
-***
-1600
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()
-1209
-***
-1244
+380
()
-1208
-***
-1609
-***
-1704
+379
()
-1207
-***
-1237
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()
-1206
-***
-1468
+375
()
-1205
-***
-1547
+374
()
-1204
-***
-1246
+373
()
-1203
-***
-1593
-***
-1734
+372
()
-1202
-***
-1535
+371
()
-1200
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()
-1198
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()
-1196
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()
-1195
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()
-1194
-***
-1302
+365
()
-1192
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()
-1191
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()
-1189
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()
-1188
+360
()
-1187
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()
-1186
+358
()
-1183
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()
-1181
-***
-1778
+356
()
-1179
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()
-1178
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()
-1177
-***
-1645
+352
()
-1176
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()
-1175
-***
-1318
-***
-1649
+347
()
-1173
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()
-1172
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()
-1171
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()
-1169
-***
-1654
+340
()
-1168
-***
-1692
+339
()
-1167
+338
()
-1164
+332
()
-1163
+325
()
-1162
+320
***
-1716
-()
-1160
+345
()
-1159
+319
***
-1663
-()
-1157
-()
-1156
-()
-1155
-()
-1154
-()
-1153
-()
-1152
-()
-1150
-()
-1149
-()
-1147
-()
-1145
+497
()
-1143
+318
***
-1711
-()
-1142
-()
-1141
-()
-1140
+349
()
-1139
+317
***
-1755
-()
-1138
+408
()
-1137
+316
***
-1218
+324
()
-1136
-***
-1248
+315
***
-1670
-()
-1135
-()
-1134
+328
()
-1133
+314
***
-1662
-()
-1132
-()
-1131
-()
-1129
-()
-1128
-()
-1127
+335
()
-1126
+313
***
-1301
-()
-1125
-()
-1124
-()
-1123
-()
-1122
+378
()
-1120
+312
***
-1332
+426
()
-1119
+311
***
-1737
+411
()
-1118
+304
***
-1718
+343
()
-1117
-***
-1250
+303
***
-1658
-()
-1116
-()
-1114
-()
-1113
-()
-1112
+417
()
-1111
+302
***
-1772
+485
()
-1110
+301
***
-1359
-()
-1109
+363
()
-1108
+300
***
-1251
-()
-1106
+376
()
-1105
+299
***
-1771
-()
-1104
-()
-1102
-()
-1101
-()
-1100
+333
()
-1099
+292
***
-1689
-()
-1098
+337
()
-1097
+291
***
-1785
+409
()
-1096
+290
***
-1685
-()
-1095
-()
-1094
-()
-1093
-()
-1092
-()
-1091
-()
-1090
-()
-1089
-()
-1088
-()
-1087
-()
-1086
-()
-1085
+421
()
-1084
+289
***
-1739
+437
()
-1083
+288
***
-1405
-()
-1082
-()
-1081
-()
-1080
-()
-1078
-()
-1077
-()
-1076
-()
-1075
-()
-1074
-()
-1073
-()
-1072
-()
-1071
+430
()
-1070
+287
***
-1707
+348
()
-1069
+286
***
-1334
-()
-1068
-()
-1066
-()
-1065
-()
-1064
-()
-1063
-()
-1062
-()
-1061
-()
-1060
-()
-1059
+326
()
-1058
+284
()
-1057
+282
***
-1744
-()
-1056
-()
-1055
+308
()
-1054
+279
***
-1335
-()
-1052
+297
***
-1660
-()
-1051
-()
-1050
-()
-1049
-()
-1048
-()
-1047
+305
()
-1046
+278
()
-1045
+277
***
-1357
+307
()
-1044
+276
***
-1659
-()
-1043
-()
-1041
-()
-1040
-()
-1039
-()
-1038
-()
-1037
+296
()
-1036
+273
()
-1035
+271
()
-1034
+265
()
-1033
+246
***
-1690
-()
-1031
-()
-1030
-()
-1029
+267
()
-1028
+245
***
-1675
-()
-1027
-()
-1026
+280
()
-1025
+244
***
-1257
-()
-1024
-()
-1023
-()
-1022
-()
-1021
-()
-1020
+391
()
-1019
+243
***
-1284
-()
-1018
+330
()
-1017
+242
***
-1754
-()
-1016
+456
()
-1015
+241
***
-1247
-()
-1014
-()
-1013
+346
()
-1012
+240
***
-1319
+483
()
-1011
-***
-1352
+239
***
-1651
-()
-1010
+260
()
-1009
+238
***
-1705
-()
-1008
-()
-1007
-()
-1006
+261
()
-1005
+237
***
-1679
-()
-1004
-()
-1003
-()
-1002
-()
-1001
-()
-1000
+262
***
-1731
-()
-999
-()
-998
-()
-996
-()
-995
-()
-994
-()
-993
+294
()
-991
+236
***
-1799
-()
-990
-()
-989
-()
-987
-()
-986
-()
-985
-()
-984
+253
()
-983
+229
***
-1745
-()
-982
+397
()
-981
+228
***
-1644
-()
-980
-()
-979
-()
-978
-()
-977
-()
-976
-()
-975
+298
()
-974
+227
***
-1222
-()
-973
-()
-972
-()
-971
-()
-970
-()
-968
-()
-967
-()
-966
+415
()
-965
+226
***
-1347
-()
-964
-()
-963
+264
()
-962
+224
***
-1743
+232
()
-961
+222
***
-1719
+233
()
-960
+217
***
-1758
-()
-959
+250
()
-958
+211
***
-1733
+331
()
-957
+210
***
-1775
-()
-956
-()
-955
-()
-954
-()
-953
+394
()
-952
+209
***
-1393
-()
-951
-()
-950
+410
()
-949
+208
***
-1669
-()
-948
-()
-947
+321
()
-946
+207
***
-1681
+327
()
-944
+206
***
-1686
-()
-943
-()
-942
+309
()
-940
+199
***
-1783
-()
-939
-()
-938
-()
-937
-()
-936
-()
-934
-()
-933
-()
-932
-()
-931
-()
-930
+259
()
-929
+198
***
-1713
+219
()
-928
+197
***
-1725
-()
-927
-()
-926
-()
-925
-()
-924
-()
-923
-()
-922
+220
()
-921
+195
***
-1394
+429
()
-920
+194
***
-1741
+470
()
-919
+193
***
-1708
-()
-918
-()
-917
+274
()
-916
+191
***
-1723
-()
-915
-()
-914
-()
-913
-()
-912
-()
-911
-()
-910
+203
()
-909
+190
***
-1795
-()
-908
-()
-907
-()
-906
-()
-905
-()
-904
+263
()
-903
+189
+215
***
-1330
-()
-902
-()
-901
-()
-900
-()
-899
-()
-898
+230
()
-897
+188
***
-1790
-()
-896
+266
***
-1652
+295
()
-895
+182
***
-1761
-()
-894
-()
-893
-()
-892
-()
-891
+329
()
-890
+181
***
-1253
+351
()
-889
+180
***
-1698
-()
-888
-()
-887
-()
-885
+441
()
-884
+179
***
-1703
-()
-883
-()
-882
+453
()
-881
+178
***
-1747
-()
-880
+418
()
-879
+177
***
-1647
+353
()
-878
+176
***
-1358
+422
()
-877
+175
***
-1407
-()
-876
-()
-875
-()
-874
+225
***
-1283
+255
()
-873
+174
***
-1682
-()
-872
-()
-871
-()
-870
-()
-869
-()
-868
+269
()
-867
+173
***
-1751
-()
-866
-()
-865
-()
-864
-()
-863
+214
()
-862
+172
***
-1753
-()
-861
-()
-860
-()
-859
+186
()
-858
+171
***
-1348
-()
-857
+447
()
-856
+170
***
-1350
-()
-855
+270
***
-1252
-()
-854
+306
()
-853
+169
***
-1201
-()
-852
-()
-851
+336
()
-850
+168
***
-1361
-()
-849
-()
-848
-()
-847
-()
-846
-()
-845
-()
-844
-()
-843
-()
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***
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***
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***
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***
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***
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***
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***
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***
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***
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***
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***
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diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout
index 272fc2ce1..51a3ec215 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout
@@ -4,19 +4,15 @@ by Andreas Loebel
Copyright (c) 1998,1999 ZIB Berlin
All Rights Reserved.
-nodes : 1800
-active arcs : 8190
-simplex iterations : 6837
-flow value : 12860044181
-new implicit arcs : 300000
-active arcs : 308190
-simplex iterations : 11843
-flow value : 9360043604
-new implicit arcs : 22787
-active arcs : 330977
-simplex iterations : 11931
-flow value : 9360043512
-checksum : 798014
+nodes : 500
+active arcs : 1905
+simplex iterations : 1502
+flow value : 4990014995
+new implicit arcs : 23867
+active arcs : 25772
+simplex iterations : 2663
+flow value : 3080014995
+checksum : 68389
optimal
M5 Simulator System
@@ -25,9 +21,9 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled May 15 2007 13:02:31
-M5 started Tue May 15 15:05:32 2007
+M5 compiled Jun 21 2007 21:15:48
+M5 started Fri Jun 22 02:01:52 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing tests/run.py long/10.mcf/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 2669284585000 because target called exit()
+Exiting @ tick 359340764000 because target called exit()