diff options
Diffstat (limited to 'tests/long')
11 files changed, 2052 insertions, 2049 deletions
diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout index 8176c7e05..ffb5e6ddd 100755 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout @@ -3,10 +3,11 @@ Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing/si gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 20 2011 13:24:14 -gem5 started Aug 20 2011 13:24:28 -gem5 executing on zizzer +gem5 compiled Nov 16 2011 11:08:03 +gem5 started Nov 17 2011 13:09:16 +gem5 executing on ribera.cs.wisc.edu command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing +tests Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -1064,4 +1065,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 586755503000 because target called exit() +Exiting @ tick 586294224000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt index 5610b27f8..db687aea5 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,144 +1,144 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.586756 # Number of seconds simulated -sim_ticks 586755503000 # Number of ticks simulated +sim_seconds 0.586294 # Number of seconds simulated +sim_ticks 586294224000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 143909 # Simulator instruction rate (inst/s) -host_tick_rate 52074943 # Simulator tick rate (ticks/s) -host_mem_usage 212036 # Number of bytes of host memory used -host_seconds 11267.52 # Real time elapsed on the host +host_inst_rate 112274 # Simulator instruction rate (inst/s) +host_tick_rate 40595683 # Simulator tick rate (ticks/s) +host_mem_usage 244844 # Number of bytes of host memory used +host_seconds 14442.28 # Real time elapsed on the host sim_insts 1621493982 # Number of instructions simulated system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1173511007 # number of cpu cycles simulated +system.cpu.numCycles 1172588449 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 142841694 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 142841694 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 7891104 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 135940863 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 135060067 # Number of BTB hits +system.cpu.BPredUnit.lookups 142448983 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 142448983 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 7804844 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 134509889 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 133615988 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 143543484 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1144373207 # Number of instructions fetch has processed -system.cpu.fetch.Branches 142841694 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 135060067 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 330625683 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 57747911 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 649508878 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 57 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 359 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 137309352 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 979465 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1173333177 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.784853 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.106580 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 143149229 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1143761055 # Number of instructions fetch has processed +system.cpu.fetch.Branches 142448983 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 133615988 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 330199440 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 57554993 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 649541012 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 52 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 331 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 137027209 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 996742 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1172439660 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.784546 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.109877 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 845712931 72.08% 72.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 16031093 1.37% 73.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 18099843 1.54% 74.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 17610691 1.50% 76.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 23355712 1.99% 78.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 16618957 1.42% 79.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 23183901 1.98% 81.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28217498 2.40% 84.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 184502551 15.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 845244296 72.09% 72.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 17110181 1.46% 73.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 18043141 1.54% 75.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 16408368 1.40% 76.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 23340182 1.99% 78.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 16629602 1.42% 79.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 21855680 1.86% 81.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28257046 2.41% 84.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 185551164 15.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1173333177 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.121722 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.975170 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 241132491 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 558355752 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 229474776 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 94715442 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 49654716 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2072768748 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 49654716 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 290885704 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 132416469 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 3327 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 257077103 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 443295858 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2043085659 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 2266 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 278274210 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 129493006 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2031275937 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4957669219 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4957665711 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3508 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1172439660 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.121483 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.975416 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 240695556 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 558473143 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 228947071 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 94774294 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 49549596 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2070409567 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 49549596 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 290323713 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 132525789 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 3175 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 256725592 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 443311795 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2043122328 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2634 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 278313629 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 129499394 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2031527324 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4954653616 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4954649396 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4220 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1617994650 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 413281287 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 97 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 97 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 792932011 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 519352258 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 227004848 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 355033834 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 148905529 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1987362019 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 91 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1782207350 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 181989 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 365718291 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 672335048 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1173333177 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.518927 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.333963 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 413532674 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 91 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 91 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 793190427 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 519090632 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 226808407 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 354951645 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 148937435 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1986583518 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 216 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1781630005 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 180825 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 364939190 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 670712331 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 166 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1172439660 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.519592 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.333662 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 272616502 23.23% 23.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 416904584 35.53% 58.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 234897308 20.02% 78.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 156871571 13.37% 92.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 54320414 4.63% 96.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 21136145 1.80% 98.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 14479536 1.23% 99.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1803096 0.15% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 304021 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 271921708 23.19% 23.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 416937500 35.56% 58.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 234725234 20.02% 78.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 156776493 13.37% 92.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 54385701 4.64% 96.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 21203892 1.81% 98.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 14378982 1.23% 99.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1804798 0.15% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 305352 0.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1173333177 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1172439660 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 181055 7.04% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2242910 87.15% 94.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 149595 5.81% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 179772 6.92% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2269895 87.35% 94.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 148998 5.73% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 26996432 1.51% 1.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1102299326 61.85% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 26894248 1.51% 1.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1102052870 61.86% 63.37% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 63.37% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 63.37% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 63.37% # Type of FU issued @@ -167,85 +167,85 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 63.37% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 63.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 458202367 25.71% 89.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 194709225 10.93% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 457985397 25.71% 89.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 194697490 10.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1782207350 # Type of FU issued -system.cpu.iq.rate 1.518697 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2573560 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001444 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4740503284 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2353289601 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1760306484 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 142 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 608 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 36 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1757784406 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 72 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 205673181 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1781630005 # Type of FU issued +system.cpu.iq.rate 1.519399 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2598665 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001459 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4738479065 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2351732069 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1760053766 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 95 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 542 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1757334382 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 40 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 205665909 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 100310133 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 59834 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 216613 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 38818791 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 100048507 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 60622 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 216417 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 38622350 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1385 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 35852 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 849 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 34395 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 49654716 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1300952 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 134624 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1987362110 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 591185 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 519352258 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 227004848 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 91 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 65366 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 32 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 216613 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4590434 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3486470 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8076904 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1768811104 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 452331737 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 13396246 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 49549596 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1308890 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 133908 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1986583734 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 659432 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 519090632 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 226808407 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 86 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 64911 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 28 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 216417 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4603219 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3388875 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7992094 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1768232809 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 452047218 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 13397196 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 646217865 # number of memory reference insts executed -system.cpu.iew.exec_branches 112172746 # Number of branches executed -system.cpu.iew.exec_stores 193886128 # Number of stores executed -system.cpu.iew.exec_rate 1.507281 # Inst execution rate -system.cpu.iew.wb_sent 1766741886 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1760306520 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1336435928 # num instructions producing a value -system.cpu.iew.wb_consumers 2002913192 # num instructions consuming a value +system.cpu.iew.exec_refs 645919458 # number of memory reference insts executed +system.cpu.iew.exec_branches 112169596 # Number of branches executed +system.cpu.iew.exec_stores 193872240 # Number of stores executed +system.cpu.iew.exec_rate 1.507974 # Inst execution rate +system.cpu.iew.wb_sent 1766226830 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1760053778 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1336567337 # num instructions producing a value +system.cpu.iew.wb_consumers 2003494286 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.500034 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.667246 # average fanout of values written-back +system.cpu.iew.wb_rate 1.500999 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.667118 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1621493982 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 365887065 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 365103312 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7891152 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1123678461 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.443023 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.662640 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7804888 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1122890064 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.444036 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.662985 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 347480674 30.92% 30.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 438655867 39.04% 69.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 94938828 8.45% 78.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 133745830 11.90% 90.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 36833685 3.28% 93.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26175862 2.33% 95.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 22548594 2.01% 97.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 8175613 0.73% 98.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 15123508 1.35% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 346724877 30.88% 30.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 438665808 39.07% 69.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 94902960 8.45% 78.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 133728922 11.91% 90.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 36854784 3.28% 93.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26115374 2.33% 95.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 22565758 2.01% 97.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8207714 0.73% 98.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 15123867 1.35% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1123678461 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1122890064 # Number of insts commited each cycle system.cpu.commit.count 1621493982 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 607228182 # Number of memory references committed @@ -255,48 +255,48 @@ system.cpu.commit.branches 107161579 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1621354492 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 15123508 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 15123867 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3095936000 # The number of ROB reads -system.cpu.rob.rob_writes 4024437562 # The number of ROB writes -system.cpu.timesIdled 44153 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 177830 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3094363491 # The number of ROB reads +system.cpu.rob.rob_writes 4022764791 # The number of ROB writes +system.cpu.timesIdled 43542 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 148789 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1621493982 # Number of Instructions Simulated system.cpu.committedInsts_total 1621493982 # Number of Instructions Simulated -system.cpu.cpi 0.723722 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.723722 # CPI: Total CPI of All Threads -system.cpu.ipc 1.381746 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.381746 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3273654764 # number of integer regfile reads -system.cpu.int_regfile_writes 1756473314 # number of integer regfile writes -system.cpu.fp_regfile_reads 36 # number of floating regfile reads -system.cpu.misc_regfile_reads 909253494 # number of misc regfile reads -system.cpu.icache.replacements 16 # number of replacements -system.cpu.icache.tagsinuse 813.268656 # Cycle average of tags in use -system.cpu.icache.total_refs 137308116 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 900 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 152564.573333 # Average number of references to valid blocks. +system.cpu.cpi 0.723153 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.723153 # CPI: Total CPI of All Threads +system.cpu.ipc 1.382833 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.382833 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3273039620 # number of integer regfile reads +system.cpu.int_regfile_writes 1756091293 # number of integer regfile writes +system.cpu.fp_regfile_reads 12 # number of floating regfile reads +system.cpu.misc_regfile_reads 908871446 # number of misc regfile reads +system.cpu.icache.replacements 12 # number of replacements +system.cpu.icache.tagsinuse 810.394392 # Cycle average of tags in use +system.cpu.icache.total_refs 137025977 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 893 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 153444.543113 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 813.268656 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.397104 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 137308116 # number of ReadReq hits -system.cpu.icache.demand_hits 137308116 # number of demand (read+write) hits -system.cpu.icache.overall_hits 137308116 # number of overall hits -system.cpu.icache.ReadReq_misses 1236 # number of ReadReq misses -system.cpu.icache.demand_misses 1236 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1236 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 43480000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 43480000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 43480000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 137309352 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 137309352 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 137309352 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 810.394392 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.395700 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 137025977 # number of ReadReq hits +system.cpu.icache.demand_hits 137025977 # number of demand (read+write) hits +system.cpu.icache.overall_hits 137025977 # number of overall hits +system.cpu.icache.ReadReq_misses 1232 # number of ReadReq misses +system.cpu.icache.demand_misses 1232 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1232 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 43328500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 43328500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 43328500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 137027209 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 137027209 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 137027209 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35177.993528 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35177.993528 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35177.993528 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 35169.237013 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35169.237013 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35169.237013 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -306,130 +306,130 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 336 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 336 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 336 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 900 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 900 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 900 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 339 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 339 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 339 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 893 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 893 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 893 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 31792500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 31792500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 31792500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 31560500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 31560500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 31560500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000007 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000007 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35325 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35325 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35325 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35342.105263 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35342.105263 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35342.105263 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 459082 # number of replacements -system.cpu.dcache.tagsinuse 4094.908409 # Cycle average of tags in use -system.cpu.dcache.total_refs 433296852 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 463178 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 935.486685 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 317735000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.908409 # Average occupied blocks per context +system.cpu.dcache.replacements 459077 # number of replacements +system.cpu.dcache.tagsinuse 4094.907333 # Cycle average of tags in use +system.cpu.dcache.total_refs 433034493 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 463173 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 934.930346 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 317767000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4094.907333 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.999733 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 246417961 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 186878891 # number of WriteReq hits -system.cpu.dcache.demand_hits 433296852 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 433296852 # number of overall hits -system.cpu.dcache.ReadReq_misses 217222 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1307166 # number of WriteReq misses -system.cpu.dcache.demand_misses 1524388 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1524388 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 2206460500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 25191688497 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 27398148997 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 27398148997 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 246635183 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits 246142702 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 186891791 # number of WriteReq hits +system.cpu.dcache.demand_hits 433034493 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 433034493 # number of overall hits +system.cpu.dcache.ReadReq_misses 217277 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1294266 # number of WriteReq misses +system.cpu.dcache.demand_misses 1511543 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1511543 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 2206130500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 25062764496 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 27268894996 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 27268894996 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 246359979 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 434821240 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 434821240 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000881 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.006946 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.003506 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.003506 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 10157.629062 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 19271.988789 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 17973.212199 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 17973.212199 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1884500 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 490158000 # number of cycles access was blocked +system.cpu.dcache.demand_accesses 434546036 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 434546036 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.000882 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.006878 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.003478 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.003478 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 10153.539031 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 19364.461785 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 18040.436161 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 18040.436161 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1883000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 482947000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 482 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 33499 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3909.751037 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 14632.018866 # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_targets 32670 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3906.639004 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 14782.583410 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 410010 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 3618 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1057590 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1061208 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1061208 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 213604 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 249576 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 463180 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 463180 # number of overall MSHR misses +system.cpu.dcache.writebacks 410037 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 3648 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1044720 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1048368 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1048368 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 213629 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 249546 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 463175 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 463175 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1533784000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2518332500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4052116500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4052116500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1533480500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2506697000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4040177500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4040177500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000866 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000867 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.001326 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.001065 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.001065 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7180.502238 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10090.443392 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 8748.470357 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 8748.470357 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.001066 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.001066 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7178.241250 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10045.029774 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 8722.788363 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 8722.788363 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 73626 # number of replacements -system.cpu.l2cache.tagsinuse 17961.057219 # Cycle average of tags in use -system.cpu.l2cache.total_refs 452680 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 89247 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.072215 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 73618 # number of replacements +system.cpu.l2cache.tagsinuse 17964.500601 # Cycle average of tags in use +system.cpu.l2cache.total_refs 452679 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 89237 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.072773 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1976.377276 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15984.679942 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.060314 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.487814 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 181326 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 410010 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 190857 # number of ReadExReq hits +system.cpu.l2cache.occ_blocks::0 1976.098849 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15988.401752 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.060306 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.487927 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 181359 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 410037 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 190824 # number of ReadExReq hits system.cpu.l2cache.demand_hits 372183 # number of demand (read+write) hits system.cpu.l2cache.overall_hits 372183 # number of overall hits -system.cpu.l2cache.ReadReq_misses 33178 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 58719 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 91897 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 91897 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1131489500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2019003500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3150493000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3150493000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 214504 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 410010 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 249576 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 464080 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 464080 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.154673 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.235275 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.198020 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.198020 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34103.607812 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34384.160153 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34282.871040 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34282.871040 # average overall miss latency +system.cpu.l2cache.ReadReq_misses 33163 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 58722 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 91885 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 91885 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1130840000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2017374000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3148214000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3148214000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 214522 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 410037 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 249546 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 464068 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 464068 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.154590 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.235315 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.197999 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.197999 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34099.448180 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34354.654133 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34262.545573 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34262.545573 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 202000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 122 # number of cycles access was blocked @@ -438,27 +438,27 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 1655.737705 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 58507 # number of writebacks +system.cpu.l2cache.writebacks 58503 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 33178 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 58719 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 91897 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 91897 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 33163 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 58722 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 91885 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 91885 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1028691000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1828336500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2857027500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2857027500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1028236500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1828595500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2856832000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2856832000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.154673 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235275 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.198020 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.198020 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.214299 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31137.051040 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31089.453410 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31089.453410 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.154590 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235315 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.197999 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.197999 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.533275 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31139.870917 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31091.385972 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31091.385972 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index 96389038f..b4c2d7806 100755 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -3,13 +3,14 @@ Redirecting stderr to build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 20 2011 15:40:58 -gem5 started Aug 20 2011 15:42:13 -gem5 executing on zizzer +gem5 compiled Nov 17 2011 18:36:33 +gem5 started Nov 17 2011 18:37:39 +gem5 executing on ribera.cs.wisc.edu command line: build/X86_FS/gem5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing +tests warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5147601271500 because m5_exit instruction encountered +Exiting @ tick 5145286546500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index e13689c4a..4f78f7da1 100644 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,97 +1,97 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.147601 # Number of seconds simulated -sim_ticks 5147601271500 # Number of ticks simulated +sim_seconds 5.145287 # Number of seconds simulated +sim_ticks 5145286546500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 290249 # Simulator instruction rate (inst/s) -host_tick_rate 1780077210 # Simulator tick rate (ticks/s) -host_mem_usage 361700 # Number of bytes of host memory used -host_seconds 2891.79 # Real time elapsed on the host -sim_insts 839336586 # Number of instructions simulated -system.l2c.replacements 169225 # number of replacements -system.l2c.tagsinuse 38391.632338 # Cycle average of tags in use -system.l2c.total_refs 3787611 # Total number of references to valid blocks. -system.l2c.sampled_refs 204461 # Sample count of references to valid blocks. -system.l2c.avg_refs 18.524858 # Average number of references to valid blocks. +host_inst_rate 252508 # Simulator instruction rate (inst/s) +host_tick_rate 1546872935 # Simulator tick rate (ticks/s) +host_mem_usage 390244 # Number of bytes of host memory used +host_seconds 3326.25 # Real time elapsed on the host +sim_insts 839904894 # Number of instructions simulated +system.l2c.replacements 171120 # number of replacements +system.l2c.tagsinuse 38411.926866 # Cycle average of tags in use +system.l2c.total_refs 3818646 # Total number of references to valid blocks. +system.l2c.sampled_refs 206013 # Sample count of references to valid blocks. +system.l2c.avg_refs 18.535947 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 12004.760540 # Average occupied blocks per context -system.l2c.occ_blocks::1 26386.871797 # Average occupied blocks per context -system.l2c.occ_percent::0 0.183178 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.402632 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 2307522 # number of ReadReq hits -system.l2c.ReadReq_hits::1 137003 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2444525 # number of ReadReq hits -system.l2c.Writeback_hits::0 1590016 # number of Writeback hits -system.l2c.Writeback_hits::total 1590016 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 326 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 326 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::0 147596 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 147596 # number of ReadExReq hits -system.l2c.demand_hits::0 2455118 # number of demand (read+write) hits -system.l2c.demand_hits::1 137003 # number of demand (read+write) hits -system.l2c.demand_hits::total 2592121 # number of demand (read+write) hits -system.l2c.overall_hits::0 2455118 # number of overall hits -system.l2c.overall_hits::1 137003 # number of overall hits -system.l2c.overall_hits::total 2592121 # number of overall hits -system.l2c.ReadReq_misses::0 66466 # number of ReadReq misses -system.l2c.ReadReq_misses::1 86 # number of ReadReq misses -system.l2c.ReadReq_misses::total 66552 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 3784 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3784 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 142440 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 142440 # number of ReadExReq misses -system.l2c.demand_misses::0 208906 # number of demand (read+write) misses -system.l2c.demand_misses::1 86 # number of demand (read+write) misses -system.l2c.demand_misses::total 208992 # number of demand (read+write) misses -system.l2c.overall_misses::0 208906 # number of overall misses -system.l2c.overall_misses::1 86 # number of overall misses -system.l2c.overall_misses::total 208992 # number of overall misses -system.l2c.ReadReq_miss_latency 3490673000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 33240000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 7454154500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 10944827500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 10944827500 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2373988 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 137089 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2511077 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 1590016 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1590016 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 4110 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4110 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 290036 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 290036 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2664024 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 137089 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2801113 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2664024 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 137089 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2801113 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.027998 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.000627 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.028625 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.920681 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.491111 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.078417 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.000627 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.079045 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.078417 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.000627 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.079045 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52518.174706 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 40589220.930233 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 40641739.104938 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 8784.355180 # average UpgradeReq miss latency +system.l2c.occ_blocks::0 11983.527500 # Average occupied blocks per context +system.l2c.occ_blocks::1 26428.399366 # Average occupied blocks per context +system.l2c.occ_percent::0 0.182854 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.403265 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 2330328 # number of ReadReq hits +system.l2c.ReadReq_hits::1 145914 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2476242 # number of ReadReq hits +system.l2c.Writeback_hits::0 1599020 # number of Writeback hits +system.l2c.Writeback_hits::total 1599020 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 343 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 343 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::0 150210 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 150210 # number of ReadExReq hits +system.l2c.demand_hits::0 2480538 # number of demand (read+write) hits +system.l2c.demand_hits::1 145914 # number of demand (read+write) hits +system.l2c.demand_hits::total 2626452 # number of demand (read+write) hits +system.l2c.overall_hits::0 2480538 # number of overall hits +system.l2c.overall_hits::1 145914 # number of overall hits +system.l2c.overall_hits::total 2626452 # number of overall hits +system.l2c.ReadReq_misses::0 68080 # number of ReadReq misses +system.l2c.ReadReq_misses::1 84 # number of ReadReq misses +system.l2c.ReadReq_misses::total 68164 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 3905 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3905 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::0 142426 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 142426 # number of ReadExReq misses +system.l2c.demand_misses::0 210506 # number of demand (read+write) misses +system.l2c.demand_misses::1 84 # number of demand (read+write) misses +system.l2c.demand_misses::total 210590 # number of demand (read+write) misses +system.l2c.overall_misses::0 210506 # number of overall misses +system.l2c.overall_misses::1 84 # number of overall misses +system.l2c.overall_misses::total 210590 # number of overall misses +system.l2c.ReadReq_miss_latency 3574844000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 37228000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 7453066500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 11027910500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 11027910500 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 2398408 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 145998 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2544406 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 1599020 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1599020 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 4248 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 4248 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 292636 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 292636 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 2691044 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 145998 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2837042 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 2691044 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 145998 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2837042 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.028385 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.000575 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.028961 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.919256 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.486700 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.078225 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.000575 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.078800 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.078225 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.000575 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.078800 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 52509.459459 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 42557666.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 42610176.126126 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 9533.418694 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52331.890621 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 52329.395616 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52391.159182 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 127265436.046512 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 127317827.205693 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52391.159182 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 127265436.046512 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 127317827.205693 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 52387.630281 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 131284648.809524 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 131337036.439805 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 52387.630281 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 131284648.809524 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 131337036.439805 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -100,88 +100,88 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 142484 # number of writebacks +system.l2c.writebacks 142550 # number of writebacks system.l2c.ReadReq_mshr_hits 2 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits 2 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits 2 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 66550 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 3784 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 142440 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 208990 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 208990 # number of overall MSHR misses +system.l2c.ReadReq_mshr_misses 68162 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 3905 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 142426 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 210588 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 210588 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 2679045000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 151709500 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5718096500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 8397141500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 8397141500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 61568859000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1235122000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 62803981000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.028033 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.485451 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.513484 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.920681 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_latency 2743592500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 156565000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 5717024500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 8460617000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 8460617000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 61532546500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 1222452000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 62754998500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.028420 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.466869 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.495289 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 0.919256 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.491111 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.486700 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.078449 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.524484 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 1.602933 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.078449 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.524484 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 1.602933 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40256.123216 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40092.362579 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40143.895675 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40179.632997 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40179.632997 # average overall mshr miss latency +system.l2c.demand_mshr_miss_rate::0 0.078255 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.442403 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 1.520658 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.078255 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.442403 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 1.520658 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency 40251.056307 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40093.469910 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40140.314971 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40176.159135 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40176.159135 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47520 # number of replacements -system.iocache.tagsinuse 0.153992 # Cycle average of tags in use +system.iocache.replacements 47572 # number of replacements +system.iocache.tagsinuse 0.146650 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47536 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47588 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4994510016000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 0.153992 # Average occupied blocks per context -system.iocache.occ_percent::1 0.009624 # Average percentage of cache occupancy +system.iocache.warmup_cycle 4994510051000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 0.146650 # Average occupied blocks per context +system.iocache.occ_percent::1 0.009166 # Average percentage of cache occupancy system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.ReadReq_misses::1 870 # number of ReadReq misses -system.iocache.ReadReq_misses::total 870 # number of ReadReq misses -system.iocache.WriteReq_misses::1 46704 # number of WriteReq misses -system.iocache.WriteReq_misses::total 46704 # number of WriteReq misses +system.iocache.ReadReq_misses::1 907 # number of ReadReq misses +system.iocache.ReadReq_misses::total 907 # number of ReadReq misses +system.iocache.WriteReq_misses::1 46720 # number of WriteReq misses +system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 47574 # number of demand (read+write) misses -system.iocache.demand_misses::total 47574 # number of demand (read+write) misses +system.iocache.demand_misses::1 47627 # number of demand (read+write) misses +system.iocache.demand_misses::total 47627 # number of demand (read+write) misses system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 47574 # number of overall misses -system.iocache.overall_misses::total 47574 # number of overall misses -system.iocache.ReadReq_miss_latency 108834936 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency 6370051162 # number of WriteReq miss cycles -system.iocache.demand_miss_latency 6478886098 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 6478886098 # number of overall miss cycles -system.iocache.ReadReq_accesses::1 870 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 870 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::1 46704 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_accesses::total 46704 # number of WriteReq accesses(hits+misses) +system.iocache.overall_misses::1 47627 # number of overall misses +system.iocache.overall_misses::total 47627 # number of overall misses +system.iocache.ReadReq_miss_latency 113785932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency 6369912160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency 6483698092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 6483698092 # number of overall miss cycles +system.iocache.ReadReq_accesses::1 907 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses) +system.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 47574 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47574 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 47627 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47627 # number of demand (read+write) accesses system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 47574 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47574 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 47627 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47627 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses @@ -191,37 +191,37 @@ system.iocache.overall_miss_rate::0 no_value # mi system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 125097.627586 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 125453.067255 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 136391.982742 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 136342.297945 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 136185.439484 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 136134.925399 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 136185.439484 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 136134.925399 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 68653524 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 68669502 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11268 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11260 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6092.787007 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6098.534813 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 46652 # number of writebacks +system.iocache.writebacks 46667 # number of writebacks system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.ReadReq_mshr_misses 870 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses 46704 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses 47574 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 47574 # number of overall MSHR misses +system.iocache.ReadReq_mshr_misses 907 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses 46720 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses 47627 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses 47627 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.ReadReq_mshr_miss_latency 63576976 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3941129874 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 4004706850 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 4004706850 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 66598982 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3940155856 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency 4006754838 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 4006754838 # number of overall MSHR miss cycles system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses @@ -235,434 +235,434 @@ system.iocache.demand_mshr_miss_rate::total inf # system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency 73076.983908 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 84385.274794 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 84178.476689 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 84178.476689 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 73427.764057 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 84335.527740 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 84127.802255 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 84127.802255 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 29 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. -system.pc.south_bridge.ide.disks0.dma_write_bytes 2984960 # Number of bytes transfered via DMA writes. -system.pc.south_bridge.ide.disks0.dma_write_txs 811 # Number of DMA write transactions. +system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. +system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 447857914 # number of cpu cycles simulated +system.cpu.numCycles 449021643 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 90944358 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 90944358 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1226473 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 89599267 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 83628993 # Number of BTB hits +system.cpu.BPredUnit.lookups 91138491 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 91138491 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1248082 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 89857544 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 83686998 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 27835932 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 449937499 # Number of instructions fetch has processed -system.cpu.fetch.Branches 90944358 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 83628993 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 170885862 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5925894 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 181270 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 82341776 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 36741 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 58576 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 302 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9686350 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 533599 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 3672 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 285953148 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.092624 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.403694 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28288670 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 450771327 # Number of instructions fetch has processed +system.cpu.fetch.Branches 91138491 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 83686998 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 171087914 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6045536 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 191873 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 82674920 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 36392 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 54951 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 281 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9822160 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 542562 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4016 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 287044907 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.085924 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.403637 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 115559786 40.41% 40.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1486948 0.52% 40.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72839284 25.47% 66.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1399836 0.49% 66.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1849088 0.65% 67.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3956894 1.38% 68.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1519974 0.53% 69.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2050817 0.72% 70.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 85290521 29.83% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 116472661 40.58% 40.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1490084 0.52% 41.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72800190 25.36% 66.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1427390 0.50% 66.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1806479 0.63% 67.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3992507 1.39% 68.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1571582 0.55% 69.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2063795 0.72% 70.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 85420219 29.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 285953148 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.203065 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.004643 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32848686 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 78733964 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 165420335 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4337474 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4612689 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 880519790 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 603 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4612689 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37008244 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 52433742 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9987311 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 165318823 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 16592339 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 876077378 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 14259 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 11608934 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2117422 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 878323292 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1719903468 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1719903124 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 344 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 842717831 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 35605454 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 480050 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 481410 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 42986896 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19404127 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10589665 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1106439 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 977378 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 869234759 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 887302 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 865293083 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 172874 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 29947401 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 43606928 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 139213 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 285953148 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.025996 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.373161 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 287044907 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.202971 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.003897 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 33370892 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 79040686 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 165533455 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4389968 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4709906 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 881886507 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 578 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4709906 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37547254 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 52554502 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10077381 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 165462513 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 16693351 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 877383155 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 14371 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 11668719 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2142745 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 879650717 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1723132927 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1723132383 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 544 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 843287047 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 36363663 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 486686 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 487762 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 43318784 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19666821 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10717044 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1121000 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1013044 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 870450598 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 900193 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 866206507 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 178001 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 30597956 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 44655599 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 144106 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 287044907 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.017669 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.373774 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 81963860 28.66% 28.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 22232412 7.77% 36.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 13907684 4.86% 41.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 9593533 3.35% 44.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 79512028 27.81% 72.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4973941 1.74% 74.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72992433 25.53% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 625767 0.22% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 151490 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 82633676 28.79% 28.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 22379993 7.80% 36.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 14042555 4.89% 41.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 9676323 3.37% 44.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 79535811 27.71% 72.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 5032653 1.75% 74.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72954170 25.42% 99.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 636902 0.22% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 152824 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 285953148 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 287044907 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 192405 8.66% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1837790 82.69% 91.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 192432 8.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 195893 8.77% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1841396 82.43% 91.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 196729 8.81% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 296605 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 830140846 95.94% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25417132 2.94% 98.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9438500 1.09% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 302784 0.03% 0.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 830728417 95.90% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25630184 2.96% 98.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9545122 1.10% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 865293083 # Type of FU issued -system.cpu.iq.rate 1.932071 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2222627 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.002569 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2019084567 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 900079448 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 854502226 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 147 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 154 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 42 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 867219037 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 68 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1353310 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 866206507 # Type of FU issued +system.cpu.iq.rate 1.929097 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2234018 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.002579 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2022023513 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 901959019 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 855369267 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 203 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 252 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 52 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 868137651 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 90 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1362479 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4224491 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 17341 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 10951 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2251290 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4321864 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 17926 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11344 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2286443 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7817207 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 160453 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7817280 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 160300 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4612689 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 33472492 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6015693 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 870122061 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 301987 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19404127 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10589719 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 886500 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 5552993 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 26264 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 10951 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 883301 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 519788 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1403089 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 863190269 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 24933733 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2102813 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4709906 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 33528904 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6021560 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 871350791 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 302780 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19666821 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10717077 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 894230 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 5567968 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 26441 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11344 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 900317 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 526461 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1426778 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 864071451 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25139822 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2135055 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 34134363 # number of memory reference insts executed -system.cpu.iew.exec_branches 86606805 # Number of branches executed -system.cpu.iew.exec_stores 9200630 # Number of stores executed -system.cpu.iew.exec_rate 1.927375 # Inst execution rate -system.cpu.iew.wb_sent 862563162 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 854502268 # cumulative count of insts written-back -system.cpu.iew.wb_producers 670839861 # num instructions producing a value -system.cpu.iew.wb_consumers 1171063083 # num instructions consuming a value +system.cpu.iew.exec_refs 34444060 # number of memory reference insts executed +system.cpu.iew.exec_branches 86704764 # Number of branches executed +system.cpu.iew.exec_stores 9304238 # Number of stores executed +system.cpu.iew.exec_rate 1.924343 # Inst execution rate +system.cpu.iew.wb_sent 863434483 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 855369319 # cumulative count of insts written-back +system.cpu.iew.wb_producers 671433691 # num instructions producing a value +system.cpu.iew.wb_consumers 1171953644 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.907976 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.572847 # average fanout of values written-back +system.cpu.iew.wb_rate 1.904962 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.572918 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 839336586 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 30675414 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 748087 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1233611 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 281355498 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.983189 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.864496 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 839904894 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 31338704 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 756085 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1254700 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 282350978 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.974684 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.863709 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 102129547 36.30% 36.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 12394321 4.41% 40.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4610399 1.64% 42.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 76952670 27.35% 69.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4007315 1.42% 71.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1836126 0.65% 71.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1044804 0.37% 72.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71657785 25.47% 97.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6722531 2.39% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 102836465 36.42% 36.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 12523164 4.44% 40.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4697520 1.66% 42.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 76975529 27.26% 69.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4042949 1.43% 71.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1857352 0.66% 71.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1067382 0.38% 72.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71607681 25.36% 97.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6742936 2.39% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 281355498 # Number of insts commited each cycle -system.cpu.commit.count 839336586 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 282350978 # Number of insts commited each cycle +system.cpu.commit.count 839904894 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 23518062 # Number of memory references committed -system.cpu.commit.loads 15179633 # Number of loads committed -system.cpu.commit.membars 801 # Number of memory barriers committed -system.cpu.commit.branches 85448275 # Number of branches committed +system.cpu.commit.refs 23775588 # Number of memory references committed +system.cpu.commit.loads 15344954 # Number of loads committed +system.cpu.commit.membars 3541 # Number of memory barriers committed +system.cpu.commit.branches 85526796 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 767896653 # Number of committed integer instructions. +system.cpu.commit.int_insts 768518485 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6722531 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6742936 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1144564074 # The number of ROB reads -system.cpu.rob.rob_writes 1744648535 # The number of ROB writes -system.cpu.timesIdled 3067742 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 161904766 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 839336586 # Number of Instructions Simulated -system.cpu.committedInsts_total 839336586 # Number of Instructions Simulated -system.cpu.cpi 0.533586 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.533586 # CPI: Total CPI of All Threads -system.cpu.ipc 1.874114 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.874114 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1405583914 # number of integer regfile reads -system.cpu.int_regfile_writes 856547410 # number of integer regfile writes -system.cpu.fp_regfile_reads 42 # number of floating regfile reads -system.cpu.misc_regfile_reads 281786405 # number of misc regfile reads -system.cpu.misc_regfile_writes 403681 # number of misc regfile writes -system.cpu.icache.replacements 1011974 # number of replacements -system.cpu.icache.tagsinuse 510.480374 # Cycle average of tags in use -system.cpu.icache.total_refs 8606970 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1012486 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8.500829 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 54553287000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 510.480374 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.997032 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 8606970 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8606970 # number of ReadReq hits -system.cpu.icache.demand_hits::0 8606970 # number of demand (read+write) hits +system.cpu.rob.rob_reads 1146769000 # The number of ROB reads +system.cpu.rob.rob_writes 1747209492 # The number of ROB writes +system.cpu.timesIdled 3079387 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 161976736 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 839904894 # Number of Instructions Simulated +system.cpu.committedInsts_total 839904894 # Number of Instructions Simulated +system.cpu.cpi 0.534610 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.534610 # CPI: Total CPI of All Threads +system.cpu.ipc 1.870522 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.870522 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1407118516 # number of integer regfile reads +system.cpu.int_regfile_writes 857404874 # number of integer regfile writes +system.cpu.fp_regfile_reads 52 # number of floating regfile reads +system.cpu.misc_regfile_reads 282285829 # number of misc regfile reads +system.cpu.misc_regfile_writes 410057 # number of misc regfile writes +system.cpu.icache.replacements 1028866 # number of replacements +system.cpu.icache.tagsinuse 510.467349 # Cycle average of tags in use +system.cpu.icache.total_refs 8724446 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1029378 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 8.475454 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 54553290000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 510.467349 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.997007 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::0 8724446 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8724446 # number of ReadReq hits +system.cpu.icache.demand_hits::0 8724446 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8606970 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 8606970 # number of overall hits +system.cpu.icache.demand_hits::total 8724446 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 8724446 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 8606970 # number of overall hits -system.cpu.icache.ReadReq_misses::0 1079377 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1079377 # number of ReadReq misses -system.cpu.icache.demand_misses::0 1079377 # number of demand (read+write) misses +system.cpu.icache.overall_hits::total 8724446 # number of overall hits +system.cpu.icache.ReadReq_misses::0 1097711 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1097711 # number of ReadReq misses +system.cpu.icache.demand_misses::0 1097711 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1079377 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 1079377 # number of overall misses +system.cpu.icache.demand_misses::total 1097711 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 1097711 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1079377 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 16165039489 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 16165039489 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 16165039489 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 9686347 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9686347 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 9686347 # number of demand (read+write) accesses +system.cpu.icache.overall_misses::total 1097711 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 16447038991 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 16447038991 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 16447038991 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 9822157 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9822157 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 9822157 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9686347 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 9686347 # number of overall (read+write) accesses +system.cpu.icache.demand_accesses::total 9822157 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 9822157 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9686347 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.111433 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.111433 # miss rate for demand accesses +system.cpu.icache.overall_accesses::total 9822157 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.111759 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.111759 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.111433 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.111759 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14976.268245 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::0 14983.031956 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14976.268245 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::0 14983.031956 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14976.268245 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 14983.031956 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2584490 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 2545992 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 245 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 258 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 10548.938776 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 9868.186047 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 1557 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 64335 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 64335 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 64335 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1015042 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1015042 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1015042 # number of overall MSHR misses +system.cpu.icache.writebacks 1562 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 65787 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 65787 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 65787 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 1031924 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 1031924 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 1031924 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 12263411490 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 12263411490 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 12263411490 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 12476028992 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 12476028992 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 12476028992 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.104791 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.105061 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.104791 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.105061 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.104791 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.105061 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 12081.678876 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 12081.678876 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 12081.678876 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12090.065734 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12090.065734 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12090.065734 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 12307 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.013157 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 27450 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 12318 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.228446 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5128990426000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::1 6.013157 # Average occupied blocks per context -system.cpu.itb_walker_cache.occ_percent::1 0.375822 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::1 27562 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 27562 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 14158 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.014381 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 26217 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 14168 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 1.850438 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5108050090000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::1 6.014381 # Average occupied blocks per context +system.cpu.itb_walker_cache.occ_percent::1 0.375899 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::1 26573 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 26573 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::1 3 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits system.cpu.itb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::1 27565 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 27565 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::1 26576 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 26576 # number of demand (read+write) hits system.cpu.itb_walker_cache.overall_hits::0 0 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::1 27565 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 27565 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::1 13090 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 13090 # number of ReadReq misses +system.cpu.itb_walker_cache.overall_hits::1 26576 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 26576 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::1 15025 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 15025 # number of ReadReq misses system.cpu.itb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::1 13090 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 13090 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::1 15025 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 15025 # number of demand (read+write) misses system.cpu.itb_walker_cache.overall_misses::0 0 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::1 13090 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 13090 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency 170458000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency 170458000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency 170458000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::1 40652 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 40652 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.overall_misses::1 15025 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 15025 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency 189764500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency 189764500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency 189764500 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::1 41598 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 41598 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::1 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::1 40655 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 40655 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::1 41601 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 41601 # number of demand (read+write) accesses system.cpu.itb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::1 40655 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 40655 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.322001 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.overall_accesses::1 41601 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 41601 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.361195 # miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::1 0.321978 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::1 0.361169 # miss rate for demand accesses system.cpu.itb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu.itb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::1 0.321978 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::1 0.361169 # miss rate for overall accesses system.cpu.itb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 13022.001528 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 12629.916805 # average ReadReq miss latency system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu.itb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::1 13022.001528 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::1 12629.916805 # average overall miss latency system.cpu.itb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu.itb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::1 13022.001528 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::1 12629.916805 # average overall miss latency system.cpu.itb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -672,83 +672,83 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks 2568 # number of writebacks +system.cpu.itb_walker_cache.writebacks 2705 # number of writebacks system.cpu.itb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.itb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.itb_walker_cache.ReadReq_mshr_misses 13090 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses 13090 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses 13090 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses 15025 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses 15025 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses 15025 # number of overall MSHR misses system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency 130828500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency 130828500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency 130828500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency 144320000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency 144320000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency 144320000 # number of overall MSHR miss cycles system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1 0.322001 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1 0.361195 # mshr miss rate for ReadReq accesses system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0.321978 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0.361169 # mshr miss rate for demand accesses system.cpu.itb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu.itb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0.321978 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0.361169 # mshr miss rate for overall accesses system.cpu.itb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency 9994.537815 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency 9994.537815 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency 9994.537815 # average overall mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency 9605.324459 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency 9605.324459 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency 9605.324459 # average overall mshr miss latency system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.itb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.itb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 134574 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 13.858456 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 145276 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 134589 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.079405 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5098934716000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::1 13.858456 # Average occupied blocks per context -system.cpu.dtb_walker_cache.occ_percent::1 0.866154 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::1 145328 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 145328 # number of ReadReq hits +system.cpu.dtb_walker_cache.replacements 144708 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 13.855241 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 146935 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 144723 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.015284 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5098934458000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::1 13.855241 # Average occupied blocks per context +system.cpu.dtb_walker_cache.occ_percent::1 0.865953 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::1 147187 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 147187 # number of ReadReq hits system.cpu.dtb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::1 145328 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 145328 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::1 147187 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 147187 # number of demand (read+write) hits system.cpu.dtb_walker_cache.overall_hits::0 0 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::1 145328 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 145328 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::1 135405 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 135405 # number of ReadReq misses +system.cpu.dtb_walker_cache.overall_hits::1 147187 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 147187 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::1 145638 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 145638 # number of ReadReq misses system.cpu.dtb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::1 135405 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 135405 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::1 145638 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 145638 # number of demand (read+write) misses system.cpu.dtb_walker_cache.overall_misses::0 0 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::1 135405 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 135405 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency 1884318500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency 1884318500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency 1884318500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::1 280733 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 280733 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.overall_misses::1 145638 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 145638 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency 2011660500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency 2011660500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency 2011660500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::1 292825 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 292825 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::1 280733 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 280733 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::1 292825 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 292825 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::1 280733 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 280733 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.482327 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.overall_accesses::1 292825 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 292825 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.497355 # miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::1 0.482327 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::1 0.497355 # miss rate for demand accesses system.cpu.dtb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu.dtb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::1 0.482327 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::1 0.497355 # miss rate for overall accesses system.cpu.dtb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 13916.166316 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 13812.744613 # average ReadReq miss latency system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu.dtb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 13916.166316 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 13812.744613 # average overall miss latency system.cpu.dtb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu.dtb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 13916.166316 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 13812.744613 # average overall miss latency system.cpu.dtb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -758,136 +758,136 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks 43317 # number of writebacks +system.cpu.dtb_walker_cache.writebacks 46772 # number of writebacks system.cpu.dtb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dtb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dtb_walker_cache.ReadReq_mshr_misses 135405 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses 135405 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses 135405 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses 145638 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses 145638 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses 145638 # number of overall MSHR misses system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency 1474266000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency 1474266000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency 1474266000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency 1570780000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency 1570780000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency 1570780000 # number of overall MSHR miss cycles system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1 0.482327 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1 0.497355 # mshr miss rate for ReadReq accesses system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0.482327 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0.497355 # mshr miss rate for demand accesses system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0.482327 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0.497355 # mshr miss rate for overall accesses system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 10887.825413 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 10887.825413 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 10887.825413 # average overall mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 10785.509276 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 10785.509276 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 10785.509276 # average overall mshr miss latency system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dtb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1651577 # number of replacements -system.cpu.dcache.tagsinuse 511.998478 # Cycle average of tags in use -system.cpu.dcache.total_refs 17702284 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1652089 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 10.715091 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1661747 # number of replacements +system.cpu.dcache.tagsinuse 511.998367 # Cycle average of tags in use +system.cpu.dcache.total_refs 17960054 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1662259 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 10.804606 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 13135000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.998478 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 511.998367 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.999997 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 11207304 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11207304 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 6473053 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6473053 # number of WriteReq hits -system.cpu.dcache.demand_hits::0 17680357 # number of demand (read+write) hits +system.cpu.dcache.ReadReq_hits::0 11390626 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11390626 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 6547450 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6547450 # number of WriteReq hits +system.cpu.dcache.demand_hits::0 17938076 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 17680357 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 17680357 # number of overall hits +system.cpu.dcache.demand_hits::total 17938076 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 17938076 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 17680357 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 2476228 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2476228 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 1855910 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1855910 # number of WriteReq misses -system.cpu.dcache.demand_misses::0 4332138 # number of demand (read+write) misses +system.cpu.dcache.overall_hits::total 17938076 # number of overall hits +system.cpu.dcache.ReadReq_misses::0 2490346 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2490346 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::0 1873884 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1873884 # number of WriteReq misses +system.cpu.dcache.demand_misses::0 4364230 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4332138 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 4332138 # number of overall misses +system.cpu.dcache.demand_misses::total 4364230 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::0 4364230 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 4332138 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 37330141500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 63200421145 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 100530562645 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 100530562645 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 13683532 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13683532 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 8328963 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8328963 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 22012495 # number of demand (read+write) accesses +system.cpu.dcache.overall_misses::total 4364230 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 37598789500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 63471421475 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 101070210975 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 101070210975 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::0 13880972 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13880972 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 8421334 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8421334 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 22302306 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 22012495 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 22012495 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::total 22302306 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 22302306 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 22012495 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.180964 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.222826 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::0 0.196804 # miss rate for demand accesses +system.cpu.dcache.overall_accesses::total 22302306 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.179407 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.222516 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::0 0.195685 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.196804 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.195685 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 15075.405617 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::0 15097.817532 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 34053.602354 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 33871.585154 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 23205.761831 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::0 23158.772790 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 23205.761831 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 23158.772790 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1081837152 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 5932000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 72874 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 266 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 14845.310426 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 22300.751880 # average number of cycles each access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 1083244649 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 6672500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 73213 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 391 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14795.796498 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 17065.217391 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1542574 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1113618 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1561886 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 2675504 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 2675504 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1362610 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 294024 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1656634 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1656634 # number of overall MSHR misses +system.cpu.dcache.writebacks 1547981 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 1120147 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1577106 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 2697253 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 2697253 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1370199 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 296778 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1666977 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1666977 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 18053047500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 9720000152 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 27773047652 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 27773047652 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 86987590000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1400743000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 88388333000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.099580 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 18186929000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 9757421649 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 27944350649 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 27944350649 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 86947016500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1386048000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 88333064500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.098711 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.035301 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.035241 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.075259 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.074745 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.075259 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.074745 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13248.873485 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 33058.526352 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 16764.745654 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 16764.745654 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13273.202652 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32877.846906 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 16763.489028 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 16763.489028 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal index 5eb8fc418..85136ebe7 100644 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal @@ -39,7 +39,7 @@ ACPI: Core revision 20070126 ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
ACPI: Unable to load the System Description Tables
Using local APIC timer interrupts.
-result 7812515
+result 7812511
Detected 7.812 MHz APIC timer.
NET: Registered protocol family 16
PCI: Using configuration type 1
diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout index d1aeffbca..f9ce22b4b 100755 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout @@ -3,10 +3,11 @@ Redirecting stderr to build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing/sim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 20 2011 13:24:14 -gem5 started Aug 20 2011 13:24:28 -gem5 executing on zizzer +gem5 compiled Nov 16 2011 11:08:03 +gem5 started Nov 17 2011 13:09:16 +gem5 executing on ribera.cs.wisc.edu command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing +tests Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -25,4 +26,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 70374234500 because target called exit() +Exiting @ tick 70312944500 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt index f17fe7434..011648483 100644 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,251 +1,251 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.070374 # Number of seconds simulated -sim_ticks 70374234500 # Number of ticks simulated +sim_seconds 0.070313 # Number of seconds simulated +sim_ticks 70312944500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 169063 # Simulator instruction rate (inst/s) -host_tick_rate 42767879 # Simulator tick rate (ticks/s) -host_mem_usage 346452 # Number of bytes of host memory used -host_seconds 1645.49 # Real time elapsed on the host +host_inst_rate 125815 # Simulator instruction rate (inst/s) +host_tick_rate 31799589 # Simulator tick rate (ticks/s) +host_mem_usage 378944 # Number of bytes of host memory used +host_seconds 2211.13 # Real time elapsed on the host sim_insts 278192519 # Number of instructions simulated system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 140748470 # number of cpu cycles simulated +system.cpu.numCycles 140625890 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 37906853 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 37906853 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1330176 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 33468761 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 32955372 # Number of BTB hits +system.cpu.BPredUnit.lookups 37833804 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 37833804 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1322933 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 33591925 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 33081589 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 29094074 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 203757407 # Number of instructions fetch has processed -system.cpu.fetch.Branches 37906853 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 32955372 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 63225813 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 10352620 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 38317432 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 97 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 28270666 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 203655 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 139622279 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.575042 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.293353 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29087381 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 203627812 # Number of instructions fetch has processed +system.cpu.fetch.Branches 37833804 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33081589 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 63297987 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 10276298 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 38195582 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 21 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 95 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 28266291 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 204981 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 139497150 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.574262 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.291399 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 78878326 56.49% 56.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3468234 2.48% 58.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2811542 2.01% 60.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4524513 3.24% 64.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 6755323 4.84% 69.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5317016 3.81% 72.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 7687744 5.51% 78.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4301095 3.08% 81.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 25878486 18.53% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 78673130 56.40% 56.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3606277 2.59% 58.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2810090 2.01% 61.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4532102 3.25% 64.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 6824412 4.89% 69.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5279008 3.78% 72.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 7637539 5.48% 78.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4315201 3.09% 81.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 25819391 18.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 139622279 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.269323 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.447670 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 41959628 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 28656621 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 52572729 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 7448460 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 8984841 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 355072137 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 8984841 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 48879402 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4457870 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6893 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 52910993 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 24382280 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 350563031 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 104227 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 20384891 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 314779048 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 862154595 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 862151489 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3106 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 139497150 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.269039 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.448011 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 41917744 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 28560060 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 52643719 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 7459543 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 8916084 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 354657218 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 8916084 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 48823983 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4469241 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 6888 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 53004642 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 24276312 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 350176569 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 101342 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20289844 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 314446851 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 861231533 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 861227904 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3629 # Number of floating rename lookups system.cpu.rename.CommittedMaps 248344192 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 66434856 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 66102659 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 479 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 472 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 56483579 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 112824537 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 37669092 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 48262856 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8162457 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 343955075 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 466 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 316373550 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 98329 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 65563048 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 93813941 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 20 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 139622279 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.265925 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.753143 # Number of insts issued each cycle +system.cpu.rename.skidInsts 56104077 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 112666461 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 37647255 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 48253520 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8188094 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 343455788 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2295 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 316242386 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 89834 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 65098177 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 92870721 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1849 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 139497150 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.267017 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.750973 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 31939796 22.88% 22.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 18447556 13.21% 36.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25584563 18.32% 54.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 29944678 21.45% 75.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 18447649 13.21% 89.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 10291416 7.37% 96.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 3138355 2.25% 98.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1781100 1.28% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 47166 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 31795649 22.79% 22.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 18418675 13.20% 36.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25717845 18.44% 54.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 29872112 21.41% 75.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 18507796 13.27% 89.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 10200782 7.31% 96.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3199934 2.29% 98.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1737869 1.25% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 46488 0.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 139622279 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 139497150 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 26426 1.39% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1802884 94.84% 96.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 71697 3.77% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 25785 1.36% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1795857 94.47% 95.83% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 79349 4.17% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 16711 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 180370396 57.01% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 163 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101485830 32.08% 89.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 34500450 10.90% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 180262574 57.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 195 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101451147 32.08% 89.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 34511759 10.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 316373550 # Type of FU issued -system.cpu.iq.rate 2.247794 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1901007 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006009 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 774367858 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 409550255 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 312670753 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 857 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1937 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 344 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 318257421 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 425 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 45906074 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 316242386 # Type of FU issued +system.cpu.iq.rate 2.248821 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1900991 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006011 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 773971833 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 408587092 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 312537049 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 914 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2332 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 382 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 318126211 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 455 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 45906656 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 22045149 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 125133 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34222 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6229341 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 21887073 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 122159 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 33758 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6207504 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2799 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 15405 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2763 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 15488 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 8984841 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 901233 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 88686 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 343955541 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 25713 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 112824537 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 37669092 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 466 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1563 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 48845 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34222 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1237215 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 226162 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1463377 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 314277739 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100905928 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2095811 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 8916084 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 901068 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 88602 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 343458083 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 26305 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 112666461 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 37647255 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1597 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 48733 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 33758 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1219939 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 230098 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1450037 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 314144155 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100864248 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2098231 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 134999174 # number of memory reference insts executed -system.cpu.iew.exec_branches 31825957 # Number of branches executed -system.cpu.iew.exec_stores 34093246 # Number of stores executed -system.cpu.iew.exec_rate 2.232903 # Inst execution rate -system.cpu.iew.wb_sent 313326251 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 312671097 # cumulative count of insts written-back -system.cpu.iew.wb_producers 232527981 # num instructions producing a value -system.cpu.iew.wb_consumers 318649991 # num instructions consuming a value +system.cpu.iew.exec_refs 134973322 # number of memory reference insts executed +system.cpu.iew.exec_branches 31810521 # Number of branches executed +system.cpu.iew.exec_stores 34109074 # Number of stores executed +system.cpu.iew.exec_rate 2.233900 # Inst execution rate +system.cpu.iew.wb_sent 313190495 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 312537431 # cumulative count of insts written-back +system.cpu.iew.wb_producers 232392592 # num instructions producing a value +system.cpu.iew.wb_consumers 318468890 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.221488 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.729729 # average fanout of values written-back +system.cpu.iew.wb_rate 2.222474 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.729718 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 278192519 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 65767670 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 65270328 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1330190 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 130637438 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.129501 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.662910 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1322946 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 130581066 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.130420 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.663472 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 50443323 38.61% 38.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 24364180 18.65% 57.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 16505841 12.63% 69.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12375620 9.47% 79.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3710115 2.84% 82.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 3458000 2.65% 84.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2751645 2.11% 86.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1180245 0.90% 87.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 15848469 12.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 50414718 38.61% 38.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 24339651 18.64% 57.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 16499074 12.64% 69.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12376450 9.48% 79.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3696747 2.83% 82.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3466084 2.65% 84.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2761727 2.11% 86.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1175320 0.90% 87.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 15851295 12.14% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 130637438 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 130581066 # Number of insts commited each cycle system.cpu.commit.count 278192519 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 122219139 # Number of memory references committed @@ -255,49 +255,49 @@ system.cpu.commit.branches 29309710 # Nu system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.int_insts 278186227 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 15848469 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 15851295 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 458749158 # The number of ROB reads -system.cpu.rob.rob_writes 696922141 # The number of ROB writes -system.cpu.timesIdled 33627 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1126191 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 458192618 # The number of ROB reads +system.cpu.rob.rob_writes 695856607 # The number of ROB writes +system.cpu.timesIdled 33615 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1128740 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 278192519 # Number of Instructions Simulated system.cpu.committedInsts_total 278192519 # Number of Instructions Simulated -system.cpu.cpi 0.505939 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.505939 # CPI: Total CPI of All Threads -system.cpu.ipc 1.976523 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.976523 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 555004477 # number of integer regfile reads -system.cpu.int_regfile_writes 279973081 # number of integer regfile writes -system.cpu.fp_regfile_reads 378 # number of floating regfile reads -system.cpu.fp_regfile_writes 284 # number of floating regfile writes -system.cpu.misc_regfile_reads 201255053 # number of misc regfile reads +system.cpu.cpi 0.505498 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.505498 # CPI: Total CPI of All Threads +system.cpu.ipc 1.978245 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.978245 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 554794614 # number of integer regfile reads +system.cpu.int_regfile_writes 279836675 # number of integer regfile writes +system.cpu.fp_regfile_reads 437 # number of floating regfile reads +system.cpu.fp_regfile_writes 335 # number of floating regfile writes +system.cpu.misc_regfile_reads 201195947 # number of misc regfile reads system.cpu.icache.replacements 68 # number of replacements -system.cpu.icache.tagsinuse 824.627975 # Cycle average of tags in use -system.cpu.icache.total_refs 28269362 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1028 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 27499.379377 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 824.679926 # Cycle average of tags in use +system.cpu.icache.total_refs 28264985 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1027 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 27521.893866 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 824.627975 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.402650 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 28269362 # number of ReadReq hits -system.cpu.icache.demand_hits 28269362 # number of demand (read+write) hits -system.cpu.icache.overall_hits 28269362 # number of overall hits -system.cpu.icache.ReadReq_misses 1304 # number of ReadReq misses -system.cpu.icache.demand_misses 1304 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1304 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 47096500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 47096500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 47096500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 28270666 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 28270666 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 28270666 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 824.679926 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.402676 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 28264985 # number of ReadReq hits +system.cpu.icache.demand_hits 28264985 # number of demand (read+write) hits +system.cpu.icache.overall_hits 28264985 # number of overall hits +system.cpu.icache.ReadReq_misses 1306 # number of ReadReq misses +system.cpu.icache.demand_misses 1306 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1306 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 47073500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 47073500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 47073500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 28266291 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 28266291 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 28266291 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000046 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000046 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000046 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36116.947853 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36116.947853 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36116.947853 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 36044.027565 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 36044.027565 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 36044.027565 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -307,166 +307,166 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 275 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 275 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 275 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1029 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1029 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1029 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 278 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 278 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 278 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 1028 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 1028 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 1028 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 36215000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 36215000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 36215000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 36154500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 36154500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 36154500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000036 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000036 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000036 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35194.363460 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35194.363460 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35194.363460 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35169.747082 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35169.747082 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35169.747082 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2073072 # number of replacements -system.cpu.dcache.tagsinuse 4076.002534 # Cycle average of tags in use -system.cpu.dcache.total_refs 83850634 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2077168 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 40.367767 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 23897616000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4076.002534 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.995118 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 52653882 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 31196743 # number of WriteReq hits -system.cpu.dcache.demand_hits 83850625 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 83850625 # number of overall hits -system.cpu.dcache.ReadReq_misses 2263157 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 243008 # number of WriteReq misses -system.cpu.dcache.demand_misses 2506165 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2506165 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 14623728000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 4401886592 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 19025614592 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 19025614592 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 54917039 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 2073066 # number of replacements +system.cpu.dcache.tagsinuse 4076.005888 # Cycle average of tags in use +system.cpu.dcache.total_refs 83808707 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2077162 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 40.347699 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 23845092000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4076.005888 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.995119 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 52611944 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 31196754 # number of WriteReq hits +system.cpu.dcache.demand_hits 83808698 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 83808698 # number of overall hits +system.cpu.dcache.ReadReq_misses 2262875 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 242997 # number of WriteReq misses +system.cpu.dcache.demand_misses 2505872 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2505872 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 14629803500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 4394648436 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 19024451936 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 19024451936 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 54874819 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 86356790 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 86356790 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.041210 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses 86314570 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 86314570 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.041237 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.007729 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.029021 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.029021 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 6461.649810 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 18114.163287 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 7591.525136 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 7591.525136 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 296000 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate 0.029032 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.029032 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 6465.139922 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 18085.196262 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 7591.948805 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 7591.948805 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 289000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 93 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 92 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3182.795699 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3141.304348 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1447092 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 291450 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 137543 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 428993 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 428993 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1971707 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 105465 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2077172 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2077172 # number of overall MSHR misses +system.cpu.dcache.writebacks 1447147 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 291175 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 137531 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 428706 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 428706 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1971700 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 105466 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 2077166 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2077166 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 5599733000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1876757592 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 7476490592 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 7476490592 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 5609142000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1870309936 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 7479451936 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 7479451936 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.035903 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.035931 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.003355 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.024053 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.024053 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2840.043171 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17795.075068 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3599.360377 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3599.360377 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.024065 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.024065 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2844.825278 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17733.771414 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3600.796439 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3600.796439 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 49070 # number of replacements -system.cpu.l2cache.tagsinuse 18849.812777 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3318008 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 77081 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 43.045731 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 49057 # number of replacements +system.cpu.l2cache.tagsinuse 18859.305089 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3318010 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 77063 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 43.055811 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 6745.826593 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 12103.986183 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.205866 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.369384 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1938133 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 1447092 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 63539 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 2001672 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 2001672 # number of overall hits -system.cpu.l2cache.ReadReq_misses 34492 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::0 6747.919367 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 12111.385721 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.205930 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.369610 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 1938157 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 1447147 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 63526 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 2001683 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 2001683 # number of overall hits +system.cpu.l2cache.ReadReq_misses 34474 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses 42035 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 76527 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 76527 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1179607000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 1438839000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 2618446000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 2618446000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 1972625 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 1447092 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.demand_misses 76509 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 76509 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1179443000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 1438838000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 2618281000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 2618281000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 1972631 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 1447147 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 105574 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 2078199 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 2078199 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.017485 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses 105561 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 2078192 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 2078192 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.017476 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.398157 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.036824 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.036824 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34199.437551 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34229.546806 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34215.976061 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34215.976061 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 39000 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_miss_rate 0.398206 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.036815 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.036815 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34212.536984 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34229.523017 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34221.869323 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34221.869323 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 37500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 14 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2785.714286 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2678.571429 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 29193 # number of writebacks +system.cpu.l2cache.writebacks 29185 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 34492 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 34474 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 42035 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 76527 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 76527 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses 76509 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 76509 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1069993000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1069429500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1307215500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2377208500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2377208500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1307209000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2376638500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2376638500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017485 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017476 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.398157 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.036824 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.036824 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31021.483242 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.398206 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.036815 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.036815 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31021.334919 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31098.263352 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31063.657271 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31063.657271 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31098.108719 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31063.515403 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31063.515403 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/20.parser/ref/x86/linux/o3-timing/simout index bc2d966a5..7acfed5bd 100755 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/simout @@ -3,10 +3,11 @@ Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 20 2011 13:24:14 -gem5 started Aug 20 2011 13:24:28 -gem5 executing on zizzer +gem5 compiled Nov 16 2011 11:08:03 +gem5 started Nov 17 2011 13:09:16 +gem5 executing on ribera.cs.wisc.edu command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing +tests Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -81,4 +82,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 493847859500 because target called exit() +Exiting @ tick 494093841000 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt index d93a5470f..548cdcdb0 100644 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,149 +1,149 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.493848 # Number of seconds simulated -sim_ticks 493847859500 # Number of ticks simulated +sim_seconds 0.494094 # Number of seconds simulated +sim_ticks 494093841000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 141014 # Simulator instruction rate (inst/s) -host_tick_rate 45545926 # Simulator tick rate (ticks/s) -host_mem_usage 250808 # Number of bytes of host memory used -host_seconds 10842.85 # Real time elapsed on the host +host_inst_rate 111156 # Simulator instruction rate (inst/s) +host_tick_rate 35920075 # Simulator tick rate (ticks/s) +host_mem_usage 281020 # Number of bytes of host memory used +host_seconds 13755.37 # Real time elapsed on the host sim_insts 1528988756 # Number of instructions simulated system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 987695720 # number of cpu cycles simulated +system.cpu.numCycles 988187683 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 245701836 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 245701836 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 16595687 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 236380847 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 218346080 # Number of BTB hits +system.cpu.BPredUnit.lookups 245753731 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 245753731 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 16579058 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 236460078 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 218454939 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 205619767 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1343825400 # Number of instructions fetch has processed -system.cpu.fetch.Branches 245701836 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 218346080 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 436746169 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 120030037 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 218211728 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32810 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 394519 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 194794908 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 4074174 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 964173518 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.600326 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.317708 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 205538766 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1343537923 # Number of instructions fetch has processed +system.cpu.fetch.Branches 245753731 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 218454939 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 436709904 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 120016352 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 218837683 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33103 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 345399 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 194719765 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 4085375 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 964635983 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.598912 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.317298 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 531478687 55.12% 55.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 32400706 3.36% 58.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 38829894 4.03% 62.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 32544605 3.38% 65.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 21858974 2.27% 68.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 36433886 3.78% 71.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 49094534 5.09% 77.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 36959436 3.83% 80.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 184572796 19.14% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 531979476 55.15% 55.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 32383346 3.36% 58.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 38813168 4.02% 62.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 32534184 3.37% 65.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 21860326 2.27% 68.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 36455994 3.78% 71.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 49125826 5.09% 77.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 36953777 3.83% 80.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 184529886 19.13% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 964173518 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.248763 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.360566 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 264598468 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 174292947 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 373121057 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 48992521 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 103168525 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2446276906 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 964635983 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.248691 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.359598 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 264568111 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 174813294 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 373028079 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 49055371 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 103171128 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2446190376 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 103168525 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 301836329 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 39995204 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12425 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 383530410 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 135630625 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2393744264 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 2638 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 25354791 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 92046607 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 28 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2227310497 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5630161832 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5629928430 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 233402 # Number of floating rename lookups +system.cpu.rename.SquashCycles 103171128 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 301809231 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 40269862 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9996 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 383504038 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 135871728 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2393655047 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2663 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 25553817 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 92121641 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 4 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2227336205 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5630423595 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5630180918 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 242677 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1427299027 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 800011470 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1318 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1303 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 319166295 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 577919050 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 226606684 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 227271329 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 66051723 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2286915029 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 6159 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1922683409 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1316831 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 755416366 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1189575311 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 5606 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 964173518 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.994126 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.811461 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 800037178 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1323 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1277 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 319257105 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 577954406 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 226554784 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 227345729 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 66055755 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2286934263 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 9822 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1922478378 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1310077 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 755451043 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1190251690 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 9269 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 964635983 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.992957 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.810982 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 282941420 29.35% 29.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 159777972 16.57% 45.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 162985907 16.90% 62.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 148632114 15.42% 78.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 109327758 11.34% 89.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 60035944 6.23% 95.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 30803018 3.19% 99.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 8626659 0.89% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1042726 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 283040019 29.34% 29.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 160280005 16.62% 45.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 162996180 16.90% 62.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 148777682 15.42% 78.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 109013815 11.30% 89.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 60046720 6.22% 95.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 30822079 3.20% 99.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 8624231 0.89% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1035252 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 964173518 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 964635983 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2258663 14.74% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9960479 65.00% 79.74% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3103804 20.26% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2243375 14.67% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9951583 65.07% 79.74% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3098283 20.26% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2419995 0.13% 0.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1274972987 66.31% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2418078 0.13% 0.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1274783906 66.31% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 9 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.44% # Type of FU issued @@ -169,85 +169,85 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.44% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 463702844 24.12% 90.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 181587574 9.44% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 463737726 24.12% 90.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 181538665 9.44% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1922683409 # Type of FU issued -system.cpu.iq.rate 1.946635 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15322946 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007970 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4826174769 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3042532180 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1874952899 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5344 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 78632 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 143 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1935584605 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1755 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 158265730 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1922478378 # Type of FU issued +system.cpu.iq.rate 1.945459 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15293241 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007955 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4826191069 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3042585561 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1874784055 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4988 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 82956 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 103 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1935351994 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1547 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 158191943 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 193816890 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 368616 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 283851 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 77446847 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 193852246 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 372238 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 283888 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 77394965 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2334 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 14 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2343 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 34 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 103168525 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 9000117 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1434115 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2286921188 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1114031 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 577919050 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 226607032 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6159 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1032728 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 29962 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 283851 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 15679501 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2385329 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18064830 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1889474492 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 454765570 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 33208917 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 103171128 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 9041820 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1420232 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2286944085 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1121311 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 577954406 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 226555150 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6075 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1022506 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 29752 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 283888 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 15692203 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2347782 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18039985 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1889278448 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 454785721 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 33199930 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 629342688 # number of memory reference insts executed -system.cpu.iew.exec_branches 176743901 # Number of branches executed -system.cpu.iew.exec_stores 174577118 # Number of stores executed -system.cpu.iew.exec_rate 1.913013 # Inst execution rate -system.cpu.iew.wb_sent 1882825411 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1874953042 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1440779649 # num instructions producing a value -system.cpu.iew.wb_consumers 2134933130 # num instructions consuming a value +system.cpu.iew.exec_refs 629316980 # number of memory reference insts executed +system.cpu.iew.exec_branches 176731992 # Number of branches executed +system.cpu.iew.exec_stores 174531259 # Number of stores executed +system.cpu.iew.exec_rate 1.911862 # Inst execution rate +system.cpu.iew.wb_sent 1882655317 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1874784158 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1440755706 # num instructions producing a value +system.cpu.iew.wb_consumers 2135030641 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.898310 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.674859 # average fanout of values written-back +system.cpu.iew.wb_rate 1.897194 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.674817 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 757942908 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 757965703 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16623561 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 861004993 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.775819 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.288206 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16607079 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 861464855 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.774871 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.287572 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 338275347 39.29% 39.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 210593488 24.46% 63.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 75171542 8.73% 72.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92637359 10.76% 83.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 34049472 3.95% 87.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27973994 3.25% 90.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 16051033 1.86% 92.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 12256013 1.42% 93.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 53996745 6.27% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 338524013 39.30% 39.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 210779915 24.47% 63.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 75257513 8.74% 72.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92637954 10.75% 83.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 34058407 3.95% 87.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27966548 3.25% 90.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15953506 1.85% 92.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 12303443 1.43% 93.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 53983556 6.27% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 861004993 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 861464855 # Number of insts commited each cycle system.cpu.commit.count 1528988756 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 533262345 # Number of memory references committed @@ -257,49 +257,49 @@ system.cpu.commit.branches 149758588 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 53996745 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 53983556 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3093939912 # The number of ROB reads -system.cpu.rob.rob_writes 4677211584 # The number of ROB writes -system.cpu.timesIdled 604649 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 23522202 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3094435758 # The number of ROB reads +system.cpu.rob.rob_writes 4677260376 # The number of ROB writes +system.cpu.timesIdled 606046 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 23551700 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1528988756 # Number of Instructions Simulated system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated -system.cpu.cpi 0.645980 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.645980 # CPI: Total CPI of All Threads -system.cpu.ipc 1.548036 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.548036 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3179615221 # number of integer regfile reads -system.cpu.int_regfile_writes 1745014633 # number of integer regfile writes -system.cpu.fp_regfile_reads 160 # number of floating regfile reads -system.cpu.fp_regfile_writes 9 # number of floating regfile writes -system.cpu.misc_regfile_reads 1039384818 # number of misc regfile reads -system.cpu.icache.replacements 9994 # number of replacements -system.cpu.icache.tagsinuse 979.138170 # Cycle average of tags in use -system.cpu.icache.total_refs 194574782 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 11491 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 16932.798016 # Average number of references to valid blocks. +system.cpu.cpi 0.646301 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.646301 # CPI: Total CPI of All Threads +system.cpu.ipc 1.547266 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.547266 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3179235417 # number of integer regfile reads +system.cpu.int_regfile_writes 1744932190 # number of integer regfile writes +system.cpu.fp_regfile_reads 109 # number of floating regfile reads +system.cpu.fp_regfile_writes 3 # number of floating regfile writes +system.cpu.misc_regfile_reads 1039364909 # number of misc regfile reads +system.cpu.icache.replacements 9996 # number of replacements +system.cpu.icache.tagsinuse 975.733254 # Cycle average of tags in use +system.cpu.icache.total_refs 194489021 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 11497 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 16916.501783 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 979.138170 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.478095 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 194581368 # number of ReadReq hits -system.cpu.icache.demand_hits 194581368 # number of demand (read+write) hits -system.cpu.icache.overall_hits 194581368 # number of overall hits -system.cpu.icache.ReadReq_misses 213540 # number of ReadReq misses -system.cpu.icache.demand_misses 213540 # number of demand (read+write) misses -system.cpu.icache.overall_misses 213540 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 1483328000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 1483328000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 1483328000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 194794908 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 194794908 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 194794908 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.001096 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.001096 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.001096 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 6946.370703 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 6946.370703 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 6946.370703 # average overall miss latency +system.cpu.icache.occ_blocks::0 975.733254 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.476432 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 194495909 # number of ReadReq hits +system.cpu.icache.demand_hits 194495909 # number of demand (read+write) hits +system.cpu.icache.overall_hits 194495909 # number of overall hits +system.cpu.icache.ReadReq_misses 223856 # number of ReadReq misses +system.cpu.icache.demand_misses 223856 # number of demand (read+write) misses +system.cpu.icache.overall_misses 223856 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 1547338000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 1547338000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 1547338000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 194719765 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 194719765 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 194719765 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.001150 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.001150 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.001150 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 6912.202487 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 6912.202487 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 6912.202487 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -308,137 +308,137 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 7 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 2095 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 2095 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 2095 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 211445 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 211445 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 211445 # number of overall MSHR misses +system.cpu.icache.writebacks 6 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 2117 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 2117 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 2117 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 221739 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 221739 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 221739 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 798407000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 798407000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 798407000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 830917000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 830917000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 830917000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.001085 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.001085 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.001085 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3775.955922 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3775.955922 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3775.955922 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.001139 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.001139 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.001139 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 3747.274949 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 3747.274949 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 3747.274949 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2527816 # number of replacements -system.cpu.dcache.tagsinuse 4087.589623 # Cycle average of tags in use -system.cpu.dcache.total_refs 440722661 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2531912 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 174.067132 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 2123837000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4087.589623 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.997947 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 291994352 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 147612028 # number of WriteReq hits -system.cpu.dcache.demand_hits 439606380 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 439606380 # number of overall hits -system.cpu.dcache.ReadReq_misses 3097887 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1548173 # number of WriteReq misses -system.cpu.dcache.demand_misses 4646060 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 4646060 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 51505231500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 36276487000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 87781718500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 87781718500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 295092239 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 2527207 # number of replacements +system.cpu.dcache.tagsinuse 4087.569371 # Cycle average of tags in use +system.cpu.dcache.total_refs 440821768 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2531303 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 174.148163 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 2135798000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4087.569371 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.997942 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 292074612 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 147577545 # number of WriteReq hits +system.cpu.dcache.demand_hits 439652157 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 439652157 # number of overall hits +system.cpu.dcache.ReadReq_misses 3115587 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1582656 # number of WriteReq misses +system.cpu.dcache.demand_misses 4698243 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 4698243 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 51949082000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 37383634500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 89332716500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 89332716500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 295190199 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 444252440 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 444252440 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.010498 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.010379 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.010458 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.010458 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 16625.923250 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 23431.804456 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 18893.797863 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 18893.797863 # average overall miss latency +system.cpu.dcache.demand_accesses 444350400 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 444350400 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.010555 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.010610 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.010573 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.010573 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 16673.930787 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 23620.821265 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 19014.068983 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 19014.068983 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 20000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 74500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 20000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 18625 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 2229445 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1337511 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 584931 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1922442 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1922442 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1760376 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 963242 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2723618 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2723618 # number of overall MSHR misses +system.cpu.dcache.writebacks 2229206 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 1355757 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 609338 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1965095 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1965095 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1759830 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 973318 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 2733148 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2733148 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 14910828500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 16810626500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 31721455000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 31721455000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 14896925000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 17174770000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 32071695000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 32071695000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.005966 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006458 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.006131 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.006131 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8470.252094 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17452.131967 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 11646.807665 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 11646.807665 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.005962 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006525 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.006151 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.006151 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8464.979572 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17645.589622 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 11734.342597 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 11734.342597 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 574929 # number of replacements -system.cpu.l2cache.tagsinuse 21600.538558 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3193840 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 594089 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.376030 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 271573746000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 7800.784816 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13799.753742 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.238061 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.421135 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1433037 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 2229452 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits 1223 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits 524485 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 1957522 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1957522 # number of overall hits -system.cpu.l2cache.ReadReq_misses 338639 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 198705 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 247104 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 585743 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 585743 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 11565729500 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency 9755500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 8475498500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 20041228000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 20041228000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 1771676 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 2229452 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 199928 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 771589 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 2543265 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 2543265 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.191140 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 0.993883 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.320253 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.230311 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.230311 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34153.566187 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency 49.095393 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34299.317292 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34215.053360 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34215.053360 # average overall miss latency +system.cpu.l2cache.replacements 574699 # number of replacements +system.cpu.l2cache.tagsinuse 21595.701500 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3193363 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 593876 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.377154 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 271431195000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 7794.557657 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13801.143843 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.237871 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.421177 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 1432788 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 2229212 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits 1238 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits 524381 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 1957169 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 1957169 # number of overall hits +system.cpu.l2cache.ReadReq_misses 338369 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 208965 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 247135 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 585504 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 585504 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 11556474000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 9921000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 8477435500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 20033909500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 20033909500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 1771157 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 2229212 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 210203 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 771516 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 2542673 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 2542673 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.191044 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate 0.994110 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.320324 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.230271 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.230271 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34153.465595 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 47.476850 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34302.852692 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34216.520297 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34216.520297 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -447,31 +447,31 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 411255 # number of writebacks +system.cpu.l2cache.writebacks 411193 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 338639 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 198705 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 247104 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 585743 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 585743 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 338369 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 208965 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 247135 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 585504 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 585504 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 10504876500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6160011500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 7664207000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 18169083500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 18169083500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 10496162500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6478082000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 7666148000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 18162310500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 18162310500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191140 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.993883 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.320253 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.230311 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.230311 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31020.870307 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000.787600 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31016.118719 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31018.865782 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31018.865782 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191044 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994110 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.320324 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.230271 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.230271 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.870319 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000.799177 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31020.082141 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31019.959727 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31019.959727 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout index f7d229ce0..ac0a4779d 100755 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/s gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 20 2011 13:24:14 -gem5 started Aug 20 2011 13:24:28 -gem5 executing on zizzer +gem5 compiled Nov 16 2011 11:08:03 +gem5 started Nov 17 2011 13:09:16 +gem5 executing on ribera.cs.wisc.edu command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sav -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sv2 +tests Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -26,4 +25,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 96610526000 because target called exit() +122 123 124 Exiting @ tick 96689893000 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt index 43a8220e5..7b2ddaff9 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,251 +1,251 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.096611 # Number of seconds simulated -sim_ticks 96610526000 # Number of ticks simulated +sim_seconds 0.096690 # Number of seconds simulated +sim_ticks 96689893000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 102112 # Simulator instruction rate (inst/s) -host_tick_rate 44565176 # Simulator tick rate (ticks/s) -host_mem_usage 220868 # Number of bytes of host memory used -host_seconds 2167.85 # Real time elapsed on the host +host_inst_rate 89575 # Simulator instruction rate (inst/s) +host_tick_rate 39125952 # Simulator tick rate (ticks/s) +host_mem_usage 253168 # Number of bytes of host memory used +host_seconds 2471.25 # Real time elapsed on the host sim_insts 221363017 # Number of instructions simulated system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 193221053 # number of cpu cycles simulated +system.cpu.numCycles 193379787 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 25817967 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 25817967 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2894858 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 23614164 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 20981330 # Number of BTB hits +system.cpu.BPredUnit.lookups 25818202 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 25818202 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2898724 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 23602930 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 20841363 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 30977399 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 261503264 # Number of instructions fetch has processed -system.cpu.fetch.Branches 25817967 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 20981330 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 70791188 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 26915794 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 67651206 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 160 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1398 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 28846864 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 549492 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 193133856 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.260391 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.334586 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30995459 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 261573615 # Number of instructions fetch has processed +system.cpu.fetch.Branches 25818202 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 20841363 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 70808397 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 26924712 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 67767699 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 120 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1017 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 28859729 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 549788 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 193293197 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.259018 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.335260 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 124189193 64.30% 64.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4110604 2.13% 66.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3242349 1.68% 68.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4337138 2.25% 70.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4293938 2.22% 72.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4598067 2.38% 74.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5546943 2.87% 77.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3021455 1.56% 79.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 39794169 20.60% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 124336745 64.33% 64.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4112034 2.13% 66.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3238737 1.68% 68.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4462671 2.31% 70.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4295145 2.22% 72.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4476640 2.32% 74.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5418723 2.80% 77.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3020771 1.56% 79.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 39931731 20.66% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 193133856 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.133619 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.353389 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 44744191 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 57710964 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 57165261 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9800935 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 23712505 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 424257825 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 23712505 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 53368695 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14594998 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 21883 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 57606354 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 43829421 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 411666463 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 18981117 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22454802 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 438110122 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1066455351 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1055559190 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10896161 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 193293197 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.133510 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.352642 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 44764810 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 57827624 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 57161965 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9818293 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 23720505 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 424367292 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 23720505 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 53388300 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14632169 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 21921 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 57615812 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 43914490 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 411765049 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 18 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 19034939 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22478875 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 438156432 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1066580371 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1055689317 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10891054 # Number of floating rename lookups system.cpu.rename.CommittedMaps 234363409 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 203746713 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1780 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1774 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 94916865 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 104240418 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 37277466 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 67123936 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 21592423 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 396698453 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1768 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 287681057 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 248197 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 174766428 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 350779105 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 522 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 193133856 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.489542 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.479240 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 203793023 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1794 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1788 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 94980657 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 104262380 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 37289638 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 67232013 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 21668119 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 396788007 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2705 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 287703359 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 254770 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 174855842 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 350938331 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1459 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 193293197 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.488430 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.480803 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 60593209 31.37% 31.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 53908728 27.91% 59.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 35738338 18.50% 77.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 21062429 10.91% 88.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 13747169 7.12% 95.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 5239198 2.71% 98.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2106456 1.09% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 621668 0.32% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 116661 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 60724695 31.42% 31.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 54019027 27.95% 59.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 35712551 18.48% 77.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 21012235 10.87% 88.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 13686479 7.08% 95.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 5222239 2.70% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2184583 1.13% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 593188 0.31% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 138200 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 193133856 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 193293197 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 106266 3.87% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2319161 84.53% 88.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 318223 11.60% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 110269 4.01% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2317531 84.31% 88.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 321034 11.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1204809 0.42% 0.42% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 187032245 65.01% 65.43% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.43% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1651608 0.57% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 73242981 25.46% 91.47% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 24549414 8.53% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1208234 0.42% 0.42% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 187072997 65.02% 65.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1650386 0.57% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 73223880 25.45% 91.47% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 24547862 8.53% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 287681057 # Type of FU issued -system.cpu.iq.rate 1.488870 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2743650 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009537 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 765972748 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 566387994 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 278383951 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5515069 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 5414925 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2649060 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 286446350 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2773548 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18375293 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 287703359 # Type of FU issued +system.cpu.iq.rate 1.487763 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2748834 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009554 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 766190945 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 566572341 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 278374724 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 5512574 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 5407408 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2648186 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 286471551 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2772408 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18351013 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 47590828 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 32389 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 343467 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16761750 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 47612790 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 32223 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 339608 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 16773922 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 46017 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 46155 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 23712505 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 356267 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 212332 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 396700221 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 134682 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 104240418 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 37277466 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1768 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 118966 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 14039 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 343467 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2505670 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 594786 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3100456 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 283858854 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 71711617 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3822203 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 23720505 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 359624 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 213865 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 396790712 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 135718 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 104262380 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 37289638 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1786 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 119790 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15845 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 339608 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2505263 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 598160 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3103423 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 283855997 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 71689961 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3847362 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 95762495 # number of memory reference insts executed -system.cpu.iew.exec_branches 15668383 # Number of branches executed -system.cpu.iew.exec_stores 24050878 # Number of stores executed -system.cpu.iew.exec_rate 1.469089 # Inst execution rate -system.cpu.iew.wb_sent 282330192 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 281033011 # cumulative count of insts written-back -system.cpu.iew.wb_producers 227942764 # num instructions producing a value -system.cpu.iew.wb_consumers 378918606 # num instructions consuming a value +system.cpu.iew.exec_refs 95739480 # number of memory reference insts executed +system.cpu.iew.exec_branches 15662592 # Number of branches executed +system.cpu.iew.exec_stores 24049519 # Number of stores executed +system.cpu.iew.exec_rate 1.467868 # Inst execution rate +system.cpu.iew.wb_sent 282319460 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 281022910 # cumulative count of insts written-back +system.cpu.iew.wb_producers 227917239 # num instructions producing a value +system.cpu.iew.wb_consumers 378870882 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.454464 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.601561 # average fanout of values written-back +system.cpu.iew.wb_rate 1.453218 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.601570 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 175344362 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 175435625 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2895014 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 169421351 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.306583 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.742468 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2898838 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 169572692 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.305417 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.741291 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 63568929 37.52% 37.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 62259787 36.75% 74.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15643694 9.23% 83.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11988406 7.08% 90.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 5417709 3.20% 93.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2980917 1.76% 95.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2013932 1.19% 96.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1192205 0.70% 97.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4355772 2.57% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 63662174 37.54% 37.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 62350604 36.77% 74.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15592003 9.19% 83.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11999288 7.08% 90.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5440588 3.21% 93.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2982193 1.76% 95.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2011991 1.19% 96.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1185528 0.70% 97.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4348323 2.56% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 169421351 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 169572692 # Number of insts commited each cycle system.cpu.commit.count 221363017 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 77165306 # Number of memory references committed @@ -255,50 +255,50 @@ system.cpu.commit.branches 12326943 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339606 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4355772 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4348323 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 561772958 # The number of ROB reads -system.cpu.rob.rob_writes 817171098 # The number of ROB writes -system.cpu.timesIdled 1889 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 87197 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 562023011 # The number of ROB reads +system.cpu.rob.rob_writes 817360743 # The number of ROB writes +system.cpu.timesIdled 1880 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 86590 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 221363017 # Number of Instructions Simulated system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated -system.cpu.cpi 0.872870 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.872870 # CPI: Total CPI of All Threads -system.cpu.ipc 1.145646 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.145646 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 530742767 # number of integer regfile reads -system.cpu.int_regfile_writes 288972647 # number of integer regfile writes -system.cpu.fp_regfile_reads 3616458 # number of floating regfile reads -system.cpu.fp_regfile_writes 2303580 # number of floating regfile writes -system.cpu.misc_regfile_reads 149927786 # number of misc regfile reads +system.cpu.cpi 0.873587 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.873587 # CPI: Total CPI of All Threads +system.cpu.ipc 1.144706 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.144706 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 530675330 # number of integer regfile reads +system.cpu.int_regfile_writes 288962100 # number of integer regfile writes +system.cpu.fp_regfile_reads 3614411 # number of floating regfile reads +system.cpu.fp_regfile_writes 2302807 # number of floating regfile writes +system.cpu.misc_regfile_reads 149913222 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.icache.replacements 4235 # number of replacements -system.cpu.icache.tagsinuse 1597.100373 # Cycle average of tags in use -system.cpu.icache.total_refs 28839309 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 6200 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4651.501452 # Average number of references to valid blocks. +system.cpu.icache.replacements 4227 # number of replacements +system.cpu.icache.tagsinuse 1595.324923 # Cycle average of tags in use +system.cpu.icache.total_refs 28852140 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 6194 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4658.078786 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1597.100373 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.779834 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 28839309 # number of ReadReq hits -system.cpu.icache.demand_hits 28839309 # number of demand (read+write) hits -system.cpu.icache.overall_hits 28839309 # number of overall hits -system.cpu.icache.ReadReq_misses 7555 # number of ReadReq misses -system.cpu.icache.demand_misses 7555 # number of demand (read+write) misses -system.cpu.icache.overall_misses 7555 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 173857500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 173857500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 173857500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 28846864 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 28846864 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 28846864 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000262 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000262 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000262 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 23012.243547 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 23012.243547 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 23012.243547 # average overall miss latency +system.cpu.icache.occ_blocks::0 1595.324923 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.778967 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 28852140 # number of ReadReq hits +system.cpu.icache.demand_hits 28852140 # number of demand (read+write) hits +system.cpu.icache.overall_hits 28852140 # number of overall hits +system.cpu.icache.ReadReq_misses 7589 # number of ReadReq misses +system.cpu.icache.demand_misses 7589 # number of demand (read+write) misses +system.cpu.icache.overall_misses 7589 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 174464500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 174464500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 174464500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 28859729 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 28859729 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 28859729 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000263 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000263 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000263 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 22989.129003 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 22989.129003 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 22989.129003 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -308,59 +308,59 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1113 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1113 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1113 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 6442 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 6442 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 6442 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 1125 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 1125 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 1125 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 6464 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 6464 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 6464 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 125492000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 125492000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 125492000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 125677000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 125677000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 125677000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000223 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000223 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000223 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 19480.285626 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 19480.285626 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 19480.285626 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000224 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000224 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000224 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 19442.605198 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 19442.605198 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 19442.605198 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 59 # number of replacements -system.cpu.dcache.tagsinuse 1420.172872 # Cycle average of tags in use -system.cpu.dcache.total_refs 73596568 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1416.877097 # Cycle average of tags in use +system.cpu.dcache.total_refs 73598603 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1986 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37057.687815 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 37058.712487 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1420.172872 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.346722 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 53088625 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 20507488 # number of WriteReq hits -system.cpu.dcache.demand_hits 73596113 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 73596113 # number of overall hits -system.cpu.dcache.ReadReq_misses 844 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 8242 # number of WriteReq misses -system.cpu.dcache.demand_misses 9086 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 9086 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 26292500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 227102000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 253394500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 253394500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 53089469 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::0 1416.877097 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.345917 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 53090649 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 20507453 # number of WriteReq hits +system.cpu.dcache.demand_hits 73598102 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 73598102 # number of overall hits +system.cpu.dcache.ReadReq_misses 848 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 8277 # number of WriteReq misses +system.cpu.dcache.demand_misses 9125 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 9125 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 26447500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 228348000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 254795500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 254795500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 53091497 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 73605199 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 73605199 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses 73607227 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 73607227 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate 0.000016 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000402 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000123 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000123 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 31152.251185 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 27554.234409 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 27888.454766 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 27888.454766 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate 0.000403 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.000124 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000124 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 31188.089623 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 27588.256615 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 27922.794521 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 27922.794521 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -370,71 +370,71 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 14 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 420 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 6436 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 6856 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 6856 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 424 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 6443 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 6867 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 6867 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses 424 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1806 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2230 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2230 # number of overall MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1834 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 2258 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2258 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 14047000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 63209500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 77256500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 77256500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 13981500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 64146500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 78128000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 78128000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000088 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000030 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000030 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 33129.716981 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34999.723145 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34644.170404 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34644.170404 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.000031 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.000031 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32975.235849 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34976.281352 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34600.531444 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34600.531444 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2499.008056 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2867 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3761 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.762297 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2499.166941 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2858 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3763 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.759500 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2497.026903 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 1.981153 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.076203 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000060 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 2866 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::0 2497.181729 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 1.985212 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.076208 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000061 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 2857 # number of ReadReq hits system.cpu.l2cache.Writeback_hits 14 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 8 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 2874 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 2874 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3757 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 242 # number of UpgradeReq misses +system.cpu.l2cache.demand_hits 2865 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 2865 # number of overall hits +system.cpu.l2cache.ReadReq_misses 3759 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 270 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses 1557 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 5314 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 5314 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 128666000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 53239000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 181905000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 181905000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 6623 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses 5316 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 5316 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 128731000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 53240500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 181971500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 181971500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 6616 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 14 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 242 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 270 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 1565 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 8188 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 8188 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.567266 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses 8181 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 8181 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.568168 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate 0.994888 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.648999 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.648999 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34247.005590 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34193.320488 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34231.275875 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34231.275875 # average overall miss latency +system.cpu.l2cache.demand_miss_rate 0.649798 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.649798 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34246.076084 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34194.283879 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34230.906697 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34230.906697 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -446,28 +446,28 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3757 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 242 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 3759 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 270 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 1557 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 5314 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 5314 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses 5316 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 5316 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 116539500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7502000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 48375000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 164914500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 164914500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 116600500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 8370000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 48374500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 164975000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 164975000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.567266 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.568168 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.994888 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.648999 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.648999 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.297312 # average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate 0.649798 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.649798 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.021016 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31069.364162 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31033.966880 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31033.966880 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31069.043031 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31033.671934 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31033.671934 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |