diff options
Diffstat (limited to 'tests/long')
68 files changed, 3558 insertions, 3569 deletions
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini index 647cf0cf8..ca675ac92 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -489,7 +489,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing +cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing egid=100 env= errout=cerr @@ -512,7 +512,7 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout index 196024f42..5518ac66c 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:54:18 -gem5 started Jul 2 2012 11:32:18 +gem5 compiled Aug 13 2012 17:04:37 +gem5 started Aug 13 2012 18:13:42 gem5 executing on zizzer -command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 389181871500 because target called exit() +Exiting @ tick 389171398000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 09d53c6a6..1f6271301 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,173 +1,173 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.389182 # Number of seconds simulated -sim_ticks 389181871500 # Number of ticks simulated -final_tick 389181871500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.389171 # Number of seconds simulated +sim_ticks 389171398000 # Number of ticks simulated +final_tick 389171398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 233275 # Simulator instruction rate (inst/s) -host_op_rate 234010 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64792479 # Simulator tick rate (ticks/s) -host_mem_usage 223132 # Number of bytes of host memory used -host_seconds 6006.59 # Real time elapsed on the host -sim_insts 1401188958 # Number of instructions simulated -sim_ops 1405604152 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 78592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1679360 # Number of bytes read from this memory -system.physmem.bytes_read::total 1757952 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 78592 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 78592 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 163456 # Number of bytes written to this memory -system.physmem.bytes_written::total 163456 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1228 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26240 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27468 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2554 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2554 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 201942 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4315103 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4517045 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 201942 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 201942 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 419999 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 419999 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 419999 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 201942 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4315103 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4937044 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 172352 # Simulator instruction rate (inst/s) +host_op_rate 172895 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47869738 # Simulator tick rate (ticks/s) +host_mem_usage 232600 # Number of bytes of host memory used +host_seconds 8129.80 # Real time elapsed on the host +sim_insts 1401188945 # Number of instructions simulated +sim_ops 1405604139 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 78528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1679232 # Number of bytes read from this memory +system.physmem.bytes_read::total 1757760 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 78528 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 78528 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 163392 # Number of bytes written to this memory +system.physmem.bytes_written::total 163392 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1227 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26238 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27465 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2553 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2553 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 201783 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4314891 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4516673 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 201783 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 201783 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 419846 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 419846 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 419846 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 201783 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4314891 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4936519 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 778363744 # number of cpu cycles simulated +system.cpu.numCycles 778342797 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 98202538 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 88418167 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3786555 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 66007710 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 65666961 # Number of BTB hits +system.cpu.BPredUnit.lookups 98197174 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 88413236 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3785239 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 66015510 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 65664831 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1332 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 219 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 165889798 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1648919647 # Number of instructions fetch has processed -system.cpu.fetch.Branches 98202538 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 65668293 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 330430884 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 21692843 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 264292230 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 125 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2686 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 162826473 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 754831 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 778319405 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.124393 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.146166 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1336 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 221 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 165881717 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1648798034 # Number of instructions fetch has processed +system.cpu.fetch.Branches 98197174 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 65666167 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 330411204 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 21674066 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 264316799 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 122 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2684 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 162819499 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 755607 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 778298464 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.124294 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.146110 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 447888521 57.55% 57.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 74380250 9.56% 67.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 37976870 4.88% 71.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 9085355 1.17% 73.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28165073 3.62% 76.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18828553 2.42% 79.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 11512004 1.48% 80.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3871007 0.50% 81.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 146611772 18.84% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 447887260 57.55% 57.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 74376407 9.56% 67.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 37977630 4.88% 71.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 9084449 1.17% 73.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28163510 3.62% 76.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18828809 2.42% 79.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 11510131 1.48% 80.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3871378 0.50% 81.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 146598890 18.84% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 778319405 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126165 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.118444 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 217790097 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 214638982 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 285156910 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 43029734 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 17703682 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 1642636299 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 17703682 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 241734353 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36955708 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 51946820 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 303044657 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 126934185 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1631312586 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 31546408 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 73332264 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 3116970 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1360939473 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2755912805 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2722068159 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 33844646 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1244770452 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 116169021 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2679381 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2694981 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 272918574 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 438732735 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 180262547 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 255381650 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 82499363 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1517064379 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2634738 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1460855259 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 54931 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 113760463 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 136767182 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 391067 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 778319405 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.876935 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.427664 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 778298464 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126162 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.118344 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 217730423 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 214714894 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 285147826 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 43019383 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 17685938 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 1642518992 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 17685938 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 241679768 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36912628 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 51960575 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 303022356 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 127037199 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1631180439 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 31545211 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 73402474 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3147906 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1360824399 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2755700072 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2721856567 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 33843505 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1244770439 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 116053960 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2679524 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2694715 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 273063750 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 438707438 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 180249753 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 255184370 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 82754828 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1516941659 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2635026 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1460769058 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 54636 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 113641063 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 136677185 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 391355 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 778298464 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.876875 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.427909 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 147026932 18.89% 18.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 186493885 23.96% 42.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 211074443 27.12% 69.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 130841076 16.81% 86.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 70678954 9.08% 95.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 20414805 2.62% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7717737 0.99% 99.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3979587 0.51% 99.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 91986 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 147064057 18.90% 18.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 186545297 23.97% 42.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 210910023 27.10% 69.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 130868567 16.81% 86.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 70782480 9.09% 95.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20278912 2.61% 98.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7762488 1.00% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3994514 0.51% 99.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 92126 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 778319405 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 778298464 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 100522 6.26% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 166576 10.38% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1142590 71.19% 87.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 195193 12.16% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 113664 7.00% 7.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 166579 10.26% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1139490 70.19% 87.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 203791 12.55% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 867158324 59.36% 59.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 867086456 59.36% 59.36% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.36% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2642655 0.18% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2642669 0.18% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.54% # Type of FU issued @@ -193,160 +193,160 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.54% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 419786972 28.74% 88.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 171267308 11.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 419773044 28.74% 88.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 171266889 11.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1460855259 # Type of FU issued -system.cpu.iq.rate 1.876829 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1604881 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001099 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3684016874 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1624580550 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1444446185 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 17672861 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9115596 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 8537125 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1453449423 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 9010717 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 215321766 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1460769058 # Type of FU issued +system.cpu.iq.rate 1.876768 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1623524 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001111 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3683829696 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1624339460 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1444358901 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 17685044 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9115270 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 8537907 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1453371390 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 9021192 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 215484580 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 36219891 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 54743 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 244893 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 13414405 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 36194595 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 55177 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 245195 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 13401611 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3575 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 58855 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3537 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 56120 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 17703682 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1537187 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 135114 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1613898993 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4122313 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 438732735 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 180262547 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2549072 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 88195 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3279 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 244893 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2354936 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1566356 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3921292 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1455308115 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 417068435 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5547144 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 17685938 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1543124 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 135108 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1613772123 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4123534 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 438707438 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 180249753 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2549312 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 88176 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3284 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 245195 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2354964 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1564711 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3919675 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1455222367 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 417054039 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5546691 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 94199876 # number of nop insts executed -system.cpu.iew.exec_refs 587640720 # number of memory reference insts executed -system.cpu.iew.exec_branches 89112594 # Number of branches executed -system.cpu.iew.exec_stores 170572285 # Number of stores executed -system.cpu.iew.exec_rate 1.869702 # Inst execution rate -system.cpu.iew.wb_sent 1453906115 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1452983310 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1154403216 # num instructions producing a value -system.cpu.iew.wb_consumers 1205257004 # num instructions consuming a value +system.cpu.iew.exec_nop 94195438 # number of nop insts executed +system.cpu.iew.exec_refs 587626307 # number of memory reference insts executed +system.cpu.iew.exec_branches 89109233 # Number of branches executed +system.cpu.iew.exec_stores 170572268 # Number of stores executed +system.cpu.iew.exec_rate 1.869642 # Inst execution rate +system.cpu.iew.wb_sent 1453822475 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1452896808 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1154316777 # num instructions producing a value +system.cpu.iew.wb_consumers 1205166277 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.866715 # insts written-back per cycle +system.cpu.iew.wb_rate 1.866654 # insts written-back per cycle system.cpu.iew.wb_fanout 0.957807 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 1485108101 # The number of committed instructions -system.cpu.commit.commitCommittedOps 1489523295 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 124289069 # The number of squashed insts skipped by commit +system.cpu.commit.commitCommittedInsts 1485108088 # The number of committed instructions +system.cpu.commit.commitCommittedOps 1489523282 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 124161815 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3786555 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 760616334 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.958311 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.503558 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3785239 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 760613137 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.958319 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.503249 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 241729742 31.78% 31.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 276918822 36.41% 68.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43178321 5.68% 73.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 54835847 7.21% 81.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19622698 2.58% 83.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13346857 1.75% 85.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 30466514 4.01% 89.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10424135 1.37% 90.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 70093398 9.22% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 241688690 31.78% 31.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 276879553 36.40% 68.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43195227 5.68% 73.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 54904670 7.22% 81.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19686775 2.59% 83.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13341138 1.75% 85.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 30448610 4.00% 89.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10352977 1.36% 90.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 70115497 9.22% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 760616334 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1485108101 # Number of instructions committed -system.cpu.commit.committedOps 1489523295 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 760613137 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1485108088 # Number of instructions committed +system.cpu.commit.committedOps 1489523282 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 569360986 # Number of memory references committed -system.cpu.commit.loads 402512844 # Number of loads committed +system.cpu.commit.refs 569360985 # Number of memory references committed +system.cpu.commit.loads 402512843 # Number of loads committed system.cpu.commit.membars 51356 # Number of memory barriers committed -system.cpu.commit.branches 86248929 # Number of branches committed +system.cpu.commit.branches 86248928 # Number of branches committed system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1319476388 # Number of committed integer instructions. +system.cpu.commit.int_insts 1319476376 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 70093398 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 70115497 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2304270430 # The number of ROB reads -system.cpu.rob.rob_writes 3245352893 # The number of ROB writes -system.cpu.timesIdled 1469 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 44339 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1401188958 # Number of Instructions Simulated -system.cpu.committedOps 1405604152 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1401188958 # Number of Instructions Simulated -system.cpu.cpi 0.555502 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.555502 # CPI: Total CPI of All Threads -system.cpu.ipc 1.800172 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.800172 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1980619061 # number of integer regfile reads -system.cpu.int_regfile_writes 1276279795 # number of integer regfile writes -system.cpu.fp_regfile_reads 16952700 # number of floating regfile reads -system.cpu.fp_regfile_writes 10491726 # number of floating regfile writes -system.cpu.misc_regfile_reads 593312421 # number of misc regfile reads +system.cpu.rob.rob_reads 2304117867 # The number of ROB reads +system.cpu.rob.rob_writes 3245080355 # The number of ROB writes +system.cpu.timesIdled 1467 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 44333 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1401188945 # Number of Instructions Simulated +system.cpu.committedOps 1405604139 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1401188945 # Number of Instructions Simulated +system.cpu.cpi 0.555487 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.555487 # CPI: Total CPI of All Threads +system.cpu.ipc 1.800221 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.800221 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1980525328 # number of integer regfile reads +system.cpu.int_regfile_writes 1276196147 # number of integer regfile writes +system.cpu.fp_regfile_reads 16956232 # number of floating regfile reads +system.cpu.fp_regfile_writes 10491758 # number of floating regfile writes +system.cpu.misc_regfile_reads 593298094 # number of misc regfile reads system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes -system.cpu.icache.replacements 216 # number of replacements -system.cpu.icache.tagsinuse 1046.067933 # Cycle average of tags in use -system.cpu.icache.total_refs 162824561 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1364 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 119372.845308 # Average number of references to valid blocks. +system.cpu.icache.replacements 214 # number of replacements +system.cpu.icache.tagsinuse 1046.066234 # Cycle average of tags in use +system.cpu.icache.total_refs 162817587 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1362 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 119543.015419 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1046.067933 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1046.066234 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.510775 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.510775 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 162824561 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 162824561 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 162824561 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 162824561 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 162824561 # number of overall hits -system.cpu.icache.overall_hits::total 162824561 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 162817587 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 162817587 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 162817587 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 162817587 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 162817587 # number of overall hits +system.cpu.icache.overall_hits::total 162817587 # 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average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 32912.395397 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 32912.395397 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 32912.395397 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -355,106 +355,106 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 547 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 547 # 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number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11940266500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11940266500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57531206941 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57531206941 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 69000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 69000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 69471473441 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 69471473441 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 69471473441 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 69471473441 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 201522884 # 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miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 368369700 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 368369700 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 368369700 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 368369700 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004467 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004467 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011218 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.011218 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007522 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.007522 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007522 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007522 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13261.632517 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13261.632517 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30702.327831 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30702.327831 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 9928.571429 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 9928.571429 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25037.155900 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25037.155900 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25037.155900 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25037.155900 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.007525 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007525 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007525 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007525 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13262.541930 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13262.541930 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30738.524956 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30738.524956 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 9857.142857 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 9857.142857 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25062.473914 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25062.473914 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25062.473914 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25062.473914 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 4500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -463,140 +463,140 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 2250 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 442976 # number of writebacks -system.cpu.dcache.writebacks::total 442976 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 700359 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 700359 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1609620 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1609620 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2309979 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2309979 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2309979 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2309979 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200091 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 200091 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262039 # 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number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6834850258 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6834850258 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6834850258 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6834850258 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6841701005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6841701005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6841701005 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6841701005 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000992 # 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average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 4637.384990 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22542.259961 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22542.259961 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 4637.577767 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 4637.577767 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22571.938086 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22571.938086 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 6714.285714 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 6714.285714 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14789.886521 # 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number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 262039 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 262039 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1363 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 461987 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 463350 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1363 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 461987 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 463350 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.900220 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022181 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.028126 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083205 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.083205 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.900220 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.056794 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.059275 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.900220 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.056794 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.059275 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34795.436023 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34234.836528 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34356.322854 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38657.042609 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38657.042609 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34792.752443 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37909.260671 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 37769.932285 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34792.752443 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37909.260671 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 37769.932285 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34795.436023 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37909.558655 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 37770.435099 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34795.436023 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37909.558655 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 37770.435099 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -605,52 +605,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 2554 # number of writebacks -system.cpu.l2cache.writebacks::total 2554 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1228 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4437 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5665 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 2553 # number of writebacks +system.cpu.l2cache.writebacks::total 2553 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1227 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4435 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5662 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21803 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 21803 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1228 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 26240 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 27468 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1228 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 26240 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 27468 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38798500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 138491500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 177290000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1227 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26238 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27465 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1227 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 26238 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 27465 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38769500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 138429500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 177199000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 776754500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 776754500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38798500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 915246000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 954044500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38798500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 915246000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 954044500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.899634 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022175 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.028121 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083201 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083201 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.899634 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056780 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.059262 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.899634 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056780 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.059262 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31594.869707 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31212.869056 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31295.675199 # average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38769500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 915184000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 953953500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38769500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 915184000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 953953500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.900220 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022181 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.028126 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083205 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083205 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.900220 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056794 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.059275 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.900220 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056794 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.059275 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31596.984515 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31212.965051 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31296.185094 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35626.037701 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35626.037701 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31594.869707 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34879.801829 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34732.943789 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31594.869707 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34879.801829 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34732.943789 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31596.984515 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34880.097568 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34733.424358 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31596.984515 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34880.097568 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34733.424358 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini index 47913c070..bd29989f9 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini @@ -99,8 +99,8 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 -master=system.physmem.port[0] +width=8 +master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.physmem] diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout index bf7412ed2..a424ec0a0 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:01:47 -gem5 started Jun 4 2012 14:45:41 +gem5 compiled Aug 13 2012 17:04:37 +gem5 started Aug 13 2012 18:13:47 gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 744764119000 because target called exit() +Exiting @ tick 744764112500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt index ed36e3ce0..4e5a83c19 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.744764 # Number of seconds simulated -sim_ticks 744764119000 # Number of ticks simulated -final_tick 744764119000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 744764112500 # Number of ticks simulated +final_tick 744764112500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3186892 # Simulator instruction rate (inst/s) -host_op_rate 3196366 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1598188492 # Simulator tick rate (ticks/s) -host_mem_usage 214172 # Number of bytes of host memory used -host_seconds 466.01 # Real time elapsed on the host -sim_insts 1485108101 # Number of instructions simulated -sim_ops 1489523295 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 5940452044 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1385817593 # Number of bytes read from this memory -system.physmem.bytes_read::total 7326269637 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5940452044 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5940452044 # Number of instructions bytes read from this memory +host_inst_rate 3155762 # Simulator instruction rate (inst/s) +host_op_rate 3165144 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1582576951 # Simulator tick rate (ticks/s) +host_mem_usage 222108 # Number of bytes of host memory used +host_seconds 470.60 # Real time elapsed on the host +sim_insts 1485108088 # Number of instructions simulated +sim_ops 1489523282 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 5940451992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1385817592 # Number of bytes read from this memory +system.physmem.bytes_read::total 7326269584 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5940451992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5940451992 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 614672063 # Number of bytes written to this memory system.physmem.bytes_written::total 614672063 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1485113011 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 402512844 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1887625855 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1485112998 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 402512843 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1887625841 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 166846816 # Number of write requests responded to by this memory system.physmem.num_writes::total 166846816 # Number of write requests responded to by this memory system.physmem.num_other::cpu.data 1326 # Number of other requests responded to by this memory system.physmem.num_other::total 1326 # Number of other requests responded to by this memory system.physmem.bw_read::cpu.inst 7976286575 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1860746990 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9837033566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1860747005 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9837033580 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 7976286575 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 7976286575 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 825324485 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 825324485 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 825324492 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 825324492 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::cpu.inst 7976286575 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2686071475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10662358051 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2686071498 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10662358072 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 1489528239 # number of cpu cycles simulated +system.cpu.numCycles 1489528226 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1485108101 # Number of instructions committed -system.cpu.committedOps 1489523295 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1319481298 # Number of integer alu accesses +system.cpu.committedInsts 1485108088 # Number of instructions committed +system.cpu.committedOps 1489523282 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1319481286 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 8454127 # Number of float alu accesses system.cpu.num_func_calls 1207835 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 78161763 # number of instructions that are conditional controls -system.cpu.num_int_insts 1319481298 # number of integer instructions +system.cpu.num_conditional_control_insts 78161762 # number of instructions that are conditional controls +system.cpu.num_int_insts 1319481286 # number of integer instructions system.cpu.num_fp_insts 8454127 # number of float instructions -system.cpu.num_int_register_reads 2499743582 # number of times the integer registers were read -system.cpu.num_int_register_writes 1234343158 # number of times the integer registers were written +system.cpu.num_int_register_reads 2499743560 # number of times the integer registers were read +system.cpu.num_int_register_writes 1234343145 # number of times the integer registers were written system.cpu.num_fp_register_reads 16769332 # number of times the floating registers were read system.cpu.num_fp_register_writes 10359244 # number of times the floating registers were written -system.cpu.num_mem_refs 569365767 # number of memory refs -system.cpu.num_load_insts 402515346 # Number of load instructions +system.cpu.num_mem_refs 569365766 # number of memory refs +system.cpu.num_load_insts 402515345 # Number of load instructions system.cpu.num_store_insts 166850421 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1489528239 # Number of busy cycles +system.cpu.num_busy_cycles 1489528226 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini index ed5d7509c..cd17d9d73 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -158,7 +158,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing +cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing egid=100 env= errout=cerr @@ -181,7 +181,7 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout index 7b12cccb1..7275352c5 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:54:18 -gem5 started Jul 2 2012 12:13:11 +gem5 compiled Aug 13 2012 17:04:37 +gem5 started Aug 13 2012 18:13:49 gem5 executing on zizzer -command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2063177751000 because target called exit() +Exiting @ tick 2063177737000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt index 607412a81..3078a0fec 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.063178 # Number of seconds simulated -sim_ticks 2063177751000 # Number of ticks simulated -final_tick 2063177751000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2063177737000 # Number of ticks simulated +final_tick 2063177737000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1349558 # Simulator instruction rate (inst/s) -host_op_rate 1353570 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1874864984 # Simulator tick rate (ticks/s) -host_mem_usage 222108 # Number of bytes of host memory used -host_seconds 1100.44 # Real time elapsed on the host -sim_insts 1485108101 # Number of instructions simulated -sim_ops 1489523295 # Number of ops (including micro ops) simulated +host_inst_rate 1527975 # Simulator instruction rate (inst/s) +host_op_rate 1532517 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2122729697 # Simulator tick rate (ticks/s) +host_mem_usage 231576 # Number of bytes of host memory used +host_seconds 971.95 # Real time elapsed on the host +sim_insts 1485108088 # Number of instructions simulated +sim_ops 1489523282 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 65728 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1672576 # Number of bytes read from this memory system.physmem.bytes_read::total 1738304 # Number of bytes read from this memory @@ -35,43 +35,43 @@ system.physmem.bw_total::cpu.inst 31858 # To system.physmem.bw_total::cpu.data 810680 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 920801 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 4126355502 # number of cpu cycles simulated +system.cpu.numCycles 4126355474 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1485108101 # Number of instructions committed -system.cpu.committedOps 1489523295 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1319481298 # Number of integer alu accesses +system.cpu.committedInsts 1485108088 # Number of instructions committed +system.cpu.committedOps 1489523282 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1319481286 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 8454127 # Number of float alu accesses system.cpu.num_func_calls 1207835 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 78161763 # number of instructions that are conditional controls -system.cpu.num_int_insts 1319481298 # number of integer instructions +system.cpu.num_conditional_control_insts 78161762 # number of instructions that are conditional controls +system.cpu.num_int_insts 1319481286 # number of integer instructions system.cpu.num_fp_insts 8454127 # number of float instructions -system.cpu.num_int_register_reads 2499743582 # number of times the integer registers were read -system.cpu.num_int_register_writes 1234343157 # number of times the integer registers were written +system.cpu.num_int_register_reads 2499743560 # number of times the integer registers were read +system.cpu.num_int_register_writes 1234343144 # number of times the integer registers were written system.cpu.num_fp_register_reads 16769332 # number of times the floating registers were read system.cpu.num_fp_register_writes 10359244 # number of times the floating registers were written -system.cpu.num_mem_refs 569365767 # number of memory refs -system.cpu.num_load_insts 402515346 # Number of load instructions +system.cpu.num_mem_refs 569365766 # number of memory refs +system.cpu.num_load_insts 402515345 # Number of load instructions system.cpu.num_store_insts 166850421 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 4126355502 # Number of busy cycles +system.cpu.num_busy_cycles 4126355474 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 118 # number of replacements -system.cpu.icache.tagsinuse 906.409372 # Cycle average of tags in use -system.cpu.icache.total_refs 1485111905 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 906.409378 # Cycle average of tags in use +system.cpu.icache.total_refs 1485111892 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1341564.503162 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1341564.491418 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 906.409372 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 906.409378 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.442583 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.442583 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1485111905 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1485111905 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1485111905 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1485111905 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1485111905 # number of overall hits -system.cpu.icache.overall_hits::total 1485111905 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 1485111892 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1485111892 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1485111892 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1485111892 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1485111892 # number of overall hits +system.cpu.icache.overall_hits::total 1485111892 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1107 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1107 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1107 # number of demand (read+write) misses @@ -84,12 +84,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 58777000 system.cpu.icache.demand_miss_latency::total 58777000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 58777000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 58777000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1485113012 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1485113012 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1485113012 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1485113012 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1485113012 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1485113012 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 1485112999 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1485112999 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1485112999 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1485112999 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1485112999 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1485112999 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses @@ -136,24 +136,24 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50095.754291 system.cpu.icache.overall_avg_mshr_miss_latency::total 50095.754291 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 449125 # number of replacements -system.cpu.dcache.tagsinuse 4095.205153 # Cycle average of tags in use -system.cpu.dcache.total_refs 568907765 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4095.205181 # Cycle average of tags in use +system.cpu.dcache.total_refs 568907764 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 588945000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.205153 # Average occupied blocks per requestor +system.cpu.dcache.avg_refs 1255.254642 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 588931000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4095.205181 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999806 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999806 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 402319358 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 402319358 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 402319357 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 402319357 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 166587088 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 166587088 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 568906446 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 568906446 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 568906446 # number of overall hits -system.cpu.dcache.overall_hits::total 568906446 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 568906445 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 568906445 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 568906445 # number of overall hits +system.cpu.dcache.overall_hits::total 568906445 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 193486 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 193486 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 259728 # number of WriteReq misses @@ -174,16 +174,16 @@ system.cpu.dcache.demand_miss_latency::cpu.data 7443302000 system.cpu.dcache.demand_miss_latency::total 7443302000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 7443302000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 7443302000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 402512844 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 402512844 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 402512843 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 402512843 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 569359660 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 569359660 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 569359660 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 569359660 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 569359659 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 569359659 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 569359659 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 569359659 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000481 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000481 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001557 # miss rate for WriteReq accesses @@ -256,14 +256,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13423.371741 system.cpu.dcache.overall_avg_mshr_miss_latency::total 13423.371741 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2614 # number of replacements -system.cpu.l2cache.tagsinuse 22185.384662 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 22185.384813 # Cycle average of tags in use system.cpu.l2cache.total_refs 527657 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23998 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 21.987541 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20828.536366 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 857.441703 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 499.406594 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 20828.536507 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 857.441709 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 499.406597 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.635636 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.026167 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.015241 # Average percentage of cache occupancy diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini index 9d85601cf..c34a24e32 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini @@ -510,7 +510,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing +cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing egid=100 env= errout=cerr @@ -533,7 +533,7 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout index e9fade7f1..df6cae2da 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:58:39 -gem5 started Jul 2 2012 12:44:41 +gem5 compiled Aug 13 2012 17:08:22 +gem5 started Aug 13 2012 18:23:13 gem5 executing on zizzer -command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -19,12 +19,12 @@ info: Increasing stack size by one page. Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Compressing Input Data, level 3 +info: Increasing stack size by one page. Compressed data 97831 bytes in length Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Compressing Input Data, level 5 -info: Increasing stack size by one page. Compressed data 83382 bytes in length Uncompressing Data Uncompressed data 1048576 bytes in length @@ -40,4 +40,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 636963896500 because target called exit() +Exiting @ tick 636923447500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index 5a09d9960..e0bb93d0f 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,171 +1,171 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.636964 # Number of seconds simulated -sim_ticks 636963896500 # Number of ticks simulated -final_tick 636963896500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.636923 # Number of seconds simulated +sim_ticks 636923447500 # Number of ticks simulated +final_tick 636923447500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 94339 # Simulator instruction rate (inst/s) -host_op_rate 173825 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 68282764 # Simulator tick rate (ticks/s) -host_mem_usage 230548 # Number of bytes of host memory used -host_seconds 9328.33 # Real time elapsed on the host -sim_insts 880025312 # Number of instructions simulated -sim_ops 1621493982 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 59072 # Number of bytes read from this memory +host_inst_rate 70364 # Simulator instruction rate (inst/s) +host_op_rate 129650 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50926468 # Simulator tick rate (ticks/s) +host_mem_usage 235448 # Number of bytes of host memory used +host_seconds 12506.73 # Real time elapsed on the host +sim_insts 880025277 # Number of instructions simulated +sim_ops 1621493925 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 58944 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1694720 # Number of bytes read from this memory -system.physmem.bytes_read::total 1753792 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 59072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 59072 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 162752 # Number of bytes written to this memory -system.physmem.bytes_written::total 162752 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 923 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 1753664 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 58944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 58944 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 163072 # Number of bytes written to this memory +system.physmem.bytes_written::total 163072 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 921 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 26480 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27403 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2543 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2543 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 92740 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2660622 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2753362 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 92740 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 92740 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 255512 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 255512 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 255512 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 92740 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2660622 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3008874 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 27401 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2548 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2548 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 92545 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2660791 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2753336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 92545 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 92545 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 256031 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 256031 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 256031 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 92545 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2660791 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3009366 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1273927794 # number of cpu cycles simulated +system.cpu.numCycles 1273846896 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 155476696 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 155476696 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 26665974 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 76215157 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 75849392 # Number of BTB hits +system.cpu.BPredUnit.lookups 155381473 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 155381473 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 26661992 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 76481328 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 76085061 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 180766435 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1491872316 # Number of instructions fetch has processed -system.cpu.fetch.Branches 155476696 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 75849392 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 402325403 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 93614087 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 624018674 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 140 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1031 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 185889439 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8548075 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1273900868 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.002953 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.238276 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 180777781 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1491151373 # Number of instructions fetch has processed +system.cpu.fetch.Branches 155381473 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 76085061 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 402336644 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 93587210 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 623938160 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 145 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1139 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 185942531 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8615707 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1273819882 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.001935 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.237130 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 878792706 68.98% 68.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 24409433 1.92% 70.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14960209 1.17% 72.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 18025508 1.41% 73.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 26731742 2.10% 75.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18277101 1.43% 77.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 28493019 2.24% 79.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 39802935 3.12% 82.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 224408215 17.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 878702474 68.98% 68.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 24435713 1.92% 70.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 15105270 1.19% 72.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 18072889 1.42% 73.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26727903 2.10% 75.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18276740 1.43% 77.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 28604131 2.25% 79.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 39838610 3.13% 82.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 224056152 17.59% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1273900868 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.122045 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.171081 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 300130332 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 537055352 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 281851498 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 88074501 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 66789185 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2370363864 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 66789185 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 352614235 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 124117956 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1807 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 302560946 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 427816739 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2274265358 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 293377579 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 103041568 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 112 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 3464406080 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 7122244281 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 7122237233 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7048 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 2493860970 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 970545110 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 88 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 88 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 745535849 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 545979333 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 222242756 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 352158228 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 146951837 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2027253751 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 556 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1785885865 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 143298 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 405620982 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1049961378 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 506 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1273900868 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.401903 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.311945 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1273819882 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.121978 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.170589 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 300142098 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 537000439 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 281769365 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 88141967 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 66766013 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2369867389 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 66766013 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 352580189 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 124109997 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1918 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 302594361 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 427767404 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2274189452 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 293406849 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 103032322 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 51 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 3464260390 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 7121426016 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 7121418052 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7964 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 2493860878 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 970399512 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 94 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 94 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 745525627 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 545851562 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 222235793 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 352099065 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 146974262 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2027094513 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 587 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1785918647 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 140586 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 405462466 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1049512028 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 537 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1273819882 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.402018 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.312119 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 346798223 27.22% 27.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 447596849 35.14% 62.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 243149127 19.09% 81.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 151409869 11.89% 93.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 40759247 3.20% 96.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 32504128 2.55% 99.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9931846 0.78% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1400181 0.11% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 351398 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 346849812 27.23% 27.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 447400536 35.12% 62.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 243205365 19.09% 81.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 151321871 11.88% 93.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 40825213 3.20% 96.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 32566088 2.56% 99.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9897563 0.78% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1402374 0.11% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 351060 0.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1273900868 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1273819882 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 262837 10.20% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2136217 82.89% 93.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 178017 6.91% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 260443 10.10% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2141420 83.03% 93.13% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 177309 6.87% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 46812745 2.62% 2.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1067077874 59.75% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 46812744 2.62% 2.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1067089927 59.75% 62.37% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.37% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.37% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.37% # Type of FU issued @@ -194,158 +194,158 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.37% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 479524386 26.85% 89.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 192470860 10.78% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 479538721 26.85% 89.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 192477255 10.78% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1785885865 # Type of FU issued -system.cpu.iq.rate 1.401874 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2577071 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001443 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4848392282 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2433055974 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1727031567 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 685 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2066 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 68 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1741649976 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 215 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 208887212 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1785918647 # Type of FU issued +system.cpu.iq.rate 1.401988 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2579172 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001444 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4848376217 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2432738390 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1727118998 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 717 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2336 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 76 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1741684846 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 229 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 208839211 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 126937208 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 36775 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 189921 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 34056699 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 126809441 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 36531 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 190384 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 34049736 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2072 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 462 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2138 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 453 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 66789185 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 397482 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 85620 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2027254307 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 63893728 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 545979333 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 222242756 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 83 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 48032 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 669 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 189921 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2137684 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 24653436 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 26791120 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1767797184 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 473889834 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 18088681 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 66766013 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 400873 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 86074 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2027095100 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 63749855 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 545851562 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 222235793 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 88 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 48364 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 665 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 190384 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2138396 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 24649145 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 26787541 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1767801211 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 473822669 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 18117436 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 665730625 # number of memory reference insts executed -system.cpu.iew.exec_branches 109718993 # Number of branches executed -system.cpu.iew.exec_stores 191840791 # Number of stores executed -system.cpu.iew.exec_rate 1.387675 # Inst execution rate -system.cpu.iew.wb_sent 1728379028 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1727031635 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1262282896 # num instructions producing a value -system.cpu.iew.wb_consumers 2985352291 # num instructions consuming a value +system.cpu.iew.exec_refs 665669278 # number of memory reference insts executed +system.cpu.iew.exec_branches 109723805 # Number of branches executed +system.cpu.iew.exec_stores 191846609 # Number of stores executed +system.cpu.iew.exec_rate 1.387766 # Inst execution rate +system.cpu.iew.wb_sent 1728448502 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1727119074 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1262324846 # num instructions producing a value +system.cpu.iew.wb_consumers 2985456049 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.355675 # insts written-back per cycle +system.cpu.iew.wb_rate 1.355829 # insts written-back per cycle system.cpu.iew.wb_fanout 0.422825 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 880025312 # The number of committed instructions -system.cpu.commit.commitCommittedOps 1621493982 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 405765098 # The number of squashed insts skipped by commit +system.cpu.commit.commitCommittedInsts 880025277 # The number of committed instructions +system.cpu.commit.commitCommittedOps 1621493925 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 405606358 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 26666115 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1207111683 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.343284 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.660206 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 26662143 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1207053869 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.343348 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.659934 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 437166011 36.22% 36.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 432802967 35.85% 72.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 93484629 7.74% 79.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 134841213 11.17% 90.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 35727207 2.96% 93.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 23483214 1.95% 95.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 25551681 2.12% 98.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 8874954 0.74% 98.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 15179807 1.26% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 437041200 36.21% 36.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 432850092 35.86% 72.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 93447270 7.74% 79.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 134928627 11.18% 90.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 35706636 2.96% 93.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 23539949 1.95% 95.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 25505485 2.11% 98.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8872667 0.74% 98.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 15161943 1.26% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1207111683 # Number of insts commited each cycle -system.cpu.commit.committedInsts 880025312 # Number of instructions committed -system.cpu.commit.committedOps 1621493982 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1207053869 # Number of insts commited each cycle +system.cpu.commit.committedInsts 880025277 # Number of instructions committed +system.cpu.commit.committedOps 1621493925 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 607228182 # Number of memory references committed -system.cpu.commit.loads 419042125 # Number of loads committed +system.cpu.commit.refs 607228178 # Number of memory references committed +system.cpu.commit.loads 419042121 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 107161579 # Number of branches committed +system.cpu.commit.branches 107161574 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1621354492 # Number of committed integer instructions. +system.cpu.commit.int_insts 1621354435 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 15179807 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 15161943 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3219190956 # The number of ROB reads -system.cpu.rob.rob_writes 4121324121 # The number of ROB writes -system.cpu.timesIdled 604 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 26926 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 880025312 # Number of Instructions Simulated -system.cpu.committedOps 1621493982 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 880025312 # Number of Instructions Simulated -system.cpu.cpi 1.447604 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.447604 # CPI: Total CPI of All Threads -system.cpu.ipc 0.690797 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.690797 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4473882728 # number of integer regfile reads -system.cpu.int_regfile_writes 2589957068 # number of integer regfile writes -system.cpu.fp_regfile_reads 68 # number of floating regfile reads -system.cpu.misc_regfile_reads 911502074 # number of misc regfile reads -system.cpu.icache.replacements 17 # number of replacements -system.cpu.icache.tagsinuse 828.056964 # Cycle average of tags in use -system.cpu.icache.total_refs 185888078 # Total number of references to valid blocks. +system.cpu.rob.rob_reads 3218992209 # The number of ROB reads +system.cpu.rob.rob_writes 4120983322 # The number of ROB writes +system.cpu.timesIdled 600 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 27014 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 880025277 # Number of Instructions Simulated +system.cpu.committedOps 1621493925 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 880025277 # Number of Instructions Simulated +system.cpu.cpi 1.447512 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.447512 # CPI: Total CPI of All Threads +system.cpu.ipc 0.690841 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.690841 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4473913165 # number of integer regfile reads +system.cpu.int_regfile_writes 2590095162 # number of integer regfile writes +system.cpu.fp_regfile_reads 76 # number of floating regfile reads +system.cpu.misc_regfile_reads 911461004 # number of misc regfile reads +system.cpu.icache.replacements 22 # number of replacements +system.cpu.icache.tagsinuse 826.529270 # Cycle average of tags in use +system.cpu.icache.total_refs 185941160 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 930 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 199879.653763 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 199936.731183 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 828.056964 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.404325 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.404325 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 185888078 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 185888078 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 185888078 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 185888078 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 185888078 # number of overall hits -system.cpu.icache.overall_hits::total 185888078 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1361 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1361 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1361 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1361 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1361 # number of overall misses -system.cpu.icache.overall_misses::total 1361 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 47861000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 47861000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 47861000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 47861000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 47861000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 47861000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 185889439 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 185889439 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 185889439 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 185889439 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 185889439 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 185889439 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 826.529270 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.403579 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.403579 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 185941162 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 185941162 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 185941162 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 185941162 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 185941162 # number of overall hits +system.cpu.icache.overall_hits::total 185941162 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1369 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1369 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1369 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1369 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1369 # number of overall misses +system.cpu.icache.overall_misses::total 1369 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 47914000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 47914000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 47914000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 47914000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 47914000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 47914000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 185942531 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 185942531 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 185942531 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 185942531 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 185942531 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 185942531 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35166.054372 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35166.054372 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35166.054372 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35166.054372 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35166.054372 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35166.054372 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34999.269540 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34999.269540 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34999.269540 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34999.269540 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34999.269540 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34999.269540 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -354,94 +354,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 431 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 431 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 431 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 431 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 431 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 431 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 930 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 930 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 930 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 930 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 930 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 930 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 34220000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 34220000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 34220000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 34220000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34220000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 34220000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 435 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 435 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 435 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 435 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 435 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 435 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 934 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 934 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 934 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 934 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 934 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 934 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 34118000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 34118000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 34118000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 34118000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34118000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 34118000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36795.698925 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36795.698925 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36795.698925 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36795.698925 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36795.698925 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36795.698925 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36528.907923 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36528.907923 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36528.907923 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36528.907923 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36528.907923 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36528.907923 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 445433 # number of replacements -system.cpu.dcache.tagsinuse 4093.428364 # Cycle average of tags in use -system.cpu.dcache.total_refs 452731874 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 449529 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 1007.124955 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 738592000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.428364 # Average occupied blocks per requestor +system.cpu.dcache.replacements 445452 # number of replacements +system.cpu.dcache.tagsinuse 4093.428018 # Cycle average of tags in use +system.cpu.dcache.total_refs 452712586 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 449548 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 1007.039484 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 738623000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4093.428018 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999372 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999372 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 264792027 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 264792027 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 187939847 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 187939847 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 452731874 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 452731874 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 452731874 # number of overall hits -system.cpu.dcache.overall_hits::total 452731874 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 206669 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 206669 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 246210 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 246210 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 452879 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 452879 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 452879 # number of overall misses -system.cpu.dcache.overall_misses::total 452879 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1300622500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1300622500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2040839000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2040839000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 3341461500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 3341461500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 3341461500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 3341461500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 264998696 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 264998696 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits::cpu.data 264772769 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 264772769 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 187939813 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 187939813 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 452712582 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 452712582 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 452712582 # number of overall hits +system.cpu.dcache.overall_hits::total 452712582 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 206710 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 206710 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 246244 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 246244 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 452954 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 452954 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 452954 # number of overall misses +system.cpu.dcache.overall_misses::total 452954 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1296370500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1296370500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2046596000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2046596000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 3342966500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 3342966500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 3342966500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 3342966500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 264979479 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 264979479 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 453184753 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 453184753 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 453184753 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 453184753 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 453165536 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 453165536 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 453165536 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 453165536 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000780 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000780 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001308 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001308 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000999 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000999 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000999 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000999 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 6293.263624 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 6293.263624 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8289.017505 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 8289.017505 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 7378.265497 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 7378.265497 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 7378.265497 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 7378.265497 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001309 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001309 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.001000 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.001000 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.001000 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.001000 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 6271.445503 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 6271.445503 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8311.252254 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8311.252254 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 7380.366439 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 7380.366439 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 7380.366439 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 7380.366439 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -450,32 +450,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 428496 # number of writebacks -system.cpu.dcache.writebacks::total 428496 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3328 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3328 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 20 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 20 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3348 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3348 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3348 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3348 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203341 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 203341 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246190 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 246190 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 449531 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 449531 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 449531 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 449531 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 607771500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 607771500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1249776500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1249776500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1857548000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 1857548000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1857548000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 1857548000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 428527 # number of writebacks +system.cpu.dcache.writebacks::total 428527 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3377 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3377 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 23 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 23 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3400 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3400 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3400 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3400 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203333 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 203333 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246221 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 246221 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 449554 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 449554 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 449554 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 449554 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 608060000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 608060000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1250112000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1250112000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1858172000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 1858172000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1858172000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 1858172000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000767 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000767 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001308 # mshr miss rate for WriteReq accesses @@ -484,98 +484,102 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000992 system.cpu.dcache.demand_mshr_miss_rate::total 0.000992 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000992 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2988.927467 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2988.927467 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 5076.471425 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 5076.471425 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 4132.191106 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 4132.191106 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 4132.191106 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 4132.191106 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2990.463919 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2990.463919 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 5077.194878 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 5077.194878 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 4133.367738 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 4133.367738 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 4133.367738 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 4133.367738 # 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Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 737.283312 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 678.172973 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.635050 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.022500 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.020696 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.678246 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 7 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 198771 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 198778 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 428496 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 428496 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 224280 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.026781 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089067 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089067 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.990323 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058903 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060826 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990323 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058903 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060826 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32241.585233 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31099.362497 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31291.681901 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31013.975651 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31013.975651 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32241.585233 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31028.644260 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31069.413525 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32241.585233 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31028.644260 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31069.413525 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini index 6c78f711c..6d1d261c9 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini @@ -120,8 +120,8 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 -master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +width=8 +master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master [system.physmem] diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout index db4607fa4..177dd7f45 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 13:44:28 -gem5 started Jun 4 2012 15:08:17 +gem5 compiled Aug 13 2012 17:08:22 +gem5 started Aug 13 2012 18:24:05 gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 963992704000 because target called exit() +Exiting @ tick 963992671000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt index 0e02ab2e6..a463fb589 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.963993 # Number of seconds simulated -sim_ticks 963992704000 # Number of ticks simulated -final_tick 963992704000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 963992671000 # Number of ticks simulated +final_tick 963992671000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1254577 # Simulator instruction rate (inst/s) -host_op_rate 2311626 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1374282564 # Simulator tick rate (ticks/s) -host_mem_usage 216676 # Number of bytes of host memory used -host_seconds 701.45 # Real time elapsed on the host -sim_insts 880025313 # Number of instructions simulated -sim_ops 1621493983 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 9492133912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1842452913 # Number of bytes read from this memory -system.physmem.bytes_read::total 11334586825 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 9492133912 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 9492133912 # Number of instructions bytes read from this memory +host_inst_rate 1263596 # Simulator instruction rate (inst/s) +host_op_rate 2328243 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1384161146 # Simulator tick rate (ticks/s) +host_mem_usage 224820 # Number of bytes of host memory used +host_seconds 696.45 # Real time elapsed on the host +sim_insts 880025278 # Number of instructions simulated +sim_ops 1621493926 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 9492133560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1842452909 # Number of bytes read from this memory +system.physmem.bytes_read::total 11334586469 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 9492133560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 9492133560 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 864451000 # Number of bytes written to this memory system.physmem.bytes_written::total 864451000 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1186516739 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 419042125 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1605558864 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1186516695 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 419042121 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1605558816 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 188186057 # Number of write requests responded to by this memory system.physmem.num_writes::total 188186057 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 9846686466 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1911272674 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 11757959140 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 9846686466 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 9846686466 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 896740189 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 896740189 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 9846686466 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2808012863 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12654699330 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 9846686438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1911272735 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11757959173 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 9846686438 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 9846686438 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 896740220 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 896740220 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 9846686438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2808012955 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12654699393 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1927985409 # number of cpu cycles simulated +system.cpu.numCycles 1927985343 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 880025313 # Number of instructions committed -system.cpu.committedOps 1621493983 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses +system.cpu.committedInsts 880025278 # Number of instructions committed +system.cpu.committedOps 1621493926 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1621354436 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 99478861 # number of instructions that are conditional controls -system.cpu.num_int_insts 1621354493 # number of integer instructions +system.cpu.num_conditional_control_insts 99478856 # number of instructions that are conditional controls +system.cpu.num_int_insts 1621354436 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 5129484088 # number of times the integer registers were read -system.cpu.num_int_register_writes 2493860970 # number of times the integer registers were written +system.cpu.num_int_register_reads 5129483910 # number of times the integer registers were read +system.cpu.num_int_register_writes 2493860878 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 607228182 # number of memory refs -system.cpu.num_load_insts 419042125 # Number of load instructions +system.cpu.num_mem_refs 607228178 # number of memory refs +system.cpu.num_load_insts 419042121 # Number of load instructions system.cpu.num_store_insts 188186057 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1927985409 # Number of busy cycles +system.cpu.num_busy_cycles 1927985343 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini index 2eec436ef..05ff130e5 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini @@ -179,7 +179,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing +cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing egid=100 env= errout=cerr @@ -202,7 +202,7 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout index d6878297d..371c8d53f 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:58:39 -gem5 started Jul 2 2012 13:03:08 +gem5 compiled Aug 13 2012 17:08:22 +gem5 started Aug 13 2012 18:30:12 gem5 executing on zizzer -command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 1801979727000 because target called exit() +Exiting @ tick 1801979679000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt index 79bdadab4..12b9ffa30 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.801980 # Number of seconds simulated -sim_ticks 1801979727000 # Number of ticks simulated -final_tick 1801979727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1801979679000 # Number of ticks simulated +final_tick 1801979679000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 622629 # Simulator instruction rate (inst/s) -host_op_rate 1147227 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1274922997 # Simulator tick rate (ticks/s) -host_mem_usage 228496 # Number of bytes of host memory used -host_seconds 1413.40 # Real time elapsed on the host -sim_insts 880025313 # Number of instructions simulated -sim_ops 1621493983 # Number of ops (including micro ops) simulated +host_inst_rate 670221 # Simulator instruction rate (inst/s) +host_op_rate 1234919 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1372375195 # Simulator tick rate (ticks/s) +host_mem_usage 233400 # Number of bytes of host memory used +host_seconds 1313.04 # Real time elapsed on the host +sim_insts 880025278 # Number of instructions simulated +sim_ops 1621493926 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1682368 # Number of bytes read from this memory system.physmem.bytes_read::total 1728576 # Number of bytes read from this memory @@ -35,43 +35,43 @@ system.physmem.bw_total::cpu.inst 25643 # To system.physmem.bw_total::cpu.data 933622 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1048411 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 3603959454 # number of cpu cycles simulated +system.cpu.numCycles 3603959358 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 880025313 # Number of instructions committed -system.cpu.committedOps 1621493983 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses +system.cpu.committedInsts 880025278 # Number of instructions committed +system.cpu.committedOps 1621493926 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1621354436 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 99478861 # number of instructions that are conditional controls -system.cpu.num_int_insts 1621354493 # number of integer instructions +system.cpu.num_conditional_control_insts 99478856 # number of instructions that are conditional controls +system.cpu.num_int_insts 1621354436 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 5129484088 # number of times the integer registers were read -system.cpu.num_int_register_writes 2493860970 # number of times the integer registers were written +system.cpu.num_int_register_reads 5129483910 # number of times the integer registers were read +system.cpu.num_int_register_writes 2493860878 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 607228182 # number of memory refs -system.cpu.num_load_insts 419042125 # Number of load instructions +system.cpu.num_mem_refs 607228178 # number of memory refs +system.cpu.num_load_insts 419042121 # Number of load instructions system.cpu.num_store_insts 188186057 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 3603959454 # Number of busy cycles +system.cpu.num_busy_cycles 3603959358 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.tagsinuse 660.169533 # Cycle average of tags in use -system.cpu.icache.total_refs 1186516018 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 660.169550 # Cycle average of tags in use +system.cpu.icache.total_refs 1186515974 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1643373.986150 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1643373.925208 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 660.169533 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 660.169550 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.322348 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.322348 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1186516018 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1186516018 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1186516018 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1186516018 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1186516018 # number of overall hits -system.cpu.icache.overall_hits::total 1186516018 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 1186515974 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1186515974 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1186515974 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1186515974 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1186515974 # number of overall hits +system.cpu.icache.overall_hits::total 1186515974 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 722 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 722 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 722 # number of demand (read+write) misses @@ -84,12 +84,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 40521000 system.cpu.icache.demand_miss_latency::total 40521000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 40521000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 40521000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1186516740 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1186516740 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1186516740 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1186516740 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1186516740 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1186516740 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 1186516696 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1186516696 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1186516696 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1186516696 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1186516696 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1186516696 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses @@ -136,22 +136,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53123.268698 system.cpu.icache.overall_avg_mshr_miss_latency::total 53123.268698 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 437952 # number of replacements -system.cpu.dcache.tagsinuse 4094.884021 # Cycle average of tags in use -system.cpu.dcache.total_refs 606786134 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4094.884130 # Cycle average of tags in use +system.cpu.dcache.total_refs 606786130 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 1372.670239 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 788858000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.884021 # Average occupied blocks per requestor +system.cpu.dcache.avg_refs 1372.670230 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 788810000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.884130 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999728 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999728 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 418844799 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 418844799 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 418844795 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 418844795 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 187941335 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 187941335 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 606786134 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 606786134 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 606786134 # number of overall hits -system.cpu.dcache.overall_hits::total 606786134 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 606786130 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 606786130 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 606786130 # number of overall hits +system.cpu.dcache.overall_hits::total 606786130 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 197326 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 197326 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 244722 # number of WriteReq misses @@ -168,14 +168,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 7311185000 system.cpu.dcache.demand_miss_latency::total 7311185000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 7311185000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 7311185000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 419042125 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 419042125 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 419042121 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 419042121 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 607228182 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 607228182 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 607228182 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 607228182 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 607228178 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 607228178 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 607228178 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 607228178 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000471 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000471 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001300 # miss rate for WriteReq accesses @@ -236,14 +236,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13539.346406 system.cpu.dcache.overall_avg_mshr_miss_latency::total 13539.346406 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2581 # number of replacements -system.cpu.l2cache.tagsinuse 22161.849584 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 22161.850174 # Cycle average of tags in use system.cpu.l2cache.total_refs 506758 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23832 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 21.263763 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21018.400125 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 596.832039 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 546.617420 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 21018.400685 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 596.832055 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 546.617434 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.641431 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.018214 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.016681 # Average percentage of cache occupancy diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini index a0039b696..771a85baa 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini @@ -99,8 +99,8 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 -master=system.physmem.port[0] +width=8 +master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.physmem] diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout index c071d26fa..fddfdedb3 100755 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:01:47 -gem5 started Jun 4 2012 14:53:37 +gem5 compiled Aug 13 2012 17:04:37 +gem5 started Aug 13 2012 18:13:50 gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second @@ -23,4 +23,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 122215830000 because target called exit() +Exiting @ tick 122215823500 because target called exit() diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt index 804f585d6..7dd162db7 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.122216 # Number of seconds simulated -sim_ticks 122215830000 # Number of ticks simulated -final_tick 122215830000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 122215823500 # Number of ticks simulated +final_tick 122215823500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2951739 # Simulator instruction rate (inst/s) -host_op_rate 2951861 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1479540198 # Simulator tick rate (ticks/s) -host_mem_usage 346528 # Number of bytes of host memory used -host_seconds 82.60 # Real time elapsed on the host -sim_insts 243825163 # Number of instructions simulated -sim_ops 243835278 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 977686044 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 328674009 # Number of bytes read from this memory -system.physmem.bytes_read::total 1306360053 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 977686044 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 977686044 # Number of instructions bytes read from this memory +host_inst_rate 2900370 # Simulator instruction rate (inst/s) +host_op_rate 2900489 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1453791405 # Simulator tick rate (ticks/s) +host_mem_usage 355144 # Number of bytes of host memory used +host_seconds 84.07 # Real time elapsed on the host +sim_insts 243825150 # Number of instructions simulated +sim_ops 243835265 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 977685992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 328674008 # Number of bytes read from this memory +system.physmem.bytes_read::total 1306360000 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 977685992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 977685992 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 91606089 # Number of bytes written to this memory system.physmem.bytes_written::total 91606089 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 244421511 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 82220434 # Number of read requests responded to by this memory -system.physmem.num_reads::total 326641945 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 244421498 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 82220433 # Number of read requests responded to by this memory +system.physmem.num_reads::total 326641931 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 22901951 # Number of write requests responded to by this memory system.physmem.num_writes::total 22901951 # Number of write requests responded to by this memory system.physmem.num_other::cpu.data 3886 # Number of other requests responded to by this memory system.physmem.num_other::total 3886 # Number of other requests responded to by this memory system.physmem.bw_read::cpu.inst 7999667834 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2689291633 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10688959466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2689291768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10688959601 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 7999667834 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 7999667834 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 749543566 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 749543566 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 749543606 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 749543606 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::cpu.inst 7999667834 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3438835198 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11438503032 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3438835373 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11438503207 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 443 # Number of system calls -system.cpu.numCycles 244431661 # number of cpu cycles simulated +system.cpu.numCycles 244431648 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 243825163 # Number of instructions committed -system.cpu.committedOps 243835278 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 194726506 # Number of integer alu accesses +system.cpu.committedInsts 243825150 # Number of instructions committed +system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses system.cpu.num_func_calls 4252956 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18619960 # number of instructions that are conditional controls -system.cpu.num_int_insts 194726506 # number of integer instructions +system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls +system.cpu.num_int_insts 194726494 # number of integer instructions system.cpu.num_fp_insts 11630 # number of float instructions -system.cpu.num_int_register_reads 456819010 # number of times the integer registers were read -system.cpu.num_int_register_writes 215451567 # number of times the integer registers were written +system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read +system.cpu.num_int_register_writes 215451554 # number of times the integer registers were written system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read system.cpu.num_fp_register_writes 90 # number of times the floating registers were written -system.cpu.num_mem_refs 105711442 # number of memory refs -system.cpu.num_load_insts 82803522 # Number of load instructions +system.cpu.num_mem_refs 105711441 # number of memory refs +system.cpu.num_load_insts 82803521 # Number of load instructions system.cpu.num_store_insts 22907920 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 244431661 # Number of busy cycles +system.cpu.num_busy_cycles 244431648 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini index 2ba8ced6e..22dd9c24e 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini @@ -158,7 +158,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing +cwd=build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing egid=100 env= errout=cerr @@ -181,7 +181,7 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout index f34d81d26..869cdf524 100755 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:54:18 -gem5 started Jul 2 2012 12:31:43 +gem5 compiled Aug 13 2012 17:04:37 +gem5 started Aug 13 2012 18:15:25 gem5 executing on zizzer -command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +23,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 362481577000 because target called exit() +Exiting @ tick 362481563000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 5f77178bc..44702e46f 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.362482 # Number of seconds simulated -sim_ticks 362481577000 # Number of ticks simulated -final_tick 362481577000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 362481563000 # Number of ticks simulated +final_tick 362481563000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1217197 # Simulator instruction rate (inst/s) -host_op_rate 1217247 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1809539933 # Simulator tick rate (ticks/s) -host_mem_usage 354248 # Number of bytes of host memory used -host_seconds 200.32 # Real time elapsed on the host -sim_insts 243825163 # Number of instructions simulated -sim_ops 243835278 # Number of ops (including micro ops) simulated +host_inst_rate 1415125 # Simulator instruction rate (inst/s) +host_op_rate 1415183 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2103788292 # Simulator tick rate (ticks/s) +host_mem_usage 363728 # Number of bytes of host memory used +host_seconds 172.30 # Real time elapsed on the host +sim_insts 243825150 # Number of instructions simulated +sim_ops 243835265 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory system.physmem.bytes_read::total 998592 # Number of bytes read from this memory @@ -28,43 +28,43 @@ system.physmem.bw_total::cpu.inst 155197 # To system.physmem.bw_total::cpu.data 2599680 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2754877 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 443 # Number of system calls -system.cpu.numCycles 724963154 # number of cpu cycles simulated +system.cpu.numCycles 724963126 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 243825163 # Number of instructions committed -system.cpu.committedOps 243835278 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 194726506 # Number of integer alu accesses +system.cpu.committedInsts 243825150 # Number of instructions committed +system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses system.cpu.num_func_calls 4252956 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18619960 # number of instructions that are conditional controls -system.cpu.num_int_insts 194726506 # number of integer instructions +system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls +system.cpu.num_int_insts 194726494 # number of integer instructions system.cpu.num_fp_insts 11630 # number of float instructions -system.cpu.num_int_register_reads 456819010 # number of times the integer registers were read -system.cpu.num_int_register_writes 215451566 # number of times the integer registers were written +system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read +system.cpu.num_int_register_writes 215451553 # number of times the integer registers were written system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read system.cpu.num_fp_register_writes 90 # number of times the floating registers were written -system.cpu.num_mem_refs 105711442 # number of memory refs -system.cpu.num_load_insts 82803522 # Number of load instructions +system.cpu.num_mem_refs 105711441 # number of memory refs +system.cpu.num_load_insts 82803521 # Number of load instructions system.cpu.num_store_insts 22907920 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 724963154 # Number of busy cycles +system.cpu.num_busy_cycles 724963126 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 25 # number of replacements -system.cpu.icache.tagsinuse 725.564686 # Cycle average of tags in use -system.cpu.icache.total_refs 244420630 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 725.564713 # Cycle average of tags in use +system.cpu.icache.total_refs 244420617 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 277120.895692 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 277120.880952 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 725.564686 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 725.564713 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.354280 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.354280 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 244420630 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 244420630 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 244420630 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 244420630 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 244420630 # number of overall hits -system.cpu.icache.overall_hits::total 244420630 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 244420617 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 244420617 # number of overall hits +system.cpu.icache.overall_hits::total 244420617 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses @@ -77,12 +77,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 49333000 system.cpu.icache.demand_miss_latency::total 49333000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 49333000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 49333000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 244421512 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 244421512 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 244421512 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 244421512 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 244421512 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 244421512 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 244421499 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 244421499 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 244421499 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses @@ -129,24 +129,24 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52933.106576 system.cpu.icache.overall_avg_mshr_miss_latency::total 52933.106576 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 935475 # number of replacements -system.cpu.dcache.tagsinuse 3563.804804 # Cycle average of tags in use -system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3563.804941 # Cycle average of tags in use +system.cpu.dcache.total_refs 104186699 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 110.887522 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 134384281000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3563.804804 # Average occupied blocks per requestor +system.cpu.dcache.avg_refs 110.887521 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 134384267000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 3563.804941 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.870070 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.870070 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 81327577 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 81327577 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 104182818 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 104182818 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 104182818 # number of overall hits -system.cpu.dcache.overall_hits::total 104182818 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits +system.cpu.dcache.overall_hits::total 104182817 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses @@ -167,16 +167,16 @@ system.cpu.dcache.demand_miss_latency::cpu.data 13778134000 system.cpu.dcache.demand_miss_latency::total 13778134000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 13778134000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 13778134000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 82220434 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 82220434 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 105122385 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 105122385 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 105122385 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 105122385 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses @@ -249,14 +249,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11664.344320 system.cpu.dcache.overall_avg_mshr_miss_latency::total 11664.344320 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 9744.633089 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 9744.633464 # Cycle average of tags in use system.cpu.l2cache.total_refs 1813121 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 15586 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 116.330104 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 8861.504688 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 738.799807 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 144.328594 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 8861.505031 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 738.799835 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 144.328599 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.270432 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.022546 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.004405 # Average percentage of cache occupancy diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini index 02825e2f4..c43765666 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -510,7 +510,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing +cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing egid=100 env= errout=cerr @@ -533,7 +533,7 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout index dec2c9148..29d21ef45 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:58:39 -gem5 started Jul 2 2012 13:12:36 +gem5 compiled Aug 13 2012 17:08:22 +gem5 started Aug 13 2012 18:35:52 gem5 executing on zizzer -command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,6 +23,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -info: Increasing stack size by one page. -info: Increasing stack size by one page. -Exiting @ tick 68340167000 because target called exit() +Exiting @ tick 68408131000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 4e7a26f12..740e607ea 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,137 +1,137 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.068340 # Number of seconds simulated -sim_ticks 68340167000 # Number of ticks simulated -final_tick 68340167000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.068408 # Number of seconds simulated +sim_ticks 68408131000 # Number of ticks simulated +final_tick 68408131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 107513 # Simulator instruction rate (inst/s) -host_op_rate 189313 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46506224 # Simulator tick rate (ticks/s) -host_mem_usage 365660 # Number of bytes of host memory used -host_seconds 1469.48 # Real time elapsed on the host -sim_insts 157988582 # Number of instructions simulated -sim_ops 278192519 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 68608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1893120 # Number of bytes read from this memory -system.physmem.bytes_read::total 1961728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 68608 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 68608 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 20288 # Number of bytes written to this memory -system.physmem.bytes_written::total 20288 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1072 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29580 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30652 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 317 # Number of write requests responded to by this memory -system.physmem.num_writes::total 317 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1003919 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 27701425 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 28705344 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1003919 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1003919 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 296868 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 296868 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 296868 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1003919 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 27701425 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 29002212 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 92617 # Simulator instruction rate (inst/s) +host_op_rate 163083 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40102422 # Simulator tick rate (ticks/s) +host_mem_usage 370556 # Number of bytes of host memory used +host_seconds 1705.84 # Real time elapsed on the host +sim_insts 157988547 # Number of instructions simulated +sim_ops 278192462 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 68352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1892736 # Number of bytes read from this memory +system.physmem.bytes_read::total 1961088 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 68352 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 68352 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 20352 # Number of bytes written to this memory +system.physmem.bytes_written::total 20352 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1068 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29574 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30642 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 318 # Number of write requests responded to by this memory +system.physmem.num_writes::total 318 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 999179 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 27668290 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 28667469 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 999179 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 999179 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 297508 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 297508 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 297508 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 999179 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 27668290 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 28964978 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 136680335 # number of cpu cycles simulated +system.cpu.numCycles 136816263 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 36129289 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 36129289 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1086629 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 25668657 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 25566381 # Number of BTB hits +system.cpu.BPredUnit.lookups 36128371 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 36128371 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1086051 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 25676514 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 25568930 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 28038648 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 196448149 # Number of instructions fetch has processed -system.cpu.fetch.Branches 36129289 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 25566381 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 59446336 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8437809 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 41835148 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 182 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 27320717 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 151811 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 136641889 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.527241 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.343736 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28040484 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 196465722 # Number of instructions fetch has processed +system.cpu.fetch.Branches 36128371 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 25568930 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 59455138 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 8440333 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 41957570 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 37 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 207 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 27323760 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 153045 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 136778320 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.524833 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.343005 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 79944033 58.51% 58.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2167208 1.59% 60.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2997757 2.19% 62.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4111297 3.01% 65.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8027988 5.88% 71.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5053640 3.70% 74.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2897429 2.12% 76.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1474644 1.08% 78.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 29967893 21.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 80075177 58.54% 58.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2168654 1.59% 60.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2999031 2.19% 62.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4111689 3.01% 65.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8029506 5.87% 71.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5053851 3.69% 74.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2898853 2.12% 77.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1472297 1.08% 78.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 29969262 21.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 136641889 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.264334 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.437282 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 40756149 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 32464330 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 46271327 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9828540 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 7321543 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 341364323 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 7321543 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 46061495 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 6368629 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8995 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 50367831 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 26513396 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 337564097 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 23 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5026 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 24245573 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 73928 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 414895608 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1010438546 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1010435932 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2614 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 341010940 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 73884668 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 483 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 475 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 57387793 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 108215751 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 37227533 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 46388866 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 7855106 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 331925513 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2461 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 311467723 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 186069 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 53480941 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 93052835 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2015 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 136641889 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.279445 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.722907 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 136778320 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.264065 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.435982 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 40775641 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 32574420 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 46270758 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9832617 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 7324884 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 341365831 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 7324884 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 46092133 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 6411510 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9224 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 50365166 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 26575403 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 337580749 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 29 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5005 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 24325640 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 73870 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 414916926 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1010481124 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1010477953 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3171 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 341010848 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 73906078 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 481 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 476 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 57495301 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 108229908 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 37227556 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 46399442 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8017088 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 331952532 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2380 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 311468511 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 188619 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 53509766 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 93151802 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1934 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 136778320 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.277177 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.722818 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 29493706 21.58% 21.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 18268502 13.37% 34.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 26067174 19.08% 54.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 31248056 22.87% 76.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 17426975 12.75% 89.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8824728 6.46% 96.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 3769643 2.76% 98.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1473533 1.08% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 69572 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 29621399 21.66% 21.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 18208303 13.31% 34.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 26183268 19.14% 54.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 31189173 22.80% 76.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 17472478 12.77% 89.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8789771 6.43% 96.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3781191 2.76% 98.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1461656 1.07% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 71081 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 136641889 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 136778320 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 22788 1.09% 1.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 22736 1.09% 1.09% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 1.09% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 1.09% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.09% # attempts to use FU when none available @@ -160,15 +160,15 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.09% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.09% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.09% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1944579 92.77% 93.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 128653 6.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1942986 92.77% 93.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 128630 6.14% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 29247 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 177257579 56.91% 56.92% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 177262228 56.91% 56.92% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.92% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 116 0.00% 56.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 143 0.00% 56.92% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.92% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.92% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.92% # Type of FU issued @@ -194,159 +194,159 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.92% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.92% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.92% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 99693088 32.01% 88.93% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 34487693 11.07% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 99693377 32.01% 88.93% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 34483516 11.07% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 311467723 # Type of FU issued -system.cpu.iq.rate 2.278804 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2096020 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006729 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 761858485 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 385440526 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 308377955 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 939 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1362 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 296 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 313534078 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 418 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 52563213 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 311468511 # Type of FU issued +system.cpu.iq.rate 2.276546 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2094352 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006724 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 761997211 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 385495678 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 308386892 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1102 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1693 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 371 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 313533109 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 507 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 52559129 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 17436363 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 94862 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 33518 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 5787782 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 17450524 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 94828 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 33225 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 5787805 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3294 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 766 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3313 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 747 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 7321543 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 823106 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 106434 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 331927974 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 49382 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 108215751 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 37227533 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 475 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1169 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 29139 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 33518 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 614396 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 578149 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1192545 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 309546199 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 99164124 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1921524 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 7324884 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 821379 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 106718 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 331954912 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 49233 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 108229908 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 37227556 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 477 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1080 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 29147 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 33225 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 614391 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 577456 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1191847 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 309549319 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 99164391 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1919192 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 133270548 # number of memory reference insts executed -system.cpu.iew.exec_branches 31554842 # Number of branches executed -system.cpu.iew.exec_stores 34106424 # Number of stores executed -system.cpu.iew.exec_rate 2.264746 # Inst execution rate -system.cpu.iew.wb_sent 308908711 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 308378251 # cumulative count of insts written-back -system.cpu.iew.wb_producers 227159905 # num instructions producing a value -system.cpu.iew.wb_consumers 466461304 # num instructions consuming a value +system.cpu.iew.exec_refs 133267604 # number of memory reference insts executed +system.cpu.iew.exec_branches 31551799 # Number of branches executed +system.cpu.iew.exec_stores 34103213 # Number of stores executed +system.cpu.iew.exec_rate 2.262518 # Inst execution rate +system.cpu.iew.wb_sent 308913193 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 308387263 # cumulative count of insts written-back +system.cpu.iew.wb_producers 227149501 # num instructions producing a value +system.cpu.iew.wb_consumers 466434365 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.256201 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.486986 # average fanout of values written-back +system.cpu.iew.wb_rate 2.254025 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.486991 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 157988582 # The number of committed instructions -system.cpu.commit.commitCommittedOps 278192519 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 53739498 # The number of squashed insts skipped by commit +system.cpu.commit.commitCommittedInsts 157988547 # The number of committed instructions +system.cpu.commit.commitCommittedOps 278192462 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 53766564 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1086653 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 129320346 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.151189 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.664667 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1086077 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 129453436 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.148977 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.662392 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 48978430 37.87% 37.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 24328173 18.81% 56.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 16731567 12.94% 69.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12545678 9.70% 79.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3454921 2.67% 82.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 3553253 2.75% 84.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2757236 2.13% 86.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1133891 0.88% 87.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 15837197 12.25% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 48953386 37.82% 37.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 24330343 18.79% 56.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 17047293 13.17% 69.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12542277 9.69% 79.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3298814 2.55% 82.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3552746 2.74% 84.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2756547 2.13% 86.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1133806 0.88% 87.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 15838224 12.23% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 129320346 # Number of insts commited each cycle -system.cpu.commit.committedInsts 157988582 # Number of instructions committed -system.cpu.commit.committedOps 278192519 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 129453436 # Number of insts commited each cycle +system.cpu.commit.committedInsts 157988547 # Number of instructions committed +system.cpu.commit.committedOps 278192462 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 122219139 # Number of memory references committed -system.cpu.commit.loads 90779388 # Number of loads committed +system.cpu.commit.refs 122219135 # Number of memory references committed +system.cpu.commit.loads 90779384 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 29309710 # Number of branches committed +system.cpu.commit.branches 29309705 # Number of branches committed system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. -system.cpu.commit.int_insts 278186227 # Number of committed integer instructions. +system.cpu.commit.int_insts 278186170 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 15837197 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 15838224 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 445415166 # The number of ROB reads -system.cpu.rob.rob_writes 671194708 # The number of ROB writes -system.cpu.timesIdled 2012 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 38446 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 157988582 # Number of Instructions Simulated -system.cpu.committedOps 278192519 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 157988582 # Number of Instructions Simulated -system.cpu.cpi 0.865128 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.865128 # CPI: Total CPI of All Threads -system.cpu.ipc 1.155898 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.155898 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 705405399 # number of integer regfile reads -system.cpu.int_regfile_writes 373270395 # number of integer regfile writes -system.cpu.fp_regfile_reads 345 # number of floating regfile reads -system.cpu.fp_regfile_writes 188 # number of floating regfile writes -system.cpu.misc_regfile_reads 197984504 # number of misc regfile reads -system.cpu.icache.replacements 90 # number of replacements -system.cpu.icache.tagsinuse 845.686115 # Cycle average of tags in use -system.cpu.icache.total_refs 27319306 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1079 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 25319.097312 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 445574238 # The number of ROB reads +system.cpu.rob.rob_writes 671251501 # The number of ROB writes +system.cpu.timesIdled 1985 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 37943 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 157988547 # Number of Instructions Simulated +system.cpu.committedOps 278192462 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated +system.cpu.cpi 0.865988 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.865988 # CPI: Total CPI of All Threads +system.cpu.ipc 1.154750 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.154750 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 705392602 # number of integer regfile reads +system.cpu.int_regfile_writes 373276329 # number of integer regfile writes +system.cpu.fp_regfile_reads 441 # number of floating regfile reads +system.cpu.fp_regfile_writes 230 # number of floating regfile writes +system.cpu.misc_regfile_reads 197984249 # number of misc regfile reads +system.cpu.icache.replacements 87 # number of replacements +system.cpu.icache.tagsinuse 844.199846 # Cycle average of tags in use +system.cpu.icache.total_refs 27322358 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1076 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 25392.526022 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 845.686115 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.412933 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.412933 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 27319307 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27319307 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27319307 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27319307 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27319307 # number of overall hits -system.cpu.icache.overall_hits::total 27319307 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1410 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1410 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1410 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1410 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1410 # number of overall misses -system.cpu.icache.overall_misses::total 1410 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 52106500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 52106500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 52106500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 52106500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 52106500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 52106500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27320717 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27320717 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27320717 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27320717 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27320717 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27320717 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36954.964539 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36954.964539 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36954.964539 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36954.964539 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36954.964539 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36954.964539 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 844.199846 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.412207 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.412207 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 27322358 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27322358 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27322358 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27322358 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27322358 # number of overall hits +system.cpu.icache.overall_hits::total 27322358 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1402 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1402 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1402 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1402 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1402 # number of overall misses +system.cpu.icache.overall_misses::total 1402 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 51713500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 51713500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 51713500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 51713500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 51713500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 51713500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27323760 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27323760 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27323760 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27323760 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27323760 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27323760 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000051 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36885.520685 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36885.520685 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36885.520685 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36885.520685 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36885.520685 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36885.520685 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -355,94 +355,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 328 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 328 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 328 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 328 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 328 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 328 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1082 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1082 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1082 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1082 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1082 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1082 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39682000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 39682000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39682000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 39682000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39682000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 39682000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36674.676525 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36674.676525 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36674.676525 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36674.676525 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36674.676525 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36674.676525 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 325 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 325 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 325 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 325 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 325 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 325 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1077 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1077 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1077 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1077 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1077 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1077 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39505500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 39505500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39505500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 39505500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39505500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 39505500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36681.058496 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36681.058496 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36681.058496 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36681.058496 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36681.058496 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36681.058496 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2072150 # number of replacements -system.cpu.dcache.tagsinuse 4072.380318 # Cycle average of tags in use -system.cpu.dcache.total_refs 75593684 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2076246 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 36.408828 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 22734551000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4072.380318 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994233 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994233 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 44236411 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 44236411 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31357262 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31357262 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 75593673 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 75593673 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 75593673 # number of overall hits -system.cpu.dcache.overall_hits::total 75593673 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2315078 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2315078 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 82489 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 82489 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2397567 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2397567 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2397567 # number of overall misses -system.cpu.dcache.overall_misses::total 2397567 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 16784018500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 16784018500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1571310000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1571310000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18355328500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18355328500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18355328500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18355328500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 46551489 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 46551489 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 2072121 # number of replacements +system.cpu.dcache.tagsinuse 4072.371520 # Cycle average of tags in use +system.cpu.dcache.total_refs 75597840 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2076217 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 36.411339 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 22802887000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4072.371520 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994231 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994231 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 44240568 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 44240568 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31357263 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31357263 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 75597831 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 75597831 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 75597831 # number of overall hits +system.cpu.dcache.overall_hits::total 75597831 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2315103 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2315103 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 82488 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 82488 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2397591 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2397591 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2397591 # number of overall misses +system.cpu.dcache.overall_misses::total 2397591 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 16770812000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 16770812000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1571570000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1571570000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18342382000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18342382000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18342382000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18342382000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 46555671 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 46555671 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 77991240 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 77991240 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 77991240 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 77991240 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049732 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.049732 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 77995422 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 77995422 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 77995422 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 77995422 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049728 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.049728 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002624 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.002624 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.030741 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.030741 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.030741 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.030741 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7249.871711 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 7249.871711 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 19048.721648 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 19048.721648 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 7655.814624 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 7655.814624 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 7655.814624 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 7655.814624 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.030740 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.030740 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.030740 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.030740 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7244.088924 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 7244.088924 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 19052.104549 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 19052.104549 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 7650.338194 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 7650.338194 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 7650.338194 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 7650.338194 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -451,140 +451,138 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2064802 # number of writebacks -system.cpu.dcache.writebacks::total 2064802 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 320846 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 320846 # number of ReadReq MSHR hits +system.cpu.dcache.writebacks::writebacks 2065063 # number of writebacks +system.cpu.dcache.writebacks::total 2065063 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 320901 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 320901 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 469 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 469 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 321315 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 321315 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 321315 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 321315 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994232 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994232 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82020 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82020 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076252 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076252 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076252 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076252 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6184007000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6184007000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1313707000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1313707000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7497714000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7497714000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7497714000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7497714000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.042839 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.042839 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 321370 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 321370 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 321370 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 321370 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994202 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994202 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82019 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82019 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076221 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076221 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076221 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076221 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6183631000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6183631000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1313937000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1313937000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7497568000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7497568000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7497568000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7497568000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.042835 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.042835 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002609 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002609 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026622 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026622 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026622 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.026622 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 3100.946630 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 3100.946630 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16016.910510 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16016.910510 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3611.177256 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 3611.177256 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3611.177256 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 3611.177256 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026620 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.026620 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026620 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.026620 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 3100.804733 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 3100.804733 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16019.910021 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16019.910021 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3611.160854 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 3611.160854 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3611.160854 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 3611.160854 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # 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Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 233.440777 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.597809 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.008019 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.007124 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.612953 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 7 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1993528 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1993535 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2064802 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2064802 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits +system.cpu.l2cache.occ_blocks::writebacks 19572.608886 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 263.032470 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 232.337716 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.597309 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.008027 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.007090 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.612426 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 8 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1993505 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1993513 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2065063 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2065063 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 53141 # 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number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1048370500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 38191500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1010179000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1048370500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1079 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1994116 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1995195 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2064802 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2064802 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 3 # 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number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1010013500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1047999500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 37986000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1010013500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1047999500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1076 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1994087 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1995163 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2065063 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2065063 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 82133 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 82133 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1079 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2076249 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2077328 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1079 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2076249 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2077328 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993513 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000295 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000832 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.666667 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.666667 # miss rate for UpgradeReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1076 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2076220 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2077296 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1076 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2076220 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2077296 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992565 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000292 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000827 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352988 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.352988 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993513 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.014247 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.014755 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993513 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.014247 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.014755 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35626.399254 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35507.653061 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 35584.337349 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34123.223648 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34123.223648 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35626.399254 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34150.743746 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34202.352212 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35626.399254 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34150.743746 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34202.352212 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992565 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014244 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014751 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992565 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014244 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014751 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35567.415730 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35567.869416 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 35567.575758 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34123.654801 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34123.654801 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35567.415730 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34152.076148 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34201.406566 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35567.415730 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34152.076148 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34201.406566 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -593,60 +591,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 317 # number of writebacks -system.cpu.l2cache.writebacks::total 317 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1072 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 588 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1660 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 318 # number of writebacks +system.cpu.l2cache.writebacks::total 318 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1068 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 582 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1650 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28992 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 28992 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1072 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 29580 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 30652 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1072 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 29580 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 30652 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34797000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19023000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53820000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 62000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 62000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 899044500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 899044500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34797000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 918067500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 952864500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34797000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 918067500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 952864500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993513 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000295 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000832 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.666667 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.666667 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1068 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29574 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30642 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1068 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 29574 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30642 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34610000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18859500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53469500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 31000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 31000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 899045000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 899045000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34610000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 917904500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 952514500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34610000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 917904500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 952514500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000292 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000827 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352988 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352988 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993513 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014247 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014755 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993513 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014247 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014755 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32459.888060 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32352.040816 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32421.686747 # average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014244 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014751 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014244 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014751 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32406.367041 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32404.639175 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32405.757576 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31010.088990 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31010.088990 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32459.888060 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31036.764706 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31086.535952 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32459.888060 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31036.764706 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31086.535952 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31010.106236 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31010.106236 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32406.367041 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31037.549875 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31085.258795 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32406.367041 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31037.549875 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31085.258795 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini index 3fd88efc2..2bc190729 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini @@ -120,8 +120,8 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 -master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +width=8 +master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master [system.physmem] diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout index 9f1b85cdf..36c1a507a 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 13:44:28 -gem5 started Jun 4 2012 15:20:09 +gem5 compiled Aug 13 2012 17:08:22 +gem5 started Aug 13 2012 18:40:35 gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second @@ -23,4 +23,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 168950072000 because target called exit() +Exiting @ tick 168950039000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt index 75d2c32b9..624b796e9 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.168950 # Number of seconds simulated -sim_ticks 168950072000 # Number of ticks simulated -final_tick 168950072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 168950039000 # Number of ticks simulated +final_tick 168950039000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1244063 # Simulator instruction rate (inst/s) -host_op_rate 2190595 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1330377575 # Simulator tick rate (ticks/s) -host_mem_usage 351912 # Number of bytes of host memory used -host_seconds 126.99 # Real time elapsed on the host -sim_insts 157988583 # Number of instructions simulated -sim_ops 278192520 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 1741569664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 717246015 # Number of bytes read from this memory -system.physmem.bytes_read::total 2458815679 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1741569664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1741569664 # Number of instructions bytes read from this memory +host_inst_rate 1227990 # Simulator instruction rate (inst/s) +host_op_rate 2162293 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1313189467 # Simulator tick rate (ticks/s) +host_mem_usage 359036 # Number of bytes of host memory used +host_seconds 128.66 # Real time elapsed on the host +sim_insts 157988548 # Number of instructions simulated +sim_ops 278192463 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 1741569312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 717246011 # Number of bytes read from this memory +system.physmem.bytes_read::total 2458815323 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1741569312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1741569312 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 243173115 # Number of bytes written to this memory system.physmem.bytes_written::total 243173115 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 217696208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 90779450 # Number of read requests responded to by this memory -system.physmem.num_reads::total 308475658 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 217696164 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 90779446 # Number of read requests responded to by this memory +system.physmem.num_reads::total 308475610 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 31439751 # Number of write requests responded to by this memory system.physmem.num_writes::total 31439751 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10308191310 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4245313462 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14553504772 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10308191310 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10308191310 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1439319393 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1439319393 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10308191310 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5684632854 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15992824164 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 10308191240 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4245314267 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14553505507 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10308191240 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10308191240 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1439319674 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1439319674 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10308191240 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5684633941 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15992825181 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 337900145 # number of cpu cycles simulated +system.cpu.numCycles 337900079 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 157988583 # Number of instructions committed -system.cpu.committedOps 278192520 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses +system.cpu.committedInsts 157988548 # Number of instructions committed +system.cpu.committedOps 278192463 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 278186171 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls -system.cpu.num_int_insts 278186228 # number of integer instructions +system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls +system.cpu.num_int_insts 278186171 # number of integer instructions system.cpu.num_fp_insts 40 # number of float instructions -system.cpu.num_int_register_reads 834011910 # number of times the integer registers were read -system.cpu.num_int_register_writes 341010914 # number of times the integer registers were written +system.cpu.num_int_register_reads 834011732 # number of times the integer registers were read +system.cpu.num_int_register_writes 341010822 # number of times the integer registers were written system.cpu.num_fp_register_reads 40 # number of times the floating registers were read system.cpu.num_fp_register_writes 26 # number of times the floating registers were written -system.cpu.num_mem_refs 122219139 # number of memory refs -system.cpu.num_load_insts 90779388 # Number of load instructions +system.cpu.num_mem_refs 122219135 # number of memory refs +system.cpu.num_load_insts 90779384 # Number of load instructions system.cpu.num_store_insts 31439751 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 337900145 # Number of busy cycles +system.cpu.num_busy_cycles 337900079 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini index 44c2b2c0a..fb9534d75 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini @@ -179,7 +179,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing +cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing egid=100 env= errout=cerr @@ -202,7 +202,7 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout index 85144f91b..25187946e 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:58:39 -gem5 started Jul 2 2012 13:28:56 +gem5 compiled Aug 13 2012 17:08:22 +gem5 started Aug 13 2012 18:42:54 gem5 executing on zizzer -command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +23,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 368209254000 because target called exit() +Exiting @ tick 368209206000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index cca34d6d0..be2824a9d 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.368209 # Number of seconds simulated -sim_ticks 368209254000 # Number of ticks simulated -final_tick 368209254000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 368209206000 # Number of ticks simulated +final_tick 368209206000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 606195 # Simulator instruction rate (inst/s) -host_op_rate 1067413 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1412802854 # Simulator tick rate (ticks/s) -host_mem_usage 363612 # Number of bytes of host memory used -host_seconds 260.62 # Real time elapsed on the host -sim_insts 157988583 # Number of instructions simulated -sim_ops 278192520 # Number of ops (including micro ops) simulated +host_inst_rate 651126 # Simulator instruction rate (inst/s) +host_op_rate 1146527 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1517517563 # Simulator tick rate (ticks/s) +host_mem_usage 367484 # Number of bytes of host memory used +host_seconds 242.64 # Real time elapsed on the host +sim_insts 157988548 # Number of instructions simulated +sim_ops 278192463 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 51712 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1879680 # Number of bytes read from this memory system.physmem.bytes_read::total 1931392 # Number of bytes read from this memory @@ -24,54 +24,54 @@ system.physmem.num_reads::total 30178 # Nu system.physmem.num_writes::writebacks 227 # Number of write requests responded to by this memory system.physmem.num_writes::total 227 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 140442 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5104923 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 5245365 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5104924 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 5245366 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 140442 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 140442 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 39456 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 39456 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 39456 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 140442 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5104923 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5284821 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5104924 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5284822 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 736418508 # number of cpu cycles simulated +system.cpu.numCycles 736418412 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 157988583 # Number of instructions committed -system.cpu.committedOps 278192520 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses +system.cpu.committedInsts 157988548 # Number of instructions committed +system.cpu.committedOps 278192463 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 278186171 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls -system.cpu.num_int_insts 278186228 # number of integer instructions +system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls +system.cpu.num_int_insts 278186171 # number of integer instructions system.cpu.num_fp_insts 40 # number of float instructions -system.cpu.num_int_register_reads 834011910 # number of times the integer registers were read -system.cpu.num_int_register_writes 341010914 # number of times the integer registers were written +system.cpu.num_int_register_reads 834011732 # number of times the integer registers were read +system.cpu.num_int_register_writes 341010822 # number of times the integer registers were written system.cpu.num_fp_register_reads 40 # number of times the floating registers were read system.cpu.num_fp_register_writes 26 # number of times the floating registers were written -system.cpu.num_mem_refs 122219139 # number of memory refs -system.cpu.num_load_insts 90779388 # Number of load instructions +system.cpu.num_mem_refs 122219135 # number of memory refs +system.cpu.num_load_insts 90779384 # Number of load instructions system.cpu.num_store_insts 31439751 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 736418508 # Number of busy cycles +system.cpu.num_busy_cycles 736418412 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 24 # number of replacements -system.cpu.icache.tagsinuse 665.897663 # Cycle average of tags in use -system.cpu.icache.total_refs 217695401 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 665.897748 # Cycle average of tags in use +system.cpu.icache.total_refs 217695357 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 269425.001238 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 269424.946782 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 665.897663 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 665.897748 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.325145 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.325145 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 217695401 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 217695401 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 217695401 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 217695401 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 217695401 # number of overall hits -system.cpu.icache.overall_hits::total 217695401 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 217695357 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 217695357 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 217695357 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 217695357 # number of overall hits +system.cpu.icache.overall_hits::total 217695357 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses @@ -84,12 +84,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 45336000 system.cpu.icache.demand_miss_latency::total 45336000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 45336000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 45336000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 217696209 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 217696209 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 217696209 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 217696209 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 217696209 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 217696209 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 217696165 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 217696165 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 217696165 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 217696165 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 217696165 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 217696165 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses @@ -136,22 +136,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53108.910891 system.cpu.icache.overall_avg_mshr_miss_latency::total 53108.910891 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2062733 # number of replacements -system.cpu.dcache.tagsinuse 4076.463091 # Cycle average of tags in use -system.cpu.dcache.total_refs 120152372 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4076.463619 # Cycle average of tags in use +system.cpu.dcache.total_refs 120152368 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 58.133678 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 126234114000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.463091 # Average occupied blocks per requestor +system.cpu.dcache.avg_refs 58.133676 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 126234066000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4076.463619 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.995230 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.995230 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 88818730 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88818730 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 88818726 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88818726 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 31333642 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 31333642 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 120152372 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 120152372 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 120152372 # number of overall hits -system.cpu.dcache.overall_hits::total 120152372 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 120152368 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 120152368 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 120152368 # number of overall hits +system.cpu.dcache.overall_hits::total 120152368 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses @@ -168,14 +168,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 30195678000 system.cpu.dcache.demand_miss_latency::total 30195678000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 30195678000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 30195678000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 90779450 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 90779450 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 90779446 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 90779446 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 122219201 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 122219201 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 122219201 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 122219201 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 122219197 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 122219197 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 122219197 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 122219197 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses @@ -236,14 +236,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11609.663644 system.cpu.dcache.overall_avg_mshr_miss_latency::total 11609.663644 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1081 # number of replacements -system.cpu.l2cache.tagsinuse 19722.096664 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 19722.099231 # Cycle average of tags in use system.cpu.l2cache.total_refs 3991053 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 30157 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 132.342508 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 19370.042647 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 209.723692 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 142.330324 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 19370.045173 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 209.723718 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 142.330341 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.591127 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.006400 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.004344 # Average percentage of cache occupancy diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout index ea9092f76..5b84c1efd 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout @@ -1,28 +1,15 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 26 2012 21:30:36 -gem5 started Jul 26 2012 23:13:36 +gem5 compiled Aug 13 2012 17:08:22 +gem5 started Aug 13 2012 18:47:07 gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: ***********************info: Increasing stack size by one page. -***************info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -*********** +************************** 58924 words stored in 3784810 bytes @@ -35,6 +22,8 @@ Processing sentences in batch mode Echoing of input sentence turned on. * as had expected the party to be a success , it was a success * do you know where John 's +info: Increasing stack size by one page. +info: Increasing stack size by one page. * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor * how fast the program is it * I am wondering whether to invite to the party @@ -80,4 +69,4 @@ Echoing of input sentence turned on. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 460506550000 because target called exit() +Exiting @ tick 460397003000 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index ba1f3f77b..622f1b256 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,172 +1,172 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.460507 # Number of seconds simulated -sim_ticks 460506550000 # Number of ticks simulated -final_tick 460506550000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.460397 # Number of seconds simulated +sim_ticks 460397003000 # Number of ticks simulated +final_tick 460397003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 78127 # Simulator instruction rate (inst/s) -host_op_rate 144467 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43510964 # Simulator tick rate (ticks/s) -host_mem_usage 271484 # Number of bytes of host memory used -host_seconds 10583.69 # Real time elapsed on the host -sim_insts 826877144 # Number of instructions simulated -sim_ops 1528988756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 221568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 27602688 # Number of bytes read from this memory -system.physmem.bytes_read::total 27824256 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 221568 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 221568 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 20791168 # Number of bytes written to this memory -system.physmem.bytes_written::total 20791168 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3462 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 431292 # Number of read requests responded to by this memory -system.physmem.num_reads::total 434754 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 324862 # Number of write requests responded to by this memory -system.physmem.num_writes::total 324862 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 481140 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 59939838 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 60420978 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 481140 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 481140 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 45148474 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 45148474 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 45148474 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 481140 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 59939838 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 105569452 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 79363 # Simulator instruction rate (inst/s) +host_op_rate 146752 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44188751 # Simulator tick rate (ticks/s) +host_mem_usage 271496 # Number of bytes of host memory used +host_seconds 10418.87 # Real time elapsed on the host +sim_insts 826877109 # Number of instructions simulated +sim_ops 1528988699 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 220608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 27602816 # Number of bytes read from this memory +system.physmem.bytes_read::total 27823424 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 220608 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 220608 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 20793216 # Number of bytes written to this memory +system.physmem.bytes_written::total 20793216 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3447 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 431294 # Number of read requests responded to by this memory +system.physmem.num_reads::total 434741 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 324894 # Number of write requests responded to by this memory +system.physmem.num_writes::total 324894 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 479169 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 59954378 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 60433547 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 479169 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 479169 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 45163665 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 45163665 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 45163665 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 479169 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 59954378 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 105597212 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 921013101 # number of cpu cycles simulated +system.cpu.numCycles 920794007 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 225814140 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 225814140 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 14312639 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 160732187 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 155963049 # Number of BTB hits +system.cpu.BPredUnit.lookups 225794462 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 225794462 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 14310990 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 160522970 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 155979425 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 191714211 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1263294933 # Number of instructions fetch has processed -system.cpu.fetch.Branches 225814140 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 155963049 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 392136096 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 98589209 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 239295269 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 25132 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 236819 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 183551766 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 3669107 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 907433762 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.580701 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.385285 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 191744262 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1263331162 # Number of instructions fetch has processed +system.cpu.fetch.Branches 225794462 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 155979425 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 392171634 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 98591454 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 238962985 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 25426 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 259827 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 183595750 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 3654130 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 907193017 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.581432 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.385361 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 519759842 57.28% 57.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 26004641 2.87% 60.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 29087197 3.21% 63.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 30312943 3.34% 66.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 19607781 2.16% 68.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 25619101 2.82% 71.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 32643698 3.60% 75.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30879699 3.40% 78.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 193518860 21.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 519485485 57.26% 57.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25996327 2.87% 60.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 29110749 3.21% 63.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 30309742 3.34% 66.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 19641750 2.17% 68.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 25638200 2.83% 71.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 32631023 3.60% 75.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30872435 3.40% 78.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 193507306 21.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 907433762 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.245180 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.371636 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 253860681 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 190389456 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 329095586 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 50061804 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 84026235 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2290781397 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 907193017 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.245217 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.372002 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 253820361 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 190155093 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 329181376 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 50007304 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 84028883 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2290797520 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 84026235 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 290493220 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 45042707 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 15282 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 340016370 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 147839948 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2240790840 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1987 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 24419621 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 107426362 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 12159 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2887400396 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6494628948 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6493753174 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 875774 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1993077484 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 894322912 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1296 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1278 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 351952477 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 540247389 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 217453734 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 211358657 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 61297047 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2143407595 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 68408 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1846659650 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1592160 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 612815347 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1231279567 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 67855 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 907433762 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.035035 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.801518 # Number of insts issued each cycle +system.cpu.rename.SquashCycles 84028883 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 290488558 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 45108603 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 15221 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 340002879 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 147548873 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2240764057 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2605 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 24418127 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 107087338 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 11838 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2887342076 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6494384791 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6493512354 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 872437 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1993077392 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 894264684 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1272 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1264 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 351172253 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 540287564 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 217471494 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 211537272 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 61160620 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2143475674 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 68305 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1846648177 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1590040 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 612877032 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1231244444 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 67752 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 907193017 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.035563 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.801610 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 248935467 27.43% 27.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 159182837 17.54% 44.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 153661987 16.93% 61.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 149232137 16.45% 78.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 98738940 10.88% 89.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 59680898 6.58% 95.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 27969436 3.08% 98.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 8976918 0.99% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1055142 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 248716450 27.42% 27.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 159225433 17.55% 44.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 153829003 16.96% 61.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 148683388 16.39% 78.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 98997552 10.91% 89.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 59757299 6.59% 95.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 27989930 3.09% 98.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 8953405 0.99% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1040557 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 907433762 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 907193017 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2635361 18.49% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8379879 58.81% 77.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3234007 22.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2618041 18.27% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8472648 59.14% 77.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3236053 22.59% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2716087 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1219498090 66.04% 66.19% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2706611 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1219512996 66.04% 66.19% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.19% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.19% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.19% # Type of FU issued @@ -195,159 +195,159 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.19% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.19% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.19% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 447052191 24.21% 90.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 177393282 9.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 447033831 24.21% 90.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 177394739 9.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1846659650 # Type of FU issued -system.cpu.iq.rate 2.005031 # Inst issue rate -system.cpu.iq.fu_busy_cnt 14249247 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007716 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4616586705 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2756248953 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1806266388 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 7764 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 302326 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 267 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1858190079 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2731 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 168174825 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1846648177 # Type of FU issued +system.cpu.iq.rate 2.005495 # Inst issue rate +system.cpu.iq.fu_busy_cnt 14326742 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007758 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4616398570 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2756384375 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1806263116 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 7583 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 297698 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 240 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1858265657 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2651 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 168095723 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 156145229 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 432412 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 271180 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 68293794 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 156185408 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 429800 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 272503 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 68311550 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7298 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 6430 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 84026235 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 6572859 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1284585 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2143476003 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2866964 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 540247389 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 217453979 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5268 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 966767 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 66701 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 271180 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10086388 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5256785 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 15343173 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1818783281 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 438633483 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 27876369 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 84028883 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 6582029 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1299784 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2143543979 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2844739 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 540287564 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 217471735 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5098 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 982320 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 66743 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 272503 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10083086 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5258850 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 15341936 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1818766036 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 438618649 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 27882141 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 610463331 # number of memory reference insts executed -system.cpu.iew.exec_branches 170879553 # Number of branches executed -system.cpu.iew.exec_stores 171829848 # Number of stores executed -system.cpu.iew.exec_rate 1.974764 # Inst execution rate -system.cpu.iew.wb_sent 1813538943 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1806266655 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1378870906 # num instructions producing a value -system.cpu.iew.wb_consumers 2933493121 # num instructions consuming a value +system.cpu.iew.exec_refs 610454199 # number of memory reference insts executed +system.cpu.iew.exec_branches 170875981 # Number of branches executed +system.cpu.iew.exec_stores 171835550 # Number of stores executed +system.cpu.iew.exec_rate 1.975215 # Inst execution rate +system.cpu.iew.wb_sent 1813520986 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1806263356 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1378693447 # num instructions producing a value +system.cpu.iew.wb_consumers 2933323666 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.961174 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.470044 # average fanout of values written-back +system.cpu.iew.wb_rate 1.961637 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.470011 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 826877144 # The number of committed instructions -system.cpu.commit.commitCommittedOps 1528988756 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 614512471 # The number of squashed insts skipped by commit +system.cpu.commit.commitCommittedInsts 826877109 # The number of committed instructions +system.cpu.commit.commitCommittedOps 1528988699 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 614579352 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14337883 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 823407527 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.856904 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.319659 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14336742 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 823164134 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.857453 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.320209 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 305105182 37.05% 37.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 205650111 24.98% 62.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 74228668 9.01% 71.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 96597559 11.73% 82.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29968597 3.64% 86.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 28751826 3.49% 89.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15821579 1.92% 91.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11746400 1.43% 93.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 55537605 6.74% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 305087340 37.06% 37.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 205283379 24.94% 62.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 74494797 9.05% 71.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 96404931 11.71% 82.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29976642 3.64% 86.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 28775074 3.50% 89.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15838255 1.92% 91.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11740263 1.43% 93.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 55563453 6.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 823407527 # Number of insts commited each cycle -system.cpu.commit.committedInsts 826877144 # Number of instructions committed -system.cpu.commit.committedOps 1528988756 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 823164134 # Number of insts commited each cycle +system.cpu.commit.committedInsts 826877109 # Number of instructions committed +system.cpu.commit.committedOps 1528988699 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 533262345 # Number of memory references committed -system.cpu.commit.loads 384102160 # Number of loads committed +system.cpu.commit.refs 533262341 # Number of memory references committed +system.cpu.commit.loads 384102156 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 149758588 # Number of branches committed +system.cpu.commit.branches 149758583 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions. +system.cpu.commit.int_insts 1528317557 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 55537605 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 55563453 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2911371149 # The number of ROB reads -system.cpu.rob.rob_writes 4371143864 # The number of ROB writes -system.cpu.timesIdled 309440 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13579339 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 826877144 # Number of Instructions Simulated -system.cpu.committedOps 1528988756 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 826877144 # Number of Instructions Simulated -system.cpu.cpi 1.113845 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.113845 # CPI: Total CPI of All Threads -system.cpu.ipc 0.897791 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.897791 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4004246874 # number of integer regfile reads -system.cpu.int_regfile_writes 2286313998 # number of integer regfile writes -system.cpu.fp_regfile_reads 266 # number of floating regfile reads -system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 1001920728 # number of misc regfile reads -system.cpu.icache.replacements 5588 # number of replacements -system.cpu.icache.tagsinuse 1044.044381 # Cycle average of tags in use -system.cpu.icache.total_refs 183312403 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 7204 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 25445.919350 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 2911168732 # The number of ROB reads +system.cpu.rob.rob_writes 4371280103 # The number of ROB writes +system.cpu.timesIdled 309541 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13600990 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 826877109 # Number of Instructions Simulated +system.cpu.committedOps 1528988699 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated +system.cpu.cpi 1.113580 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.113580 # CPI: Total CPI of All Threads +system.cpu.ipc 0.898004 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.898004 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4004208844 # number of integer regfile reads +system.cpu.int_regfile_writes 2286339718 # number of integer regfile writes +system.cpu.fp_regfile_reads 238 # number of floating regfile reads +system.cpu.fp_regfile_writes 2 # number of floating regfile writes +system.cpu.misc_regfile_reads 1001924846 # number of misc regfile reads +system.cpu.icache.replacements 5564 # number of replacements +system.cpu.icache.tagsinuse 1044.277661 # Cycle average of tags in use +system.cpu.icache.total_refs 183360161 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7185 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 25519.855393 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1044.044381 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.509787 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.509787 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 183329342 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 183329342 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 183329342 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 183329342 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 183329342 # number of overall hits -system.cpu.icache.overall_hits::total 183329342 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 222424 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 222424 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 222424 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 222424 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 222424 # number of overall misses -system.cpu.icache.overall_misses::total 222424 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1554709500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1554709500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1554709500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1554709500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1554709500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1554709500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 183551766 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 183551766 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 183551766 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 183551766 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 183551766 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 183551766 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001212 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001212 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001212 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001212 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001212 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001212 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6989.845970 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6989.845970 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6989.845970 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6989.845970 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6989.845970 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6989.845970 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1044.277661 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.509901 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.509901 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 183377049 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 183377049 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 183377049 # 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number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1530978500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1530978500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 183595750 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 183595750 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 183595750 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 183595750 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 183595750 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 183595750 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001191 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001191 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001191 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001191 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001191 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001191 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7000.326930 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 7000.326930 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 7000.326930 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 7000.326930 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 7000.326930 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 7000.326930 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -356,94 +356,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1671 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1671 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1671 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1671 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1671 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1671 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 220753 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 220753 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 220753 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 220753 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 220753 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 220753 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 807012500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 807012500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 807012500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 807012500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 807012500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 807012500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001203 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001203 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001203 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001203 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001203 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001203 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3655.726083 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3655.726083 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3655.726083 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 3655.726083 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3655.726083 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 3655.726083 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1667 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1667 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1667 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1667 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1667 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1667 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 217034 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 217034 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 217034 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 217034 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 217034 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 217034 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 795818000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 795818000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 795818000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 795818000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 795818000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 795818000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001182 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001182 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001182 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001182 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001182 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001182 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3666.789535 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3666.789535 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3666.789535 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 3666.789535 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3666.789535 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 3666.789535 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2526911 # number of replacements -system.cpu.dcache.tagsinuse 4087.001481 # Cycle average of tags in use -system.cpu.dcache.total_refs 415013959 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2531007 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 163.971873 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 2119650000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.001481 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997803 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997803 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 266164816 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 266164816 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148172858 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148172858 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 414337674 # 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Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 163.995484 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 2118352000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.012033 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997806 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997806 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 266229970 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 266229970 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148176522 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148176522 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 414406492 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 414406492 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 414406492 # 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number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 55557310000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 55557310000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 55557310000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 55557310000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 268882957 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 268882957 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 417977527 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 417977527 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 417977527 # 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miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008708 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008708 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13843.841871 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13843.841871 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 19229.820842 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 19229.820842 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15304.837311 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15304.837311 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15304.837311 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15304.837311 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006595 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006595 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008699 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008699 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008699 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008699 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13839.328651 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13839.328651 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 19154.369464 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 19154.369464 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15276.989968 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15276.989968 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15276.989968 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15276.989968 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -452,144 +452,144 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2302631 # number of writebacks -system.cpu.dcache.writebacks::total 2302631 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 892307 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 892307 # 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average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16083.027367 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10321.543492 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 10321.543492 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10321.543492 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 10321.543492 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2302737 # number of writebacks +system.cpu.dcache.writebacks::total 2302737 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 892793 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 892793 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3022 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3022 # 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average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 49.799051 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 49.799051 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34258.569674 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34258.569674 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35087.666089 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34292.529619 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34298.860880 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35087.666089 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34292.529619 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34298.860880 # average overall miss latency +system.cpu.l2cache.ReadReq_accesses::total 1766511 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2302737 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2302737 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 209807 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 209807 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 771643 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 771643 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 7110 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2531044 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2538154 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 7110 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2531044 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2538154 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.484810 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.126258 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.127701 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.993956 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.993956 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.271094 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.271094 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.484810 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.170415 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.171295 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.484810 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.170415 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.171295 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35059.326951 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34323.585377 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34334.827658 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 50.688360 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 50.688360 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34258.697918 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34258.697918 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35059.326951 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34292.115801 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34298.198448 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35059.326951 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34292.115801 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34298.198448 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -598,60 +598,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 324862 # number of writebacks -system.cpu.l2cache.writebacks::total 324862 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3462 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222130 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 225592 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 212243 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 212243 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 209197 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 209197 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3462 # number of demand (read+write) MSHR misses +system.cpu.l2cache.writebacks::writebacks 324894 # number of writebacks +system.cpu.l2cache.writebacks::total 324894 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3447 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222139 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 225586 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 208539 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 208539 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 209188 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 209188 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3447 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 431327 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 434789 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3462 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 434774 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3447 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 431327 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 434789 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 110501000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6934646999 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7045147999 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6580894500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6580894500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6486675500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6486675500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110501000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13421322499 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 13531823499 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110501000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13421322499 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 13531823499 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.484399 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.126253 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.127702 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.994103 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.994103 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.271118 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.271118 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.484399 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170417 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.171301 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.484399 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170417 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.171301 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31918.255344 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31218.867325 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31229.600336 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31006.414817 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31006.414817 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31007.497717 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31007.497717 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31918.255344 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31116.351397 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31122.736543 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31918.255344 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31116.351397 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31122.736543 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::total 434774 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 109944000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6934594999 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7044538999 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6467053500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6467053500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6486625500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6486625500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 109944000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13421220499 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13531164499 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 109944000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13421220499 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13531164499 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.484810 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.126258 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.127701 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.993956 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.993956 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.271094 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.271094 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.484810 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170415 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.171295 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.484810 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170415 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.171295 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31895.561358 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31217.368400 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31227.731326 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31011.242501 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31011.242501 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31008.592749 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31008.592749 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31895.561358 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31116.114917 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31122.294569 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31895.561358 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31116.114917 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31122.294569 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini index 8e0e263be..631aee4c4 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini @@ -120,8 +120,8 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 -master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +width=8 +master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master [system.physmem] diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout index 337e5053a..2e1cac91e 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 13:44:28 -gem5 started Jun 4 2012 15:38:11 +gem5 compiled Aug 13 2012 17:08:22 +gem5 started Aug 13 2012 18:52:16 gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second @@ -69,4 +69,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 885229360000 because target called exit() +Exiting @ tick 885229327000 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt index a8445ed5c..84b45e732 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.885229 # Number of seconds simulated -sim_ticks 885229360000 # Number of ticks simulated -final_tick 885229360000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 885229327000 # Number of ticks simulated +final_tick 885229327000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1285236 # Simulator instruction rate (inst/s) -host_op_rate 2376545 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1375933868 # Simulator tick rate (ticks/s) -host_mem_usage 220604 # Number of bytes of host memory used -host_seconds 643.37 # Real time elapsed on the host -sim_insts 826877145 # Number of instructions simulated -sim_ops 1528988757 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 8546776872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2285655660 # Number of bytes read from this memory -system.physmem.bytes_read::total 10832432532 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 8546776872 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 8546776872 # Number of instructions bytes read from this memory +host_inst_rate 1279506 # Simulator instruction rate (inst/s) +host_op_rate 2365950 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1369799774 # Simulator tick rate (ticks/s) +host_mem_usage 228100 # Number of bytes of host memory used +host_seconds 646.25 # Real time elapsed on the host +sim_insts 826877110 # Number of instructions simulated +sim_ops 1528988700 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 8546776520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2285655656 # Number of bytes read from this memory +system.physmem.bytes_read::total 10832432176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 8546776520 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 8546776520 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 991849460 # Number of bytes written to this memory system.physmem.bytes_written::total 991849460 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1068347109 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 384102189 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1452449298 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1068347065 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 384102185 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1452449250 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 149160201 # Number of write requests responded to by this memory system.physmem.num_writes::total 149160201 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 9654872803 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2581992604 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12236865406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 9654872803 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 9654872803 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1120443475 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1120443475 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 9654872803 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3702436078 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13357308881 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 9654872765 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2581992695 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12236865460 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 9654872765 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 9654872765 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1120443516 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1120443516 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 9654872765 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3702436212 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13357308977 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 1770458721 # number of cpu cycles simulated +system.cpu.numCycles 1770458655 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 826877145 # Number of instructions committed -system.cpu.committedOps 1528988757 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses +system.cpu.committedInsts 826877110 # Number of instructions committed +system.cpu.committedOps 1528988700 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1528317558 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls -system.cpu.num_int_insts 1528317615 # number of integer instructions +system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls +system.cpu.num_int_insts 1528317558 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 4441632810 # number of times the integer registers were read -system.cpu.num_int_register_writes 1993077484 # number of times the integer registers were written +system.cpu.num_int_register_reads 4441632632 # number of times the integer registers were read +system.cpu.num_int_register_writes 1993077392 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 533262345 # number of memory refs -system.cpu.num_load_insts 384102160 # Number of load instructions +system.cpu.num_mem_refs 533262341 # number of memory refs +system.cpu.num_load_insts 384102156 # Number of load instructions system.cpu.num_store_insts 149160185 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1770458721 # Number of busy cycles +system.cpu.num_busy_cycles 1770458655 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini index 2d97cc0b1..5307ccc0b 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini @@ -179,7 +179,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing +cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing egid=100 env= errout=cerr @@ -202,7 +202,7 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout index 1335d3658..d712433e8 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:58:39 -gem5 started Jul 2 2012 13:47:25 +gem5 compiled Aug 13 2012 17:08:22 +gem5 started Aug 13 2012 19:03:12 gem5 executing on zizzer -command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -69,4 +69,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 1652606875000 because target called exit() +Exiting @ tick 1652606827000 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index ae8bc7b58..9139f6ef0 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.652607 # Number of seconds simulated -sim_ticks 1652606875000 # Number of ticks simulated -final_tick 1652606875000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1652606827000 # Number of ticks simulated +final_tick 1652606827000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 673883 # Simulator instruction rate (inst/s) -host_op_rate 1246085 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1346830511 # Simulator tick rate (ticks/s) -host_mem_usage 232676 # Number of bytes of host memory used -host_seconds 1227.03 # Real time elapsed on the host -sim_insts 826877145 # Number of instructions simulated -sim_ops 1528988757 # Number of ops (including micro ops) simulated +host_inst_rate 715148 # Simulator instruction rate (inst/s) +host_op_rate 1322389 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1429304042 # Simulator tick rate (ticks/s) +host_mem_usage 236556 # Number of bytes of host memory used +host_seconds 1156.23 # Real time elapsed on the host +sim_insts 826877110 # Number of instructions simulated +sim_ops 1528988700 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 123584 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 27359872 # Number of bytes read from this memory system.physmem.bytes_read::total 27483456 # Number of bytes read from this memory @@ -24,54 +24,54 @@ system.physmem.num_reads::total 429429 # Nu system.physmem.num_writes::writebacks 323570 # Number of write requests responded to by this memory system.physmem.num_writes::total 323570 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 74781 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 16555584 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 16630365 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 16555585 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 16630366 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 74781 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 74781 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 12530796 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 12530796 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 12530796 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 12530797 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 12530797 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 12530797 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 74781 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 16555584 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 16555585 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 29161162 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 3305213750 # number of cpu cycles simulated +system.cpu.numCycles 3305213654 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 826877145 # Number of instructions committed -system.cpu.committedOps 1528988757 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses +system.cpu.committedInsts 826877110 # Number of instructions committed +system.cpu.committedOps 1528988700 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1528317558 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls -system.cpu.num_int_insts 1528317615 # number of integer instructions +system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls +system.cpu.num_int_insts 1528317558 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 4441632810 # number of times the integer registers were read -system.cpu.num_int_register_writes 1993077484 # number of times the integer registers were written +system.cpu.num_int_register_reads 4441632632 # number of times the integer registers were read +system.cpu.num_int_register_writes 1993077392 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 533262345 # number of memory refs -system.cpu.num_load_insts 384102160 # Number of load instructions +system.cpu.num_mem_refs 533262341 # number of memory refs +system.cpu.num_load_insts 384102156 # Number of load instructions system.cpu.num_store_insts 149160185 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 3305213750 # Number of busy cycles +system.cpu.num_busy_cycles 3305213654 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1253 # number of replacements -system.cpu.icache.tagsinuse 881.608185 # Cycle average of tags in use -system.cpu.icache.total_refs 1068344296 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 881.608211 # Cycle average of tags in use +system.cpu.icache.total_refs 1068344252 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 379653.267946 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 379653.252310 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 881.608185 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 881.608211 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.430473 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.430473 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1068344296 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1068344296 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1068344296 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1068344296 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1068344296 # number of overall hits -system.cpu.icache.overall_hits::total 1068344296 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 1068344252 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1068344252 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1068344252 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1068344252 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1068344252 # number of overall hits +system.cpu.icache.overall_hits::total 1068344252 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses @@ -84,12 +84,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 120792000 system.cpu.icache.demand_miss_latency::total 120792000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 120792000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 120792000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1068347110 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1068347110 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1068347110 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1068347110 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1068347110 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1068347110 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 1068347066 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1068347066 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1068347066 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1068347066 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1068347066 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1068347066 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses @@ -136,22 +136,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39925.373134 system.cpu.icache.overall_avg_mshr_miss_latency::total 39925.373134 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2514362 # number of replacements -system.cpu.dcache.tagsinuse 4086.431953 # Cycle average of tags in use -system.cpu.dcache.total_refs 530743932 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4086.432071 # Cycle average of tags in use +system.cpu.dcache.total_refs 530743928 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 210.741625 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 8218697000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4086.431953 # Average occupied blocks per requestor +system.cpu.dcache.avg_refs 210.741624 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 8218649000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4086.432071 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.997664 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.997664 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 382374775 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 382374775 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 382374771 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 382374771 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 148369157 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 148369157 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 530743932 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 530743932 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 530743932 # number of overall hits -system.cpu.dcache.overall_hits::total 530743932 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 530743928 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 530743928 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 530743928 # number of overall hits +system.cpu.dcache.overall_hits::total 530743928 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses @@ -168,14 +168,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 53256878500 system.cpu.dcache.demand_miss_latency::total 53256878500 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 53256878500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 53256878500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 384102189 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 384102189 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 384102185 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 384102185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 533262390 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 533262390 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 533262390 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 533262390 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 533262386 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 533262386 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 533262386 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 533262386 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses @@ -236,14 +236,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18146.617494 system.cpu.dcache.overall_avg_mshr_miss_latency::total 18146.617494 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 403150 # number of replacements -system.cpu.l2cache.tagsinuse 29113.385052 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 29113.385897 # Cycle average of tags in use system.cpu.l2cache.total_refs 3572765 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 435501 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 8.203804 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 773011530000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21035.861184 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 79.696348 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 7997.827520 # Average occupied blocks per requestor +system.cpu.l2cache.warmup_cycle 773011482000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 21035.861795 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 79.696350 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 7997.827752 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.641964 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.002432 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.244074 # Average percentage of cache occupancy diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini index 49574e0d6..dd4ef298a 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini @@ -99,8 +99,8 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 -master=system.physmem.port[0] +width=8 +master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.physmem] diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout index ea448ddba..0a5ffdd78 100755 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:01:47 -gem5 started Jun 4 2012 14:58:33 +gem5 compiled Aug 13 2012 17:04:37 +gem5 started Aug 13 2012 18:18:28 gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 68148678500 because target called exit() +Exiting @ tick 68148672000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt index 158c6976f..932598cf9 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.068149 # Number of seconds simulated -sim_ticks 68148678500 # Number of ticks simulated -final_tick 68148678500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 68148672000 # Number of ticks simulated +final_tick 68148672000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2876458 # Simulator instruction rate (inst/s) -host_op_rate 2913702 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1458542737 # Simulator tick rate (ticks/s) -host_mem_usage 222372 # Number of bytes of host memory used -host_seconds 46.72 # Real time elapsed on the host -sim_insts 134398975 # Number of instructions simulated -sim_ops 136139203 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 538214332 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 147559361 # Number of bytes read from this memory -system.physmem.bytes_read::total 685773693 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 538214332 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 538214332 # Number of instructions bytes read from this memory +host_inst_rate 2819750 # Simulator instruction rate (inst/s) +host_op_rate 2856259 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1429788311 # Simulator tick rate (ticks/s) +host_mem_usage 230172 # Number of bytes of host memory used +host_seconds 47.66 # Real time elapsed on the host +sim_insts 134398962 # Number of instructions simulated +sim_ops 136139190 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 538214280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 147559360 # Number of bytes read from this memory +system.physmem.bytes_read::total 685773640 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 538214280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 538214280 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 89882950 # Number of bytes written to this memory system.physmem.bytes_written::total 89882950 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 134553583 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 37231301 # Number of read requests responded to by this memory -system.physmem.num_reads::total 171784884 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 134553570 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 37231300 # Number of read requests responded to by this memory +system.physmem.num_reads::total 171784870 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 20864304 # Number of write requests responded to by this memory system.physmem.num_writes::total 20864304 # Number of write requests responded to by this memory system.physmem.num_other::cpu.data 15916 # Number of other requests responded to by this memory system.physmem.num_other::total 15916 # Number of other requests responded to by this memory -system.physmem.bw_read::cpu.inst 7897648844 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2165256381 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10062905226 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7897648844 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7897648844 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1318924328 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1318924328 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7897648844 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3484180709 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11381829554 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 7897648835 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2165256573 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10062905408 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7897648835 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7897648835 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1318924454 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1318924454 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7897648835 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3484181027 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11381829862 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 136297358 # number of cpu cycles simulated +system.cpu.numCycles 136297345 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 134398975 # Number of instructions committed -system.cpu.committedOps 136139203 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 115187758 # Number of integer alu accesses +system.cpu.committedInsts 134398962 # Number of instructions committed +system.cpu.committedOps 136139190 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 115187746 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2326977 # Number of float alu accesses system.cpu.num_func_calls 1709332 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8898970 # number of instructions that are conditional controls -system.cpu.num_int_insts 115187758 # number of integer instructions +system.cpu.num_conditional_control_insts 8898969 # number of instructions that are conditional controls +system.cpu.num_int_insts 115187746 # number of integer instructions system.cpu.num_fp_insts 2326977 # number of float instructions -system.cpu.num_int_register_reads 263032383 # number of times the integer registers were read -system.cpu.num_int_register_writes 113147747 # number of times the integer registers were written +system.cpu.num_int_register_reads 263032361 # number of times the integer registers were read +system.cpu.num_int_register_writes 113147734 # number of times the integer registers were written system.cpu.num_fp_register_reads 4725607 # number of times the floating registers were read system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written -system.cpu.num_mem_refs 58160249 # number of memory refs -system.cpu.num_load_insts 37275868 # Number of load instructions +system.cpu.num_mem_refs 58160248 # number of memory refs +system.cpu.num_load_insts 37275867 # Number of load instructions system.cpu.num_store_insts 20884381 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 136297358 # Number of busy cycles +system.cpu.num_busy_cycles 136297345 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini index 221d86591..a3a928813 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -158,7 +158,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex bendian.raw -cwd=build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing +cwd=build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing egid=100 env= errout=cerr @@ -181,7 +181,7 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout index 98fb0b2cd..3a91ca093 100755 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:54:18 -gem5 started Jul 2 2012 12:32:55 +gem5 compiled Aug 13 2012 17:04:37 +gem5 started Aug 13 2012 18:19:26 gem5 executing on zizzer -command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 204097192000 because target called exit() +Exiting @ tick 204097178000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index a6ef18324..fbfcfb090 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.204097 # Number of seconds simulated -sim_ticks 204097192000 # Number of ticks simulated -final_tick 204097192000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 204097178000 # Number of ticks simulated +final_tick 204097178000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1236624 # Simulator instruction rate (inst/s) -host_op_rate 1252636 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1877926206 # Simulator tick rate (ticks/s) -host_mem_usage 229284 # Number of bytes of host memory used -host_seconds 108.68 # Real time elapsed on the host -sim_insts 134398975 # Number of instructions simulated -sim_ops 136139203 # Number of ops (including micro ops) simulated +host_inst_rate 1441199 # Simulator instruction rate (inst/s) +host_op_rate 1459859 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2188591939 # Simulator tick rate (ticks/s) +host_mem_usage 238748 # Number of bytes of host memory used +host_seconds 93.26 # Real time elapsed on the host +sim_insts 134398962 # Number of instructions simulated +sim_ops 136139190 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 665664 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7906112 # Number of bytes read from this memory system.physmem.bytes_read::total 8571776 # Number of bytes read from this memory @@ -24,54 +24,54 @@ system.physmem.num_reads::total 133934 # Nu system.physmem.num_writes::writebacks 82834 # Number of write requests responded to by this memory system.physmem.num_writes::total 82834 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 3261505 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 38736995 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 41998500 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 38736998 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 41998503 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 3261505 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 3261505 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 25974762 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 25974762 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 25974762 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 25974764 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 25974764 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 25974764 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 3261505 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 38736995 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 67973262 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 38736998 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 67973267 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 408194384 # number of cpu cycles simulated +system.cpu.numCycles 408194356 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 134398975 # Number of instructions committed -system.cpu.committedOps 136139203 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 115187758 # Number of integer alu accesses +system.cpu.committedInsts 134398962 # Number of instructions committed +system.cpu.committedOps 136139190 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 115187746 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2326977 # Number of float alu accesses system.cpu.num_func_calls 1709332 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8898970 # number of instructions that are conditional controls -system.cpu.num_int_insts 115187758 # number of integer instructions +system.cpu.num_conditional_control_insts 8898969 # number of instructions that are conditional controls +system.cpu.num_int_insts 115187746 # number of integer instructions system.cpu.num_fp_insts 2326977 # number of float instructions -system.cpu.num_int_register_reads 263032383 # number of times the integer registers were read -system.cpu.num_int_register_writes 113147746 # number of times the integer registers were written +system.cpu.num_int_register_reads 263032361 # number of times the integer registers were read +system.cpu.num_int_register_writes 113147733 # number of times the integer registers were written system.cpu.num_fp_register_reads 4725607 # number of times the floating registers were read system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written -system.cpu.num_mem_refs 58160249 # number of memory refs -system.cpu.num_load_insts 37275868 # Number of load instructions +system.cpu.num_mem_refs 58160248 # number of memory refs +system.cpu.num_load_insts 37275867 # Number of load instructions system.cpu.num_store_insts 20884381 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 408194384 # Number of busy cycles +system.cpu.num_busy_cycles 408194356 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 184976 # number of replacements -system.cpu.icache.tagsinuse 2004.409813 # Cycle average of tags in use -system.cpu.icache.total_refs 134366560 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 2004.409949 # Cycle average of tags in use +system.cpu.icache.total_refs 134366547 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 718.445547 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 145330300000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 2004.409813 # Average occupied blocks per requestor +system.cpu.icache.avg_refs 718.445478 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 145330286000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 2004.409949 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.978716 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.978716 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 134366560 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 134366560 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 134366560 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 134366560 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 134366560 # number of overall hits -system.cpu.icache.overall_hits::total 134366560 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 134366547 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 134366547 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 134366547 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 134366547 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 134366547 # number of overall hits +system.cpu.icache.overall_hits::total 134366547 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 187024 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 187024 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 187024 # number of demand (read+write) misses @@ -84,12 +84,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 3060544000 system.cpu.icache.demand_miss_latency::total 3060544000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 3060544000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 3060544000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 134553584 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 134553584 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 134553584 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 134553584 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 134553584 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 134553584 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 134553571 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 134553571 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 134553571 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 134553571 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 134553571 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 134553571 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001390 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001390 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 # miss rate for demand accesses @@ -136,24 +136,24 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13364.445205 system.cpu.icache.overall_avg_mshr_miss_latency::total 13364.445205 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 146582 # number of replacements -system.cpu.dcache.tagsinuse 4087.412837 # Cycle average of tags in use -system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4087.413116 # Cycle average of tags in use +system.cpu.dcache.total_refs 57960842 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 384.666925 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 812044000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.412837 # Average occupied blocks per requestor +system.cpu.dcache.avg_refs 384.666919 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 812030000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.413116 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.997904 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.997904 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 37185802 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 37185802 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 37185801 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 37185801 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 57944942 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 57944942 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 57944942 # number of overall hits -system.cpu.dcache.overall_hits::total 57944942 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 57944941 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 57944941 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 57944941 # number of overall hits +system.cpu.dcache.overall_hits::total 57944941 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 45499 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 45499 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 105164 # number of WriteReq misses @@ -174,16 +174,16 @@ system.cpu.dcache.demand_miss_latency::cpu.data 7299977000 system.cpu.dcache.demand_miss_latency::total 7299977000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 7299977000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 7299977000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 37231301 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 37231301 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20864304 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 15916 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 15916 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 58095605 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 58095605 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 58095605 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 58095605 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 58095604 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 58095604 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 58095604 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 58095604 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001222 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.001222 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005040 # miss rate for WriteReq accesses @@ -256,14 +256,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45452.353929 system.cpu.dcache.overall_avg_mshr_miss_latency::total 45452.353929 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 101560 # number of replacements -system.cpu.l2cache.tagsinuse 29278.940429 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 29278.942435 # Cycle average of tags in use system.cpu.l2cache.total_refs 222505 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 132357 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 1.681097 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 24760.226438 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3263.271337 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1255.442654 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 24760.228137 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 3263.271559 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1255.442739 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.755622 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.099587 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.038313 # Average percentage of cache occupancy diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini index 4b0cea416..d332c41fc 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini @@ -120,8 +120,8 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 -master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +width=8 +master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master [system.physmem] diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout index c6605043f..3c6a6098c 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 13:44:28 -gem5 started Jun 4 2012 15:49:05 +gem5 compiled Aug 13 2012 17:08:22 +gem5 started Aug 13 2012 19:04:29 gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second @@ -24,4 +24,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2846007259500 because target called exit() +Exiting @ tick 2846007226500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index d066014cc..f428cd228 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.846007 # Number of seconds simulated -sim_ticks 2846007259500 # Number of ticks simulated -final_tick 2846007259500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2846007226500 # Number of ticks simulated +final_tick 2846007226500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1390065 # Simulator instruction rate (inst/s) -host_op_rate 2165848 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1315169413 # Simulator tick rate (ticks/s) -host_mem_usage 216596 # Number of bytes of host memory used -host_seconds 2163.99 # Real time elapsed on the host -sim_insts 3008081057 # Number of instructions simulated -sim_ops 4686862651 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 32105863408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5023868347 # Number of bytes read from this memory -system.physmem.bytes_read::total 37129731755 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 32105863408 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 32105863408 # Number of instructions bytes read from this memory +host_inst_rate 1386030 # Simulator instruction rate (inst/s) +host_op_rate 2159560 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1311351119 # Simulator tick rate (ticks/s) +host_mem_usage 224788 # Number of bytes of host memory used +host_seconds 2170.29 # Real time elapsed on the host +sim_insts 3008081022 # Number of instructions simulated +sim_ops 4686862594 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 32105863056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5023868343 # Number of bytes read from this memory +system.physmem.bytes_read::total 37129731399 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 32105863056 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 32105863056 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 1544656790 # Number of bytes written to this memory system.physmem.bytes_written::total 1544656790 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4013232926 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1239184749 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5252417675 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 4013232882 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1239184745 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5252417627 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 438528337 # Number of write requests responded to by this memory system.physmem.num_writes::total 438528337 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11281019506 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1765233848 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13046253354 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11281019506 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11281019506 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 542745204 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 542745204 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11281019506 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2307979052 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13588998558 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 11281019513 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1765233867 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13046253380 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11281019513 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11281019513 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 542745210 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 542745210 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11281019513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2307979077 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13588998590 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 5692014520 # number of cpu cycles simulated +system.cpu.numCycles 5692014454 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 3008081057 # Number of instructions committed -system.cpu.committedOps 4686862651 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses +system.cpu.committedInsts 3008081022 # Number of instructions committed +system.cpu.committedOps 4686862594 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4686862523 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 182173305 # number of instructions that are conditional controls -system.cpu.num_int_insts 4686862580 # number of integer instructions +system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls +system.cpu.num_int_insts 4686862523 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 14165752766 # number of times the integer registers were read -system.cpu.num_int_register_writes 6716691823 # number of times the integer registers were written +system.cpu.num_int_register_reads 14165752588 # number of times the integer registers were read +system.cpu.num_int_register_writes 6716691731 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 1677713086 # number of memory refs -system.cpu.num_load_insts 1239184749 # Number of load instructions +system.cpu.num_mem_refs 1677713082 # number of memory refs +system.cpu.num_load_insts 1239184745 # Number of load instructions system.cpu.num_store_insts 438528337 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5692014520 # Number of busy cycles +system.cpu.num_busy_cycles 5692014454 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini index f840aa9a4..4471a2bb3 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini @@ -179,7 +179,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing +cwd=build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing egid=100 env= errout=cerr @@ -202,7 +202,7 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout index 05d9e4afd..93d28d354 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:58:39 -gem5 started Jul 2 2012 14:08:03 +gem5 compiled Aug 13 2012 17:08:22 +gem5 started Aug 13 2012 19:22:39 gem5 executing on zizzer -command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -24,4 +24,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 5901048931000 because target called exit() +Exiting @ tick 5901048883000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 50b0e856f..b95834217 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 5.901049 # Number of seconds simulated -sim_ticks 5901048931000 # Number of ticks simulated -final_tick 5901048931000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 5901048883000 # Number of ticks simulated +final_tick 5901048883000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 821481 # Simulator instruction rate (inst/s) -host_op_rate 1279942 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1611526350 # Simulator tick rate (ticks/s) -host_mem_usage 228472 # Number of bytes of host memory used -host_seconds 3661.78 # Real time elapsed on the host -sim_insts 3008081057 # Number of instructions simulated -sim_ops 4686862651 # Number of ops (including micro ops) simulated +host_inst_rate 766833 # Simulator instruction rate (inst/s) +host_op_rate 1194795 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1504320663 # Simulator tick rate (ticks/s) +host_mem_usage 233368 # Number of bytes of host memory used +host_seconds 3922.73 # Real time elapsed on the host +sim_insts 3008081022 # Number of instructions simulated +sim_ops 4686862594 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 139043584 # Number of bytes read from this memory system.physmem.bytes_read::total 139086784 # Number of bytes read from this memory @@ -35,43 +35,43 @@ system.physmem.bw_total::cpu.inst 7321 # To system.physmem.bw_total::cpu.data 23562520 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 34990498 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 11802097862 # number of cpu cycles simulated +system.cpu.numCycles 11802097766 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 3008081057 # Number of instructions committed -system.cpu.committedOps 4686862651 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses +system.cpu.committedInsts 3008081022 # Number of instructions committed +system.cpu.committedOps 4686862594 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4686862523 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 182173305 # number of instructions that are conditional controls -system.cpu.num_int_insts 4686862580 # number of integer instructions +system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls +system.cpu.num_int_insts 4686862523 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 14165752766 # number of times the integer registers were read -system.cpu.num_int_register_writes 6716691823 # number of times the integer registers were written +system.cpu.num_int_register_reads 14165752588 # number of times the integer registers were read +system.cpu.num_int_register_writes 6716691731 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 1677713086 # number of memory refs -system.cpu.num_load_insts 1239184749 # Number of load instructions +system.cpu.num_mem_refs 1677713082 # number of memory refs +system.cpu.num_load_insts 1239184745 # Number of load instructions system.cpu.num_store_insts 438528337 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 11802097862 # Number of busy cycles +system.cpu.num_busy_cycles 11802097766 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 10 # number of replacements -system.cpu.icache.tagsinuse 555.745883 # Cycle average of tags in use -system.cpu.icache.total_refs 4013232252 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 555.745887 # Cycle average of tags in use +system.cpu.icache.total_refs 4013232208 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5945529.262222 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5945529.197037 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 555.745883 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 555.745887 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.271360 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.271360 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 4013232252 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4013232252 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4013232252 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4013232252 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4013232252 # number of overall hits -system.cpu.icache.overall_hits::total 4013232252 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 4013232208 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4013232208 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4013232208 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4013232208 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4013232208 # number of overall hits +system.cpu.icache.overall_hits::total 4013232208 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 675 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 675 # number of demand (read+write) misses @@ -84,12 +84,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 37868000 system.cpu.icache.demand_miss_latency::total 37868000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 37868000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 37868000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 4013232927 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 4013232927 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 4013232927 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 4013232927 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 4013232927 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 4013232927 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 4013232883 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 4013232883 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 4013232883 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 4013232883 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 4013232883 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 4013232883 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses @@ -136,22 +136,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53100.740741 system.cpu.icache.overall_avg_mshr_miss_latency::total 53100.740741 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9108581 # number of replacements -system.cpu.dcache.tagsinuse 4084.618075 # Cycle average of tags in use -system.cpu.dcache.total_refs 1668600409 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4084.618108 # Cycle average of tags in use +system.cpu.dcache.total_refs 1668600405 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 58864243000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4084.618075 # Average occupied blocks per requestor +system.cpu.dcache.warmup_cycle 58864195000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4084.618108 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.997221 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.997221 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1231961899 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1231961899 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 1231961895 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1231961895 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 436638510 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 436638510 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1668600409 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1668600409 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1668600409 # number of overall hits -system.cpu.dcache.overall_hits::total 1668600409 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 1668600405 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1668600405 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1668600405 # number of overall hits +system.cpu.dcache.overall_hits::total 1668600405 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses @@ -168,14 +168,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 218826366000 system.cpu.dcache.demand_miss_latency::total 218826366000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 218826366000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 218826366000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1239184749 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1239184749 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 1239184745 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1239184745 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 438528337 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 438528337 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1677713086 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1677713086 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1677713086 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1677713086 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 1677713082 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1677713082 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1677713082 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1677713082 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses @@ -236,14 +236,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21013.400892 system.cpu.dcache.overall_avg_mshr_miss_latency::total 21013.400892 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2158210 # number of replacements -system.cpu.l2cache.tagsinuse 30851.471232 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 30851.471482 # Cycle average of tags in use system.cpu.l2cache.total_refs 8410861 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 2187939 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 3.844194 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 1317386171000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14661.795010 # Average occupied blocks per requestor +system.cpu.l2cache.warmup_cycle 1317386123000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14661.795129 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 21.581563 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 16168.094659 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 16168.094790 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.447442 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.000659 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.493411 # Average percentage of cache occupancy diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini index 505ad335a..48cbbbbde 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini @@ -99,8 +99,8 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 -master=system.physmem.port[0] +width=8 +master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.physmem] diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout index 435dd5018..a6bbf65c9 100755 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:01:47 -gem5 started Jun 4 2012 15:01:23 +gem5 compiled Aug 13 2012 17:04:37 +gem5 started Aug 13 2012 18:21:10 gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sav @@ -23,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 info: Increasing stack size by one page. -122 123 124 Exiting @ tick 96722951500 because target called exit() +122 123 124 Exiting @ tick 96722945000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt index 7fc4c3f51..fd4974069 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.096723 # Number of seconds simulated -sim_ticks 96722951500 # Number of ticks simulated -final_tick 96722951500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 96722945000 # Number of ticks simulated +final_tick 96722945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2785942 # Simulator instruction rate (inst/s) -host_op_rate 2785945 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1392980356 # Simulator tick rate (ticks/s) -host_mem_usage 218424 # Number of bytes of host memory used -host_seconds 69.44 # Real time elapsed on the host -sim_insts 193444531 # Number of instructions simulated -sim_ops 193444769 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 773782192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 223463414 # Number of bytes read from this memory -system.physmem.bytes_read::total 997245606 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 773782192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 773782192 # Number of instructions bytes read from this memory +host_inst_rate 2917410 # Simulator instruction rate (inst/s) +host_op_rate 2917413 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1458714810 # Simulator tick rate (ticks/s) +host_mem_usage 226640 # Number of bytes of host memory used +host_seconds 66.31 # Real time elapsed on the host +sim_insts 193444518 # Number of instructions simulated +sim_ops 193444756 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 773782140 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 223463413 # Number of bytes read from this memory +system.physmem.bytes_read::total 997245553 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 773782140 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 773782140 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 72065412 # Number of bytes written to this memory system.physmem.bytes_written::total 72065412 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 193445548 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 57735069 # Number of read requests responded to by this memory -system.physmem.num_reads::total 251180617 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 193445535 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 57735068 # Number of read requests responded to by this memory +system.physmem.num_reads::total 251180603 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 18976439 # Number of write requests responded to by this memory system.physmem.num_writes::total 18976439 # Number of write requests responded to by this memory system.physmem.num_other::cpu.data 22406 # Number of other requests responded to by this memory system.physmem.num_other::total 22406 # Number of other requests responded to by this memory system.physmem.bw_read::cpu.inst 7999985319 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2310345275 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10310330594 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2310345420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10310330739 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 7999985319 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 7999985319 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 745070440 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 745070440 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 745070490 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 745070490 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::cpu.inst 7999985319 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3055415715 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11055401034 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3055415910 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11055401229 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 401 # Number of system calls -system.cpu.numCycles 193445904 # number of cpu cycles simulated +system.cpu.numCycles 193445891 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 193444531 # Number of instructions committed -system.cpu.committedOps 193444769 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 167974818 # Number of integer alu accesses +system.cpu.committedInsts 193444518 # Number of instructions committed +system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses system.cpu.num_func_calls 1957920 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8665107 # number of instructions that are conditional controls -system.cpu.num_int_insts 167974818 # number of integer instructions +system.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls +system.cpu.num_int_insts 167974806 # number of integer instructions system.cpu.num_fp_insts 1970372 # number of float instructions -system.cpu.num_int_register_reads 352617963 # number of times the integer registers were read -system.cpu.num_int_register_writes 163060137 # number of times the integer registers were written +system.cpu.num_int_register_reads 352617941 # number of times the integer registers were read +system.cpu.num_int_register_writes 163060124 # number of times the integer registers were written system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written -system.cpu.num_mem_refs 76733959 # number of memory refs -system.cpu.num_load_insts 57735092 # Number of load instructions +system.cpu.num_mem_refs 76733958 # number of memory refs +system.cpu.num_load_insts 57735091 # Number of load instructions system.cpu.num_store_insts 18998867 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 193445904 # Number of busy cycles +system.cpu.num_busy_cycles 193445891 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini index fd32216ef..27af806dd 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -158,7 +158,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing +cwd=build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing egid=100 env= errout=cerr @@ -181,7 +181,7 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout index 123985114..d049db054 100755 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:54:18 -gem5 started Jul 2 2012 12:35:14 +gem5 compiled Aug 13 2012 17:04:37 +gem5 started Aug 13 2012 18:21:48 gem5 executing on zizzer -command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing -Couldn't unlink build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing/smred.sav -Couldn't unlink build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing/smred.sv2 +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing +Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sav +Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 info: Increasing stack size by one page. -122 123 124 Exiting @ tick 270628681000 because target called exit() +122 123 124 Exiting @ tick 270628667000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index 23f251d47..9d89c8f58 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.270629 # Number of seconds simulated -sim_ticks 270628681000 # Number of ticks simulated -final_tick 270628681000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 270628667000 # Number of ticks simulated +final_tick 270628667000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1015199 # Simulator instruction rate (inst/s) -host_op_rate 1015200 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1420261450 # Simulator tick rate (ticks/s) -host_mem_usage 225612 # Number of bytes of host memory used -host_seconds 190.55 # Real time elapsed on the host -sim_insts 193444531 # Number of instructions simulated -sim_ops 193444769 # Number of ops (including micro ops) simulated +host_inst_rate 1532509 # Simulator instruction rate (inst/s) +host_op_rate 1532510 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2143977461 # Simulator tick rate (ticks/s) +host_mem_usage 235212 # Number of bytes of host memory used +host_seconds 126.23 # Real time elapsed on the host +sim_insts 193444518 # Number of instructions simulated +sim_ops 193444756 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory system.physmem.bytes_read::total 331072 # Number of bytes read from this memory @@ -28,43 +28,43 @@ system.physmem.bw_total::cpu.inst 850642 # To system.physmem.bw_total::cpu.data 372703 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1223344 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 401 # Number of system calls -system.cpu.numCycles 541257362 # number of cpu cycles simulated +system.cpu.numCycles 541257334 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 193444531 # Number of instructions committed -system.cpu.committedOps 193444769 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 167974818 # Number of integer alu accesses +system.cpu.committedInsts 193444518 # Number of instructions committed +system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses system.cpu.num_func_calls 1957920 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8665107 # number of instructions that are conditional controls -system.cpu.num_int_insts 167974818 # number of integer instructions +system.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls +system.cpu.num_int_insts 167974806 # number of integer instructions system.cpu.num_fp_insts 1970372 # number of float instructions -system.cpu.num_int_register_reads 352617963 # number of times the integer registers were read -system.cpu.num_int_register_writes 163060136 # number of times the integer registers were written +system.cpu.num_int_register_reads 352617941 # number of times the integer registers were read +system.cpu.num_int_register_writes 163060123 # number of times the integer registers were written system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written -system.cpu.num_mem_refs 76733959 # number of memory refs -system.cpu.num_load_insts 57735092 # Number of load instructions +system.cpu.num_mem_refs 76733958 # number of memory refs +system.cpu.num_load_insts 57735091 # Number of load instructions system.cpu.num_store_insts 18998867 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 541257362 # Number of busy cycles +system.cpu.num_busy_cycles 541257334 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 10362 # number of replacements -system.cpu.icache.tagsinuse 1591.549936 # Cycle average of tags in use -system.cpu.icache.total_refs 193433261 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1591.550018 # Cycle average of tags in use +system.cpu.icache.total_refs 193433248 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 15741.639079 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 15741.638021 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1591.549936 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1591.550018 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.777124 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.777124 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 193433261 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 193433261 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 193433261 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 193433261 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 193433261 # number of overall hits -system.cpu.icache.overall_hits::total 193433261 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 193433248 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 193433248 # number of overall hits +system.cpu.icache.overall_hits::total 193433248 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 12288 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 12288 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 12288 # number of demand (read+write) misses @@ -77,12 +77,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 323106000 system.cpu.icache.demand_miss_latency::total 323106000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 323106000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 323106000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 193445549 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 193445549 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 193445549 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 193445549 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 193445549 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 193445549 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 193445536 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 193445536 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 193445536 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000064 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000064 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 # miss rate for demand accesses @@ -129,24 +129,24 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23294.433594 system.cpu.icache.overall_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2 # number of replacements -system.cpu.dcache.tagsinuse 1237.179086 # Cycle average of tags in use -system.cpu.dcache.total_refs 76732338 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1237.179149 # Cycle average of tags in use +system.cpu.dcache.total_refs 76732337 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1576 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 48688.031726 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 48688.031091 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1237.179086 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 1237.179149 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.302046 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.302046 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 57734571 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 57734571 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 76709933 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 76709933 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 76709933 # number of overall hits -system.cpu.dcache.overall_hits::total 76709933 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 76709932 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 76709932 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 76709932 # number of overall hits +system.cpu.dcache.overall_hits::total 76709932 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 498 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 498 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1077 # number of WriteReq misses @@ -167,16 +167,16 @@ system.cpu.dcache.demand_miss_latency::cpu.data 88200000 system.cpu.dcache.demand_miss_latency::total 88200000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 88200000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 88200000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 57735069 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 57735069 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 18976439 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 22406 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 22406 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 76711508 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 76711508 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 76711508 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 76711508 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 76711507 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 76711507 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 76711507 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 76711507 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000009 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses @@ -249,14 +249,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2678.289467 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2678.289604 # Cycle average of tags in use system.cpu.l2cache.total_refs 8691 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 4097 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.121308 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 0.000456 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2275.240506 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 403.048505 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2275.240623 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 403.048526 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.069435 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini index c72ea59c4..1bbc05455 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -510,7 +510,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing +cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing egid=100 env= errout=cerr @@ -533,7 +533,7 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout index 6f015db37..4fc266b67 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:58:39 -gem5 started Jul 2 2012 14:16:35 +gem5 compiled Aug 13 2012 17:08:22 +gem5 started Aug 13 2012 19:40:50 gem5 executing on zizzer -command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing -Couldn't unlink build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing/smred.sav -Couldn't unlink build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing/smred.sv2 +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing +Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav +Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -24,4 +24,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 87870590500 because target called exit() +122 123 124 Exiting @ tick 87745680500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index d6435aa8f..a2fae1867 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,167 +1,167 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.087871 # Number of seconds simulated -sim_ticks 87870590500 # Number of ticks simulated -final_tick 87870590500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.087746 # Number of seconds simulated +sim_ticks 87745680500 # Number of ticks simulated +final_tick 87745680500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71260 # Simulator instruction rate (inst/s) -host_op_rate 119437 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47410913 # Simulator tick rate (ticks/s) -host_mem_usage 239040 # Number of bytes of host memory used -host_seconds 1853.38 # Real time elapsed on the host -sim_insts 132071227 # Number of instructions simulated -sim_ops 221363017 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 219328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125312 # Number of bytes read from this memory -system.physmem.bytes_read::total 344640 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 219328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 219328 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3427 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1958 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5385 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2496034 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1426097 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3922131 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2496034 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2496034 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2496034 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1426097 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3922131 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 74091 # Simulator instruction rate (inst/s) +host_op_rate 124183 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49224615 # Simulator tick rate (ticks/s) +host_mem_usage 243944 # Number of bytes of host memory used +host_seconds 1782.56 # Real time elapsed on the host +sim_insts 132071192 # Number of instructions simulated +sim_ops 221362960 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 219904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125632 # Number of bytes read from this memory +system.physmem.bytes_read::total 345536 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 219904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219904 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3436 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1963 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5399 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2506152 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1431774 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3937926 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2506152 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2506152 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2506152 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1431774 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3937926 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 175741182 # number of cpu cycles simulated +system.cpu.numCycles 175491362 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 20899544 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 20899544 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2209301 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 15564510 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 13831117 # Number of BTB hits +system.cpu.BPredUnit.lookups 20912942 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 20912942 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2216763 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 15581100 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 13825679 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 27321618 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 227238507 # Number of instructions fetch has processed -system.cpu.fetch.Branches 20899544 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13831117 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 59893533 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 19501221 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 71423982 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 856 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 5992 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 25806035 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 465205 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 175660343 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.136482 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.300848 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27332947 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 227227686 # Number of instructions fetch has processed +system.cpu.fetch.Branches 20912942 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13825679 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 59890374 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 19506044 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 71169937 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 648 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 5818 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 25808663 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 466739 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 175411287 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.139847 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.302571 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 117444586 66.86% 66.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3198914 1.82% 68.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2491940 1.42% 70.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3160979 1.80% 71.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3538324 2.01% 73.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3753773 2.14% 76.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4538217 2.58% 78.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2790941 1.59% 80.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 34742669 19.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 117195884 66.81% 66.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3196193 1.82% 68.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2495974 1.42% 70.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3146701 1.79% 71.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3544894 2.02% 73.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3750522 2.14% 76.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4536949 2.59% 78.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2782229 1.59% 80.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 34761941 19.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 175660343 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.118922 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.293029 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 40683921 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 61195549 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 46567945 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10198566 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 17014362 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 366345235 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 17014362 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 48576080 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 16382165 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 23120 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 48162732 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 45501884 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 357078991 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 31 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 20682611 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22563031 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 2159 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 507023115 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1130829367 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1120559538 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10269829 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 320143989 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 186879126 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1752 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1748 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 95224460 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 89733433 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 33126423 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 59021419 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 19494501 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 344814343 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 7981 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 271092174 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 252461 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 122957683 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 297045432 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 6735 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 175660343 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.543275 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.467777 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 175411287 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.119168 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.294808 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 40672745 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 60972096 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 46577224 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10177659 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 17011563 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 366355504 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 17011563 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 48566329 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 16269709 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 22974 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 48161797 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 45378915 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 357087422 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 17 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 20597536 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22542401 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 2240 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 506970122 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1130784117 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1120479639 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10304478 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 320143897 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 186826225 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1722 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1714 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 95149637 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89685413 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 33120690 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 58937447 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 19448557 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 344768238 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 7633 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 271173389 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 254823 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 122910358 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 296566546 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 6387 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 175411287 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.545929 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.469162 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 49300631 28.07% 28.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 52565821 29.92% 57.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34438082 19.60% 77.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18985110 10.81% 88.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12671961 7.21% 95.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4951895 2.82% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2092177 1.19% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 542850 0.31% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 111816 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 49124172 28.01% 28.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 52503398 29.93% 57.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 34371281 19.59% 77.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18965832 10.81% 88.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12724485 7.25% 95.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4970567 2.83% 98.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2095715 1.19% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 541828 0.31% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 114009 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 175660343 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 175411287 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 90987 3.50% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2226720 85.76% 89.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 278883 10.74% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 95040 3.65% 3.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2235381 85.95% 89.60% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 270412 10.40% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1212971 0.45% 0.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 176440740 65.09% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1212866 0.45% 0.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 176481640 65.08% 65.53% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.53% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1591628 0.59% 66.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1593197 0.59% 66.12% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.12% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.12% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.12% # Type of FU issued @@ -187,160 +187,160 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.12% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.12% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.12% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 68336239 25.21% 91.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 23510596 8.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 68356368 25.21% 91.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 23529318 8.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 271092174 # Type of FU issued -system.cpu.iq.rate 1.542565 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2596590 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009578 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 715388458 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 463212218 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 263468773 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5305284 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4868318 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2548590 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 269817574 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2658219 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18900853 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 271173389 # Type of FU issued +system.cpu.iq.rate 1.545224 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2600833 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009591 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 715305678 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 463103362 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 263539409 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 5308043 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4883539 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2551351 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 269902017 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2659339 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18957330 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 33083843 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 30126 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 305710 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12610707 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 33035827 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 30313 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 305871 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12604974 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 47697 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 47688 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 17014362 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 531971 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 245364 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 344822324 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 299116 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 89733433 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 33126423 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1715 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 158423 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 34384 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 305710 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1300553 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1025953 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2326506 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 267978293 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 67258020 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3113881 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 17011563 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 523331 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 253149 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 344775871 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 305918 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 89685413 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 33120690 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1684 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 166880 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 32620 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 305871 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1304049 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1033069 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2337118 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 268044549 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 67281784 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3128840 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 90379162 # number of memory reference insts executed -system.cpu.iew.exec_branches 14791945 # Number of branches executed -system.cpu.iew.exec_stores 23121142 # Number of stores executed -system.cpu.iew.exec_rate 1.524846 # Inst execution rate -system.cpu.iew.wb_sent 266905236 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 266017363 # cumulative count of insts written-back -system.cpu.iew.wb_producers 214552655 # num instructions producing a value -system.cpu.iew.wb_consumers 504482299 # num instructions consuming a value +system.cpu.iew.exec_refs 90419534 # number of memory reference insts executed +system.cpu.iew.exec_branches 14798772 # Number of branches executed +system.cpu.iew.exec_stores 23137750 # Number of stores executed +system.cpu.iew.exec_rate 1.527395 # Inst execution rate +system.cpu.iew.wb_sent 266978184 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 266090760 # cumulative count of insts written-back +system.cpu.iew.wb_producers 214617061 # num instructions producing a value +system.cpu.iew.wb_consumers 504567875 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.513688 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.425293 # average fanout of values written-back +system.cpu.iew.wb_rate 1.516261 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.425348 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 132071227 # The number of committed instructions -system.cpu.commit.commitCommittedOps 221363017 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 123572958 # The number of squashed insts skipped by commit +system.cpu.commit.commitCommittedInsts 132071192 # The number of committed instructions +system.cpu.commit.commitCommittedOps 221362960 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 123521765 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2210019 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158645981 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.395327 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.792270 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2217341 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158399724 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.397496 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.795426 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 54337756 34.25% 34.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 60487783 38.13% 72.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15594396 9.83% 82.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12721179 8.02% 90.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4547355 2.87% 93.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2966330 1.87% 94.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2094139 1.32% 96.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1239343 0.78% 97.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4657700 2.94% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 54208957 34.22% 34.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 60399478 38.13% 72.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15563923 9.83% 82.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12697970 8.02% 90.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4547982 2.87% 93.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2968547 1.87% 94.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2080222 1.31% 96.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1235429 0.78% 97.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4697216 2.97% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158645981 # Number of insts commited each cycle -system.cpu.commit.committedInsts 132071227 # Number of instructions committed -system.cpu.commit.committedOps 221363017 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 158399724 # Number of insts commited each cycle +system.cpu.commit.committedInsts 132071192 # Number of instructions committed +system.cpu.commit.committedOps 221362960 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 77165306 # Number of memory references committed -system.cpu.commit.loads 56649590 # Number of loads committed +system.cpu.commit.refs 77165302 # Number of memory references committed +system.cpu.commit.loads 56649586 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 12326943 # Number of branches committed +system.cpu.commit.branches 12326938 # Number of branches committed system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. -system.cpu.commit.int_insts 220339606 # Number of committed integer instructions. +system.cpu.commit.int_insts 220339549 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4657700 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4697216 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 498924256 # The number of ROB reads -system.cpu.rob.rob_writes 706924128 # The number of ROB writes -system.cpu.timesIdled 1775 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 80839 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 132071227 # Number of Instructions Simulated -system.cpu.committedOps 221363017 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 132071227 # Number of Instructions Simulated -system.cpu.cpi 1.330655 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.330655 # CPI: Total CPI of All Threads -system.cpu.ipc 0.751510 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.751510 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 657690172 # number of integer regfile reads -system.cpu.int_regfile_writes 365563414 # number of integer regfile writes -system.cpu.fp_regfile_reads 3506965 # number of floating regfile reads -system.cpu.fp_regfile_writes 2222676 # number of floating regfile writes -system.cpu.misc_regfile_reads 139526646 # number of misc regfile reads +system.cpu.rob.rob_reads 498587233 # The number of ROB reads +system.cpu.rob.rob_writes 706819353 # The number of ROB writes +system.cpu.timesIdled 1778 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 80075 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 132071192 # Number of Instructions Simulated +system.cpu.committedOps 221362960 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated +system.cpu.cpi 1.328763 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.328763 # CPI: Total CPI of All Threads +system.cpu.ipc 0.752579 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.752579 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 657890956 # number of integer regfile reads +system.cpu.int_regfile_writes 365630254 # number of integer regfile writes +system.cpu.fp_regfile_reads 3509539 # number of floating regfile reads +system.cpu.fp_regfile_writes 2224150 # number of floating regfile writes +system.cpu.misc_regfile_reads 139559443 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.icache.replacements 5610 # number of replacements -system.cpu.icache.tagsinuse 1629.478377 # Cycle average of tags in use -system.cpu.icache.total_refs 25796956 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 7578 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3404.190552 # Average number of references to valid blocks. +system.cpu.icache.replacements 5776 # number of replacements +system.cpu.icache.tagsinuse 1633.892050 # Cycle average of tags in use +system.cpu.icache.total_refs 25799407 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7743 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 3331.965259 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1629.478377 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.795644 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.795644 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25796956 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25796956 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25796956 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25796956 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25796956 # number of overall hits -system.cpu.icache.overall_hits::total 25796956 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 9079 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 9079 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 9079 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 9079 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 9079 # number of overall misses -system.cpu.icache.overall_misses::total 9079 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 194493000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 194493000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 194493000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 194493000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 194493000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 194493000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25806035 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25806035 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25806035 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25806035 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25806035 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25806035 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000352 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000352 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000352 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000352 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000352 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000352 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21422.293204 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21422.293204 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21422.293204 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21422.293204 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21422.293204 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21422.293204 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1633.892050 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.797799 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.797799 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25799407 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25799407 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25799407 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25799407 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25799407 # number of overall hits +system.cpu.icache.overall_hits::total 25799407 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 9256 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 9256 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 9256 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 9256 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 9256 # number of overall misses +system.cpu.icache.overall_misses::total 9256 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 196263500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 196263500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 196263500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 196263500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 196263500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 196263500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25808663 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25808663 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25808663 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25808663 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25808663 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25808663 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000359 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000359 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000359 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000359 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000359 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000359 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21203.921780 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21203.921780 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21203.921780 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21203.921780 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21203.921780 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21203.921780 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -349,94 +349,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1363 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1363 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1363 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1363 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1363 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1363 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7716 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 7716 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 7716 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 7716 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 7716 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 7716 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 136466500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 136466500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 136466500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 136466500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 136466500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 136466500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000299 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000299 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000299 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17686.171591 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17686.171591 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17686.171591 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17686.171591 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17686.171591 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17686.171591 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1390 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1390 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1390 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1390 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1390 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1390 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7866 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 7866 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 7866 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 7866 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 7866 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 7866 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 137281500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 137281500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 137281500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 137281500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 137281500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 137281500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000305 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000305 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000305 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000305 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000305 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000305 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17452.517162 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17452.517162 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17452.517162 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 17452.517162 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17452.517162 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 17452.517162 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 57 # number of replacements -system.cpu.dcache.tagsinuse 1427.277065 # Cycle average of tags in use -system.cpu.dcache.total_refs 68700923 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1995 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34436.552882 # Average number of references to valid blocks. +system.cpu.dcache.replacements 56 # number of replacements +system.cpu.dcache.tagsinuse 1432.539933 # Cycle average of tags in use +system.cpu.dcache.total_refs 68667989 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2001 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34316.836082 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1427.277065 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.348456 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.348456 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 48186723 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 48186723 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20514032 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20514032 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 68700755 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 68700755 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 68700755 # number of overall hits -system.cpu.dcache.overall_hits::total 68700755 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 751 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 751 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1698 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1698 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2449 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2449 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2449 # number of overall misses -system.cpu.dcache.overall_misses::total 2449 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 26925000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 26925000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 64818000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 64818000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 91743000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 91743000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 91743000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 91743000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 48187474 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 48187474 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 1432.539933 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.349741 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.349741 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 48153803 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 48153803 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20514043 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20514043 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 68667846 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 68667846 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 68667846 # number of overall hits +system.cpu.dcache.overall_hits::total 68667846 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 738 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 738 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1687 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1687 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2425 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2425 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2425 # number of overall misses +system.cpu.dcache.overall_misses::total 2425 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 26760000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 26760000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 64476000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 64476000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 91236000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 91236000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 91236000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 91236000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 48154541 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 48154541 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 68703204 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 68703204 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 68703204 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 68703204 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000016 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000083 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000083 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000036 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000036 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000036 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000036 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35852.197071 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 35852.197071 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38173.144876 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38173.144876 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37461.412822 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37461.412822 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37461.412822 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37461.412822 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 68670271 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 68670271 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 68670271 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 68670271 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000015 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000015 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000082 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000082 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000035 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000035 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000035 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000035 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36260.162602 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36260.162602 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38219.324244 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38219.324244 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37623.092784 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37623.092784 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37623.092784 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37623.092784 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -447,136 +447,136 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 13 # number of writebacks system.cpu.dcache.writebacks::total 13 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 310 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 310 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 295 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 295 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 4 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 4 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 314 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 314 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 314 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 314 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 441 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 441 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1694 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1694 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2135 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2135 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2135 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15484500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 15484500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59638500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 59638500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 75123000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 75123000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 75123000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 75123000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 299 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 299 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 299 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 299 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 443 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 443 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1683 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1683 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2126 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2126 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2126 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2126 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15550500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 15550500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59322000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 59322000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 74872500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 74872500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 74872500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 74872500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000083 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000083 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000082 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000082 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000031 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35112.244898 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35112.244898 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35205.726092 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35205.726092 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35186.416862 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 35186.416862 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35186.416862 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 35186.416862 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35102.708804 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35102.708804 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35247.771836 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35247.771836 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35217.544685 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 35217.544685 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35217.544685 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 35217.544685 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2583.556674 # Cycle average of tags in use -system.cpu.l2cache.total_refs 4185 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3837 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 1.090696 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2579.346605 # Cycle average of tags in use +system.cpu.l2cache.total_refs 4342 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3848 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 1.128378 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 1.869475 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2280.566529 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 301.120670 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000057 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.069597 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.009189 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.078844 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 4151 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 31 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 4182 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 171772000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.443756 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.927602 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.469884 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994862 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994862 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.452230 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980471 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.562402 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.452230 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980471 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.562402 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31936.095711 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33152.811736 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32065.823775 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994875 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994875 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.443756 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980030 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.553971 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.443756 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980030 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.553971 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31886.350407 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33150 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32021.060842 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31286.636540 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31286.636540 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31936.095711 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31676.455567 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31841.689879 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31936.095711 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31676.455567 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31841.689879 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31306.503542 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31306.503542 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31886.350407 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31691.543556 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31815.521393 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31886.350407 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31691.543556 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31815.521393 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini index 5b797a438..a704c3927 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini @@ -120,8 +120,8 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 -master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +width=8 +master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master [system.physmem] diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout index f20b23119..7016aa168 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 13:44:28 -gem5 started Jun 4 2012 16:58:23 +gem5 compiled Aug 13 2012 17:08:22 +gem5 started Aug 13 2012 20:10:43 gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sav @@ -24,4 +24,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 131393100000 because target called exit() +122 123 124 Exiting @ tick 131393067000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt index 52d17f26b..3993acb05 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.131393 # Number of seconds simulated -sim_ticks 131393100000 # Number of ticks simulated -final_tick 131393100000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 131393067000 # Number of ticks simulated +final_tick 131393067000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1290267 # Simulator instruction rate (inst/s) -host_op_rate 2162601 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1283641901 # Simulator tick rate (ticks/s) -host_mem_usage 223844 # Number of bytes of host memory used -host_seconds 102.36 # Real time elapsed on the host -sim_insts 132071228 # Number of instructions simulated -sim_ops 221363018 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 1387955288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 310423754 # Number of bytes read from this memory -system.physmem.bytes_read::total 1698379042 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1387955288 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1387955288 # Number of instructions bytes read from this memory +host_inst_rate 1300121 # Simulator instruction rate (inst/s) +host_op_rate 2179118 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1293445391 # Simulator tick rate (ticks/s) +host_mem_usage 231396 # Number of bytes of host memory used +host_seconds 101.58 # Real time elapsed on the host +sim_insts 132071193 # Number of instructions simulated +sim_ops 221362961 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 1387954936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 310423750 # Number of bytes read from this memory +system.physmem.bytes_read::total 1698378686 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1387954936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1387954936 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 99822189 # Number of bytes written to this memory system.physmem.bytes_written::total 99822189 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 173494411 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 56682008 # Number of read requests responded to by this memory -system.physmem.num_reads::total 230176419 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 173494367 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 56682004 # Number of read requests responded to by this memory +system.physmem.num_reads::total 230176371 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 20515730 # Number of write requests responded to by this memory system.physmem.num_writes::total 20515730 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10563380330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2362557501 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12925937831 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10563380330 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10563380330 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 759721698 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 759721698 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10563380330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3122279199 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13685659529 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 10563380304 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2362558064 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12925938368 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10563380304 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10563380304 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 759721889 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 759721889 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10563380304 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3122279953 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13685660256 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 262786201 # number of cpu cycles simulated +system.cpu.numCycles 262786135 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 132071228 # Number of instructions committed -system.cpu.committedOps 221363018 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses +system.cpu.committedInsts 132071193 # Number of instructions committed +system.cpu.committedOps 221362961 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 220339550 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8268471 # number of instructions that are conditional controls -system.cpu.num_int_insts 220339607 # number of integer instructions +system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls +system.cpu.num_int_insts 220339550 # number of integer instructions system.cpu.num_fp_insts 2162459 # number of float instructions -system.cpu.num_int_register_reads 705008823 # number of times the integer registers were read -system.cpu.num_int_register_writes 318312586 # number of times the integer registers were written +system.cpu.num_int_register_reads 705008645 # number of times the integer registers were read +system.cpu.num_int_register_writes 318312494 # number of times the integer registers were written system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written -system.cpu.num_mem_refs 77165306 # number of memory refs -system.cpu.num_load_insts 56649590 # Number of load instructions +system.cpu.num_mem_refs 77165302 # number of memory refs +system.cpu.num_load_insts 56649586 # Number of load instructions system.cpu.num_store_insts 20515716 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 262786201 # Number of busy cycles +system.cpu.num_busy_cycles 262786135 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini index 1ebce5cb8..6a05638c8 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini @@ -179,7 +179,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing +cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing egid=100 env= errout=cerr @@ -202,7 +202,7 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout index 2dfefd0be..54930ae6e 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:58:39 -gem5 started Jul 2 2012 14:50:18 +gem5 compiled Aug 13 2012 17:08:22 +gem5 started Aug 13 2012 20:12:35 gem5 executing on zizzer -command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing -Couldn't unlink build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing/smred.sav -Couldn't unlink build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing/smred.sv2 +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing +Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sav +Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -24,4 +24,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 250981042000 because target called exit() +122 123 124 Exiting @ tick 250980994000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index f0166c804..b04007fc9 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.250981 # Number of seconds simulated -sim_ticks 250981042000 # Number of ticks simulated -final_tick 250981042000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 250980994000 # Number of ticks simulated +final_tick 250980994000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 522050 # Simulator instruction rate (inst/s) -host_op_rate 875003 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 992076486 # Simulator tick rate (ticks/s) -host_mem_usage 235972 # Number of bytes of host memory used -host_seconds 252.99 # Real time elapsed on the host -sim_insts 132071228 # Number of instructions simulated -sim_ops 221363018 # Number of ops (including micro ops) simulated +host_inst_rate 746540 # Simulator instruction rate (inst/s) +host_op_rate 1251266 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1418683559 # Simulator tick rate (ticks/s) +host_mem_usage 239848 # Number of bytes of host memory used +host_seconds 176.91 # Real time elapsed on the host +sim_insts 132071193 # Number of instructions simulated +sim_ops 221362961 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory system.physmem.bytes_read::total 303040 # Number of bytes read from this memory @@ -28,43 +28,43 @@ system.physmem.bw_total::cpu.inst 724198 # To system.physmem.bw_total::cpu.data 483224 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1207422 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 501962084 # number of cpu cycles simulated +system.cpu.numCycles 501961988 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 132071228 # Number of instructions committed -system.cpu.committedOps 221363018 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses +system.cpu.committedInsts 132071193 # Number of instructions committed +system.cpu.committedOps 221362961 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 220339550 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8268471 # number of instructions that are conditional controls -system.cpu.num_int_insts 220339607 # number of integer instructions +system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls +system.cpu.num_int_insts 220339550 # number of integer instructions system.cpu.num_fp_insts 2162459 # number of float instructions -system.cpu.num_int_register_reads 705008823 # number of times the integer registers were read -system.cpu.num_int_register_writes 318312586 # number of times the integer registers were written +system.cpu.num_int_register_reads 705008645 # number of times the integer registers were read +system.cpu.num_int_register_writes 318312494 # number of times the integer registers were written system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written -system.cpu.num_mem_refs 77165306 # number of memory refs -system.cpu.num_load_insts 56649590 # Number of load instructions +system.cpu.num_mem_refs 77165302 # number of memory refs +system.cpu.num_load_insts 56649586 # Number of load instructions system.cpu.num_store_insts 20515716 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 501962084 # Number of busy cycles +system.cpu.num_busy_cycles 501961988 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 2836 # number of replacements -system.cpu.icache.tagsinuse 1455.271683 # Cycle average of tags in use -system.cpu.icache.total_refs 173489718 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1455.271959 # Cycle average of tags in use +system.cpu.icache.total_refs 173489674 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 36959.888794 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 36959.879421 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1455.271683 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1455.271959 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.710582 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.710582 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 173489718 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 173489718 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 173489718 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 173489718 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 173489718 # number of overall hits -system.cpu.icache.overall_hits::total 173489718 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 173489674 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 173489674 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 173489674 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 173489674 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 173489674 # number of overall hits +system.cpu.icache.overall_hits::total 173489674 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 4694 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 4694 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 4694 # number of demand (read+write) misses @@ -77,12 +77,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 185042500 system.cpu.icache.demand_miss_latency::total 185042500 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 185042500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 185042500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 173494412 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 173494412 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 173494412 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 173494412 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 173494412 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 173494412 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 173494368 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 173494368 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 173494368 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 173494368 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 173494368 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 173494368 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000027 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 # miss rate for demand accesses @@ -129,22 +129,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.358756 system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.358756 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 41 # number of replacements -system.cpu.dcache.tagsinuse 1363.438791 # Cycle average of tags in use -system.cpu.dcache.total_refs 77195833 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1363.439047 # Cycle average of tags in use +system.cpu.dcache.total_refs 77195829 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 40522.746982 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 40522.744882 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1363.438791 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 1363.439047 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.332871 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.332871 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 56681681 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 56681681 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 56681677 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 56681677 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20514152 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 20514152 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 77195833 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 77195833 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 77195833 # number of overall hits -system.cpu.dcache.overall_hits::total 77195833 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 77195829 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 77195829 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 77195829 # number of overall hits +system.cpu.dcache.overall_hits::total 77195829 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses @@ -161,14 +161,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 106263000 system.cpu.dcache.demand_miss_latency::total 106263000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 106263000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 106263000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 56682008 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 56682008 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 56682004 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 56682004 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 77197738 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 77197738 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 77197738 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 77197738 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 77197734 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 77197734 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 77197734 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 77197734 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses @@ -229,14 +229,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.839895 system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.839895 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2058.146079 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2058.146468 # Cycle average of tags in use system.cpu.l2cache.total_refs 1862 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3164 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.588496 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 0.021788 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1829.948431 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 228.175860 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1829.948778 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 228.175901 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.055846 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy |