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-rw-r--r--tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini43
-rw-r--r--tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini47
-rw-r--r--tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini45
-rw-r--r--tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini48
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini268
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini62
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini326
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini792
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini324
-rwxr-xr-xtests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr1
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini71
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini70
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini64
-rw-r--r--tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini123
-rw-r--r--tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt2460
-rw-r--r--tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal12
-rw-r--r--tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini113
-rw-r--r--tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt1611
-rw-r--r--tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/system.pc.com_1.terminal8
-rw-r--r--tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini126
-rw-r--r--tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json1148
-rw-r--r--tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt3082
-rw-r--r--tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal12
-rw-r--r--tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini18
-rw-r--r--tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json22
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini40
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini369
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini7
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini7
-rw-r--r--tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini7
-rw-r--r--tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini7
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini42
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini7
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini7
-rw-r--r--tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini40
-rw-r--r--tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini40
-rw-r--r--tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini369
-rw-r--r--tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini7
-rw-r--r--tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini7
-rw-r--r--tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini42
-rw-r--r--tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini7
-rw-r--r--tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini7
-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini40
-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini45
-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini7
-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini7
-rw-r--r--tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini40
-rw-r--r--tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini369
-rw-r--r--tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini7
-rw-r--r--tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini7
-rw-r--r--tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini42
-rw-r--r--tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini47
-rw-r--r--tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini9
-rw-r--r--tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini9
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini42
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini371
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt12
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini9
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini9
-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini40
-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini45
-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini7
-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini7
-rw-r--r--tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini40
-rw-r--r--tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini369
-rw-r--r--tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini7
-rw-r--r--tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini7
-rw-r--r--tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini7
-rw-r--r--tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini7
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini40
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini45
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini7
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini7
-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini40
-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini369
-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini7
-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini7
-rw-r--r--tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini7
-rw-r--r--tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini7
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini40
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini45
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini7
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini7
-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini40
-rwxr-xr-x[-rw-r--r--]tests/long/se/70.twolf/ref/arm/linux/minor-timing/simerr0
-rwxr-xr-x[-rw-r--r--]tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout0
-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini369
-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini7
-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini7
-rw-r--r--tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini7
-rw-r--r--tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini7
-rw-r--r--tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini42
-rw-r--r--tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini7
-rw-r--r--tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini7
94 files changed, 8253 insertions, 6391 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini
index 8f8a452cd..20e3fa665 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini
@@ -648,10 +648,11 @@ sequential_access=false
size=4194304
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -730,7 +731,7 @@ eventq_index=0
sys=system
[system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
@@ -776,11 +777,12 @@ sequential_access=false
size=1024
[system.membus]
-type=CoherentBus
+type=CoherentXBar
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -808,8 +810,33 @@ pio=system.membus.default
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -818,6 +845,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -831,19 +859,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
@@ -932,6 +967,7 @@ HeaderType=0
InterruptLine=30
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
@@ -1387,6 +1423,7 @@ HeaderType=0
InterruptLine=31
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
index 646b91983..f8b77d3d8 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
@@ -90,6 +90,7 @@ do_statistics_insts=true
dtb=system.cpu0.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -142,7 +143,6 @@ switched_out=false
system=system
tracer=system.cpu0.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=
dcache_port=system.cpu0.dcache.cpu_side
@@ -596,6 +596,7 @@ do_statistics_insts=true
dtb=system.cpu1.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -648,7 +649,6 @@ switched_out=false
system=system
tracer=system.cpu1.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=
dcache_port=system.cpu1.dcache.cpu_side
@@ -1139,7 +1139,7 @@ eventq_index=0
sys=system
[system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
@@ -1220,11 +1220,12 @@ sequential_access=false
size=4194304
[system.membus]
-type=CoherentBus
+type=CoherentXBar
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -1252,8 +1253,33 @@ pio=system.membus.default
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -1262,6 +1288,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -1275,19 +1302,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
@@ -1315,10 +1349,11 @@ output=true
port=3456
[system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -1387,6 +1422,7 @@ HeaderType=0
InterruptLine=30
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
@@ -1842,6 +1878,7 @@ HeaderType=0
InterruptLine=31
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
index 7628c3772..30c3fd76c 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
@@ -90,6 +90,7 @@ do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -142,7 +143,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=
dcache_port=system.cpu.dcache.cpu_side
@@ -597,10 +597,11 @@ sequential_access=false
size=4194304
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -679,7 +680,7 @@ eventq_index=0
sys=system
[system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
@@ -725,11 +726,12 @@ sequential_access=false
size=1024
[system.membus]
-type=CoherentBus
+type=CoherentXBar
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -757,8 +759,33 @@ pio=system.membus.default
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -767,6 +794,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -780,19 +808,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
@@ -881,6 +916,7 @@ HeaderType=0
InterruptLine=30
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
@@ -1336,6 +1372,7 @@ HeaderType=0
InterruptLine=31
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini
index d6b54e875..7ff9bd533 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini
@@ -84,9 +84,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -273,6 +270,7 @@ do_statistics_insts=true
dtb=system.cpu2.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -325,7 +323,6 @@ switched_out=true
system=system
tracer=system.cpu2.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=
@@ -740,7 +737,7 @@ eventq_index=0
sys=system
[system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
@@ -821,11 +818,12 @@ sequential_access=false
size=4194304
[system.membus]
-type=CoherentBus
+type=CoherentXBar
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -853,8 +851,33 @@ pio=system.membus.default
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -863,6 +886,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -876,19 +900,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
@@ -916,10 +947,11 @@ output=true
port=3456
[system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -988,6 +1020,7 @@ HeaderType=0
InterruptLine=30
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
@@ -1443,6 +1476,7 @@ HeaderType=0
InterruptLine=31
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini
index b768d26a9..a0c959df8 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini
@@ -99,7 +99,7 @@ voltage_domain=system.voltage_domain
[system.cpu0]
type=MinorCPU
-children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb tracer
+children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
branchPred=system.cpu0.branchPred
checker=Null
clk_domain=system.cpu_clk_domain
@@ -184,14 +184,14 @@ predType=tournament
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
-assoc=4
+assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=4
+mshrs=6
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -199,15 +199,15 @@ sequential_access=false
size=32768
system=system
tags=system.cpu0.dcache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
two_queue=false
-write_buffers=8
+write_buffers=16
cpu_side=system.cpu0.dcache_port
-mem_side=system.toL2Bus.slave[1]
+mem_side=system.cpu0.toL2Bus.slave[1]
[system.cpu0.dcache.tags]
type=LRU
-assoc=4
+assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
@@ -237,7 +237,7 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[5]
+port=system.cpu0.toL2Bus.slave[5]
[system.cpu0.dtb]
type=ArmTLB
@@ -254,7 +254,7 @@ eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[3]
+port=system.cpu0.toL2Bus.slave[3]
[system.cpu0.executeFuncUnits]
type=MinorFUPool
@@ -643,34 +643,34 @@ opClass=InstPrefetch
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
-assoc=1
+assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
-hit_latency=2
+hit_latency=1
is_top_level=true
max_miss_count=0
-mshrs=4
+mshrs=2
prefetch_on_access=false
prefetcher=Null
-response_latency=2
+response_latency=1
sequential_access=false
size=32768
system=system
tags=system.cpu0.icache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
-mem_side=system.toL2Bus.slave[0]
+mem_side=system.cpu0.toL2Bus.slave[0]
[system.cpu0.icache.tags]
type=LRU
-assoc=1
+assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
-hit_latency=2
+hit_latency=1
sequential_access=false
size=32768
@@ -729,7 +729,7 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[4]
+port=system.cpu0.toL2Bus.slave[4]
[system.cpu0.itb]
type=ArmTLB
@@ -746,7 +746,71 @@ eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[2]
+port=system.cpu0.toL2Bus.slave[2]
+
+[system.cpu0.l2cache]
+type=BaseCache
+children=prefetcher tags
+addr_ranges=0:18446744073709551615
+assoc=16
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=12
+is_top_level=false
+max_miss_count=0
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu0.l2cache.prefetcher
+response_latency=12
+sequential_access=false
+size=1048576
+system=system
+tags=system.cpu0.l2cache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.toL2Bus.master[0]
+mem_side=system.toL2Bus.slave[0]
+
+[system.cpu0.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
+[system.cpu0.l2cache.tags]
+type=RandomRepl
+assoc=16
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=12
+sequential_access=false
+size=1048576
+
+[system.cpu0.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=32
+master=system.cpu0.l2cache.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
[system.cpu0.tracer]
type=ExeTracer
@@ -754,7 +818,7 @@ eventq_index=0
[system.cpu1]
type=MinorCPU
-children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb tracer
+children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
branchPred=system.cpu1.branchPred
checker=Null
clk_domain=system.cpu_clk_domain
@@ -839,14 +903,14 @@ predType=tournament
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
-assoc=4
+assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=4
+mshrs=6
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -854,15 +918,15 @@ sequential_access=false
size=32768
system=system
tags=system.cpu1.dcache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
two_queue=false
-write_buffers=8
+write_buffers=16
cpu_side=system.cpu1.dcache_port
-mem_side=system.toL2Bus.slave[7]
+mem_side=system.cpu1.toL2Bus.slave[1]
[system.cpu1.dcache.tags]
type=LRU
-assoc=4
+assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
@@ -892,7 +956,7 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[11]
+port=system.cpu1.toL2Bus.slave[5]
[system.cpu1.dtb]
type=ArmTLB
@@ -909,7 +973,7 @@ eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[9]
+port=system.cpu1.toL2Bus.slave[3]
[system.cpu1.executeFuncUnits]
type=MinorFUPool
@@ -1298,34 +1362,34 @@ opClass=InstPrefetch
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
-assoc=1
+assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
-hit_latency=2
+hit_latency=1
is_top_level=true
max_miss_count=0
-mshrs=4
+mshrs=2
prefetch_on_access=false
prefetcher=Null
-response_latency=2
+response_latency=1
sequential_access=false
size=32768
system=system
tags=system.cpu1.icache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
-mem_side=system.toL2Bus.slave[6]
+mem_side=system.cpu1.toL2Bus.slave[0]
[system.cpu1.icache.tags]
type=LRU
-assoc=1
+assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
-hit_latency=2
+hit_latency=1
sequential_access=false
size=32768
@@ -1384,7 +1448,7 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[10]
+port=system.cpu1.toL2Bus.slave[4]
[system.cpu1.itb]
type=ArmTLB
@@ -1401,7 +1465,71 @@ eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[8]
+port=system.cpu1.toL2Bus.slave[2]
+
+[system.cpu1.l2cache]
+type=BaseCache
+children=prefetcher tags
+addr_ranges=0:18446744073709551615
+assoc=16
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=12
+is_top_level=false
+max_miss_count=0
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu1.l2cache.prefetcher
+response_latency=12
+sequential_access=false
+size=1048576
+system=system
+tags=system.cpu1.l2cache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.toL2Bus.master[0]
+mem_side=system.toL2Bus.slave[1]
+
+[system.cpu1.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
+[system.cpu1.l2cache.tags]
+type=RandomRepl
+assoc=16
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=12
+sequential_access=false
+size=1048576
+
+[system.cpu1.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=32
+master=system.cpu1.l2cache.cpu_side
+slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
[system.cpu1.tracer]
type=ExeTracer
@@ -1429,13 +1557,13 @@ eventq_index=0
sys=system
[system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
use_default_range=false
width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache]
@@ -1460,7 +1588,7 @@ tags=system.iocache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
-cpu_side=system.iobus.master[25]
+cpu_side=system.iobus.master[26]
mem_side=system.membus.slave[2]
[system.iocache.tags]
@@ -1509,11 +1637,12 @@ sequential_access=false
size=4194304
[system.membus]
-type=CoherentBus
+type=CoherentXBar
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -1541,8 +1670,33 @@ pio=system.membus.default
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -1551,6 +1705,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -1564,19 +1719,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
@@ -1584,12 +1746,12 @@ port=system.membus.master[6]
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
-max_mem_size=268435456
-mem_start_addr=0
pci_cfg_base=0
+pci_cfg_gen_offsets=false
+pci_io_base=0
system=system
[system.realview.a9scu]
@@ -1644,6 +1806,7 @@ HeaderType=0
InterruptLine=31
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
@@ -1728,6 +1891,16 @@ pio_latency=100000
system=system
pio=system.iobus.master[9]
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=268496896
+pio_latency=100000
+system=system
+pio=system.iobus.master[25]
+
[system.realview.flash_fake]
type=IsaFake
clk_domain=system.clk_domain
@@ -2046,15 +2219,16 @@ output=true
port=3456
[system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
master=system.l2c.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
[system.vncserver]
type=VncServer
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini
index dcd779005..240d456d3 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini
@@ -784,10 +784,11 @@ sequential_access=false
size=4194304
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -820,13 +821,13 @@ eventq_index=0
sys=system
[system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
use_default_range=false
width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache]
@@ -851,7 +852,7 @@ tags=system.iocache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
-cpu_side=system.iobus.master[25]
+cpu_side=system.iobus.master[26]
mem_side=system.membus.slave[2]
[system.iocache.tags]
@@ -865,11 +866,12 @@ sequential_access=false
size=1024
[system.membus]
-type=CoherentBus
+type=CoherentXBar
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -897,8 +899,33 @@ pio=system.membus.default
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -907,6 +934,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -920,19 +948,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
@@ -940,12 +975,12 @@ port=system.membus.master[6]
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
-max_mem_size=268435456
-mem_start_addr=0
pci_cfg_base=0
+pci_cfg_gen_offsets=false
+pci_io_base=0
system=system
[system.realview.a9scu]
@@ -1000,6 +1035,7 @@ HeaderType=0
InterruptLine=31
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
@@ -1084,6 +1120,16 @@ pio_latency=100000
system=system
pio=system.iobus.master[9]
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=268496896
+pio_latency=100000
+system=system
+pio=system.iobus.master[25]
+
[system.realview.flash_fake]
type=IsaFake
clk_domain=system.clk_domain
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
index 26a641846..a708031a0 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
@@ -37,7 +37,7 @@ load_offset=0
machine_type=RealView_PBX
mem_mode=timing
mem_ranges=0:134217727
-memories=system.physmem system.realview.nvmem
+memories=system.realview.nvmem system.physmem
multi_proc=true
num_work_ids=16
panic_on_oops=true
@@ -101,10 +101,10 @@ voltage_domain=system.voltage_domain
type=DerivO3CPU
children=branchPred checker dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
LFSTSize=1024
-LQEntries=32
+LQEntries=16
LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
+LSQDepCheckShift=0
+SQEntries=16
SSITSize=1024
activity=0
backComSize=5
@@ -119,19 +119,20 @@ commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-dispatchWidth=8
+decodeToRenameDelay=2
+decodeWidth=3
+dispatchWidth=6
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
-fetchBufferSize=64
-fetchToDecodeDelay=1
+fetchBufferSize=16
+fetchQueueSize=32
+fetchToDecodeDelay=3
fetchTrapLatency=1
-fetchWidth=8
+fetchWidth=3
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
@@ -151,20 +152,20 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
-numIQEntries=64
-numPhysCCRegs=0
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
+numIQEntries=32
+numPhysCCRegs=640
+numPhysFloatRegs=192
+numPhysIntRegs=128
+numROBEntries=40
numRobs=1
numThreads=1
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
-renameToIEWDelay=2
+renameToIEWDelay=1
renameToROBDelay=1
-renameWidth=8
+renameWidth=3
simpoint_start_insts=
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
@@ -182,7 +183,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=
dcache_port=system.cpu.dcache.cpu_side
@@ -190,8 +190,8 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=BranchPredictor
-BTBEntries=4096
-BTBTagSize=16
+BTBEntries=2048
+BTBTagSize=18
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
@@ -203,7 +203,7 @@ localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
+predType=bi-mode
[system.cpu.checker]
type=O3Checker
@@ -433,14 +433,14 @@ port=system.cpu.toL2Bus.slave[3]
[system.cpu.fuPool]
type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+children=FUList0 FUList1 FUList2 FUList3 FUList4
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
eventq_index=0
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
-count=6
+count=2
eventq_index=0
opList=system.cpu.fuPool.FUList0.opList
@@ -453,10 +453,10 @@ opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
-children=opList0 opList1
-count=2
+children=opList0 opList1 opList2
+count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
@@ -468,275 +468,233 @@ opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
-issueLat=19
+issueLat=12
opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+opLat=12
-[system.cpu.fuPool.FUList2.opList0]
+[system.cpu.fuPool.FUList1.opList2]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=FloatAdd
-opLat=2
+opClass=IprAccess
+opLat=3
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList
+count=1
eventq_index=0
-issueLat=1
-opClass=FloatCmp
-opLat=2
+opList=system.cpu.fuPool.FUList2.opList
-[system.cpu.fuPool.FUList2.opList2]
+[system.cpu.fuPool.FUList2.opList]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=FloatCvt
+opClass=MemRead
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
-children=opList0 opList1 opList2
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
children=opList
-count=0
+count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList
+opList=system.cpu.fuPool.FUList3.opList
-[system.cpu.fuPool.FUList4.opList]
+[system.cpu.fuPool.FUList3.opList]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemRead
-opLat=1
+opClass=MemWrite
+opLat=2
-[system.cpu.fuPool.FUList5]
+[system.cpu.fuPool.FUList4]
type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+count=2
eventq_index=0
-opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
-[system.cpu.fuPool.FUList5.opList00]
+[system.cpu.fuPool.FUList4.opList00]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAdd
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList01]
+[system.cpu.fuPool.FUList4.opList01]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAddAcc
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList02]
+[system.cpu.fuPool.FUList4.opList02]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAlu
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList03]
+[system.cpu.fuPool.FUList4.opList03]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCmp
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList04]
+[system.cpu.fuPool.FUList4.opList04]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCvt
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList05]
+[system.cpu.fuPool.FUList4.opList05]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMisc
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList06]
+[system.cpu.fuPool.FUList4.opList06]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMult
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList07]
+[system.cpu.fuPool.FUList4.opList07]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMultAcc
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList08]
+[system.cpu.fuPool.FUList4.opList08]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShift
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList09]
+[system.cpu.fuPool.FUList4.opList09]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShiftAcc
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList10]
+[system.cpu.fuPool.FUList4.opList10]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdSqrt
-opLat=1
+opLat=9
-[system.cpu.fuPool.FUList5.opList11]
+[system.cpu.fuPool.FUList4.opList11]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAdd
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList12]
+[system.cpu.fuPool.FUList4.opList12]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAlu
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList13]
+[system.cpu.fuPool.FUList4.opList13]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCmp
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList14]
+[system.cpu.fuPool.FUList4.opList14]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCvt
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList15]
+[system.cpu.fuPool.FUList4.opList15]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatDiv
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList16]
+[system.cpu.fuPool.FUList4.opList16]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMisc
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList17]
+[system.cpu.fuPool.FUList4.opList17]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMult
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList18]
+[system.cpu.fuPool.FUList4.opList18]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
-[system.cpu.fuPool.FUList5.opList19]
+[system.cpu.fuPool.FUList4.opList19]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatSqrt
-opLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList6.opList
+opLat=9
-[system.cpu.fuPool.FUList6.opList]
+[system.cpu.fuPool.FUList4.opList20]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemWrite
-opLat=1
+opClass=FloatAdd
+opLat=5
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
+[system.cpu.fuPool.FUList4.opList21]
+type=OpDesc
eventq_index=0
-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+issueLat=1
+opClass=FloatCmp
+opLat=5
-[system.cpu.fuPool.FUList7.opList0]
+[system.cpu.fuPool.FUList4.opList22]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemRead
-opLat=1
+opClass=FloatCvt
+opLat=5
-[system.cpu.fuPool.FUList7.opList1]
+[system.cpu.fuPool.FUList4.opList23]
type=OpDesc
eventq_index=0
-issueLat=1
-opClass=MemWrite
-opLat=1
+issueLat=9
+opClass=FloatDiv
+opLat=9
-[system.cpu.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
+[system.cpu.fuPool.FUList4.opList24]
+type=OpDesc
eventq_index=0
-opList=system.cpu.fuPool.FUList8.opList
+issueLat=33
+opClass=FloatSqrt
+opLat=33
-[system.cpu.fuPool.FUList8.opList]
+[system.cpu.fuPool.FUList4.opList25]
type=OpDesc
eventq_index=0
-issueLat=3
-opClass=IprAccess
-opLat=3
+issueLat=1
+opClass=FloatMult
+opLat=4
[system.cpu.icache]
type=BaseCache
@@ -883,10 +841,11 @@ sequential_access=false
size=4194304
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -919,13 +878,13 @@ eventq_index=0
sys=system
[system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
use_default_range=false
width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache]
@@ -950,7 +909,7 @@ tags=system.iocache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
-cpu_side=system.iobus.master[25]
+cpu_side=system.iobus.master[26]
mem_side=system.membus.slave[2]
[system.iocache.tags]
@@ -964,11 +923,12 @@ sequential_access=false
size=1024
[system.membus]
-type=CoherentBus
+type=CoherentXBar
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -996,8 +956,33 @@ pio=system.membus.default
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -1006,6 +991,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -1019,19 +1005,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
@@ -1039,12 +1032,12 @@ port=system.membus.master[6]
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
-max_mem_size=268435456
-mem_start_addr=0
pci_cfg_base=0
+pci_cfg_gen_offsets=false
+pci_io_base=0
system=system
[system.realview.a9scu]
@@ -1099,6 +1092,7 @@ HeaderType=0
InterruptLine=31
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
@@ -1183,6 +1177,16 @@ pio_latency=100000
system=system
pio=system.iobus.master[9]
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=268496896
+pio_latency=100000
+system=system
+pio=system.iobus.master[25]
+
[system.realview.flash_fake]
type=IsaFake
clk_domain=system.clk_domain
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
index 319208ed0..a054d64a7 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
@@ -99,12 +99,12 @@ voltage_domain=system.voltage_domain
[system.cpu0]
type=DerivO3CPU
-children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb tracer
+children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
LFSTSize=1024
-LQEntries=32
+LQEntries=16
LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
+LSQDepCheckShift=0
+SQEntries=16
SSITSize=1024
activity=0
backComSize=5
@@ -119,19 +119,20 @@ commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-dispatchWidth=8
+decodeToRenameDelay=2
+decodeWidth=3
+dispatchWidth=6
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu0.dstage2_mmu
dtb=system.cpu0.dtb
eventq_index=0
-fetchBufferSize=64
-fetchToDecodeDelay=1
+fetchBufferSize=16
+fetchQueueSize=32
+fetchToDecodeDelay=3
fetchTrapLatency=1
-fetchWidth=8
+fetchWidth=3
forwardComSize=5
fuPool=system.cpu0.fuPool
function_trace=false
@@ -151,20 +152,20 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
-numIQEntries=64
-numPhysCCRegs=0
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
+numIQEntries=32
+numPhysCCRegs=640
+numPhysFloatRegs=192
+numPhysIntRegs=128
+numROBEntries=40
numRobs=1
numThreads=1
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
-renameToIEWDelay=2
+renameToIEWDelay=1
renameToROBDelay=1
-renameWidth=8
+renameWidth=3
simpoint_start_insts=
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
@@ -182,7 +183,6 @@ switched_out=false
system=system
tracer=system.cpu0.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=
dcache_port=system.cpu0.dcache.cpu_side
@@ -190,8 +190,8 @@ icache_port=system.cpu0.icache.cpu_side
[system.cpu0.branchPred]
type=BranchPredictor
-BTBEntries=4096
-BTBTagSize=16
+BTBEntries=2048
+BTBTagSize=18
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
@@ -203,20 +203,20 @@ localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
+predType=bi-mode
[system.cpu0.dcache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
-assoc=4
+assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=4
+mshrs=6
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -224,15 +224,15 @@ sequential_access=false
size=32768
system=system
tags=system.cpu0.dcache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
two_queue=false
-write_buffers=8
+write_buffers=16
cpu_side=system.cpu0.dcache_port
-mem_side=system.toL2Bus.slave[1]
+mem_side=system.cpu0.toL2Bus.slave[1]
[system.cpu0.dcache.tags]
type=LRU
-assoc=4
+assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
@@ -262,7 +262,7 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[5]
+port=system.cpu0.toL2Bus.slave[5]
[system.cpu0.dtb]
type=ArmTLB
@@ -279,18 +279,18 @@ eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[3]
+port=system.cpu0.toL2Bus.slave[3]
[system.cpu0.fuPool]
type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8
+children=FUList0 FUList1 FUList2 FUList3 FUList4
+FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4
eventq_index=0
[system.cpu0.fuPool.FUList0]
type=FUDesc
children=opList
-count=6
+count=2
eventq_index=0
opList=system.cpu0.fuPool.FUList0.opList
@@ -303,10 +303,10 @@ opLat=1
[system.cpu0.fuPool.FUList1]
type=FUDesc
-children=opList0 opList1
-count=2
+children=opList0 opList1 opList2
+count=1
eventq_index=0
-opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1
+opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 system.cpu0.fuPool.FUList1.opList2
[system.cpu0.fuPool.FUList1.opList0]
type=OpDesc
@@ -318,308 +318,266 @@ opLat=3
[system.cpu0.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
-issueLat=19
+issueLat=12
opClass=IntDiv
-opLat=20
-
-[system.cpu0.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2
+opLat=12
-[system.cpu0.fuPool.FUList2.opList0]
+[system.cpu0.fuPool.FUList1.opList2]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=FloatAdd
-opLat=2
+opClass=IprAccess
+opLat=3
-[system.cpu0.fuPool.FUList2.opList1]
-type=OpDesc
+[system.cpu0.fuPool.FUList2]
+type=FUDesc
+children=opList
+count=1
eventq_index=0
-issueLat=1
-opClass=FloatCmp
-opLat=2
+opList=system.cpu0.fuPool.FUList2.opList
-[system.cpu0.fuPool.FUList2.opList2]
+[system.cpu0.fuPool.FUList2.opList]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=FloatCvt
+opClass=MemRead
opLat=2
[system.cpu0.fuPool.FUList3]
type=FUDesc
-children=opList0 opList1 opList2
-count=2
-eventq_index=0
-opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2
-
-[system.cpu0.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu0.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu0.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu0.fuPool.FUList4]
-type=FUDesc
children=opList
-count=0
+count=1
eventq_index=0
-opList=system.cpu0.fuPool.FUList4.opList
+opList=system.cpu0.fuPool.FUList3.opList
-[system.cpu0.fuPool.FUList4.opList]
+[system.cpu0.fuPool.FUList3.opList]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemRead
-opLat=1
+opClass=MemWrite
+opLat=2
-[system.cpu0.fuPool.FUList5]
+[system.cpu0.fuPool.FUList4]
type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+count=2
eventq_index=0
-opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19
+opList=system.cpu0.fuPool.FUList4.opList00 system.cpu0.fuPool.FUList4.opList01 system.cpu0.fuPool.FUList4.opList02 system.cpu0.fuPool.FUList4.opList03 system.cpu0.fuPool.FUList4.opList04 system.cpu0.fuPool.FUList4.opList05 system.cpu0.fuPool.FUList4.opList06 system.cpu0.fuPool.FUList4.opList07 system.cpu0.fuPool.FUList4.opList08 system.cpu0.fuPool.FUList4.opList09 system.cpu0.fuPool.FUList4.opList10 system.cpu0.fuPool.FUList4.opList11 system.cpu0.fuPool.FUList4.opList12 system.cpu0.fuPool.FUList4.opList13 system.cpu0.fuPool.FUList4.opList14 system.cpu0.fuPool.FUList4.opList15 system.cpu0.fuPool.FUList4.opList16 system.cpu0.fuPool.FUList4.opList17 system.cpu0.fuPool.FUList4.opList18 system.cpu0.fuPool.FUList4.opList19 system.cpu0.fuPool.FUList4.opList20 system.cpu0.fuPool.FUList4.opList21 system.cpu0.fuPool.FUList4.opList22 system.cpu0.fuPool.FUList4.opList23 system.cpu0.fuPool.FUList4.opList24 system.cpu0.fuPool.FUList4.opList25
-[system.cpu0.fuPool.FUList5.opList00]
+[system.cpu0.fuPool.FUList4.opList00]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAdd
-opLat=1
+opLat=4
-[system.cpu0.fuPool.FUList5.opList01]
+[system.cpu0.fuPool.FUList4.opList01]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAddAcc
-opLat=1
+opLat=4
-[system.cpu0.fuPool.FUList5.opList02]
+[system.cpu0.fuPool.FUList4.opList02]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAlu
-opLat=1
+opLat=4
-[system.cpu0.fuPool.FUList5.opList03]
+[system.cpu0.fuPool.FUList4.opList03]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCmp
-opLat=1
+opLat=4
-[system.cpu0.fuPool.FUList5.opList04]
+[system.cpu0.fuPool.FUList4.opList04]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCvt
-opLat=1
+opLat=3
-[system.cpu0.fuPool.FUList5.opList05]
+[system.cpu0.fuPool.FUList4.opList05]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMisc
-opLat=1
+opLat=3
-[system.cpu0.fuPool.FUList5.opList06]
+[system.cpu0.fuPool.FUList4.opList06]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMult
-opLat=1
+opLat=5
-[system.cpu0.fuPool.FUList5.opList07]
+[system.cpu0.fuPool.FUList4.opList07]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMultAcc
-opLat=1
+opLat=5
-[system.cpu0.fuPool.FUList5.opList08]
+[system.cpu0.fuPool.FUList4.opList08]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShift
-opLat=1
+opLat=3
-[system.cpu0.fuPool.FUList5.opList09]
+[system.cpu0.fuPool.FUList4.opList09]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShiftAcc
-opLat=1
+opLat=3
-[system.cpu0.fuPool.FUList5.opList10]
+[system.cpu0.fuPool.FUList4.opList10]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdSqrt
-opLat=1
+opLat=9
-[system.cpu0.fuPool.FUList5.opList11]
+[system.cpu0.fuPool.FUList4.opList11]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAdd
-opLat=1
+opLat=5
-[system.cpu0.fuPool.FUList5.opList12]
+[system.cpu0.fuPool.FUList4.opList12]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAlu
-opLat=1
+opLat=5
-[system.cpu0.fuPool.FUList5.opList13]
+[system.cpu0.fuPool.FUList4.opList13]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCmp
-opLat=1
+opLat=3
-[system.cpu0.fuPool.FUList5.opList14]
+[system.cpu0.fuPool.FUList4.opList14]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCvt
-opLat=1
+opLat=3
-[system.cpu0.fuPool.FUList5.opList15]
+[system.cpu0.fuPool.FUList4.opList15]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatDiv
-opLat=1
+opLat=3
-[system.cpu0.fuPool.FUList5.opList16]
+[system.cpu0.fuPool.FUList4.opList16]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMisc
-opLat=1
+opLat=3
-[system.cpu0.fuPool.FUList5.opList17]
+[system.cpu0.fuPool.FUList4.opList17]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMult
-opLat=1
+opLat=3
-[system.cpu0.fuPool.FUList5.opList18]
+[system.cpu0.fuPool.FUList4.opList18]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
-[system.cpu0.fuPool.FUList5.opList19]
+[system.cpu0.fuPool.FUList4.opList19]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatSqrt
-opLat=1
+opLat=9
-[system.cpu0.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu0.fuPool.FUList6.opList
-
-[system.cpu0.fuPool.FUList6.opList]
+[system.cpu0.fuPool.FUList4.opList20]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemWrite
-opLat=1
+opClass=FloatAdd
+opLat=5
-[system.cpu0.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
+[system.cpu0.fuPool.FUList4.opList21]
+type=OpDesc
eventq_index=0
-opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1
+issueLat=1
+opClass=FloatCmp
+opLat=5
-[system.cpu0.fuPool.FUList7.opList0]
+[system.cpu0.fuPool.FUList4.opList22]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemRead
-opLat=1
+opClass=FloatCvt
+opLat=5
-[system.cpu0.fuPool.FUList7.opList1]
+[system.cpu0.fuPool.FUList4.opList23]
type=OpDesc
eventq_index=0
-issueLat=1
-opClass=MemWrite
-opLat=1
+issueLat=9
+opClass=FloatDiv
+opLat=9
-[system.cpu0.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
+[system.cpu0.fuPool.FUList4.opList24]
+type=OpDesc
eventq_index=0
-opList=system.cpu0.fuPool.FUList8.opList
+issueLat=33
+opClass=FloatSqrt
+opLat=33
-[system.cpu0.fuPool.FUList8.opList]
+[system.cpu0.fuPool.FUList4.opList25]
type=OpDesc
eventq_index=0
-issueLat=3
-opClass=IprAccess
-opLat=3
+issueLat=1
+opClass=FloatMult
+opLat=4
[system.cpu0.icache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
-assoc=1
+assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
-hit_latency=2
+hit_latency=1
is_top_level=true
max_miss_count=0
-mshrs=4
+mshrs=2
prefetch_on_access=false
prefetcher=Null
-response_latency=2
+response_latency=1
sequential_access=false
size=32768
system=system
tags=system.cpu0.icache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
-mem_side=system.toL2Bus.slave[0]
+mem_side=system.cpu0.toL2Bus.slave[0]
[system.cpu0.icache.tags]
type=LRU
-assoc=1
+assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
-hit_latency=2
+hit_latency=1
sequential_access=false
size=32768
@@ -678,7 +636,7 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[4]
+port=system.cpu0.toL2Bus.slave[4]
[system.cpu0.itb]
type=ArmTLB
@@ -695,7 +653,71 @@ eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[2]
+port=system.cpu0.toL2Bus.slave[2]
+
+[system.cpu0.l2cache]
+type=BaseCache
+children=prefetcher tags
+addr_ranges=0:18446744073709551615
+assoc=16
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=12
+is_top_level=false
+max_miss_count=0
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu0.l2cache.prefetcher
+response_latency=12
+sequential_access=false
+size=1048576
+system=system
+tags=system.cpu0.l2cache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.toL2Bus.master[0]
+mem_side=system.toL2Bus.slave[0]
+
+[system.cpu0.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
+[system.cpu0.l2cache.tags]
+type=RandomRepl
+assoc=16
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=12
+sequential_access=false
+size=1048576
+
+[system.cpu0.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=32
+master=system.cpu0.l2cache.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
[system.cpu0.tracer]
type=ExeTracer
@@ -703,12 +725,12 @@ eventq_index=0
[system.cpu1]
type=DerivO3CPU
-children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb tracer
+children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
LFSTSize=1024
-LQEntries=32
+LQEntries=16
LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
+LSQDepCheckShift=0
+SQEntries=16
SSITSize=1024
activity=0
backComSize=5
@@ -723,19 +745,20 @@ commitToRenameDelay=1
commitWidth=8
cpu_id=1
decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-dispatchWidth=8
+decodeToRenameDelay=2
+decodeWidth=3
+dispatchWidth=6
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu1.dstage2_mmu
dtb=system.cpu1.dtb
eventq_index=0
-fetchBufferSize=64
-fetchToDecodeDelay=1
+fetchBufferSize=16
+fetchQueueSize=32
+fetchToDecodeDelay=3
fetchTrapLatency=1
-fetchWidth=8
+fetchWidth=3
forwardComSize=5
fuPool=system.cpu1.fuPool
function_trace=false
@@ -755,20 +778,20 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
-numIQEntries=64
-numPhysCCRegs=0
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
+numIQEntries=32
+numPhysCCRegs=640
+numPhysFloatRegs=192
+numPhysIntRegs=128
+numROBEntries=40
numRobs=1
numThreads=1
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
-renameToIEWDelay=2
+renameToIEWDelay=1
renameToROBDelay=1
-renameWidth=8
+renameWidth=3
simpoint_start_insts=
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
@@ -786,7 +809,6 @@ switched_out=false
system=system
tracer=system.cpu1.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=
dcache_port=system.cpu1.dcache.cpu_side
@@ -794,8 +816,8 @@ icache_port=system.cpu1.icache.cpu_side
[system.cpu1.branchPred]
type=BranchPredictor
-BTBEntries=4096
-BTBTagSize=16
+BTBEntries=2048
+BTBTagSize=18
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
@@ -807,20 +829,20 @@ localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
+predType=bi-mode
[system.cpu1.dcache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
-assoc=4
+assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=4
+mshrs=6
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -828,15 +850,15 @@ sequential_access=false
size=32768
system=system
tags=system.cpu1.dcache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
two_queue=false
-write_buffers=8
+write_buffers=16
cpu_side=system.cpu1.dcache_port
-mem_side=system.toL2Bus.slave[7]
+mem_side=system.cpu1.toL2Bus.slave[1]
[system.cpu1.dcache.tags]
type=LRU
-assoc=4
+assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
@@ -866,7 +888,7 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[11]
+port=system.cpu1.toL2Bus.slave[5]
[system.cpu1.dtb]
type=ArmTLB
@@ -883,18 +905,18 @@ eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[9]
+port=system.cpu1.toL2Bus.slave[3]
[system.cpu1.fuPool]
type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8
+children=FUList0 FUList1 FUList2 FUList3 FUList4
+FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4
eventq_index=0
[system.cpu1.fuPool.FUList0]
type=FUDesc
children=opList
-count=6
+count=2
eventq_index=0
opList=system.cpu1.fuPool.FUList0.opList
@@ -907,10 +929,10 @@ opLat=1
[system.cpu1.fuPool.FUList1]
type=FUDesc
-children=opList0 opList1
-count=2
+children=opList0 opList1 opList2
+count=1
eventq_index=0
-opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1
+opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 system.cpu1.fuPool.FUList1.opList2
[system.cpu1.fuPool.FUList1.opList0]
type=OpDesc
@@ -922,308 +944,266 @@ opLat=3
[system.cpu1.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
-issueLat=19
+issueLat=12
opClass=IntDiv
-opLat=20
-
-[system.cpu1.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2
+opLat=12
-[system.cpu1.fuPool.FUList2.opList0]
+[system.cpu1.fuPool.FUList1.opList2]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=FloatAdd
-opLat=2
+opClass=IprAccess
+opLat=3
-[system.cpu1.fuPool.FUList2.opList1]
-type=OpDesc
+[system.cpu1.fuPool.FUList2]
+type=FUDesc
+children=opList
+count=1
eventq_index=0
-issueLat=1
-opClass=FloatCmp
-opLat=2
+opList=system.cpu1.fuPool.FUList2.opList
-[system.cpu1.fuPool.FUList2.opList2]
+[system.cpu1.fuPool.FUList2.opList]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=FloatCvt
+opClass=MemRead
opLat=2
[system.cpu1.fuPool.FUList3]
type=FUDesc
-children=opList0 opList1 opList2
-count=2
-eventq_index=0
-opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2
-
-[system.cpu1.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu1.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu1.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu1.fuPool.FUList4]
-type=FUDesc
children=opList
-count=0
+count=1
eventq_index=0
-opList=system.cpu1.fuPool.FUList4.opList
+opList=system.cpu1.fuPool.FUList3.opList
-[system.cpu1.fuPool.FUList4.opList]
+[system.cpu1.fuPool.FUList3.opList]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemRead
-opLat=1
+opClass=MemWrite
+opLat=2
-[system.cpu1.fuPool.FUList5]
+[system.cpu1.fuPool.FUList4]
type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+count=2
eventq_index=0
-opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19
+opList=system.cpu1.fuPool.FUList4.opList00 system.cpu1.fuPool.FUList4.opList01 system.cpu1.fuPool.FUList4.opList02 system.cpu1.fuPool.FUList4.opList03 system.cpu1.fuPool.FUList4.opList04 system.cpu1.fuPool.FUList4.opList05 system.cpu1.fuPool.FUList4.opList06 system.cpu1.fuPool.FUList4.opList07 system.cpu1.fuPool.FUList4.opList08 system.cpu1.fuPool.FUList4.opList09 system.cpu1.fuPool.FUList4.opList10 system.cpu1.fuPool.FUList4.opList11 system.cpu1.fuPool.FUList4.opList12 system.cpu1.fuPool.FUList4.opList13 system.cpu1.fuPool.FUList4.opList14 system.cpu1.fuPool.FUList4.opList15 system.cpu1.fuPool.FUList4.opList16 system.cpu1.fuPool.FUList4.opList17 system.cpu1.fuPool.FUList4.opList18 system.cpu1.fuPool.FUList4.opList19 system.cpu1.fuPool.FUList4.opList20 system.cpu1.fuPool.FUList4.opList21 system.cpu1.fuPool.FUList4.opList22 system.cpu1.fuPool.FUList4.opList23 system.cpu1.fuPool.FUList4.opList24 system.cpu1.fuPool.FUList4.opList25
-[system.cpu1.fuPool.FUList5.opList00]
+[system.cpu1.fuPool.FUList4.opList00]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAdd
-opLat=1
+opLat=4
-[system.cpu1.fuPool.FUList5.opList01]
+[system.cpu1.fuPool.FUList4.opList01]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAddAcc
-opLat=1
+opLat=4
-[system.cpu1.fuPool.FUList5.opList02]
+[system.cpu1.fuPool.FUList4.opList02]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAlu
-opLat=1
+opLat=4
-[system.cpu1.fuPool.FUList5.opList03]
+[system.cpu1.fuPool.FUList4.opList03]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCmp
-opLat=1
+opLat=4
-[system.cpu1.fuPool.FUList5.opList04]
+[system.cpu1.fuPool.FUList4.opList04]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCvt
-opLat=1
+opLat=3
-[system.cpu1.fuPool.FUList5.opList05]
+[system.cpu1.fuPool.FUList4.opList05]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMisc
-opLat=1
+opLat=3
-[system.cpu1.fuPool.FUList5.opList06]
+[system.cpu1.fuPool.FUList4.opList06]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMult
-opLat=1
+opLat=5
-[system.cpu1.fuPool.FUList5.opList07]
+[system.cpu1.fuPool.FUList4.opList07]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMultAcc
-opLat=1
+opLat=5
-[system.cpu1.fuPool.FUList5.opList08]
+[system.cpu1.fuPool.FUList4.opList08]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShift
-opLat=1
+opLat=3
-[system.cpu1.fuPool.FUList5.opList09]
+[system.cpu1.fuPool.FUList4.opList09]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShiftAcc
-opLat=1
+opLat=3
-[system.cpu1.fuPool.FUList5.opList10]
+[system.cpu1.fuPool.FUList4.opList10]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdSqrt
-opLat=1
+opLat=9
-[system.cpu1.fuPool.FUList5.opList11]
+[system.cpu1.fuPool.FUList4.opList11]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAdd
-opLat=1
+opLat=5
-[system.cpu1.fuPool.FUList5.opList12]
+[system.cpu1.fuPool.FUList4.opList12]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAlu
-opLat=1
+opLat=5
-[system.cpu1.fuPool.FUList5.opList13]
+[system.cpu1.fuPool.FUList4.opList13]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCmp
-opLat=1
+opLat=3
-[system.cpu1.fuPool.FUList5.opList14]
+[system.cpu1.fuPool.FUList4.opList14]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCvt
-opLat=1
+opLat=3
-[system.cpu1.fuPool.FUList5.opList15]
+[system.cpu1.fuPool.FUList4.opList15]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatDiv
-opLat=1
+opLat=3
-[system.cpu1.fuPool.FUList5.opList16]
+[system.cpu1.fuPool.FUList4.opList16]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMisc
-opLat=1
+opLat=3
-[system.cpu1.fuPool.FUList5.opList17]
+[system.cpu1.fuPool.FUList4.opList17]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMult
-opLat=1
+opLat=3
-[system.cpu1.fuPool.FUList5.opList18]
+[system.cpu1.fuPool.FUList4.opList18]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
-[system.cpu1.fuPool.FUList5.opList19]
+[system.cpu1.fuPool.FUList4.opList19]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatSqrt
-opLat=1
-
-[system.cpu1.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu1.fuPool.FUList6.opList
+opLat=9
-[system.cpu1.fuPool.FUList6.opList]
+[system.cpu1.fuPool.FUList4.opList20]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemWrite
-opLat=1
+opClass=FloatAdd
+opLat=5
-[system.cpu1.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
+[system.cpu1.fuPool.FUList4.opList21]
+type=OpDesc
eventq_index=0
-opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1
+issueLat=1
+opClass=FloatCmp
+opLat=5
-[system.cpu1.fuPool.FUList7.opList0]
+[system.cpu1.fuPool.FUList4.opList22]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemRead
-opLat=1
+opClass=FloatCvt
+opLat=5
-[system.cpu1.fuPool.FUList7.opList1]
+[system.cpu1.fuPool.FUList4.opList23]
type=OpDesc
eventq_index=0
-issueLat=1
-opClass=MemWrite
-opLat=1
+issueLat=9
+opClass=FloatDiv
+opLat=9
-[system.cpu1.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
+[system.cpu1.fuPool.FUList4.opList24]
+type=OpDesc
eventq_index=0
-opList=system.cpu1.fuPool.FUList8.opList
+issueLat=33
+opClass=FloatSqrt
+opLat=33
-[system.cpu1.fuPool.FUList8.opList]
+[system.cpu1.fuPool.FUList4.opList25]
type=OpDesc
eventq_index=0
-issueLat=3
-opClass=IprAccess
-opLat=3
+issueLat=1
+opClass=FloatMult
+opLat=4
[system.cpu1.icache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
-assoc=1
+assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
-hit_latency=2
+hit_latency=1
is_top_level=true
max_miss_count=0
-mshrs=4
+mshrs=2
prefetch_on_access=false
prefetcher=Null
-response_latency=2
+response_latency=1
sequential_access=false
size=32768
system=system
tags=system.cpu1.icache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
-mem_side=system.toL2Bus.slave[6]
+mem_side=system.cpu1.toL2Bus.slave[0]
[system.cpu1.icache.tags]
type=LRU
-assoc=1
+assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
-hit_latency=2
+hit_latency=1
sequential_access=false
size=32768
@@ -1282,7 +1262,7 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[10]
+port=system.cpu1.toL2Bus.slave[4]
[system.cpu1.itb]
type=ArmTLB
@@ -1299,7 +1279,71 @@ eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[8]
+port=system.cpu1.toL2Bus.slave[2]
+
+[system.cpu1.l2cache]
+type=BaseCache
+children=prefetcher tags
+addr_ranges=0:18446744073709551615
+assoc=16
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=12
+is_top_level=false
+max_miss_count=0
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu1.l2cache.prefetcher
+response_latency=12
+sequential_access=false
+size=1048576
+system=system
+tags=system.cpu1.l2cache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.toL2Bus.master[0]
+mem_side=system.toL2Bus.slave[1]
+
+[system.cpu1.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
+[system.cpu1.l2cache.tags]
+type=RandomRepl
+assoc=16
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=12
+sequential_access=false
+size=1048576
+
+[system.cpu1.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=32
+master=system.cpu1.l2cache.cpu_side
+slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
[system.cpu1.tracer]
type=ExeTracer
@@ -1327,13 +1371,13 @@ eventq_index=0
sys=system
[system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
use_default_range=false
width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache]
@@ -1358,7 +1402,7 @@ tags=system.iocache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
-cpu_side=system.iobus.master[25]
+cpu_side=system.iobus.master[26]
mem_side=system.membus.slave[2]
[system.iocache.tags]
@@ -1407,11 +1451,12 @@ sequential_access=false
size=4194304
[system.membus]
-type=CoherentBus
+type=CoherentXBar
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -1439,8 +1484,33 @@ pio=system.membus.default
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -1449,6 +1519,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -1462,19 +1533,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
@@ -1482,12 +1560,12 @@ port=system.membus.master[6]
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
-max_mem_size=268435456
-mem_start_addr=0
pci_cfg_base=0
+pci_cfg_gen_offsets=false
+pci_io_base=0
system=system
[system.realview.a9scu]
@@ -1542,6 +1620,7 @@ HeaderType=0
InterruptLine=31
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
@@ -1626,6 +1705,16 @@ pio_latency=100000
system=system
pio=system.iobus.master[9]
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=268496896
+pio_latency=100000
+system=system
+pio=system.iobus.master[25]
+
[system.realview.flash_fake]
type=IsaFake
clk_domain=system.clk_domain
@@ -1944,15 +2033,16 @@ output=true
port=3456
[system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
master=system.l2c.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
[system.vncserver]
type=VncServer
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
index 240be98a7..51ab195cc 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
@@ -101,10 +101,10 @@ voltage_domain=system.voltage_domain
type=DerivO3CPU
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
LFSTSize=1024
-LQEntries=32
+LQEntries=16
LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
+LSQDepCheckShift=0
+SQEntries=16
SSITSize=1024
activity=0
backComSize=5
@@ -119,19 +119,20 @@ commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-dispatchWidth=8
+decodeToRenameDelay=2
+decodeWidth=3
+dispatchWidth=6
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
-fetchBufferSize=64
-fetchToDecodeDelay=1
+fetchBufferSize=16
+fetchQueueSize=32
+fetchToDecodeDelay=3
fetchTrapLatency=1
-fetchWidth=8
+fetchWidth=3
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
@@ -151,20 +152,20 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
-numIQEntries=64
-numPhysCCRegs=0
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
+numIQEntries=32
+numPhysCCRegs=640
+numPhysFloatRegs=192
+numPhysIntRegs=128
+numROBEntries=40
numRobs=1
numThreads=1
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
-renameToIEWDelay=2
+renameToIEWDelay=1
renameToROBDelay=1
-renameWidth=8
+renameWidth=3
simpoint_start_insts=
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
@@ -182,7 +183,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=
dcache_port=system.cpu.dcache.cpu_side
@@ -190,8 +190,8 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=BranchPredictor
-BTBEntries=4096
-BTBTagSize=16
+BTBEntries=2048
+BTBTagSize=18
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
@@ -203,7 +203,7 @@ localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
+predType=bi-mode
[system.cpu.dcache]
type=BaseCache
@@ -283,14 +283,14 @@ port=system.cpu.toL2Bus.slave[3]
[system.cpu.fuPool]
type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+children=FUList0 FUList1 FUList2 FUList3 FUList4
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
eventq_index=0
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
-count=6
+count=2
eventq_index=0
opList=system.cpu.fuPool.FUList0.opList
@@ -303,10 +303,10 @@ opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
-children=opList0 opList1
-count=2
+children=opList0 opList1 opList2
+count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
@@ -318,275 +318,233 @@ opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
-issueLat=19
+issueLat=12
opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+opLat=12
-[system.cpu.fuPool.FUList2.opList0]
+[system.cpu.fuPool.FUList1.opList2]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=FloatAdd
-opLat=2
+opClass=IprAccess
+opLat=3
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList
+count=1
eventq_index=0
-issueLat=1
-opClass=FloatCmp
-opLat=2
+opList=system.cpu.fuPool.FUList2.opList
-[system.cpu.fuPool.FUList2.opList2]
+[system.cpu.fuPool.FUList2.opList]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=FloatCvt
+opClass=MemRead
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
-children=opList0 opList1 opList2
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
children=opList
-count=0
+count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList
+opList=system.cpu.fuPool.FUList3.opList
-[system.cpu.fuPool.FUList4.opList]
+[system.cpu.fuPool.FUList3.opList]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemRead
-opLat=1
+opClass=MemWrite
+opLat=2
-[system.cpu.fuPool.FUList5]
+[system.cpu.fuPool.FUList4]
type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+count=2
eventq_index=0
-opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
-[system.cpu.fuPool.FUList5.opList00]
+[system.cpu.fuPool.FUList4.opList00]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAdd
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList01]
+[system.cpu.fuPool.FUList4.opList01]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAddAcc
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList02]
+[system.cpu.fuPool.FUList4.opList02]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAlu
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList03]
+[system.cpu.fuPool.FUList4.opList03]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCmp
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList04]
+[system.cpu.fuPool.FUList4.opList04]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCvt
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList05]
+[system.cpu.fuPool.FUList4.opList05]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMisc
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList06]
+[system.cpu.fuPool.FUList4.opList06]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMult
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList07]
+[system.cpu.fuPool.FUList4.opList07]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMultAcc
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList08]
+[system.cpu.fuPool.FUList4.opList08]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShift
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList09]
+[system.cpu.fuPool.FUList4.opList09]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShiftAcc
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList10]
+[system.cpu.fuPool.FUList4.opList10]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdSqrt
-opLat=1
+opLat=9
-[system.cpu.fuPool.FUList5.opList11]
+[system.cpu.fuPool.FUList4.opList11]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAdd
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList12]
+[system.cpu.fuPool.FUList4.opList12]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAlu
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList13]
+[system.cpu.fuPool.FUList4.opList13]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCmp
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList14]
+[system.cpu.fuPool.FUList4.opList14]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCvt
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList15]
+[system.cpu.fuPool.FUList4.opList15]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatDiv
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList16]
+[system.cpu.fuPool.FUList4.opList16]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMisc
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList17]
+[system.cpu.fuPool.FUList4.opList17]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMult
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList18]
+[system.cpu.fuPool.FUList4.opList18]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
-[system.cpu.fuPool.FUList5.opList19]
+[system.cpu.fuPool.FUList4.opList19]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatSqrt
-opLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList6.opList
+opLat=9
-[system.cpu.fuPool.FUList6.opList]
+[system.cpu.fuPool.FUList4.opList20]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemWrite
-opLat=1
+opClass=FloatAdd
+opLat=5
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
+[system.cpu.fuPool.FUList4.opList21]
+type=OpDesc
eventq_index=0
-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+issueLat=1
+opClass=FloatCmp
+opLat=5
-[system.cpu.fuPool.FUList7.opList0]
+[system.cpu.fuPool.FUList4.opList22]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemRead
-opLat=1
+opClass=FloatCvt
+opLat=5
-[system.cpu.fuPool.FUList7.opList1]
+[system.cpu.fuPool.FUList4.opList23]
type=OpDesc
eventq_index=0
-issueLat=1
-opClass=MemWrite
-opLat=1
+issueLat=9
+opClass=FloatDiv
+opLat=9
-[system.cpu.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
+[system.cpu.fuPool.FUList4.opList24]
+type=OpDesc
eventq_index=0
-opList=system.cpu.fuPool.FUList8.opList
+issueLat=33
+opClass=FloatSqrt
+opLat=33
-[system.cpu.fuPool.FUList8.opList]
+[system.cpu.fuPool.FUList4.opList25]
type=OpDesc
eventq_index=0
-issueLat=3
-opClass=IprAccess
-opLat=3
+issueLat=1
+opClass=FloatMult
+opLat=4
[system.cpu.icache]
type=BaseCache
@@ -733,10 +691,11 @@ sequential_access=false
size=4194304
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -769,13 +728,13 @@ eventq_index=0
sys=system
[system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
use_default_range=false
width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache]
@@ -800,7 +759,7 @@ tags=system.iocache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
-cpu_side=system.iobus.master[25]
+cpu_side=system.iobus.master[26]
mem_side=system.membus.slave[2]
[system.iocache.tags]
@@ -814,11 +773,12 @@ sequential_access=false
size=1024
[system.membus]
-type=CoherentBus
+type=CoherentXBar
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -846,8 +806,33 @@ pio=system.membus.default
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -856,6 +841,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -869,19 +855,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
@@ -889,12 +882,12 @@ port=system.membus.master[6]
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
-max_mem_size=268435456
-mem_start_addr=0
pci_cfg_base=0
+pci_cfg_gen_offsets=false
+pci_io_base=0
system=system
[system.realview.a9scu]
@@ -949,6 +942,7 @@ HeaderType=0
InterruptLine=31
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
@@ -1033,6 +1027,16 @@ pio_latency=100000
system=system
pio=system.iobus.master[9]
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=268496896
+pio_latency=100000
+system=system
+pio=system.iobus.master[25]
+
[system.realview.flash_fake]
type=IsaFake
clk_domain=system.clk_domain
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
index 9dee17aa2..056f4dd22 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
@@ -1,6 +1,7 @@
warn: Sockets disabled, not accepting vnc client connections
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
warn: The clidr register always reports 0 caches.
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
warn: The csselr register isn't implemented.
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
index 0158d2186..8a89971a1 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
@@ -37,7 +37,7 @@ load_offset=0
machine_type=RealView_PBX
mem_mode=atomic
mem_ranges=0:134217727
-memories=system.realview.nvmem system.physmem
+memories=system.physmem system.realview.nvmem
multi_proc=true
num_work_ids=16
panic_on_oops=true
@@ -124,9 +124,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -504,6 +501,7 @@ dstage2_mmu=system.cpu2.dstage2_mmu
dtb=system.cpu2.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -527,7 +525,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
-numPhysCCRegs=0
+numPhysCCRegs=1280
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
@@ -557,7 +555,6 @@ switched_out=true
system=system
tracer=system.cpu2.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=
@@ -1018,13 +1015,13 @@ eventq_index=0
sys=system
[system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
use_default_range=false
width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache]
@@ -1049,7 +1046,7 @@ tags=system.iocache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
-cpu_side=system.iobus.master[25]
+cpu_side=system.iobus.master[26]
mem_side=system.membus.slave[2]
[system.iocache.tags]
@@ -1098,11 +1095,12 @@ sequential_access=false
size=4194304
[system.membus]
-type=CoherentBus
+type=CoherentXBar
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -1130,8 +1128,33 @@ pio=system.membus.default
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -1140,6 +1163,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -1153,19 +1177,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
@@ -1173,12 +1204,12 @@ port=system.membus.master[6]
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
-max_mem_size=268435456
-mem_start_addr=0
pci_cfg_base=0
+pci_cfg_gen_offsets=false
+pci_io_base=0
system=system
[system.realview.a9scu]
@@ -1233,6 +1264,7 @@ HeaderType=0
InterruptLine=31
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
@@ -1317,6 +1349,16 @@ pio_latency=100000
system=system
pio=system.iobus.master[9]
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=268496896
+pio_latency=100000
+system=system
+pio=system.iobus.master[25]
+
[system.realview.flash_fake]
type=IsaFake
clk_domain=system.clk_domain
@@ -1635,10 +1677,11 @@ output=true
port=3456
[system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
index 0248bee20..5d2c59c2a 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
@@ -129,6 +129,7 @@ dstage2_mmu=system.cpu0.dstage2_mmu
dtb=system.cpu0.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -152,7 +153,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
-numPhysCCRegs=0
+numPhysCCRegs=1280
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
@@ -182,7 +183,6 @@ switched_out=false
system=system
tracer=system.cpu0.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=
dcache_port=system.cpu0.dcache.cpu_side
@@ -733,6 +733,7 @@ dstage2_mmu=system.cpu1.dstage2_mmu
dtb=system.cpu1.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -756,7 +757,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
-numPhysCCRegs=0
+numPhysCCRegs=1280
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
@@ -786,7 +787,6 @@ switched_out=true
system=system
tracer=system.cpu1.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=
@@ -1247,13 +1247,13 @@ eventq_index=0
sys=system
[system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
use_default_range=false
width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache]
@@ -1278,7 +1278,7 @@ tags=system.iocache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
-cpu_side=system.iobus.master[25]
+cpu_side=system.iobus.master[26]
mem_side=system.membus.slave[2]
[system.iocache.tags]
@@ -1327,11 +1327,12 @@ sequential_access=false
size=4194304
[system.membus]
-type=CoherentBus
+type=CoherentXBar
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -1359,8 +1360,33 @@ pio=system.membus.default
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -1369,6 +1395,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -1382,19 +1409,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
@@ -1402,12 +1436,12 @@ port=system.membus.master[6]
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
-max_mem_size=268435456
-mem_start_addr=0
pci_cfg_base=0
+pci_cfg_gen_offsets=false
+pci_io_base=0
system=system
[system.realview.a9scu]
@@ -1462,6 +1496,7 @@ HeaderType=0
InterruptLine=31
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
@@ -1546,6 +1581,16 @@ pio_latency=100000
system=system
pio=system.iobus.master[9]
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=268496896
+pio_latency=100000
+system=system
+pio=system.iobus.master[25]
+
[system.realview.flash_fake]
type=IsaFake
clk_domain=system.clk_domain
@@ -1864,10 +1909,11 @@ output=true
port=3456
[system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini
index bc1aaf76d..8b812b09c 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini
@@ -37,7 +37,7 @@ load_offset=0
machine_type=RealView_PBX
mem_mode=timing
mem_ranges=0:134217727
-memories=system.physmem system.realview.nvmem
+memories=system.realview.nvmem system.physmem
multi_proc=true
num_work_ids=16
panic_on_oops=true
@@ -487,13 +487,13 @@ eventq_index=0
sys=system
[system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
use_default_range=false
width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache]
@@ -518,7 +518,7 @@ tags=system.iocache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
-cpu_side=system.iobus.master[25]
+cpu_side=system.iobus.master[26]
mem_side=system.membus.slave[2]
[system.iocache.tags]
@@ -567,11 +567,12 @@ sequential_access=false
size=4194304
[system.membus]
-type=CoherentBus
+type=CoherentXBar
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -599,8 +600,33 @@ pio=system.membus.default
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -609,6 +635,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -622,19 +649,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
@@ -642,12 +676,12 @@ port=system.membus.master[6]
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
-max_mem_size=268435456
-mem_start_addr=0
pci_cfg_base=0
+pci_cfg_gen_offsets=false
+pci_io_base=0
system=system
[system.realview.a9scu]
@@ -702,6 +736,7 @@ HeaderType=0
InterruptLine=31
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
@@ -786,6 +821,16 @@ pio_latency=100000
system=system
pio=system.iobus.master[9]
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=268496896
+pio_latency=100000
+system=system
+pio=system.iobus.master[25]
+
[system.realview.flash_fake]
type=IsaFake
clk_domain=system.clk_domain
@@ -1104,10 +1149,11 @@ output=true
port=3456
[system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
index beeca581e..68a408e3f 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
@@ -75,7 +75,7 @@ type=Bridge
clk_domain=system.clk_domain
delay=50000
eventq_index=0
-ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
+ranges=3221225472:4294901760 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
req_size=16
resp_size=16
master=system.iobus.slave[0]
@@ -120,6 +120,7 @@ do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -172,7 +173,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=
dcache_port=system.cpu.dcache.cpu_side
@@ -730,10 +730,11 @@ sequential_access=false
size=4194304
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -762,8 +763,8 @@ transition_latency=100000000
[system.e820_table]
type=X86E820Table
-children=entries0 entries1 entries2 entries3
-entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3
+children=entries0 entries1 entries2 entries3 entries4
+entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 system.e820_table.entries4
eventq_index=0
[system.e820_table.entries0]
@@ -789,6 +790,13 @@ size=133169152
[system.e820_table.entries3]
type=X86E820Entry
+addr=134217728
+eventq_index=0
+range_type=2
+size=3087007744
+
+[system.e820_table.entries4]
+type=X86E820Entry
addr=4294901760
eventq_index=0
range_type=2
@@ -837,13 +845,13 @@ version=17
[system.intel_mp_table.base_entries02]
type=X86IntelMPBus
bus_id=0
-bus_type=ISA
+bus_type=PCI
eventq_index=0
[system.intel_mp_table.base_entries03]
type=X86IntelMPBus
bus_id=1
-bus_type=PCI
+bus_type=ISA
eventq_index=0
[system.intel_mp_table.base_entries04]
@@ -853,7 +861,7 @@ dest_io_apic_intin=16
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=1
+source_bus_id=0
source_bus_irq=16
trigger=ConformTrigger
@@ -864,7 +872,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=0
trigger=ConformTrigger
@@ -875,7 +883,7 @@ dest_io_apic_intin=2
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=0
trigger=ConformTrigger
@@ -886,7 +894,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=1
trigger=ConformTrigger
@@ -897,7 +905,7 @@ dest_io_apic_intin=1
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=1
trigger=ConformTrigger
@@ -908,7 +916,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=3
trigger=ConformTrigger
@@ -919,7 +927,7 @@ dest_io_apic_intin=3
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=3
trigger=ConformTrigger
@@ -930,7 +938,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=4
trigger=ConformTrigger
@@ -941,7 +949,7 @@ dest_io_apic_intin=4
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=4
trigger=ConformTrigger
@@ -952,7 +960,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=5
trigger=ConformTrigger
@@ -963,7 +971,7 @@ dest_io_apic_intin=5
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=5
trigger=ConformTrigger
@@ -974,7 +982,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=6
trigger=ConformTrigger
@@ -985,7 +993,7 @@ dest_io_apic_intin=6
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=6
trigger=ConformTrigger
@@ -996,7 +1004,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=7
trigger=ConformTrigger
@@ -1007,7 +1015,7 @@ dest_io_apic_intin=7
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=7
trigger=ConformTrigger
@@ -1018,7 +1026,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=8
trigger=ConformTrigger
@@ -1029,7 +1037,7 @@ dest_io_apic_intin=8
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=8
trigger=ConformTrigger
@@ -1040,7 +1048,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=9
trigger=ConformTrigger
@@ -1051,7 +1059,7 @@ dest_io_apic_intin=9
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=9
trigger=ConformTrigger
@@ -1062,7 +1070,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=10
trigger=ConformTrigger
@@ -1073,7 +1081,7 @@ dest_io_apic_intin=10
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=10
trigger=ConformTrigger
@@ -1084,7 +1092,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=11
trigger=ConformTrigger
@@ -1095,7 +1103,7 @@ dest_io_apic_intin=11
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=11
trigger=ConformTrigger
@@ -1106,7 +1114,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=12
trigger=ConformTrigger
@@ -1117,7 +1125,7 @@ dest_io_apic_intin=12
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=12
trigger=ConformTrigger
@@ -1128,7 +1136,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=13
trigger=ConformTrigger
@@ -1139,7 +1147,7 @@ dest_io_apic_intin=13
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=13
trigger=ConformTrigger
@@ -1150,7 +1158,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=14
trigger=ConformTrigger
@@ -1161,15 +1169,15 @@ dest_io_apic_intin=14
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=14
trigger=ConformTrigger
[system.intel_mp_table.ext_entries]
type=X86IntelMPBusHierarchy
-bus_id=0
+bus_id=1
eventq_index=0
-parent_bus=1
+parent_bus=0
subtractive_decode=true
[system.intrctrl]
@@ -1178,7 +1186,7 @@ eventq_index=0
sys=system
[system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
@@ -1224,11 +1232,12 @@ sequential_access=false
size=1024
[system.membus]
-type=CoherentBus
+type=CoherentXBar
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -1473,6 +1482,7 @@ HeaderType=0
InterruptLine=14
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=9223372036854775808
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
@@ -1763,8 +1773,33 @@ pio=system.iobus.master[9]
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -1773,6 +1808,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -1786,19 +1822,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
index 02f62080c..9ab6b9d66 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
@@ -1,125 +1,125 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 5.129877 # Number of seconds simulated
-sim_ticks 5129876981500 # Number of ticks simulated
-final_tick 5129876981500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.125902 # Number of seconds simulated
+sim_ticks 5125902116500 # Number of ticks simulated
+final_tick 5125902116500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 181923 # Simulator instruction rate (inst/s)
-host_op_rate 359604 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2288414721 # Simulator tick rate (ticks/s)
-host_mem_usage 752624 # Number of bytes of host memory used
-host_seconds 2241.67 # Real time elapsed on the host
-sim_insts 407812863 # Number of instructions simulated
-sim_ops 806114915 # Number of ops (including micro ops) simulated
+host_inst_rate 125787 # Simulator instruction rate (inst/s)
+host_op_rate 248644 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1580293827 # Simulator tick rate (ticks/s)
+host_mem_usage 793336 # Number of bytes of host memory used
+host_seconds 3243.64 # Real time elapsed on the host
+sim_insts 408006726 # Number of instructions simulated
+sim_ops 806511598 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 4096 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 1048192 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10832768 # Number of bytes read from this memory
-system.physmem.bytes_read::total 11913792 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1048192 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1048192 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 6597248 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker 4800 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 1043840 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10813760 # Number of bytes read from this memory
+system.physmem.bytes_read::total 11891200 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1043840 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1043840 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 6604544 # Number of bytes written to this memory
system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9587328 # Number of bytes written to this memory
+system.physmem.bytes_written::total 9594624 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 64 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 16378 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 169262 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 186153 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 103082 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 75 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 16310 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 168965 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 185800 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 103196 # Number of write requests responded to by this memory
system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 149802 # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide 5527 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 798 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 204331 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2111701 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2322432 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 204331 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 204331 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1286044 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::pc.south_bridge.ide 582876 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1868920 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1286044 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 588402 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 798 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 204331 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2111701 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4191352 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 186153 # Number of read requests accepted
-system.physmem.writeReqs 149802 # Number of write requests accepted
-system.physmem.readBursts 186153 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 149802 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 11895360 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 18432 # Total number of bytes read from write queue
-system.physmem.bytesWritten 9586112 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 11913792 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 9587328 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 288 # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_writes::total 149916 # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide 5531 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 936 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 203640 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2109631 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2319826 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 203640 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 203640 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1288465 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::pc.south_bridge.ide 583328 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1871792 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1288465 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 588859 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 936 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 203640 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 2109631 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4191618 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 185800 # Number of read requests accepted
+system.physmem.writeReqs 149916 # Number of write requests accepted
+system.physmem.readBursts 185800 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 149916 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 11876224 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 14976 # Total number of bytes read from write queue
+system.physmem.bytesWritten 9592960 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 11891200 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 9594624 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 234 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 1739 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 11465 # Per bank write bursts
-system.physmem.perBankRdBursts::1 11004 # Per bank write bursts
-system.physmem.perBankRdBursts::2 11873 # Per bank write bursts
-system.physmem.perBankRdBursts::3 11540 # Per bank write bursts
-system.physmem.perBankRdBursts::4 11961 # Per bank write bursts
-system.physmem.perBankRdBursts::5 11322 # Per bank write bursts
-system.physmem.perBankRdBursts::6 11640 # Per bank write bursts
-system.physmem.perBankRdBursts::7 11420 # Per bank write bursts
-system.physmem.perBankRdBursts::8 11351 # Per bank write bursts
-system.physmem.perBankRdBursts::9 11861 # Per bank write bursts
-system.physmem.perBankRdBursts::10 11826 # Per bank write bursts
-system.physmem.perBankRdBursts::11 12031 # Per bank write bursts
-system.physmem.perBankRdBursts::12 11538 # Per bank write bursts
-system.physmem.perBankRdBursts::13 12375 # Per bank write bursts
-system.physmem.perBankRdBursts::14 11569 # Per bank write bursts
-system.physmem.perBankRdBursts::15 11089 # Per bank write bursts
-system.physmem.perBankWrBursts::0 10234 # Per bank write bursts
-system.physmem.perBankWrBursts::1 9627 # Per bank write bursts
-system.physmem.perBankWrBursts::2 9640 # Per bank write bursts
-system.physmem.perBankWrBursts::3 9149 # Per bank write bursts
-system.physmem.perBankWrBursts::4 9237 # Per bank write bursts
-system.physmem.perBankWrBursts::5 9047 # Per bank write bursts
-system.physmem.perBankWrBursts::6 8744 # Per bank write bursts
-system.physmem.perBankWrBursts::7 8727 # Per bank write bursts
-system.physmem.perBankWrBursts::8 9070 # Per bank write bursts
-system.physmem.perBankWrBursts::9 9221 # Per bank write bursts
-system.physmem.perBankWrBursts::10 9815 # Per bank write bursts
-system.physmem.perBankWrBursts::11 9405 # Per bank write bursts
-system.physmem.perBankWrBursts::12 9499 # Per bank write bursts
-system.physmem.perBankWrBursts::13 9604 # Per bank write bursts
-system.physmem.perBankWrBursts::14 9640 # Per bank write bursts
-system.physmem.perBankWrBursts::15 9124 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 1736 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 11489 # Per bank write bursts
+system.physmem.perBankRdBursts::1 10946 # Per bank write bursts
+system.physmem.perBankRdBursts::2 11982 # Per bank write bursts
+system.physmem.perBankRdBursts::3 11463 # Per bank write bursts
+system.physmem.perBankRdBursts::4 11671 # Per bank write bursts
+system.physmem.perBankRdBursts::5 11298 # Per bank write bursts
+system.physmem.perBankRdBursts::6 11252 # Per bank write bursts
+system.physmem.perBankRdBursts::7 11687 # Per bank write bursts
+system.physmem.perBankRdBursts::8 11071 # Per bank write bursts
+system.physmem.perBankRdBursts::9 11217 # Per bank write bursts
+system.physmem.perBankRdBursts::10 11355 # Per bank write bursts
+system.physmem.perBankRdBursts::11 12125 # Per bank write bursts
+system.physmem.perBankRdBursts::12 11861 # Per bank write bursts
+system.physmem.perBankRdBursts::13 12651 # Per bank write bursts
+system.physmem.perBankRdBursts::14 12184 # Per bank write bursts
+system.physmem.perBankRdBursts::15 11314 # Per bank write bursts
+system.physmem.perBankWrBursts::0 9710 # Per bank write bursts
+system.physmem.perBankWrBursts::1 9082 # Per bank write bursts
+system.physmem.perBankWrBursts::2 8978 # Per bank write bursts
+system.physmem.perBankWrBursts::3 8996 # Per bank write bursts
+system.physmem.perBankWrBursts::4 9462 # Per bank write bursts
+system.physmem.perBankWrBursts::5 9601 # Per bank write bursts
+system.physmem.perBankWrBursts::6 9097 # Per bank write bursts
+system.physmem.perBankWrBursts::7 8837 # Per bank write bursts
+system.physmem.perBankWrBursts::8 9327 # Per bank write bursts
+system.physmem.perBankWrBursts::9 9159 # Per bank write bursts
+system.physmem.perBankWrBursts::10 9532 # Per bank write bursts
+system.physmem.perBankWrBursts::11 9463 # Per bank write bursts
+system.physmem.perBankWrBursts::12 9618 # Per bank write bursts
+system.physmem.perBankWrBursts::13 9862 # Per bank write bursts
+system.physmem.perBankWrBursts::14 9881 # Per bank write bursts
+system.physmem.perBankWrBursts::15 9285 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 2 # Number of times write queue was full causing retry
-system.physmem.totGap 5129876930000 # Total gap between requests
+system.physmem.numWrRetry 4 # Number of times write queue was full causing retry
+system.physmem.totGap 5125902065000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 186153 # Read request sizes (log2)
+system.physmem.readPktSize::6 185800 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 149802 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 171145 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 11892 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 2095 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 399 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 51 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 149916 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 170703 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 12067 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 2038 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 421 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 56 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 34 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see
@@ -159,115 +159,115 @@ system.physmem.wrQLenPdf::11 1 # Wh
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 2222 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 2928 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::20 8641 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 8986 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 9732 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 10392 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 11488 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 10681 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 9974 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::28 9052 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 7930 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::52 48 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::42 170 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 164 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 174 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 170 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 142 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 139 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 121 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 108 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 94 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 63 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 46 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 32 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 36 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 32 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 22 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 17 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 14 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 9 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 72700 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 295.480165 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 175.038242 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 318.841917 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 28215 38.81% 38.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 17447 24.00% 62.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 7490 10.30% 73.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 4112 5.66% 78.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 3047 4.19% 82.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 2009 2.76% 85.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1387 1.91% 87.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1145 1.57% 89.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 7848 10.80% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 72700 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 7372 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 25.211883 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 559.387781 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 7371 99.99% 99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::54 43 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 38 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 46 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 41 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 38 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 37 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 29 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 23 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 11 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 72846 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 294.719271 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 174.256286 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 318.919065 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 28471 39.08% 39.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 17446 23.95% 63.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 7310 10.03% 73.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 4243 5.82% 78.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2987 4.10% 82.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1984 2.72% 85.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1403 1.93% 87.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1126 1.55% 89.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 7876 10.81% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 72846 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 7377 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 25.152094 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 560.212559 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 7376 99.99% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 7372 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 7372 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 20.317824 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.630780 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 12.249046 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 6322 85.76% 85.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 58 0.79% 86.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 24 0.33% 86.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 276 3.74% 90.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 291 3.95% 94.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 18 0.24% 94.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 12 0.16% 94.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 14 0.19% 95.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 37 0.50% 95.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 4 0.05% 95.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 3 0.04% 95.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 3 0.04% 95.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 249 3.38% 99.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 3 0.04% 99.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 4 0.05% 99.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 4 0.05% 99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 19 0.26% 99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 1 0.01% 99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 7 0.09% 99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 1 0.01% 99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 1 0.01% 99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111 2 0.03% 99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 6 0.08% 99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119 1 0.01% 99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127 1 0.01% 99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 7 0.09% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135 1 0.01% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 2 0.03% 99.99% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total 7377 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 7377 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 20.318558 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.615023 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 12.539295 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 6330 85.81% 85.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 64 0.87% 86.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 33 0.45% 87.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 268 3.63% 90.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 287 3.89% 94.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 24 0.33% 94.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 24 0.33% 95.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 16 0.22% 95.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 20 0.27% 95.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 2 0.03% 95.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 6 0.08% 95.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 2 0.03% 95.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 237 3.21% 99.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 3 0.04% 99.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 2 0.03% 99.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 3 0.04% 99.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 11 0.15% 99.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95 1 0.01% 99.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 12 0.16% 99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 1 0.01% 99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 3 0.04% 99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111 2 0.03% 99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 6 0.08% 99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119 3 0.04% 99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127 1 0.01% 99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 13 0.18% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139 1 0.01% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 1 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 1 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 7372 # Writes before turning the bus around for reads
-system.physmem.totQLat 2030519500 # Total ticks spent queuing
-system.physmem.totMemAccLat 5515488250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 929325000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 10924.70 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total 7377 # Writes before turning the bus around for reads
+system.physmem.totQLat 2068154250 # Total ticks spent queuing
+system.physmem.totMemAccLat 5547516750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 927830000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 11145.11 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 29674.70 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 29895.11 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.32 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.32 # Average system read bandwidth in MiByte/s
@@ -276,146 +276,146 @@ system.physmem.peakBW 12800.00 # Th
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.49 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 25.68 # Average write queue length when enqueuing
-system.physmem.readRowHits 152396 # Number of row buffer hits during reads
-system.physmem.writeRowHits 110551 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 81.99 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 73.80 # Row buffer hit rate for writes
-system.physmem.avgGap 15269535.89 # Average gap between requests
-system.physmem.pageHitRate 78.34 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 4923406969000 # Time in different power states
-system.physmem.memoryStateTime::REF 171297620000 # Time in different power states
+system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 21.36 # Average write queue length when enqueuing
+system.physmem.readRowHits 151753 # Number of row buffer hits during reads
+system.physmem.writeRowHits 110856 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 81.78 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 73.95 # Row buffer hit rate for writes
+system.physmem.avgGap 15268566.48 # Average gap between requests
+system.physmem.pageHitRate 78.28 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 4919748958000 # Time in different power states
+system.physmem.memoryStateTime::REF 171165020000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 35172289500 # Time in different power states
+system.physmem.memoryStateTime::ACT 34988035500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem.actEnergy::0 267480360 # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1 282131640 # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0 145946625 # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1 153940875 # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0 719347200 # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1 730392000 # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0 482144400 # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1 488449440 # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0 335058144720 # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1 335058144720 # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0 129492550125 # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1 129753331110 # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0 2964331954500 # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1 2964103199250 # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0 3430497567930 # Total energy per rank (pJ)
-system.physmem.totalEnergy::1 3430569589035 # Total energy per rank (pJ)
-system.physmem.averagePower::0 668.729942 # Core power per rank (mW)
-system.physmem.averagePower::1 668.743982 # Core power per rank (mW)
-system.membus.trans_dist::ReadReq 662528 # Transaction distribution
-system.membus.trans_dist::ReadResp 662520 # Transaction distribution
-system.membus.trans_dist::WriteReq 13776 # Transaction distribution
-system.membus.trans_dist::WriteResp 13776 # Transaction distribution
-system.membus.trans_dist::Writeback 103082 # Transaction distribution
+system.physmem.actEnergy::0 267185520 # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1 283530240 # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0 145785750 # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1 154704000 # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0 715946400 # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1 731460600 # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0 477984240 # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1 493302960 # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0 334798779120 # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1 334798779120 # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0 129305495790 # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1 129519356940 # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0 2962113436500 # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1 2961925839000 # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0 3427824613320 # Total energy per rank (pJ)
+system.physmem.totalEnergy::1 3427906972860 # Total energy per rank (pJ)
+system.physmem.averagePower::0 668.726542 # Core power per rank (mW)
+system.physmem.averagePower::1 668.742609 # Core power per rank (mW)
+system.membus.trans_dist::ReadReq 662592 # Transaction distribution
+system.membus.trans_dist::ReadResp 662582 # Transaction distribution
+system.membus.trans_dist::WriteReq 13889 # Transaction distribution
+system.membus.trans_dist::WriteResp 13889 # Transaction distribution
+system.membus.trans_dist::Writeback 103196 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 2203 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 1739 # Transaction distribution
-system.membus.trans_dist::ReadExReq 133413 # Transaction distribution
-system.membus.trans_dist::ReadExResp 133410 # Transaction distribution
-system.membus.trans_dist::MessageReq 1645 # Transaction distribution
-system.membus.trans_dist::MessageResp 1645 # Transaction distribution
-system.membus.trans_dist::BadAddressError 8 # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3290 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total 3290 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471084 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775070 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 478447 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724617 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94802 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 94802 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1822709 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6580 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::total 6580 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241828 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550137 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18482688 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20274653 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::UpgradeReq 2215 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 1736 # Transaction distribution
+system.membus.trans_dist::ReadExReq 133104 # Transaction distribution
+system.membus.trans_dist::ReadExResp 133101 # Transaction distribution
+system.membus.trans_dist::MessageReq 1644 # Transaction distribution
+system.membus.trans_dist::MessageResp 1644 # Transaction distribution
+system.membus.trans_dist::BadAddressError 10 # Transaction distribution
+system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3288 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total 3288 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471544 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775066 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 477864 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 20 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724494 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94793 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 94793 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1822575 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6576 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::total 6576 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242058 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550129 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18467392 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20259579 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 23299665 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 943 # Total snoops (count)
-system.membus.snoop_fanout::samples 338647 # Request fanout histogram
+system.membus.pkt_size::total 23284587 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 949 # Total snoops (count)
+system.membus.snoop_fanout::samples 338415 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 338647 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 338415 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 338647 # Request fanout histogram
-system.membus.reqLayer0.occupancy 251233500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 338415 # Request fanout histogram
+system.membus.reqLayer0.occupancy 251687000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 583254000 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 583226500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 3290000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 3288000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer3.occupancy 1574333248 # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy 1575195000 # Layer occupancy (ticks)
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer4.occupancy 9500 # Layer occupancy (ticks)
+system.membus.reqLayer4.occupancy 13500 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer0.occupancy 1645000 # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy 1644000 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 3160566012 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 3157657266 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer4.occupancy 55015741 # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy 54931743 # Layer occupancy (ticks)
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 47584 # number of replacements
-system.iocache.tags.tagsinuse 0.103867 # Cycle average of tags in use
+system.iocache.tags.replacements 47575 # number of replacements
+system.iocache.tags.tagsinuse 0.091458 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 47600 # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs 47591 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 4992945897000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103867 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006492 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.006492 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 4992976867000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.091458 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005716 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.005716 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 428751 # Number of tag accesses
-system.iocache.tags.data_accesses 428751 # Number of data accesses
+system.iocache.tags.tag_accesses 428670 # Number of tag accesses
+system.iocache.tags.data_accesses 428670 # Number of data accesses
system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits
-system.iocache.ReadReq_misses::pc.south_bridge.ide 919 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 919 # number of ReadReq misses
-system.iocache.demand_misses::pc.south_bridge.ide 919 # number of demand (read+write) misses
-system.iocache.demand_misses::total 919 # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide 919 # number of overall misses
-system.iocache.overall_misses::total 919 # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 156299196 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 156299196 # number of ReadReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide 156299196 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 156299196 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide 156299196 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 156299196 # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide 919 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 919 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 910 # number of ReadReq misses
+system.iocache.demand_misses::pc.south_bridge.ide 910 # number of demand (read+write) misses
+system.iocache.demand_misses::total 910 # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide 910 # number of overall misses
+system.iocache.overall_misses::total 910 # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152161446 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 152161446 # number of ReadReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide 152161446 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 152161446 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide 152161446 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 152161446 # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide 919 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 919 # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide 919 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 919 # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide 910 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 910 # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide 910 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 910 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 170075.294886 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 170075.294886 # average ReadReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 170075.294886 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 170075.294886 # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 170075.294886 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 170075.294886 # average overall miss latency
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 167210.380220 # average ReadReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 167210.380220 # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 167210.380220 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 26 # number of cycles access was blocked
@@ -424,22 +424,22 @@ system.iocache.avg_blocked_cycles::no_mshrs 11.846154 #
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 46720 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 919 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 919 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide 919 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 919 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide 919 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 919 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 108481196 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 108481196 # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2843906419 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2843906419 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 108481196 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 108481196 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 108481196 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 108481196 # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::pc.south_bridge.ide 910 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide 910 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 910 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 104814946 # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2846577667 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2846577667 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 104814946 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 104814946 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses
@@ -448,14 +448,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 118042.650707 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 118042.650707 # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60871.284653 # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60871.284653 # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 118042.650707 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 118042.650707 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 118042.650707 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 118042.650707 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 115181.259341 # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60928.460338 # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60928.460338 # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 115181.259341 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 115181.259341 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
@@ -469,12 +469,12 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq 225575 # Transaction distribution
-system.iobus.trans_dist::ReadResp 225575 # Transaction distribution
-system.iobus.trans_dist::WriteReq 57606 # Transaction distribution
-system.iobus.trans_dist::WriteResp 57606 # Transaction distribution
-system.iobus.trans_dist::MessageReq 1645 # Transaction distribution
-system.iobus.trans_dist::MessageResp 1645 # Transaction distribution
+system.iobus.trans_dist::ReadReq 225681 # Transaction distribution
+system.iobus.trans_dist::ReadResp 225681 # Transaction distribution
+system.iobus.trans_dist::WriteReq 57721 # Transaction distribution
+system.iobus.trans_dist::WriteResp 57721 # Transaction distribution
+system.iobus.trans_dist::MessageReq 1644 # Transaction distribution
+system.iobus.trans_dist::MessageResp 1644 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
@@ -487,18 +487,18 @@ system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27236 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27696 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 471084 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95278 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95278 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3290 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3290 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 569652 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 471544 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95260 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95260 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3288 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3288 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 570092 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
@@ -511,19 +511,19 @@ system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13848 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 241828 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027896 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027896 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6580 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6580 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 3276304 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 3920684 # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::total 242058 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027824 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027824 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6576 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6576 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 3276458 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 3917656 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
@@ -549,7 +549,7 @@ system.iobus.reqLayer11.occupancy 170000 # La
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 20374000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy 20719000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
@@ -559,273 +559,273 @@ system.iobus.reqLayer16.occupancy 9000 # La
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 422027356 # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy 422009356 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 460198000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 460543000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 52381259 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 52362257 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer2.occupancy 1645000 # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy 1644000 # Layer occupancy (ticks)
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 86898883 # Number of BP lookups
-system.cpu.branchPred.condPredicted 86898883 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 901790 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 80120336 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 78166165 # Number of BTB hits
+system.cpu.branchPred.lookups 86911006 # Number of BP lookups
+system.cpu.branchPred.condPredicted 86911006 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 901724 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 80066722 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 78189070 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 97.560955 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1553548 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 177807 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 97.654891 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1556278 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 178526 # Number of incorrect RAS predictions.
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu.numCycles 449490093 # number of cpu cycles simulated
+system.cpu.numCycles 449563158 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 27736713 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 428990683 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 86898883 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 79719713 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 417726391 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1890728 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 147536 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 50079 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 202600 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 127031 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 405 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 9184683 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 447260 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 5357 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 446936119 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.894164 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.051823 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 27553144 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 429142218 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 86911006 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 79745348 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 417985667 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1891240 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 143316 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 50930 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 210883 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 127962 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 502 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 9183903 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 446388 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 4881 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 447018024 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.894555 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.051977 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 281459283 62.98% 62.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 2262059 0.51% 63.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 72137620 16.14% 79.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1613997 0.36% 79.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2155091 0.48% 80.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2322801 0.52% 80.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1535694 0.34% 81.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1854025 0.41% 81.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 81595549 18.26% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 281457902 62.96% 62.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 2285728 0.51% 63.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 72178245 16.15% 79.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 1597297 0.36% 79.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2150673 0.48% 80.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 2329203 0.52% 80.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1531441 0.34% 81.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1871505 0.42% 81.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 81616030 18.26% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 446936119 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.193328 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.954394 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 23065529 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 264763767 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 150736142 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 7425317 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 945364 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 838360092 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 945364 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 25914691 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 223241691 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 13213057 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 154633432 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 28987884 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 834905613 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 478581 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 12335118 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 182483 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 13727584 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 997265714 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1813395255 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1114768158 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 110 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 964051126 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 33214586 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 466449 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 470370 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 38986770 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 17343174 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 10196687 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1348761 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 1124760 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 829365293 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1208199 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 824078412 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 244412 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 23515910 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 36291432 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 152927 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 446936119 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.843839 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.418170 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 447018024 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.193323 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.954576 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 22975502 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 264891753 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 150781344 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 7423805 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 945620 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 838588132 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 945620 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 25820685 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 223318475 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 13301995 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 154670533 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 28960716 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 835102889 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 477440 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 12397064 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 181319 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 13705397 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 997542850 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 1813799496 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1115056771 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 257 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 964533940 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 33008908 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 469072 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 473209 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 39003947 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 17327061 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 10187947 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1305152 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 1075480 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 829577981 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1211612 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 824337261 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 238496 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 23343623 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 36066463 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 155823 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 447018024 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.844081 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.418172 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 262716607 58.78% 58.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 13881580 3.11% 61.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 10086185 2.26% 64.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 6914821 1.55% 65.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 74322504 16.63% 82.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 4455510 1.00% 83.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 72776226 16.28% 99.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 1206411 0.27% 99.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 576275 0.13% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 262761301 58.78% 58.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 13855312 3.10% 61.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 10080748 2.26% 64.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 6920312 1.55% 65.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 74355494 16.63% 82.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 4460813 1.00% 83.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 72820654 16.29% 99.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 1197568 0.27% 99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 565822 0.13% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 446936119 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 447018024 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 1975200 71.80% 71.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 252 0.01% 71.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 1109 0.04% 71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 614218 22.33% 94.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 160061 5.82% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 1976611 71.80% 71.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 212 0.01% 71.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 1052 0.04% 71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 614146 22.31% 94.15% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 161054 5.85% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 293084 0.04% 0.04% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 795671914 96.55% 96.59% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 150614 0.02% 96.61% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 125303 0.02% 96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 18435146 2.24% 98.86% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 9402351 1.14% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 292817 0.04% 0.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 795957786 96.56% 96.59% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 150640 0.02% 96.61% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 125262 0.02% 96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 18413325 2.23% 98.86% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 9397431 1.14% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 824078412 # Type of FU issued
-system.cpu.iq.rate 1.833363 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2750840 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.003338 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 2098087999 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 854102050 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 819507550 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 195 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 194 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 56 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 826536078 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 90 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1879985 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 824337261 # Type of FU issued
+system.cpu.iq.rate 1.833641 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2753075 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.003340 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 2098683900 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 854145561 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 819784123 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 216 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 406 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 61 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 826797417 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 102 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 1878905 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 3343174 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 14903 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 14336 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1767440 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 3325389 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 14284 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 14518 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1760345 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 2224972 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 73807 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 2224613 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 71287 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 945364 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 205481336 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 9444308 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 830573492 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 185181 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 17343194 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 10196687 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 711600 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 416792 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 8129202 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 14336 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 515306 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 539272 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1054578 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 822459197 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 18034619 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1483642 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 945620 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 205593402 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 9425350 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 830789593 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 184731 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 17327061 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 10187947 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 714336 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 416093 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 8107674 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 14518 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 515540 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 536897 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1052437 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 822725796 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 18017825 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1477345 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 27209233 # number of memory reference insts executed
-system.cpu.iew.exec_branches 83289157 # Number of branches executed
-system.cpu.iew.exec_stores 9174614 # Number of stores executed
-system.cpu.iew.exec_rate 1.829760 # Inst execution rate
-system.cpu.iew.wb_sent 821946704 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 819507606 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 640910074 # num instructions producing a value
-system.cpu.iew.wb_consumers 1050315789 # num instructions consuming a value
+system.cpu.iew.exec_refs 27187593 # number of memory reference insts executed
+system.cpu.iew.exec_branches 83308581 # Number of branches executed
+system.cpu.iew.exec_stores 9169768 # Number of stores executed
+system.cpu.iew.exec_rate 1.830056 # Inst execution rate
+system.cpu.iew.wb_sent 822221777 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 819784184 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 641108962 # num instructions producing a value
+system.cpu.iew.wb_consumers 1050701242 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.823194 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.610207 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.823513 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.610172 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 24363502 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1055272 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 913280 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 443273616 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.818549 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.675153 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 24183935 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1055789 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 913678 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 443381671 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.819001 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.675688 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 272516770 61.48% 61.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 11195258 2.53% 64.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3583043 0.81% 64.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 74523250 16.81% 81.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 2432181 0.55% 82.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1605992 0.36% 82.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 951269 0.21% 82.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 71009301 16.02% 98.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5456552 1.23% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 272578077 61.48% 61.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 11201647 2.53% 64.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3542666 0.80% 64.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 74562549 16.82% 81.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 2432578 0.55% 82.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1609465 0.36% 82.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 914477 0.21% 82.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 71049223 16.02% 98.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 5490989 1.24% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 443273616 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 407812863 # Number of instructions committed
-system.cpu.commit.committedOps 806114915 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 443381671 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 408006726 # Number of instructions committed
+system.cpu.commit.committedOps 806511598 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 22429266 # Number of memory references committed
-system.cpu.commit.loads 14000019 # Number of loads committed
-system.cpu.commit.membars 474889 # Number of memory barriers committed
-system.cpu.commit.branches 82168190 # Number of branches committed
+system.cpu.commit.refs 22429273 # Number of memory references committed
+system.cpu.commit.loads 14001671 # Number of loads committed
+system.cpu.commit.membars 475333 # Number of memory barriers committed
+system.cpu.commit.branches 82207365 # Number of branches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 734958550 # Number of committed integer instructions.
-system.cpu.commit.function_calls 1155635 # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass 174258 0.02% 0.02% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 783245185 97.16% 97.18% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 144842 0.02% 97.20% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv 121364 0.02% 97.22% # Class of committed instruction
+system.cpu.commit.int_insts 735317995 # Number of committed integer instructions.
+system.cpu.commit.function_calls 1155841 # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass 174216 0.02% 0.02% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 783641693 97.16% 97.19% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult 144853 0.02% 97.20% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv 121563 0.02% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 97.22% # Class of committed instruction
@@ -852,225 +852,225 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% #
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 14000019 1.74% 98.95% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 8429247 1.05% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead 14001671 1.74% 98.96% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite 8427602 1.04% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 806114915 # Class of committed instruction
-system.cpu.commit.bw_lim_events 5456552 # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total 806511598 # Class of committed instruction
+system.cpu.commit.bw_lim_events 5490989 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 1268217156 # The number of ROB reads
-system.cpu.rob.rob_writes 1664635865 # The number of ROB writes
-system.cpu.timesIdled 297982 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 2553974 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 9810264132 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 407812863 # Number of Instructions Simulated
-system.cpu.committedOps 806114915 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 1.102197 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.102197 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.907279 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.907279 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1092267062 # number of integer regfile reads
-system.cpu.int_regfile_writes 655932610 # number of integer regfile writes
-system.cpu.fp_regfile_reads 56 # number of floating regfile reads
-system.cpu.cc_regfile_reads 416128291 # number of cc regfile reads
-system.cpu.cc_regfile_writes 321990784 # number of cc regfile writes
-system.cpu.misc_regfile_reads 265578345 # number of misc regfile reads
-system.cpu.misc_regfile_writes 402863 # number of misc regfile writes
-system.cpu.toL2Bus.trans_dist::ReadReq 3083726 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 3083187 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 13776 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 13776 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 1587489 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46722 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 2231 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2231 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 287826 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 287826 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2007150 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6137120 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 34489 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 168921 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 8347680 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64225408 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 208172445 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1082112 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5828032 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 279307997 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 61506 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 4398693 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3.010831 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.103506 # Request fanout histogram
+system.cpu.rob.rob_reads 1268507964 # The number of ROB reads
+system.cpu.rob.rob_writes 1665044622 # The number of ROB writes
+system.cpu.timesIdled 294262 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 2545134 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 9802241311 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 408006726 # Number of Instructions Simulated
+system.cpu.committedOps 806511598 # Number of Ops (including micro ops) Simulated
+system.cpu.cpi 1.101852 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.101852 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.907563 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.907563 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 1092659743 # number of integer regfile reads
+system.cpu.int_regfile_writes 656162059 # number of integer regfile writes
+system.cpu.fp_regfile_reads 61 # number of floating regfile reads
+system.cpu.cc_regfile_reads 416306470 # number of cc regfile reads
+system.cpu.cc_regfile_writes 322125902 # number of cc regfile writes
+system.cpu.misc_regfile_reads 265627452 # number of misc regfile reads
+system.cpu.misc_regfile_writes 402647 # number of misc regfile writes
+system.cpu.toL2Bus.trans_dist::ReadReq 3066870 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 3066328 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 13889 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 13889 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 1584468 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46724 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2232 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2232 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 287069 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 287069 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError 10 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1989808 # Packet count per connected master and slave (bytes)
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+system.cpu.toL2Bus.pkt_count::total 8312590 # Packet count per connected master and slave (bytes)
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+system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1011904 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5790912 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 278167995 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 58568 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 4377947 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 3.010880 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.103740 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 4351052 98.92% 98.92% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 47641 1.08% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 4330313 98.91% 98.91% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 47634 1.09% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 4398693 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 4081523356 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 4377947 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 4068281890 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy 582000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy 567000 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1509600495 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 1496480643 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3145861612 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 3139987945 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 26384476 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy 22488486 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 116845140 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy 113254360 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu.icache.tags.replacements 1003070 # number of replacements
-system.cpu.icache.tags.tagsinuse 510.154171 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 8117984 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 1003582 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 8.089009 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 147599073250 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 510.154171 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.996395 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.996395 # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements 994393 # number of replacements
+system.cpu.icache.tags.tagsinuse 510.035216 # Cycle average of tags in use
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+system.cpu.icache.tags.sampled_refs 994905 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 8.167330 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 147627648000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 510.035216 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.996163 # Average percentage of cache occupancy
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system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 201 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id
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system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 10188308 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 10188308 # Number of data accesses
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-system.cpu.icache.ReadReq_hits::total 8117984 # number of ReadReq hits
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-system.cpu.icache.overall_misses::total 1066696 # number of overall misses
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-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116139 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.116139 # miss rate for ReadReq accesses
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-system.cpu.icache.demand_miss_rate::total 0.116139 # miss rate for demand accesses
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-system.cpu.icache.overall_miss_rate::total 0.116139 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13865.143922 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13865.143922 # average ReadReq miss latency
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-system.cpu.icache.overall_avg_miss_latency::total 13865.143922 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 6103 # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses 10178850 # Number of tag accesses
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
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-system.cpu.icache.overall_mshr_miss_latency::total 12143729999 # number of overall MSHR miss cycles
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-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109272 # mshr miss rate for ReadReq accesses
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12099.831809 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12099.831809 # average ReadReq mshr miss latency
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system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1079,85 +1079,85 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan
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+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12288.718358 # average overall miss latency
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system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1166,169 +1166,169 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
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@@ -1336,150 +1336,150 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf
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-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7662739284 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4610750 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 391500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1038765000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10062465280 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 11106232530 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4610750 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 391500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1038765000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10062465280 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 11106232530 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89251418000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89251418000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2373087500 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2373087500 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91624505500 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91624505500 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000921 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000440 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016321 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026101 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021259 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823995 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823995 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464509 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464509 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000921 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000440 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016321 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102037 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.067678 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000921 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000440 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016321 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102037 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.067678 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72042.968750 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65250 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63424.410795 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66919.297156 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65831.101285 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10025.380495 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10025.380495 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57315.934896 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57315.934896 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72042.968750 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63424.410795 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59347.019988 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59710.606556 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72042.968750 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63424.410795 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59347.019988 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59710.606556 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 75 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16310 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35874 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 52266 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1444 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 1444 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133393 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 133393 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 75 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 16310 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 169267 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 185659 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 75 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 16310 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 169267 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 185659 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5579000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 473000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1049198000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2439336749 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3494586749 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14472940 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14472940 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7638617543 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7638617543 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5579000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 473000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1049198000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10077954292 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 11133204292 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5579000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 473000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1049198000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10077954292 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 11133204292 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89275584000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89275584000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2397149000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2397149000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91672733000 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91672733000 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001093 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000560 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016394 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026176 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021364 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823731 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823731 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464684 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464684 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001093 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000560 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016394 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102118 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.067919 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001093 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000560 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016394 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102118 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.067919 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 74386.666667 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67571.428571 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64328.510116 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67997.344846 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 66861.568687 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10022.811634 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10022.811634 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57264.005930 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57264.005930 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 74386.666667 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67571.428571 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64328.510116 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59538.801373 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59965.874490 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 74386.666667 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67571.428571 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64328.510116 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59538.801373 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59965.874490 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
index 61d45995b..95ff094ce 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
@@ -4,6 +4,7 @@ BIOS-provided physical RAM map:
BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
BIOS-e820: 000000000009fc00 - 0000000000100000 (reserved)
BIOS-e820: 0000000000100000 - 0000000008000000 (usable)
+ BIOS-e820: 0000000008000000 - 00000000c0000000 (reserved)
BIOS-e820: 00000000ffff0000 - 0000000100000000 (reserved)
end_pfn_map = 1048576
kernel direct mapping tables up to 100000000 @ 8000-d000
@@ -23,18 +24,18 @@ Setting APIC routing to flat
Processors: 1
swsusp: Registered nosave memory region: 000000000009f000 - 00000000000a0000
swsusp: Registered nosave memory region: 00000000000a0000 - 0000000000100000
-Allocating PCI resources starting at 10000000 (gap: 8000000:f7ff0000)
-Built 1 zonelists. Total pages: 30612
+Allocating PCI resources starting at c4000000 (gap: c0000000:3fff0000)
+Built 1 zonelists. Total pages: 30610
Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
Initializing CPU#0
PID hash table entries: 512 (order: 9, 4096 bytes)
-time.c: Detected 1999.999 MHz processor.
+time.c: Detected 2000.008 MHz processor.
Console: colour dummy device 80x25
console handover: boot [earlyser0] -> real [ttyS0]
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)
Checking aperture...
-Memory: 122184k/131072k available (3742k kernel code, 8464k reserved, 1874k data, 232k init)
+Memory: 122176k/131072k available (3742k kernel code, 8472k reserved, 1874k data, 232k init)
Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
Mount-cache hash table entries: 256
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
@@ -44,7 +45,7 @@ ACPI: Core revision 20070126
ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
ACPI: Unable to load the System Description Tables
Using local APIC timer interrupts.
-result 7812524
+result 7812560
Detected 7.812 MHz APIC timer.
NET: Registered protocol family 16
PCI: Using configuration type 1
@@ -56,6 +57,7 @@ usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
PCI: Probing PCI hardware
+PCI->APIC IRQ transform: 0000:00:04.0[A] -> IRQ 16
PCI-GART: No AMD northbridge found.
NET: Registered protocol family 2
Time: tsc clocksource has been installed.
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini
index f38bb864d..c618cee26 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini
@@ -263,8 +263,8 @@ transition_latency=100000000
[system.e820_table]
type=X86E820Table
-children=entries0 entries1 entries2 entries3
-entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3
+children=entries0 entries1 entries2 entries3 entries4
+entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 system.e820_table.entries4
eventq_index=0
[system.e820_table.entries0]
@@ -290,6 +290,13 @@ size=133169152
[system.e820_table.entries3]
type=X86E820Entry
+addr=134217728
+eventq_index=0
+range_type=2
+size=3087007744
+
+[system.e820_table.entries4]
+type=X86E820Entry
addr=4294901760
eventq_index=0
range_type=2
@@ -350,13 +357,13 @@ version=17
[system.intel_mp_table.base_entries03]
type=X86IntelMPBus
bus_id=0
-bus_type=ISA
+bus_type=PCI
eventq_index=0
[system.intel_mp_table.base_entries04]
type=X86IntelMPBus
bus_id=1
-bus_type=PCI
+bus_type=ISA
eventq_index=0
[system.intel_mp_table.base_entries05]
@@ -366,7 +373,7 @@ dest_io_apic_intin=16
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=1
+source_bus_id=0
source_bus_irq=16
trigger=ConformTrigger
@@ -377,7 +384,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=0
trigger=ConformTrigger
@@ -388,7 +395,7 @@ dest_io_apic_intin=2
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=0
trigger=ConformTrigger
@@ -399,7 +406,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=1
trigger=ConformTrigger
@@ -410,7 +417,7 @@ dest_io_apic_intin=1
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=1
trigger=ConformTrigger
@@ -421,7 +428,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=3
trigger=ConformTrigger
@@ -432,7 +439,7 @@ dest_io_apic_intin=3
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=3
trigger=ConformTrigger
@@ -443,7 +450,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=4
trigger=ConformTrigger
@@ -454,7 +461,7 @@ dest_io_apic_intin=4
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=4
trigger=ConformTrigger
@@ -465,7 +472,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=5
trigger=ConformTrigger
@@ -476,7 +483,7 @@ dest_io_apic_intin=5
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=5
trigger=ConformTrigger
@@ -487,7 +494,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=6
trigger=ConformTrigger
@@ -498,7 +505,7 @@ dest_io_apic_intin=6
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=6
trigger=ConformTrigger
@@ -509,7 +516,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=7
trigger=ConformTrigger
@@ -520,7 +527,7 @@ dest_io_apic_intin=7
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=7
trigger=ConformTrigger
@@ -531,7 +538,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=8
trigger=ConformTrigger
@@ -542,7 +549,7 @@ dest_io_apic_intin=8
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=8
trigger=ConformTrigger
@@ -553,7 +560,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=9
trigger=ConformTrigger
@@ -564,7 +571,7 @@ dest_io_apic_intin=9
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=9
trigger=ConformTrigger
@@ -575,7 +582,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=10
trigger=ConformTrigger
@@ -586,7 +593,7 @@ dest_io_apic_intin=10
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=10
trigger=ConformTrigger
@@ -597,7 +604,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=11
trigger=ConformTrigger
@@ -608,7 +615,7 @@ dest_io_apic_intin=11
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=11
trigger=ConformTrigger
@@ -619,7 +626,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=12
trigger=ConformTrigger
@@ -630,7 +637,7 @@ dest_io_apic_intin=12
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=12
trigger=ConformTrigger
@@ -641,7 +648,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=13
trigger=ConformTrigger
@@ -652,7 +659,7 @@ dest_io_apic_intin=13
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=13
trigger=ConformTrigger
@@ -663,7 +670,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=14
trigger=ConformTrigger
@@ -674,15 +681,15 @@ dest_io_apic_intin=14
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=14
trigger=ConformTrigger
[system.intel_mp_table.ext_entries]
type=X86IntelMPBusHierarchy
-bus_id=0
+bus_id=1
eventq_index=0
-parent_bus=1
+parent_bus=0
subtractive_decode=true
[system.intrctrl]
@@ -691,7 +698,7 @@ eventq_index=0
sys=system
[system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
@@ -920,6 +927,7 @@ HeaderType=0
InterruptLine=14
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=9223372036854775808
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
@@ -1210,8 +1218,33 @@ pio=system.iobus.master[8]
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -1220,6 +1253,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -1233,19 +1267,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt
index 76fedc0c9..009902713 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt
@@ -1,79 +1,79 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 5.300439 # Number of seconds simulated
-sim_ticks 5300438650000 # Number of ticks simulated
-final_tick 5300438650000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.307664 # Number of seconds simulated
+sim_ticks 5307664297000 # Number of ticks simulated
+final_tick 5307664297000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 211376 # Simulator instruction rate (inst/s)
-host_op_rate 405302 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 10491513446 # Simulator tick rate (ticks/s)
-host_mem_usage 792492 # Number of bytes of host memory used
-host_seconds 505.21 # Real time elapsed on the host
-sim_insts 106789618 # Number of instructions simulated
-sim_ops 204763566 # Number of ops (including micro ops) simulated
+host_inst_rate 131058 # Simulator instruction rate (inst/s)
+host_op_rate 251295 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 6508784206 # Simulator tick rate (ticks/s)
+host_mem_usage 839108 # Number of bytes of host memory used
+host_seconds 815.46 # Real time elapsed on the host
+sim_insts 106872831 # Number of instructions simulated
+sim_ops 204921615 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::pc.south_bridge.ide 35184 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 121960 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 61480 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 541981136 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 38703389 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 101016 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 45856 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 470377672 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 54942760 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1106370453 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 541981136 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 470377672 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1012358808 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::pc.south_bridge.ide 35048 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 92784 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 39160 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 533690368 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 37117376 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 127944 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 68056 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 479473072 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 56585622 # Number of bytes read from this memory
+system.physmem.bytes_read::total 1107229430 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 533690368 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 479473072 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1013163440 # Number of instructions bytes read from this memory
system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 31533942 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 36447976 # Number of bytes written to this memory
-system.physmem.bytes_written::total 70973038 # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide 814 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker 15245 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 7685 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 67747642 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 6493671 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 12627 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker 5732 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 58797209 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 9219399 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 142300024 # Number of read requests responded to by this memory
+system.physmem.bytes_written::cpu0.data 30817575 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 37205147 # Number of bytes written to this memory
+system.physmem.bytes_written::total 71013842 # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide 797 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker 11598 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 4895 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 66711296 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 6242247 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 15993 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 8507 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 59934134 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 9480217 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 142409684 # Number of read requests responded to by this memory
system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 4739534 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 5091384 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 9877656 # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide 6638 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker 23009 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 11599 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 102252129 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 7301922 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 19058 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker 8651 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 88743159 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 10365701 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 208731867 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 102252129 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 88743159 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 190995288 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::pc.south_bridge.ide 564313 # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::cpu0.data 4638628 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 5197709 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 9883075 # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide 6603 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker 17481 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 7378 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 100550890 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 6993166 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 24106 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 12822 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 90335983 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 10661115 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 208609544 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 100550890 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 90335983 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 190886873 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::pc.south_bridge.ide 563544 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 5949308 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 6876407 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 13390031 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 570950 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 23009 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 11602 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 102252129 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 13251230 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 19058 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker 8651 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 88743159 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 17242108 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 222121898 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 5806240 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 7009702 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 13379490 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 570148 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 17481 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 7381 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 100550890 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 12799406 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 24106 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 12822 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 90335983 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 17670818 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 221989034 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 0 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 0 # Number of DRAM read bursts, including those serviced by the write queue
@@ -253,8 +253,8 @@ system.physmem.readRowHitRate nan # Ro
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap nan # Average gap between requests
system.physmem.pageHitRate nan # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 5123442263750 # Time in different power states
-system.physmem.memoryStateTime::REF 176993180000 # Time in different power states
+system.physmem.memoryStateTime::IDLE 5130426623750 # Time in different power states
+system.physmem.memoryStateTime::REF 177234460000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 0 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
@@ -266,61 +266,61 @@ system.physmem.readEnergy::0 0 # En
system.physmem.readEnergy::1 0 # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0 346198660080 # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1 346198660080 # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0 114660947205 # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1 114660947205 # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0 3079681479750 # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1 3079681479750 # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0 3540541087035 # Total energy per rank (pJ)
-system.physmem.totalEnergy::1 3540541087035 # Total energy per rank (pJ)
+system.physmem.refreshEnergy::0 346670603760 # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1 346670603760 # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0 114817254885 # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1 114817254885 # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0 3083879751750 # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1 3083879751750 # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0 3545367610395 # Total energy per rank (pJ)
+system.physmem.totalEnergy::1 3545367610395 # Total energy per rank (pJ)
system.physmem.averagePower::0 667.971742 # Core power per rank (mW)
system.physmem.averagePower::1 667.971742 # Core power per rank (mW)
system.ruby.clk_domain.clock 500 # Clock period in ticks
system.ruby.delayHist::bucket_size 4 # delay histogram for all message
system.ruby.delayHist::max_bucket 39 # delay histogram for all message
-system.ruby.delayHist::samples 10855969 # delay histogram for all message
-system.ruby.delayHist::mean 0.443071 # delay histogram for all message
-system.ruby.delayHist::stdev 1.830936 # delay histogram for all message
-system.ruby.delayHist | 10255101 94.47% 94.47% | 1445 0.01% 94.48% | 599037 5.52% 100.00% | 126 0.00% 100.00% | 212 0.00% 100.00% | 12 0.00% 100.00% | 36 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
-system.ruby.delayHist::total 10855969 # delay histogram for all message
+system.ruby.delayHist::samples 10848323 # delay histogram for all message
+system.ruby.delayHist::mean 0.443552 # delay histogram for all message
+system.ruby.delayHist::stdev 1.831983 # delay histogram for all message
+system.ruby.delayHist | 10247251 94.46% 94.46% | 1323 0.01% 94.47% | 599337 5.52% 100.00% | 144 0.00% 100.00% | 216 0.00% 100.00% | 20 0.00% 100.00% | 32 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
+system.ruby.delayHist::total 10848323 # delay histogram for all message
system.ruby.outstanding_req_hist::bucket_size 1
system.ruby.outstanding_req_hist::max_bucket 9
-system.ruby.outstanding_req_hist::samples 152130131
+system.ruby.outstanding_req_hist::samples 152245227
system.ruby.outstanding_req_hist::mean 1.000112
system.ruby.outstanding_req_hist::gmean 1.000078
-system.ruby.outstanding_req_hist::stdev 0.010599
-system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 152113038 99.99% 99.99% | 17093 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist::total 152130131
-system.ruby.latency_hist::bucket_size 32
-system.ruby.latency_hist::max_bucket 319
-system.ruby.latency_hist::samples 152130130
-system.ruby.latency_hist::mean 3.380455
-system.ruby.latency_hist::gmean 3.106132
-system.ruby.latency_hist::stdev 3.781513
-system.ruby.latency_hist | 151955103 99.88% 99.88% | 126 0.00% 99.89% | 79786 0.05% 99.94% | 94134 0.06% 100.00% | 979 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.latency_hist::total 152130130
+system.ruby.outstanding_req_hist::stdev 0.010603
+system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 152228110 99.99% 99.99% | 17117 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.outstanding_req_hist::total 152245227
+system.ruby.latency_hist::bucket_size 16
+system.ruby.latency_hist::max_bucket 159
+system.ruby.latency_hist::samples 152245226
+system.ruby.latency_hist::mean 3.379322
+system.ruby.latency_hist::gmean 3.105966
+system.ruby.latency_hist::stdev 3.769964
+system.ruby.latency_hist | 149590953 98.26% 98.26% | 2481061 1.63% 99.89% | 133 0.00% 99.89% | 0 0.00% 99.89% | 77046 0.05% 99.94% | 1268 0.00% 99.94% | 90138 0.06% 100.00% | 3722 0.00% 100.00% | 854 0.00% 100.00% | 51 0.00% 100.00%
+system.ruby.latency_hist::total 152245226
system.ruby.hit_latency_hist::bucket_size 1
system.ruby.hit_latency_hist::max_bucket 9
-system.ruby.hit_latency_hist::samples 149475024
+system.ruby.hit_latency_hist::samples 149590953
system.ruby.hit_latency_hist::mean 3
system.ruby.hit_latency_hist::gmean 3.000000
-system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 149475024 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.hit_latency_hist::total 149475024
-system.ruby.miss_latency_hist::bucket_size 32
-system.ruby.miss_latency_hist::max_bucket 319
-system.ruby.miss_latency_hist::samples 2655106
-system.ruby.miss_latency_hist::mean 24.799008
-system.ruby.miss_latency_hist::gmean 21.990340
-system.ruby.miss_latency_hist::stdev 18.773320
-system.ruby.miss_latency_hist | 2480079 93.41% 93.41% | 126 0.00% 93.41% | 79786 3.01% 96.42% | 94134 3.55% 99.96% | 979 0.04% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.miss_latency_hist::total 2655106
-system.ruby.l1_cntrl0.L1Dcache.demand_hits 10730190 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses 525947 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses 11256137 # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits 67423344 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses 324298 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses 67747642 # Number of cache demand accesses
+system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 149590953 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.hit_latency_hist::total 149590953
+system.ruby.miss_latency_hist::bucket_size 16
+system.ruby.miss_latency_hist::max_bucket 159
+system.ruby.miss_latency_hist::samples 2654273
+system.ruby.miss_latency_hist::mean 24.757382
+system.ruby.miss_latency_hist::gmean 21.969703
+system.ruby.miss_latency_hist::stdev 18.710561
+system.ruby.miss_latency_hist | 0 0.00% 0.00% | 2481061 93.47% 93.47% | 133 0.01% 93.48% | 0 0.00% 93.48% | 77046 2.90% 96.38% | 1268 0.05% 96.43% | 90138 3.40% 99.83% | 3722 0.14% 99.97% | 854 0.03% 100.00% | 51 0.00% 100.00%
+system.ruby.miss_latency_hist::total 2654273
+system.ruby.l1_cntrl0.L1Dcache.demand_hits 10398035 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses 499335 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses 10897370 # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_hits 66409156 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Icache.demand_misses 302140 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses 66711296 # Number of cache demand accesses
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed
system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
@@ -331,30 +331,30 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu
system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl0.fully_busy_cycles 12 # cycles for which number of transistions == max transitions
-system.ruby.network.routers0.percent_links_utilized 0.029767
-system.ruby.network.routers0.msg_count.Control::0 850245
-system.ruby.network.routers0.msg_count.Request_Control::2 42194
-system.ruby.network.routers0.msg_count.Response_Data::1 878350
-system.ruby.network.routers0.msg_count.Response_Control::1 503571
-system.ruby.network.routers0.msg_count.Response_Control::2 500402
-system.ruby.network.routers0.msg_count.Writeback_Data::0 294663
-system.ruby.network.routers0.msg_count.Writeback_Data::1 77
-system.ruby.network.routers0.msg_count.Writeback_Control::0 168221
-system.ruby.network.routers0.msg_bytes.Control::0 6801960
-system.ruby.network.routers0.msg_bytes.Request_Control::2 337552
-system.ruby.network.routers0.msg_bytes.Response_Data::1 63241200
-system.ruby.network.routers0.msg_bytes.Response_Control::1 4028568
-system.ruby.network.routers0.msg_bytes.Response_Control::2 4003216
-system.ruby.network.routers0.msg_bytes.Writeback_Data::0 21215736
-system.ruby.network.routers0.msg_bytes.Writeback_Data::1 5544
-system.ruby.network.routers0.msg_bytes.Writeback_Control::0 1345768
-system.ruby.l1_cntrl1.L1Dcache.demand_hits 13015788 # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Dcache.demand_misses 1313354 # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Dcache.demand_accesses 14329142 # Number of cache demand accesses
-system.ruby.l1_cntrl1.L1Icache.demand_hits 58305702 # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Icache.demand_misses 491507 # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Icache.demand_accesses 58797209 # Number of cache demand accesses
+system.ruby.l1_cntrl0.fully_busy_cycles 10 # cycles for which number of transistions == max transitions
+system.ruby.network.routers0.percent_links_utilized 0.028216
+system.ruby.network.routers0.msg_count.Control::0 801475
+system.ruby.network.routers0.msg_count.Request_Control::2 41656
+system.ruby.network.routers0.msg_count.Response_Data::1 829298
+system.ruby.network.routers0.msg_count.Response_Control::1 479862
+system.ruby.network.routers0.msg_count.Response_Control::2 476757
+system.ruby.network.routers0.msg_count.Writeback_Data::0 284601
+system.ruby.network.routers0.msg_count.Writeback_Data::1 103
+system.ruby.network.routers0.msg_count.Writeback_Control::0 155150
+system.ruby.network.routers0.msg_bytes.Control::0 6411800
+system.ruby.network.routers0.msg_bytes.Request_Control::2 333248
+system.ruby.network.routers0.msg_bytes.Response_Data::1 59709456
+system.ruby.network.routers0.msg_bytes.Response_Control::1 3838896
+system.ruby.network.routers0.msg_bytes.Response_Control::2 3814056
+system.ruby.network.routers0.msg_bytes.Writeback_Data::0 20491272
+system.ruby.network.routers0.msg_bytes.Writeback_Data::1 7416
+system.ruby.network.routers0.msg_bytes.Writeback_Control::0 1241200
+system.ruby.l1_cntrl1.L1Dcache.demand_hits 13362952 # Number of cache demand hits
+system.ruby.l1_cntrl1.L1Dcache.demand_misses 1339474 # Number of cache demand misses
+system.ruby.l1_cntrl1.L1Dcache.demand_accesses 14702426 # Number of cache demand accesses
+system.ruby.l1_cntrl1.L1Icache.demand_hits 59420810 # Number of cache demand hits
+system.ruby.l1_cntrl1.L1Icache.demand_misses 513324 # Number of cache demand misses
+system.ruby.l1_cntrl1.L1Icache.demand_accesses 59934134 # Number of cache demand accesses
system.ruby.l1_cntrl1.prefetcher.miss_observed 0 # number of misses observed
system.ruby.l1_cntrl1.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
system.ruby.l1_cntrl1.prefetcher.prefetches_requested 0 # number of prefetch requests made
@@ -364,111 +364,110 @@ system.ruby.l1_cntrl1.prefetcher.hits 0 # nu
system.ruby.l1_cntrl1.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl1.fully_busy_cycles 13 # cycles for which number of transistions == max transitions
-system.ruby.network.routers1.percent_links_utilized 0.057220
-system.ruby.network.routers1.msg_count.Control::0 1804861
-system.ruby.network.routers1.msg_count.Request_Control::2 38457
-system.ruby.network.routers1.msg_count.Response_Data::1 1828237
-system.ruby.network.routers1.msg_count.Response_Control::1 1255902
-system.ruby.network.routers1.msg_count.Response_Control::2 1256112
-system.ruby.network.routers1.msg_count.Writeback_Data::0 279082
-system.ruby.network.routers1.msg_count.Writeback_Data::1 227
-system.ruby.network.routers1.msg_count.Writeback_Control::0 940216
-system.ruby.network.routers1.msg_bytes.Control::0 14438888
-system.ruby.network.routers1.msg_bytes.Request_Control::2 307656
-system.ruby.network.routers1.msg_bytes.Response_Data::1 131633064
-system.ruby.network.routers1.msg_bytes.Response_Control::1 10047216
-system.ruby.network.routers1.msg_bytes.Response_Control::2 10048896
-system.ruby.network.routers1.msg_bytes.Writeback_Data::0 20093904
-system.ruby.network.routers1.msg_bytes.Writeback_Data::1 16344
-system.ruby.network.routers1.msg_bytes.Writeback_Control::0 7521728
-system.ruby.l2_cntrl0.L2cache.demand_hits 2431773 # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses 223333 # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses 2655106 # Number of cache demand accesses
-system.ruby.l2_cntrl0.fully_busy_cycles 2 # cycles for which number of transistions == max transitions
-system.ruby.network.routers2.percent_links_utilized 0.091305
-system.ruby.network.routers2.msg_count.Control::0 2830007
-system.ruby.network.routers2.msg_count.Request_Control::2 78985
-system.ruby.network.routers2.msg_count.Response_Data::1 2882064
-system.ruby.network.routers2.msg_count.Response_Control::1 1837383
-system.ruby.network.routers2.msg_count.Response_Control::2 1756514
-system.ruby.network.routers2.msg_count.Writeback_Data::0 573745
-system.ruby.network.routers2.msg_count.Writeback_Data::1 304
-system.ruby.network.routers2.msg_count.Writeback_Control::0 1108437
-system.ruby.network.routers2.msg_bytes.Control::0 22640056
-system.ruby.network.routers2.msg_bytes.Request_Control::2 631880
-system.ruby.network.routers2.msg_bytes.Response_Data::1 207508608
-system.ruby.network.routers2.msg_bytes.Response_Control::1 14699064
-system.ruby.network.routers2.msg_bytes.Response_Control::2 14052112
-system.ruby.network.routers2.msg_bytes.Writeback_Data::0 41309640
-system.ruby.network.routers2.msg_bytes.Writeback_Data::1 21888
-system.ruby.network.routers2.msg_bytes.Writeback_Control::0 8867496
+system.ruby.l1_cntrl1.fully_busy_cycles 14 # cycles for which number of transistions == max transitions
+system.ruby.network.routers1.percent_links_utilized 0.058632
+system.ruby.network.routers1.msg_count.Control::0 1852798
+system.ruby.network.routers1.msg_count.Request_Control::2 38016
+system.ruby.network.routers1.msg_count.Response_Data::1 1875931
+system.ruby.network.routers1.msg_count.Response_Control::1 1278748
+system.ruby.network.routers1.msg_count.Response_Control::2 1279400
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+system.ruby.network.routers1.msg_count.Writeback_Data::1 222
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+system.ruby.network.routers1.msg_bytes.Control::0 14822384
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+system.ruby.network.routers1.msg_bytes.Response_Data::1 135067032
+system.ruby.network.routers1.msg_bytes.Response_Control::1 10229984
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+system.ruby.network.routers1.msg_bytes.Writeback_Data::1 15984
+system.ruby.network.routers1.msg_bytes.Writeback_Control::0 7623072
+system.ruby.l2_cntrl0.L2cache.demand_hits 2433243 # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses 221030 # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses 2654273 # Number of cache demand accesses
+system.ruby.network.routers2.percent_links_utilized 0.091109
+system.ruby.network.routers2.msg_count.Control::0 2827352
+system.ruby.network.routers2.msg_count.Request_Control::2 78096
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+system.ruby.network.routers2.msg_count.Response_Control::1 1833514
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+system.ruby.network.routers2.msg_count.Writeback_Data::1 325
+system.ruby.network.routers2.msg_count.Writeback_Control::0 1108034
+system.ruby.network.routers2.msg_bytes.Control::0 22618816
+system.ruby.network.routers2.msg_bytes.Request_Control::2 624768
+system.ruby.network.routers2.msg_bytes.Response_Data::1 207279000
+system.ruby.network.routers2.msg_bytes.Response_Control::1 14668112
+system.ruby.network.routers2.msg_bytes.Response_Control::2 14049256
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+system.ruby.network.routers2.msg_bytes.Writeback_Data::1 23400
+system.ruby.network.routers2.msg_bytes.Writeback_Control::0 8864272
system.ruby.memctrl_clk_domain.clock 1500 # Clock period in ticks
-system.ruby.dir_cntrl0.memBuffer.memReq 317875 # Total number of memory requests
-system.ruby.dir_cntrl0.memBuffer.memRead 175364 # Number of memory reads
-system.ruby.dir_cntrl0.memBuffer.memWrite 142511 # Number of memory writes
-system.ruby.dir_cntrl0.memBuffer.memRefresh 714751 # Number of memory refreshes
-system.ruby.dir_cntrl0.memBuffer.memWaitCycles 942834 # Delay stalled at the head of the bank queue
-system.ruby.dir_cntrl0.memBuffer.memInputQ 46 # Delay in the input queue
-system.ruby.dir_cntrl0.memBuffer.memBankQ 6611 # Delay behind the head of the bank queue
-system.ruby.dir_cntrl0.memBuffer.totalStalls 949491 # Total number of stall cycles
-system.ruby.dir_cntrl0.memBuffer.stallsPerReq 2.986995 # Expected number of stall cycles per request
-system.ruby.dir_cntrl0.memBuffer.memBankBusy 931351 # memory stalls due to busy bank
-system.ruby.dir_cntrl0.memBuffer.memBusBusy 8237 # memory stalls due to busy bus
-system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 87 # memory stalls due to read write turnaround
-system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 8 # memory stalls due to read read turnaround
-system.ruby.dir_cntrl0.memBuffer.memArbWait 3151 # memory stalls due to arbitration
-system.ruby.dir_cntrl0.memBuffer.memBankCount | 10282 3.23% 3.23% | 9701 3.05% 6.29% | 9679 3.04% 9.33% | 9712 3.06% 12.39% | 10010 3.15% 15.54% | 9927 3.12% 18.66% | 9854 3.10% 21.76% | 9702 3.05% 24.81% | 9904 3.12% 27.93% | 9752 3.07% 30.99% | 9805 3.08% 34.08% | 9914 3.12% 37.20% | 9948 3.13% 40.33% | 9724 3.06% 43.39% | 9647 3.03% 46.42% | 8750 2.75% 49.17% | 10266 3.23% 52.40% | 9887 3.11% 55.51% | 9844 3.10% 58.61% | 9758 3.07% 61.68% | 10022 3.15% 64.83% | 9879 3.11% 67.94% | 9766 3.07% 71.01% | 9852 3.10% 74.11% | 10073 3.17% 77.28% | 9931 3.12% 80.41% | 10175 3.20% 83.61% | 10769 3.39% 86.99% | 10605 3.34% 90.33% | 10522 3.31% 93.64% | 10506 3.31% 96.95% | 9709 3.05% 100.00% # Number of accesses per bank
-system.ruby.dir_cntrl0.memBuffer.memBankCount::total 317875 # Number of accesses per bank
-system.ruby.network.routers3.percent_links_utilized 0.006727
-system.ruby.network.routers3.msg_count.Control::0 174901
-system.ruby.network.routers3.msg_count.Response_Data::1 273155
-system.ruby.network.routers3.msg_count.Response_Control::1 125034
-system.ruby.network.routers3.msg_count.Writeback_Control::0 47550
+system.ruby.dir_cntrl0.memBuffer.memReq 315612 # Total number of memory requests
+system.ruby.dir_cntrl0.memBuffer.memRead 173522 # Number of memory reads
+system.ruby.dir_cntrl0.memBuffer.memWrite 142090 # Number of memory writes
+system.ruby.dir_cntrl0.memBuffer.memRefresh 706808 # Number of memory refreshes
+system.ruby.dir_cntrl0.memBuffer.memWaitCycles 938252 # Delay stalled at the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.memInputQ 30 # Delay in the input queue
+system.ruby.dir_cntrl0.memBuffer.memBankQ 6383 # Delay behind the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.totalStalls 944665 # Total number of stall cycles
+system.ruby.dir_cntrl0.memBuffer.stallsPerReq 2.993121 # Expected number of stall cycles per request
+system.ruby.dir_cntrl0.memBuffer.memBankBusy 926705 # memory stalls due to busy bank
+system.ruby.dir_cntrl0.memBuffer.memBusBusy 8329 # memory stalls due to busy bus
+system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 104 # memory stalls due to read write turnaround
+system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 5 # memory stalls due to read read turnaround
+system.ruby.dir_cntrl0.memBuffer.memArbWait 3109 # memory stalls due to arbitration
+system.ruby.dir_cntrl0.memBuffer.memBankCount | 10201 3.23% 3.23% | 9660 3.06% 6.29% | 9611 3.05% 9.34% | 9645 3.06% 12.39% | 9963 3.16% 15.55% | 9896 3.14% 18.69% | 9791 3.10% 21.79% | 9613 3.05% 24.83% | 9895 3.14% 27.97% | 9715 3.08% 31.05% | 9712 3.08% 34.12% | 9809 3.11% 37.23% | 9865 3.13% 40.36% | 9619 3.05% 43.41% | 9583 3.04% 46.44% | 8620 2.73% 49.17% | 10251 3.25% 52.42% | 9857 3.12% 55.54% | 9748 3.09% 58.63% | 9683 3.07% 61.70% | 9944 3.15% 64.85% | 9751 3.09% 67.94% | 9685 3.07% 71.01% | 9777 3.10% 74.11% | 9976 3.16% 77.27% | 9827 3.11% 80.38% | 10062 3.19% 83.57% | 10634 3.37% 86.94% | 10589 3.36% 90.30% | 10446 3.31% 93.60% | 10476 3.32% 96.92% | 9708 3.08% 100.00% # Number of accesses per bank
+system.ruby.dir_cntrl0.memBuffer.memBankCount::total 315612 # Number of accesses per bank
+system.ruby.network.routers3.percent_links_utilized 0.006646
+system.ruby.network.routers3.msg_count.Control::0 173079
+system.ruby.network.routers3.msg_count.Response_Data::1 270344
+system.ruby.network.routers3.msg_count.Response_Control::1 121446
+system.ruby.network.routers3.msg_count.Writeback_Control::0 47533
system.ruby.network.routers3.msg_count.Writeback_Control::1 46736
-system.ruby.network.routers3.msg_bytes.Control::0 1399208
-system.ruby.network.routers3.msg_bytes.Response_Data::1 19667160
-system.ruby.network.routers3.msg_bytes.Response_Control::1 1000272
-system.ruby.network.routers3.msg_bytes.Writeback_Control::0 380400
+system.ruby.network.routers3.msg_bytes.Control::0 1384632
+system.ruby.network.routers3.msg_bytes.Response_Data::1 19464768
+system.ruby.network.routers3.msg_bytes.Response_Control::1 971568
+system.ruby.network.routers3.msg_bytes.Writeback_Control::0 380264
system.ruby.network.routers3.msg_bytes.Writeback_Control::1 373888
-system.ruby.network.routers4.percent_links_utilized 0.000240
-system.ruby.network.routers4.msg_count.Response_Data::1 814
-system.ruby.network.routers4.msg_count.Writeback_Control::0 47550
+system.ruby.network.routers4.percent_links_utilized 0.000239
+system.ruby.network.routers4.msg_count.Response_Data::1 797
+system.ruby.network.routers4.msg_count.Writeback_Control::0 47533
system.ruby.network.routers4.msg_count.Writeback_Control::1 46736
-system.ruby.network.routers4.msg_bytes.Response_Data::1 58608
-system.ruby.network.routers4.msg_bytes.Writeback_Control::0 380400
+system.ruby.network.routers4.msg_bytes.Response_Data::1 57384
+system.ruby.network.routers4.msg_bytes.Writeback_Control::0 380264
system.ruby.network.routers4.msg_bytes.Writeback_Control::1 373888
-system.ruby.network.routers5.percent_links_utilized 0.037053
-system.ruby.network.routers5.msg_count.Control::0 2830007
-system.ruby.network.routers5.msg_count.Request_Control::2 80651
-system.ruby.network.routers5.msg_count.Response_Data::1 2931310
-system.ruby.network.routers5.msg_count.Response_Control::1 1860945
-system.ruby.network.routers5.msg_count.Response_Control::2 1756514
-system.ruby.network.routers5.msg_count.Writeback_Data::0 573745
-system.ruby.network.routers5.msg_count.Writeback_Data::1 304
-system.ruby.network.routers5.msg_count.Writeback_Control::0 1155987
+system.ruby.network.routers5.percent_links_utilized 0.036969
+system.ruby.network.routers5.msg_count.Control::0 2827352
+system.ruby.network.routers5.msg_count.Request_Control::2 79672
+system.ruby.network.routers5.msg_count.Response_Data::1 2927623
+system.ruby.network.routers5.msg_count.Response_Control::1 1856785
+system.ruby.network.routers5.msg_count.Response_Control::2 1756157
+system.ruby.network.routers5.msg_count.Writeback_Data::0 574474
+system.ruby.network.routers5.msg_count.Writeback_Data::1 325
+system.ruby.network.routers5.msg_count.Writeback_Control::0 1155567
system.ruby.network.routers5.msg_count.Writeback_Control::1 46736
-system.ruby.network.routers5.msg_bytes.Control::0 22640056
-system.ruby.network.routers5.msg_bytes.Request_Control::2 645208
-system.ruby.network.routers5.msg_bytes.Response_Data::1 211054320
-system.ruby.network.routers5.msg_bytes.Response_Control::1 14887560
-system.ruby.network.routers5.msg_bytes.Response_Control::2 14052112
-system.ruby.network.routers5.msg_bytes.Writeback_Data::0 41309640
-system.ruby.network.routers5.msg_bytes.Writeback_Data::1 21888
-system.ruby.network.routers5.msg_bytes.Writeback_Control::0 9247896
+system.ruby.network.routers5.msg_bytes.Control::0 22618816
+system.ruby.network.routers5.msg_bytes.Request_Control::2 637376
+system.ruby.network.routers5.msg_bytes.Response_Data::1 210788856
+system.ruby.network.routers5.msg_bytes.Response_Control::1 14854280
+system.ruby.network.routers5.msg_bytes.Response_Control::2 14049256
+system.ruby.network.routers5.msg_bytes.Writeback_Data::0 41362128
+system.ruby.network.routers5.msg_bytes.Writeback_Data::1 23400
+system.ruby.network.routers5.msg_bytes.Writeback_Control::0 9244536
system.ruby.network.routers5.msg_bytes.Writeback_Control::1 373888
-system.ruby.network.msg_count.Control 8490021
-system.ruby.network.msg_count.Request_Control 240287
-system.ruby.network.msg_count.Response_Data 8793930
-system.ruby.network.msg_count.Response_Control 10852377
-system.ruby.network.msg_count.Writeback_Data 1722147
-system.ruby.network.msg_count.Writeback_Control 3608169
-system.ruby.network.msg_byte.Control 67920168
-system.ruby.network.msg_byte.Request_Control 1922296
-system.ruby.network.msg_byte.Response_Data 633162960
-system.ruby.network.msg_byte.Response_Control 86819016
-system.ruby.network.msg_byte.Writeback_Data 123994584
-system.ruby.network.msg_byte.Writeback_Control 28865352
+system.ruby.network.msg_count.Control 8482056
+system.ruby.network.msg_count.Request_Control 237440
+system.ruby.network.msg_count.Response_Data 8782868
+system.ruby.network.msg_count.Response_Control 10838826
+system.ruby.network.msg_count.Writeback_Data 1724397
+system.ruby.network.msg_count.Writeback_Control 3606909
+system.ruby.network.msg_byte.Control 67856448
+system.ruby.network.msg_byte.Request_Control 1899520
+system.ruby.network.msg_byte.Response_Data 632366496
+system.ruby.network.msg_byte.Response_Control 86710608
+system.ruby.network.msg_byte.Writeback_Data 124156584
+system.ruby.network.msg_byte.Writeback_Control 28855272
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD).
@@ -481,738 +480,740 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq 858433 # Transaction distribution
-system.iobus.trans_dist::ReadResp 858433 # Transaction distribution
-system.iobus.trans_dist::WriteReq 37701 # Transaction distribution
-system.iobus.trans_dist::WriteResp 37701 # Transaction distribution
+system.iobus.trans_dist::ReadReq 858552 # Transaction distribution
+system.iobus.trans_dist::ReadResp 858552 # Transaction distribution
+system.iobus.trans_dist::WriteReq 37826 # Transaction distribution
+system.iobus.trans_dist::WriteResp 37826 # Transaction distribution
system.iobus.trans_dist::MessageReq 1920 # Transaction distribution
system.iobus.trans_dist::MessageResp 1920 # Transaction distribution
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1700 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 1644 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3344 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1704 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 1646 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3350 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 5246 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 4826 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 88 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 956 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 82 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 38 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 934582 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 984 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 990 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist.pio 90 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 14276 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 743206 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 14738 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 743208 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 246 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1701984 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1702038 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 5796 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 6216 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 92 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 408 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 33042 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 33054 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 350 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist.pio 33130 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 12392 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist.pio 33142 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 12398 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 250 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 5220 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 90780 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 1796108 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 3400 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 3288 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6688 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 244 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 5208 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 91208 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 1796596 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 3408 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 3292 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6700 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 2968 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 2722 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 149 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 478 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 41 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 19 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 467291 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1968 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1980 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist.pio 45 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 7138 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1486406 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 7369 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1486410 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 492 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1971279 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1971282 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3692 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3938 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 72 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 204 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 8 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 16521 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 16527 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 700 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist.pio 16565 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 6196 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist.pio 16571 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 6199 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 500 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 10437 # Cumulative packet size per connected master and slave (bytes)
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-system.iobus.reqLayer0.occupancy 44000 # Layer occupancy (ticks)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 488 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 2000 # Layer occupancy (ticks)
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system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
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system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer2.occupancy 1790015500 # Layer occupancy (ticks)
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system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
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system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu0.numCycles 10600877300 # number of cpu cycles simulated
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system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
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-system.cpu0.committedInsts 58227397 # Number of instructions committed
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system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
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-system.cpu0.num_conditional_control_insts 9961508 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 104955708 # number of integer instructions
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system.cpu0.num_fp_insts 0 # number of float instructions
-system.cpu0.num_int_register_reads 197725542 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 89196196 # number of times the integer registers were written
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system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 60309477 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 43597657 # number of times the CC registers were written
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-system.cpu0.not_idle_fraction 0.048149 # Percentage of non-idle cycles
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-system.cpu0.op_class::No_OpClass 134403 0.12% 0.12% # Class of executed instruction
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system.cpu0.kern.inst.arm 0 # number of arm instructions executed
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system.cpu1.apic_clk_domain.clock 8000 # Clock period in ticks
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system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
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system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
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system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
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system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1 46736
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system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 373888
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system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::1 46736
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system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::1 373888
system.ruby.network.routers4.throttle1.link_utilization 0.000224
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system.ruby.network.routers5.throttle4.msg_count.Writeback_Control::1 46736
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system.ruby.network.routers5.throttle4.msg_bytes.Writeback_Control::1 373888
system.ruby.delayVCHist.vnet_0::bucket_size 4 # delay histogram for vnet_0
system.ruby.delayVCHist.vnet_0::max_bucket 39 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::samples 6093802 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::mean 0.755007 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::stdev 2.340941 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0 | 5519285 90.57% 90.57% | 399 0.01% 90.58% | 573737 9.42% 99.99% | 123 0.00% 100.00% | 210 0.00% 100.00% | 12 0.00% 100.00% | 36 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::total 6093802 # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::samples 6092938 # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::mean 0.756056 # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::stdev 2.342480 # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0 | 5517712 90.56% 90.56% | 362 0.01% 90.57% | 574462 9.43% 99.99% | 138 0.00% 100.00% | 212 0.00% 100.00% | 20 0.00% 100.00% | 32 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::total 6092938 # delay histogram for vnet_0
system.ruby.delayVCHist.vnet_1::bucket_size 2 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::max_bucket 19 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::samples 4681516 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::mean 0.044663 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::stdev 0.593096 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1 | 4654718 99.43% 99.43% | 447 0.01% 99.44% | 398 0.01% 99.45% | 648 0.01% 99.46% | 25177 0.54% 100.00% | 123 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 1 0.00% 100.00% # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::total 4681516 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::samples 4675713 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::mean 0.043880 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::stdev 0.588229 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1 | 4649466 99.44% 99.44% | 402 0.01% 99.45% | 397 0.01% 99.46% | 563 0.01% 99.47% | 24746 0.53% 100.00% | 129 0.00% 100.00% | 4 0.00% 100.00% | 2 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::total 4675713 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::samples 80651 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::mean 0.000124 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::stdev 0.015747 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2 | 80646 99.99% 99.99% | 0 0.00% 99.99% | 5 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::total 80651 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::samples 79672 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::mean 0.000276 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::stdev 0.025546 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2 | 79662 99.99% 99.99% | 0 0.00% 99.99% | 9 0.01% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::total 79672 # delay histogram for vnet_2
system.ruby.LD.latency_hist::bucket_size 16
system.ruby.LD.latency_hist::max_bucket 159
-system.ruby.LD.latency_hist::samples 14920569
-system.ruby.LD.latency_hist::mean 4.752955
-system.ruby.LD.latency_hist::gmean 3.589881
-system.ruby.LD.latency_hist::stdev 6.604009
-system.ruby.LD.latency_hist | 13535034 90.71% 90.71% | 1353292 9.07% 99.78% | 96 0.00% 99.78% | 0 0.00% 99.78% | 9982 0.07% 99.85% | 163 0.00% 99.85% | 20984 0.14% 99.99% | 796 0.01% 100.00% | 200 0.00% 100.00% | 22 0.00% 100.00%
-system.ruby.LD.latency_hist::total 14920569
+system.ruby.LD.latency_hist::samples 14929784
+system.ruby.LD.latency_hist::mean 4.746137
+system.ruby.LD.latency_hist::gmean 3.588822
+system.ruby.LD.latency_hist::stdev 6.561595
+system.ruby.LD.latency_hist | 13544851 90.72% 90.72% | 1353763 9.07% 99.79% | 97 0.00% 99.79% | 0 0.00% 99.79% | 9394 0.06% 99.85% | 137 0.00% 99.86% | 20462 0.14% 99.99% | 877 0.01% 100.00% | 177 0.00% 100.00% | 26 0.00% 100.00%
+system.ruby.LD.latency_hist::total 14929784
system.ruby.LD.hit_latency_hist::bucket_size 1
system.ruby.LD.hit_latency_hist::max_bucket 9
-system.ruby.LD.hit_latency_hist::samples 13535034
+system.ruby.LD.hit_latency_hist::samples 13544851
system.ruby.LD.hit_latency_hist::mean 3
system.ruby.LD.hit_latency_hist::gmean 3.000000
-system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 13535034 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.hit_latency_hist::total 13535034
+system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 13544851 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.hit_latency_hist::total 13544851
system.ruby.LD.miss_latency_hist::bucket_size 16
system.ruby.LD.miss_latency_hist::max_bucket 159
-system.ruby.LD.miss_latency_hist::samples 1385535
-system.ruby.LD.miss_latency_hist::mean 21.877250
-system.ruby.LD.miss_latency_hist::gmean 20.732182
-system.ruby.LD.miss_latency_hist::stdev 12.099590
-system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 1353292 97.67% 97.67% | 96 0.01% 97.68% | 0 0.00% 97.68% | 9982 0.72% 98.40% | 163 0.01% 98.41% | 20984 1.51% 99.93% | 796 0.06% 99.98% | 200 0.01% 100.00% | 22 0.00% 100.00%
-system.ruby.LD.miss_latency_hist::total 1385535
-system.ruby.ST.latency_hist::bucket_size 32
-system.ruby.ST.latency_hist::max_bucket 319
-system.ruby.ST.latency_hist::samples 9491428
-system.ruby.ST.latency_hist::mean 4.608485
-system.ruby.ST.latency_hist::gmean 3.286938
-system.ruby.ST.latency_hist::stdev 10.640707
-system.ruby.ST.latency_hist | 9365714 98.68% 98.68% | 17 0.00% 98.68% | 64552 0.68% 99.36% | 60510 0.64% 99.99% | 633 0.01% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.latency_hist::total 9491428
+system.ruby.LD.miss_latency_hist::samples 1384933
+system.ruby.LD.miss_latency_hist::mean 21.823612
+system.ruby.LD.miss_latency_hist::gmean 20.708451
+system.ruby.LD.miss_latency_hist::stdev 11.944645
+system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 1353763 97.75% 97.75% | 97 0.01% 97.76% | 0 0.00% 97.76% | 9394 0.68% 98.43% | 137 0.01% 98.44% | 20462 1.48% 99.92% | 877 0.06% 99.99% | 177 0.01% 100.00% | 26 0.00% 100.00%
+system.ruby.LD.miss_latency_hist::total 1384933
+system.ruby.ST.latency_hist::bucket_size 16
+system.ruby.ST.latency_hist::max_bucket 159
+system.ruby.ST.latency_hist::samples 9496728
+system.ruby.ST.latency_hist::mean 4.603564
+system.ruby.ST.latency_hist::gmean 3.286498
+system.ruby.ST.latency_hist::stdev 10.620395
+system.ruby.ST.latency_hist | 9146629 96.31% 96.31% | 225105 2.37% 98.68% | 21 0.00% 98.68% | 0 0.00% 98.68% | 62699 0.66% 99.34% | 1082 0.01% 99.36% | 58016 0.61% 99.97% | 2598 0.03% 99.99% | 554 0.01% 100.00% | 24 0.00% 100.00%
+system.ruby.ST.latency_hist::total 9496728
system.ruby.ST.hit_latency_hist::bucket_size 1
system.ruby.ST.hit_latency_hist::max_bucket 9
-system.ruby.ST.hit_latency_hist::samples 9141411
+system.ruby.ST.hit_latency_hist::samples 9146629
system.ruby.ST.hit_latency_hist::mean 3
system.ruby.ST.hit_latency_hist::gmean 3.000000
-system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 9141411 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.hit_latency_hist::total 9141411
-system.ruby.ST.miss_latency_hist::bucket_size 32
-system.ruby.ST.miss_latency_hist::max_bucket 319
-system.ruby.ST.miss_latency_hist::samples 350017
-system.ruby.ST.miss_latency_hist::mean 46.617353
-system.ruby.ST.miss_latency_hist::gmean 35.715902
-system.ruby.ST.miss_latency_hist::stdev 35.185303
-system.ruby.ST.miss_latency_hist | 224303 64.08% 64.08% | 17 0.00% 64.09% | 64552 18.44% 82.53% | 60510 17.29% 99.82% | 633 0.18% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.miss_latency_hist::total 350017
+system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 9146629 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.hit_latency_hist::total 9146629
+system.ruby.ST.miss_latency_hist::bucket_size 16
+system.ruby.ST.miss_latency_hist::max_bucket 159
+system.ruby.ST.miss_latency_hist::samples 350099
+system.ruby.ST.miss_latency_hist::mean 46.498022
+system.ruby.ST.miss_latency_hist::gmean 35.614929
+system.ruby.ST.miss_latency_hist::stdev 35.174934
+system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 225105 64.30% 64.30% | 21 0.01% 64.30% | 0 0.00% 64.30% | 62699 17.91% 82.21% | 1082 0.31% 82.52% | 58016 16.57% 99.09% | 2598 0.74% 99.83% | 554 0.16% 99.99% | 24 0.01% 100.00%
+system.ruby.ST.miss_latency_hist::total 350099
system.ruby.IFETCH.latency_hist::bucket_size 16
system.ruby.IFETCH.latency_hist::max_bucket 159
-system.ruby.IFETCH.latency_hist::samples 126544851
-system.ruby.IFETCH.latency_hist::mean 3.112747
-system.ruby.IFETCH.latency_hist::gmean 3.036514
-system.ruby.IFETCH.latency_hist::stdev 1.652226
-system.ruby.IFETCH.latency_hist | 125729046 99.36% 99.36% | 800495 0.63% 99.99% | 4 0.00% 99.99% | 0 0.00% 99.99% | 3856 0.00% 99.99% | 28 0.00% 99.99% | 11079 0.01% 100.00% | 224 0.00% 100.00% | 119 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.latency_hist::total 126544851
+system.ruby.IFETCH.latency_hist::samples 126645430
+system.ruby.IFETCH.latency_hist::mean 3.112625
+system.ruby.IFETCH.latency_hist::gmean 3.036470
+system.ruby.IFETCH.latency_hist::stdev 1.651951
+system.ruby.IFETCH.latency_hist | 125829966 99.36% 99.36% | 800149 0.63% 99.99% | 7 0.00% 99.99% | 0 0.00% 99.99% | 3810 0.00% 99.99% | 27 0.00% 99.99% | 11150 0.01% 100.00% | 208 0.00% 100.00% | 113 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.latency_hist::total 126645430
system.ruby.IFETCH.hit_latency_hist::bucket_size 1
system.ruby.IFETCH.hit_latency_hist::max_bucket 9
-system.ruby.IFETCH.hit_latency_hist::samples 125729046
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system.ruby.IFETCH.hit_latency_hist::mean 3
system.ruby.IFETCH.hit_latency_hist::gmean 3.000000
-system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 125729046 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.hit_latency_hist::total 125729046
+system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 125829966 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.hit_latency_hist::total 125829966
system.ruby.IFETCH.miss_latency_hist::bucket_size 16
system.ruby.IFETCH.miss_latency_hist::max_bucket 159
-system.ruby.IFETCH.miss_latency_hist::samples 815805
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-system.ruby.IFETCH.miss_latency_hist::gmean 19.593048
-system.ruby.IFETCH.miss_latency_hist::stdev 10.934190
-system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 800495 98.12% 98.12% | 4 0.00% 98.12% | 0 0.00% 98.12% | 3856 0.47% 98.60% | 28 0.00% 98.60% | 11079 1.36% 99.96% | 224 0.03% 99.99% | 119 0.01% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.miss_latency_hist::total 815805
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+system.ruby.IFETCH.miss_latency_hist::stdev 10.947392
+system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 800149 98.12% 98.12% | 7 0.00% 98.12% | 0 0.00% 98.12% | 3810 0.47% 98.59% | 27 0.00% 98.59% | 11150 1.37% 99.96% | 208 0.03% 99.99% | 113 0.01% 100.00% | 0 0.00% 100.00%
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system.ruby.RMW_Read.latency_hist::bucket_size 16
system.ruby.RMW_Read.latency_hist::max_bucket 159
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-system.ruby.RMW_Read.latency_hist::mean 5.892257
-system.ruby.RMW_Read.latency_hist::gmean 3.949809
-system.ruby.RMW_Read.latency_hist::stdev 8.207792
-system.ruby.RMW_Read.latency_hist | 428816 86.75% 86.75% | 64079 12.96% 99.72% | 2 0.00% 99.72% | 0 0.00% 99.72% | 994 0.20% 99.92% | 20 0.00% 99.92% | 365 0.07% 100.00% | 18 0.00% 100.00% | 3 0.00% 100.00% | 1 0.00% 100.00%
-system.ruby.RMW_Read.latency_hist::total 494298
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+system.ruby.RMW_Read.latency_hist::mean 5.885454
+system.ruby.RMW_Read.latency_hist::gmean 3.946599
+system.ruby.RMW_Read.latency_hist::stdev 8.214603
+system.ruby.RMW_Read.latency_hist | 428814 86.79% 86.79% | 63844 12.92% 99.72% | 3 0.00% 99.72% | 0 0.00% 99.72% | 984 0.20% 99.92% | 18 0.00% 99.92% | 359 0.07% 99.99% | 34 0.01% 100.00% | 6 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.RMW_Read.latency_hist::total 494062
system.ruby.RMW_Read.hit_latency_hist::bucket_size 1
system.ruby.RMW_Read.hit_latency_hist::max_bucket 9
-system.ruby.RMW_Read.hit_latency_hist::samples 428816
+system.ruby.RMW_Read.hit_latency_hist::samples 428814
system.ruby.RMW_Read.hit_latency_hist::mean 3
system.ruby.RMW_Read.hit_latency_hist::gmean 3.000000
-system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 428816 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.RMW_Read.hit_latency_hist::total 428816
+system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 428814 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.RMW_Read.hit_latency_hist::total 428814
system.ruby.RMW_Read.miss_latency_hist::bucket_size 16
system.ruby.RMW_Read.miss_latency_hist::max_bucket 159
-system.ruby.RMW_Read.miss_latency_hist::samples 65482
-system.ruby.RMW_Read.miss_latency_hist::mean 24.832519
-system.ruby.RMW_Read.miss_latency_hist::gmean 23.924296
-system.ruby.RMW_Read.miss_latency_hist::stdev 9.747837
-system.ruby.RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 64079 97.86% 97.86% | 2 0.00% 97.86% | 0 0.00% 97.86% | 994 1.52% 99.38% | 20 0.03% 99.41% | 365 0.56% 99.97% | 18 0.03% 99.99% | 3 0.00% 100.00% | 1 0.00% 100.00%
-system.ruby.RMW_Read.miss_latency_hist::total 65482
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+system.ruby.RMW_Read.miss_latency_hist::mean 24.848838
+system.ruby.RMW_Read.miss_latency_hist::gmean 23.931357
+system.ruby.RMW_Read.miss_latency_hist::stdev 9.830212
+system.ruby.RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 63844 97.85% 97.85% | 3 0.00% 97.85% | 0 0.00% 97.85% | 984 1.51% 99.36% | 18 0.03% 99.39% | 359 0.55% 99.94% | 34 0.05% 99.99% | 6 0.01% 100.00% | 0 0.00% 100.00%
+system.ruby.RMW_Read.miss_latency_hist::total 65248
system.ruby.Locked_RMW_Read.latency_hist::bucket_size 16
system.ruby.Locked_RMW_Read.latency_hist::max_bucket 159
-system.ruby.Locked_RMW_Read.latency_hist::samples 339492
-system.ruby.Locked_RMW_Read.latency_hist::mean 5.237555
-system.ruby.Locked_RMW_Read.latency_hist::gmean 3.760998
-system.ruby.Locked_RMW_Read.latency_hist::stdev 6.749704
-system.ruby.Locked_RMW_Read.latency_hist | 301225 88.73% 88.73% | 37910 11.17% 99.89% | 7 0.00% 99.90% | 0 0.00% 99.90% | 190 0.06% 99.95% | 1 0.00% 99.95% | 148 0.04% 100.00% | 10 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Locked_RMW_Read.latency_hist::total 339492
+system.ruby.Locked_RMW_Read.latency_hist::samples 339611
+system.ruby.Locked_RMW_Read.latency_hist::mean 5.246503
+system.ruby.Locked_RMW_Read.latency_hist::gmean 3.765925
+system.ruby.Locked_RMW_Read.latency_hist::stdev 6.740886
+system.ruby.Locked_RMW_Read.latency_hist | 301082 88.65% 88.65% | 38200 11.25% 99.90% | 5 0.00% 99.90% | 0 0.00% 99.90% | 159 0.05% 99.95% | 4 0.00% 99.95% | 151 0.04% 100.00% | 5 0.00% 100.00% | 4 0.00% 100.00% | 1 0.00% 100.00%
+system.ruby.Locked_RMW_Read.latency_hist::total 339611
system.ruby.Locked_RMW_Read.hit_latency_hist::bucket_size 1
system.ruby.Locked_RMW_Read.hit_latency_hist::max_bucket 9
-system.ruby.Locked_RMW_Read.hit_latency_hist::samples 301225
+system.ruby.Locked_RMW_Read.hit_latency_hist::samples 301082
system.ruby.Locked_RMW_Read.hit_latency_hist::mean 3
system.ruby.Locked_RMW_Read.hit_latency_hist::gmean 3.000000
-system.ruby.Locked_RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 301225 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Locked_RMW_Read.hit_latency_hist::total 301225
+system.ruby.Locked_RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 301082 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size 16
system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket 159
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system.ruby.Locked_RMW_Write.latency_hist::bucket_size 1
system.ruby.Locked_RMW_Write.latency_hist::max_bucket 9
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system.ruby.Locked_RMW_Write.latency_hist::mean 3
system.ruby.Locked_RMW_Write.latency_hist::gmean 3.000000
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system.ruby.Locked_RMW_Write.hit_latency_hist::mean 3
system.ruby.Locked_RMW_Write.hit_latency_hist::gmean 3.000000
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system.ruby.L1Cache_Controller.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00%
system.ruby.L1Cache_Controller.Fwd_GET_INSTR::total 4
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system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00%
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+system.ruby.L1Cache_Controller.SM.Ack_all::total 23271
+system.ruby.L1Cache_Controller.M_I.Ifetch | 2 28.57% 28.57% | 5 71.43% 100.00%
+system.ruby.L1Cache_Controller.M_I.Ifetch::total 7
+system.ruby.L1Cache_Controller.M_I.WB_Ack | 439751 26.14% 26.14% | 1242757 73.86% 100.00%
+system.ruby.L1Cache_Controller.M_I.WB_Ack::total 1682508
+system.ruby.L2Cache_Controller.L1_GET_INSTR 815464 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GETS 1385093 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GETX 432443 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_UPGRADE 21434 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_PUTX 1682508 0.00% 0.00%
+system.ruby.L2Cache_Controller.L2_Replacement 94918 0.00% 0.00%
+system.ruby.L2Cache_Controller.L2_Replacement_clean 11837 0.00% 0.00%
+system.ruby.L2Cache_Controller.Mem_Data 173079 0.00% 0.00%
+system.ruby.L2Cache_Controller.Mem_Ack 108223 0.00% 0.00%
+system.ruby.L2Cache_Controller.WB_Data 22674 0.00% 0.00%
+system.ruby.L2Cache_Controller.WB_Data_clean 2091 0.00% 0.00%
+system.ruby.L2Cache_Controller.Ack 1576 0.00% 0.00%
+system.ruby.L2Cache_Controller.Ack_all 6550 0.00% 0.00%
+system.ruby.L2Cache_Controller.Unblock 24440 0.00% 0.00%
+system.ruby.L2Cache_Controller.Exclusive_Unblock 1731717 0.00% 0.00%
+system.ruby.L2Cache_Controller.MEM_Inv 2936 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 15308 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS 31073 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETX 126698 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 800124 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L1_GETS 82654 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L1_GETX 1871 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L1_UPGRADE 21434 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L2_Replacement 224 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 6241 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.MEM_Inv 2 0.00% 0.00%
system.ruby.L2Cache_Controller.M.L1_GET_INSTR 28 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETS 1245738 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX 279152 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement 94920 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement_clean 6421 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.MEM_Inv 1897 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETS 1246769 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETX 280363 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement 94550 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement_clean 5479 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.MEM_Inv 1319 0.00% 0.00%
system.ruby.L2Cache_Controller.MT.L1_GET_INSTR 4 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L1_GETS 24859 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L1_GETX 23569 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L1_PUTX 1682182 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L2_Replacement 161 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 108 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.MEM_Inv 116 0.00% 0.00%
-system.ruby.L2Cache_Controller.M_I.Mem_Ack 110229 0.00% 0.00%
-system.ruby.L2Cache_Controller.M_I.MEM_Inv 1897 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_I.WB_Data 229 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L1_GETS 24436 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L1_GETX 23510 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L1_PUTX 1682508 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L2_Replacement 144 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 117 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.MEM_Inv 147 0.00% 0.00%
+system.ruby.L2Cache_Controller.M_I.Mem_Ack 108223 0.00% 0.00%
+system.ruby.L2Cache_Controller.M_I.MEM_Inv 1319 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_I.WB_Data 243 0.00% 0.00%
system.ruby.L2Cache_Controller.MT_I.Ack_all 48 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_I.MEM_Inv 116 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.WB_Data 75 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.Ack_all 33 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_I.Ack 1395 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_I.Ack_all 6335 0.00% 0.00%
-system.ruby.L2Cache_Controller.S_I.Ack 271 0.00% 0.00%
-system.ruby.L2Cache_Controller.S_I.Ack_all 271 0.00% 0.00%
-system.ruby.L2Cache_Controller.S_I.MEM_Inv 3 0.00% 0.00%
-system.ruby.L2Cache_Controller.ISS.Mem_Data 32147 0.00% 0.00%
-system.ruby.L2Cache_Controller.IS.Mem_Data 15306 0.00% 0.00%
-system.ruby.L2Cache_Controller.IM.Mem_Data 127448 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS_MB.L1_GETS 111 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 23597 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_MB.L1_GETS 37 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_I.MEM_Inv 147 0.00% 0.00%
+system.ruby.L2Cache_Controller.MCT_I.WB_Data 82 0.00% 0.00%
+system.ruby.L2Cache_Controller.MCT_I.Ack_all 35 0.00% 0.00%
+system.ruby.L2Cache_Controller.I_I.Ack 1350 0.00% 0.00%
+system.ruby.L2Cache_Controller.I_I.Ack_all 6241 0.00% 0.00%
+system.ruby.L2Cache_Controller.S_I.Ack 226 0.00% 0.00%
+system.ruby.L2Cache_Controller.S_I.Ack_all 226 0.00% 0.00%
+system.ruby.L2Cache_Controller.S_I.MEM_Inv 2 0.00% 0.00%
+system.ruby.L2Cache_Controller.ISS.L1_GETS 1 0.00% 0.00%
+system.ruby.L2Cache_Controller.ISS.Mem_Data 31072 0.00% 0.00%
+system.ruby.L2Cache_Controller.IS.Mem_Data 15309 0.00% 0.00%
+system.ruby.L2Cache_Controller.IM.Mem_Data 126698 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS_MB.L1_GETS 118 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 23305 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_MB.L1_GETS 42 0.00% 0.00%
system.ruby.L2Cache_Controller.MT_MB.L1_GETX 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1708054 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IIB.WB_Data 22706 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2155 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IIB.Unblock 2 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IB.WB_Data 2 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_SB.Unblock 24861 0.00% 0.00%
-system.ruby.DMA_Controller.ReadRequest 814 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1708412 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_IIB.WB_Data 22344 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2090 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_IIB.Unblock 6 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_IB.WB_Data 5 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_IB.WB_Data_clean 1 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_SB.Unblock 24434 0.00% 0.00%
+system.ruby.DMA_Controller.ReadRequest 797 0.00% 0.00%
system.ruby.DMA_Controller.WriteRequest 46736 0.00% 0.00%
-system.ruby.DMA_Controller.Data 814 0.00% 0.00%
+system.ruby.DMA_Controller.Data 797 0.00% 0.00%
system.ruby.DMA_Controller.Ack 46736 0.00% 0.00%
-system.ruby.DMA_Controller.READY.ReadRequest 814 0.00% 0.00%
+system.ruby.DMA_Controller.READY.ReadRequest 797 0.00% 0.00%
system.ruby.DMA_Controller.READY.WriteRequest 46736 0.00% 0.00%
-system.ruby.DMA_Controller.BUSY_RD.Data 814 0.00% 0.00%
+system.ruby.DMA_Controller.BUSY_RD.Data 797 0.00% 0.00%
system.ruby.DMA_Controller.BUSY_WR.Ack 46736 0.00% 0.00%
-system.ruby.Directory_Controller.Fetch 174901 0.00% 0.00%
-system.ruby.Directory_Controller.Data 97440 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Data 175364 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Ack 142511 0.00% 0.00%
-system.ruby.Directory_Controller.DMA_READ 814 0.00% 0.00%
+system.ruby.Directory_Controller.Fetch 173079 0.00% 0.00%
+system.ruby.Directory_Controller.Data 96468 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Data 173522 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Ack 142090 0.00% 0.00%
+system.ruby.Directory_Controller.DMA_READ 797 0.00% 0.00%
system.ruby.Directory_Controller.DMA_WRITE 46736 0.00% 0.00%
-system.ruby.Directory_Controller.CleanReplacement 12789 0.00% 0.00%
-system.ruby.Directory_Controller.I.Fetch 174901 0.00% 0.00%
-system.ruby.Directory_Controller.I.DMA_READ 463 0.00% 0.00%
-system.ruby.Directory_Controller.I.DMA_WRITE 45071 0.00% 0.00%
-system.ruby.Directory_Controller.ID.Memory_Data 463 0.00% 0.00%
-system.ruby.Directory_Controller.ID_W.Memory_Ack 45071 0.00% 0.00%
-system.ruby.Directory_Controller.M.Data 95424 0.00% 0.00%
-system.ruby.Directory_Controller.M.DMA_READ 351 0.00% 0.00%
-system.ruby.Directory_Controller.M.DMA_WRITE 1665 0.00% 0.00%
-system.ruby.Directory_Controller.M.CleanReplacement 12789 0.00% 0.00%
-system.ruby.Directory_Controller.IM.Memory_Data 174901 0.00% 0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack 95424 0.00% 0.00%
-system.ruby.Directory_Controller.M_DRD.Data 351 0.00% 0.00%
-system.ruby.Directory_Controller.M_DRDI.Memory_Ack 351 0.00% 0.00%
-system.ruby.Directory_Controller.M_DWR.Data 1665 0.00% 0.00%
-system.ruby.Directory_Controller.M_DWRI.Memory_Ack 1665 0.00% 0.00%
+system.ruby.Directory_Controller.CleanReplacement 11755 0.00% 0.00%
+system.ruby.Directory_Controller.I.Fetch 173079 0.00% 0.00%
+system.ruby.Directory_Controller.I.DMA_READ 443 0.00% 0.00%
+system.ruby.Directory_Controller.I.DMA_WRITE 45622 0.00% 0.00%
+system.ruby.Directory_Controller.ID.Memory_Data 443 0.00% 0.00%
+system.ruby.Directory_Controller.ID_W.Memory_Ack 45622 0.00% 0.00%
+system.ruby.Directory_Controller.M.Data 95000 0.00% 0.00%
+system.ruby.Directory_Controller.M.DMA_READ 354 0.00% 0.00%
+system.ruby.Directory_Controller.M.DMA_WRITE 1114 0.00% 0.00%
+system.ruby.Directory_Controller.M.CleanReplacement 11755 0.00% 0.00%
+system.ruby.Directory_Controller.IM.Memory_Data 173079 0.00% 0.00%
+system.ruby.Directory_Controller.MI.Memory_Ack 95000 0.00% 0.00%
+system.ruby.Directory_Controller.M_DRD.Data 354 0.00% 0.00%
+system.ruby.Directory_Controller.M_DRDI.Memory_Ack 354 0.00% 0.00%
+system.ruby.Directory_Controller.M_DWR.Data 1114 0.00% 0.00%
+system.ruby.Directory_Controller.M_DWRI.Memory_Ack 1114 0.00% 0.00%
---------- End Simulation Statistics ----------
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/system.pc.com_1.terminal
index c7dea2971..cbc69e80a 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/system.pc.com_1.terminal
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/system.pc.com_1.terminal
@@ -4,6 +4,7 @@ BIOS-provided physical RAM map:
BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
BIOS-e820: 000000000009fc00 - 0000000000100000 (reserved)
BIOS-e820: 0000000000100000 - 0000000008000000 (usable)
+ BIOS-e820: 0000000008000000 - 00000000c0000000 (reserved)
BIOS-e820: 00000000ffff0000 - 0000000100000000 (reserved)
end_pfn_map = 1048576
kernel direct mapping tables up to 100000000 @ 8000-d000
@@ -22,9 +23,9 @@ Processor #1
I/O APIC #2 at 0xFEC00000.
Setting APIC routing to flat
Processors: 2
-Allocating PCI resources starting at 10000000 (gap: 8000000:f7ff0000)
+Allocating PCI resources starting at c4000000 (gap: c0000000:3fff0000)
PERCPU: Allocating 34160 bytes of per cpu data
-Built 1 zonelists. Total pages: 30615
+Built 1 zonelists. Total pages: 30613
Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
Initializing CPU#0
PID hash table entries: 512 (order: 9, 4096 bytes)
@@ -35,7 +36,7 @@ console handover: boot [earlyser0] -> real [ttyS0]
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)
Checking aperture...
-Memory: 122004k/131072k available (3699k kernel code, 8516k reserved, 1767k data, 248k init)
+Memory: 121996k/131072k available (3699k kernel code, 8524k reserved, 1767k data, 248k init)
Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
Mount-cache hash table entries: 256
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
@@ -59,6 +60,7 @@ usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
PCI: Probing PCI hardware
+PCI->APIC IRQ transform: 0000:00:04.0[A] -> IRQ 16
PCI-GART: No AMD northbridge found.
NET: Registered protocol family 2
IP route cache hash table entries: 1024 (order: 1, 8192 bytes)
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
index 925d90ad5..2c304759f 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
@@ -75,7 +75,7 @@ type=Bridge
clk_domain=system.clk_domain
delay=50000
eventq_index=0
-ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
+ranges=3221225472:4294901760 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
req_size=16
resp_size=16
master=system.iobus.slave[0]
@@ -114,9 +114,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -353,6 +350,7 @@ do_statistics_insts=true
dtb=system.cpu2.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -405,7 +403,6 @@ switched_out=true
system=system
tracer=system.cpu2.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=
@@ -787,8 +784,8 @@ transition_latency=100000000
[system.e820_table]
type=X86E820Table
-children=entries0 entries1 entries2 entries3
-entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3
+children=entries0 entries1 entries2 entries3 entries4
+entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 system.e820_table.entries4
eventq_index=0
[system.e820_table.entries0]
@@ -814,6 +811,13 @@ size=133169152
[system.e820_table.entries3]
type=X86E820Entry
+addr=134217728
+eventq_index=0
+range_type=2
+size=3087007744
+
+[system.e820_table.entries4]
+type=X86E820Entry
addr=4294901760
eventq_index=0
range_type=2
@@ -862,13 +866,13 @@ version=17
[system.intel_mp_table.base_entries02]
type=X86IntelMPBus
bus_id=0
-bus_type=ISA
+bus_type=PCI
eventq_index=0
[system.intel_mp_table.base_entries03]
type=X86IntelMPBus
bus_id=1
-bus_type=PCI
+bus_type=ISA
eventq_index=0
[system.intel_mp_table.base_entries04]
@@ -878,7 +882,7 @@ dest_io_apic_intin=16
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=1
+source_bus_id=0
source_bus_irq=16
trigger=ConformTrigger
@@ -889,7 +893,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=0
trigger=ConformTrigger
@@ -900,7 +904,7 @@ dest_io_apic_intin=2
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=0
trigger=ConformTrigger
@@ -911,7 +915,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=1
trigger=ConformTrigger
@@ -922,7 +926,7 @@ dest_io_apic_intin=1
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=1
trigger=ConformTrigger
@@ -933,7 +937,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=3
trigger=ConformTrigger
@@ -944,7 +948,7 @@ dest_io_apic_intin=3
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=3
trigger=ConformTrigger
@@ -955,7 +959,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=4
trigger=ConformTrigger
@@ -966,7 +970,7 @@ dest_io_apic_intin=4
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=4
trigger=ConformTrigger
@@ -977,7 +981,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=5
trigger=ConformTrigger
@@ -988,7 +992,7 @@ dest_io_apic_intin=5
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=5
trigger=ConformTrigger
@@ -999,7 +1003,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=6
trigger=ConformTrigger
@@ -1010,7 +1014,7 @@ dest_io_apic_intin=6
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=6
trigger=ConformTrigger
@@ -1021,7 +1025,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=7
trigger=ConformTrigger
@@ -1032,7 +1036,7 @@ dest_io_apic_intin=7
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=7
trigger=ConformTrigger
@@ -1043,7 +1047,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=8
trigger=ConformTrigger
@@ -1054,7 +1058,7 @@ dest_io_apic_intin=8
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=8
trigger=ConformTrigger
@@ -1065,7 +1069,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=9
trigger=ConformTrigger
@@ -1076,7 +1080,7 @@ dest_io_apic_intin=9
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=9
trigger=ConformTrigger
@@ -1087,7 +1091,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=10
trigger=ConformTrigger
@@ -1098,7 +1102,7 @@ dest_io_apic_intin=10
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=10
trigger=ConformTrigger
@@ -1109,7 +1113,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=11
trigger=ConformTrigger
@@ -1120,7 +1124,7 @@ dest_io_apic_intin=11
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=11
trigger=ConformTrigger
@@ -1131,7 +1135,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=12
trigger=ConformTrigger
@@ -1142,7 +1146,7 @@ dest_io_apic_intin=12
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=12
trigger=ConformTrigger
@@ -1153,7 +1157,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=13
trigger=ConformTrigger
@@ -1164,7 +1168,7 @@ dest_io_apic_intin=13
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=13
trigger=ConformTrigger
@@ -1175,7 +1179,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=14
trigger=ConformTrigger
@@ -1186,15 +1190,15 @@ dest_io_apic_intin=14
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=14
trigger=ConformTrigger
[system.intel_mp_table.ext_entries]
type=X86IntelMPBusHierarchy
-bus_id=0
+bus_id=1
eventq_index=0
-parent_bus=1
+parent_bus=0
subtractive_decode=true
[system.intrctrl]
@@ -1203,7 +1207,7 @@ eventq_index=0
sys=system
[system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
@@ -1284,11 +1288,12 @@ sequential_access=false
size=4194304
[system.membus]
-type=CoherentBus
+type=CoherentXBar
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -1533,6 +1538,7 @@ HeaderType=0
InterruptLine=14
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=9223372036854775808
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
@@ -1823,8 +1829,33 @@ pio=system.iobus.master[9]
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -1833,6 +1864,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -1846,19 +1878,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
@@ -1888,10 +1927,11 @@ vendor=
version=
[system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json
index b8b06f12b..3c9f7ff5e 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json
@@ -2,39 +2,20 @@
"name": null,
"sim_quantum": 0,
"system": {
- "bridge": {
- "slave": {
- "peer": "system.membus.master[0]",
- "role": "SLAVE"
- },
- "name": "bridge",
- "req_size": 16,
- "delay": 5.0000000000000004e-08,
- "eventq_index": 0,
- "master": {
- "peer": "system.iobus.slave[0]",
- "role": "MASTER"
- },
- "cxx_class": "Bridge",
- "path": "system.bridge",
- "resp_size": 16,
- "type": "Bridge"
- },
+ "kernel": "/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9",
"l2c": {
- "assoc": 8,
- "mem_side": {
- "peer": "system.membus.slave[2]",
- "role": "MASTER"
- },
- "cpu_side": {
- "peer": "system.toL2Bus.master[0]",
- "role": "SLAVE"
- },
- "name": "l2c",
+ "is_top_level": false,
+ "prefetcher": null,
+ "clk_domain": "system.cpu_clk_domain",
+ "write_buffers": 8,
+ "response_latency": 20,
+ "cxx_class": "BaseCache",
+ "size": 4194304,
"tags": {
"name": "tags",
"eventq_index": 0,
"hit_latency": 20,
+ "clk_domain": "system.cpu_clk_domain",
"sequential_access": false,
"assoc": 8,
"cxx_class": "LRU",
@@ -43,77 +24,56 @@
"type": "LRU",
"size": 4194304
},
- "hit_latency": 20,
- "mshrs": 20,
- "response_latency": 20,
- "is_top_level": false,
- "tgts_per_mshr": 12,
- "sequential_access": false,
+ "system": "system",
"max_miss_count": 0,
"eventq_index": 0,
+ "mem_side": {
+ "peer": "system.membus.slave[2]",
+ "role": "MASTER"
+ },
+ "mshrs": 20,
+ "forward_snoops": true,
+ "hit_latency": 20,
+ "tgts_per_mshr": 12,
+ "addr_ranges": [
+ "0:18446744073709551615"
+ ],
+ "assoc": 8,
"prefetch_on_access": false,
- "cxx_class": "BaseCache",
"path": "system.l2c",
- "write_buffers": 8,
- "two_queue": false,
+ "name": "l2c",
"type": "BaseCache",
- "forward_snoops": true,
- "size": 4194304
+ "sequential_access": false,
+ "cpu_side": {
+ "peer": "system.toL2Bus.master[0]",
+ "role": "SLAVE"
+ },
+ "two_queue": false
},
"kernel_addr_check": true,
- "membus": {
+ "bridge": {
+ "ranges": [
+ "3221225472:4294901760",
+ "9223372036854775808:11529215046068469759",
+ "13835058055282163712:18446744073709551615"
+ ],
"slave": {
- "peer": [
- "system.apicbridge.master",
- "system.system_port",
- "system.l2c.mem_side",
- "system.cpu0.interrupts.int_master",
- "system.iocache.mem_side"
- ],
+ "peer": "system.membus.master[0]",
"role": "SLAVE"
},
- "name": "membus",
- "badaddr_responder": {
- "ret_data8": 255,
- "name": "badaddr_responder",
- "pio": {
- "peer": "system.membus.default",
- "role": "SLAVE"
- },
- "ret_bad_addr": true,
- "pio_latency": 1.0000000000000001e-07,
- "fake_mem": false,
- "pio_size": 8,
- "ret_data32": 4294967295,
- "eventq_index": 0,
- "update_data": false,
- "ret_data64": 18446744073709551615,
- "cxx_class": "IsaFake",
- "path": "system.membus.badaddr_responder",
- "pio_addr": 0,
- "type": "IsaFake",
- "ret_data16": 65535
- },
- "default": {
- "peer": "system.membus.badaddr_responder.pio",
- "role": "MASTER"
- },
- "header_cycles": 1,
- "width": 8,
+ "name": "bridge",
+ "req_size": 16,
+ "clk_domain": "system.clk_domain",
+ "delay": 50000,
"eventq_index": 0,
"master": {
- "peer": [
- "system.bridge.slave",
- "system.cpu0.interrupts.pio",
- "system.cpu0.interrupts.int_slave",
- "system.physmem.port"
- ],
+ "peer": "system.iobus.slave[0]",
"role": "MASTER"
},
- "cxx_class": "CoherentBus",
- "path": "system.membus",
- "type": "CoherentBus",
- "use_default_range": false
+ "cxx_class": "Bridge",
+ "path": "system.bridge",
+ "resp_size": 16,
+ "type": "Bridge"
},
"iobus": {
"slave": {
@@ -129,6 +89,7 @@
"peer": "system.pc.pciconfig.pio",
"role": "MASTER"
},
+ "clk_domain": "system.clk_domain",
"header_cycles": 1,
"width": 8,
"eventq_index": 0,
@@ -156,68 +117,23 @@
],
"role": "MASTER"
},
- "cxx_class": "NoncoherentBus",
+ "cxx_class": "NoncoherentXBar",
"path": "system.iobus",
- "type": "NoncoherentBus",
+ "type": "NoncoherentXBar",
"use_default_range": false
},
- "physmem": [
- {
- "static_frontend_latency": 1e-08,
- "tRFC": 2.6e-07,
- "activation_limit": 4,
- "tWTR": 7.500000000000001e-09,
- "write_low_thresh_perc": 50,
- "channels": 1,
- "write_buffer_size": 64,
- "device_bus_width": 8,
- "write_high_thresh_perc": 85,
- "cxx_class": "DRAMCtrl",
- "null": false,
- "port": {
- "peer": "system.membus.master[3]",
- "role": "SLAVE"
- },
- "in_addr_map": true,
- "tRRD": 6.000000000000001e-09,
- "tRTW": 2.5e-09,
- "max_accesses_per_row": 16,
- "burst_length": 8,
- "tRTP": 7.500000000000001e-09,
- "tWR": 1.5000000000000002e-08,
- "eventq_index": 0,
- "static_backend_latency": 1e-08,
- "banks_per_rank": 8,
- "addr_mapping": "RoRaBaChCo",
- "tRCD": 1.375e-08,
- "type": "DRAMCtrl",
- "min_writes_per_switch": 16,
- "ranks_per_channel": 2,
- "page_policy": "open_adaptive",
- "tCL": 1.375e-08,
- "read_buffer_size": 32,
- "conf_table_reported": true,
- "tCK": 1.25e-09,
- "tRAS": 3.5e-08,
- "tBURST": 5e-09,
- "path": "system.physmem",
- "devices_per_rank": 8,
- "name": "physmem",
- "tXAW": 3.0000000000000004e-08,
- "tREFI": 7.8e-06,
- "mem_sched_policy": "frfcfs",
- "tRP": 1.375e-08,
- "device_rowbuffer_size": 1024
- }
- ],
"apicbridge": {
+ "ranges": [
+ "11529215046068469760:11529215046068473855"
+ ],
"slave": {
"peer": "system.iobus.master[0]",
"role": "SLAVE"
},
"name": "apicbridge",
"req_size": 16,
- "delay": 5.0000000000000004e-08,
+ "clk_domain": "system.clk_domain",
+ "delay": 50000,
"eventq_index": 0,
"master": {
"peer": "system.membus.slave[0]",
@@ -228,23 +144,26 @@
"resp_size": 16,
"type": "Bridge"
},
+ "symbolfile": "",
+ "readfile": "/scratch/nilay/GEM5/gem5/tests/halt.sh",
"intel_mp_table": {
"oem_table_addr": 0,
"name": "intel_mp_table",
"ext_entries": [
{
- "parent_bus": 1,
+ "parent_bus": 0,
"name": "ext_entries",
"type": "X86IntelMPBusHierarchy",
"subtractive_decode": true,
"eventq_index": 0,
"cxx_class": "X86ISA::IntelMP::BusHierarchy",
"path": "system.intel_mp_table.ext_entries",
- "bus_id": 0
+ "bus_id": 1
}
],
- "spec_rev": 4,
+ "oem_id": "",
"eventq_index": 0,
+ "spec_rev": 4,
"base_entries": [
{
"enable": true,
@@ -273,6 +192,7 @@
"id": 1
},
{
+ "bus_type": "PCI",
"name": "base_entries02",
"type": "X86IntelMPBus",
"eventq_index": 0,
@@ -281,6 +201,7 @@
"bus_id": 0
},
{
+ "bus_type": "ISA",
"name": "base_entries03",
"type": "X86IntelMPBus",
"eventq_index": 0,
@@ -295,7 +216,7 @@
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 1,
+ "source_bus_id": 0,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 16,
"path": "system.intel_mp_table.base_entries04",
@@ -309,7 +230,7 @@
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries05",
@@ -323,7 +244,7 @@
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 2,
"path": "system.intel_mp_table.base_entries06",
@@ -337,7 +258,7 @@
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries07",
@@ -351,7 +272,7 @@
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 1,
"path": "system.intel_mp_table.base_entries08",
@@ -365,7 +286,7 @@
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries09",
@@ -379,7 +300,7 @@
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 3,
"path": "system.intel_mp_table.base_entries10",
@@ -393,7 +314,7 @@
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries11",
@@ -407,7 +328,7 @@
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 4,
"path": "system.intel_mp_table.base_entries12",
@@ -421,7 +342,7 @@
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries13",
@@ -435,7 +356,7 @@
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 5,
"path": "system.intel_mp_table.base_entries14",
@@ -449,7 +370,7 @@
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries15",
@@ -463,7 +384,7 @@
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 6,
"path": "system.intel_mp_table.base_entries16",
@@ -477,7 +398,7 @@
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries17",
@@ -491,7 +412,7 @@
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 7,
"path": "system.intel_mp_table.base_entries18",
@@ -505,7 +426,7 @@
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries19",
@@ -519,7 +440,7 @@
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 8,
"path": "system.intel_mp_table.base_entries20",
@@ -533,7 +454,7 @@
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries21",
@@ -547,7 +468,7 @@
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 9,
"path": "system.intel_mp_table.base_entries22",
@@ -561,7 +482,7 @@
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries23",
@@ -575,7 +496,7 @@
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 10,
"path": "system.intel_mp_table.base_entries24",
@@ -589,7 +510,7 @@
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries25",
@@ -603,7 +524,7 @@
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 11,
"path": "system.intel_mp_table.base_entries26",
@@ -617,7 +538,7 @@
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries27",
@@ -631,7 +552,7 @@
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 12,
"path": "system.intel_mp_table.base_entries28",
@@ -645,7 +566,7 @@
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries29",
@@ -659,7 +580,7 @@
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 13,
"path": "system.intel_mp_table.base_entries30",
@@ -673,7 +594,7 @@
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries31",
@@ -687,7 +608,7 @@
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 14,
"path": "system.intel_mp_table.base_entries32",
@@ -699,55 +620,183 @@
"path": "system.intel_mp_table",
"type": "X86IntelMPConfigTable",
"local_apic": 4276092928,
- "oem_table_size": 0
+ "oem_table_size": 0,
+ "product_id": ""
},
"cxx_class": "LinuxX86System",
"load_offset": 0,
- "work_end_ckpt_count": 0,
- "smbios_table": {
- "name": "smbios_table",
- "structures": [
- {
- "major": 0,
- "name": "structures",
- "emb_cont_firmware_major": 0,
- "rom_size": 0,
- "starting_addr_segment": 0,
- "emb_cont_firmware_minor": 0,
- "eventq_index": 0,
- "cxx_class": "X86ISA::SMBios::BiosInformation",
- "path": "system.smbios_table.structures",
- "type": "X86SMBiosBiosInformation",
- "minor": 0
- }
+ "iocache": {
+ "is_top_level": true,
+ "prefetcher": null,
+ "clk_domain": "system.clk_domain",
+ "write_buffers": 8,
+ "response_latency": 50,
+ "cxx_class": "BaseCache",
+ "size": 1024,
+ "tags": {
+ "name": "tags",
+ "eventq_index": 0,
+ "hit_latency": 50,
+ "clk_domain": "system.clk_domain",
+ "sequential_access": false,
+ "assoc": 8,
+ "cxx_class": "LRU",
+ "path": "system.iocache.tags",
+ "block_size": 64,
+ "type": "LRU",
+ "size": 1024
+ },
+ "system": "system",
+ "max_miss_count": 0,
+ "eventq_index": 0,
+ "mem_side": {
+ "peer": "system.membus.slave[4]",
+ "role": "MASTER"
+ },
+ "mshrs": 20,
+ "forward_snoops": false,
+ "hit_latency": 50,
+ "tgts_per_mshr": 12,
+ "addr_ranges": [
+ "0:134217727"
],
- "major_version": 2,
- "minor_version": 5,
+ "assoc": 8,
+ "prefetch_on_access": false,
+ "path": "system.iocache",
+ "name": "iocache",
+ "type": "BaseCache",
+ "sequential_access": false,
+ "cpu_side": {
+ "peer": "system.iobus.master[18]",
+ "role": "SLAVE"
+ },
+ "two_queue": false
+ },
+ "intel_mp_pointer": {
+ "imcr_present": true,
+ "name": "intel_mp_pointer",
+ "spec_rev": 4,
"eventq_index": 0,
- "cxx_class": "X86ISA::SMBios::SMBiosTable",
- "path": "system.smbios_table",
- "type": "X86SMBiosSMBiosTable"
+ "cxx_class": "X86ISA::IntelMP::FloatingPointer",
+ "path": "system.intel_mp_pointer",
+ "type": "X86IntelMPFloatingPointer",
+ "default_config": 0
+ },
+ "memories": [
+ "system.physmem"
+ ],
+ "acpi_description_table_pointer": {
+ "name": "acpi_description_table_pointer",
+ "cxx_class": "X86ISA::ACPI::RSDP",
+ "xsdt": {
+ "oem_table_id": "",
+ "name": "xsdt",
+ "entries": [],
+ "creator_revision": 0,
+ "creator_id": "",
+ "oem_id": "",
+ "eventq_index": 0,
+ "cxx_class": "X86ISA::ACPI::XSDT",
+ "path": "system.acpi_description_table_pointer.xsdt",
+ "oem_revision": 0,
+ "type": "X86ACPIXSDT"
+ },
+ "rsdt": null,
+ "eventq_index": 0,
+ "oem_id": "",
+ "path": "system.acpi_description_table_pointer",
+ "type": "X86ACPIRSDP",
+ "revision": 2
},
- "work_begin_ckpt_count": 0,
"clk_domain": {
"name": "clk_domain",
+ "clock": [
+ 1000
+ ],
"init_perf_level": 0,
+ "voltage_domain": "system.voltage_domain",
"eventq_index": 0,
"cxx_class": "SrcClockDomain",
"path": "system.clk_domain",
"type": "SrcClockDomain",
"domain_id": -1
},
+ "mem_ranges": [
+ "0:134217727"
+ ],
+ "membus": {
+ "default": {
+ "peer": "system.membus.badaddr_responder.pio",
+ "role": "MASTER"
+ },
+ "slave": {
+ "peer": [
+ "system.apicbridge.master",
+ "system.system_port",
+ "system.l2c.mem_side",
+ "system.cpu0.interrupts.int_master",
+ "system.iocache.mem_side"
+ ],
+ "role": "SLAVE"
+ },
+ "name": "membus",
+ "badaddr_responder": {
+ "system": "system",
+ "ret_data8": 255,
+ "name": "badaddr_responder",
+ "warn_access": "",
+ "pio": {
+ "peer": "system.membus.default",
+ "role": "SLAVE"
+ },
+ "ret_bad_addr": true,
+ "pio_latency": 100000,
+ "clk_domain": "system.clk_domain",
+ "fake_mem": false,
+ "pio_size": 8,
+ "ret_data32": 4294967295,
+ "eventq_index": 0,
+ "update_data": false,
+ "ret_data64": 18446744073709551615,
+ "cxx_class": "IsaFake",
+ "path": "system.membus.badaddr_responder",
+ "pio_addr": 0,
+ "type": "IsaFake",
+ "ret_data16": 65535
+ },
+ "snoop_filter": null,
+ "clk_domain": "system.clk_domain",
+ "header_cycles": 1,
+ "system": "system",
+ "width": 8,
+ "eventq_index": 0,
+ "master": {
+ "peer": [
+ "system.bridge.slave",
+ "system.cpu0.interrupts.pio",
+ "system.cpu0.interrupts.int_slave",
+ "system.physmem.port"
+ ],
+ "role": "MASTER"
+ },
+ "cxx_class": "CoherentXBar",
+ "path": "system.membus",
+ "type": "CoherentXBar",
+ "use_default_range": false
+ },
"pc": {
"fake_com_4": {
+ "system": "system",
"ret_data8": 255,
"name": "fake_com_4",
+ "warn_access": "",
"pio": {
"peer": "system.iobus.master[16]",
"role": "SLAVE"
},
"ret_bad_addr": false,
- "pio_latency": 1.0000000000000001e-07,
+ "pio_latency": 100000,
+ "clk_domain": "system.clk_domain",
"fake_mem": false,
"pio_size": 8,
"ret_data32": 4294967295,
@@ -767,7 +816,10 @@
"role": "SLAVE"
},
"bus": 0,
- "pio_latency": 3.0000000000000004e-08,
+ "pio_latency": 30000,
+ "clk_domain": "system.clk_domain",
+ "system": "system",
+ "platform": "system.pc",
"eventq_index": 0,
"cxx_class": "PciConfigAll",
"path": "system.pc.pciconfig",
@@ -776,14 +828,17 @@
"size": 16777216
},
"fake_com_2": {
+ "system": "system",
"ret_data8": 255,
"name": "fake_com_2",
+ "warn_access": "",
"pio": {
"peer": "system.iobus.master[14]",
"role": "SLAVE"
},
"ret_bad_addr": false,
- "pio_latency": 1.0000000000000001e-07,
+ "pio_latency": 100000,
+ "clk_domain": "system.clk_domain",
"fake_mem": false,
"pio_size": 8,
"ret_data32": 4294967295,
@@ -801,12 +856,14 @@
"int_lines": [
{
"name": "int_lines0",
+ "source": "system.pc.south_bridge.pic1.output",
"eventq_index": 0,
"sink": {
"name": "sink",
"number": 0,
"eventq_index": 0,
"cxx_class": "X86ISA::IntSinkPin",
+ "device": "system.pc.south_bridge.io_apic",
"path": "system.pc.south_bridge.int_lines0.sink",
"type": "X86IntSinkPin"
},
@@ -816,12 +873,14 @@
},
{
"name": "int_lines1",
+ "source": "system.pc.south_bridge.pic2.output",
"eventq_index": 0,
"sink": {
"name": "sink",
"number": 2,
"eventq_index": 0,
"cxx_class": "X86ISA::IntSinkPin",
+ "device": "system.pc.south_bridge.pic1",
"path": "system.pc.south_bridge.int_lines1.sink",
"type": "X86IntSinkPin"
},
@@ -831,12 +890,14 @@
},
{
"name": "int_lines2",
+ "source": "system.pc.south_bridge.cmos.int_pin",
"eventq_index": 0,
"sink": {
"name": "sink",
"number": 0,
"eventq_index": 0,
"cxx_class": "X86ISA::IntSinkPin",
+ "device": "system.pc.south_bridge.pic2",
"path": "system.pc.south_bridge.int_lines2.sink",
"type": "X86IntSinkPin"
},
@@ -846,12 +907,14 @@
},
{
"name": "int_lines3",
+ "source": "system.pc.south_bridge.pit.int_pin",
"eventq_index": 0,
"sink": {
"name": "sink",
"number": 0,
"eventq_index": 0,
"cxx_class": "X86ISA::IntSinkPin",
+ "device": "system.pc.south_bridge.pic1",
"path": "system.pc.south_bridge.int_lines3.sink",
"type": "X86IntSinkPin"
},
@@ -861,12 +924,14 @@
},
{
"name": "int_lines4",
+ "source": "system.pc.south_bridge.pit.int_pin",
"eventq_index": 0,
"sink": {
"name": "sink",
"number": 2,
"eventq_index": 0,
"cxx_class": "X86ISA::IntSinkPin",
+ "device": "system.pc.south_bridge.io_apic",
"path": "system.pc.south_bridge.int_lines4.sink",
"type": "X86IntSinkPin"
},
@@ -876,12 +941,14 @@
},
{
"name": "int_lines5",
+ "source": "system.pc.south_bridge.keyboard.keyboard_int_pin",
"eventq_index": 0,
"sink": {
"name": "sink",
"number": 1,
"eventq_index": 0,
"cxx_class": "X86ISA::IntSinkPin",
+ "device": "system.pc.south_bridge.io_apic",
"path": "system.pc.south_bridge.int_lines5.sink",
"type": "X86IntSinkPin"
},
@@ -891,12 +958,14 @@
},
{
"name": "int_lines6",
+ "source": "system.pc.south_bridge.keyboard.mouse_int_pin",
"eventq_index": 0,
"sink": {
"name": "sink",
"number": 12,
"eventq_index": 0,
"cxx_class": "X86ISA::IntSinkPin",
+ "device": "system.pc.south_bridge.io_apic",
"path": "system.pc.south_bridge.int_lines6.sink",
"type": "X86IntSinkPin"
},
@@ -912,14 +981,18 @@
"peer": "system.iobus.master[9]",
"role": "SLAVE"
},
- "pio_latency": 1.0000000000000001e-07,
+ "pio_latency": 100000,
+ "clk_domain": "system.clk_domain",
+ "system": "system",
"eventq_index": 0,
"cxx_class": "X86ISA::Speaker",
"path": "system.pc.south_bridge.speaker",
"pio_addr": 9223372036854775905,
- "type": "PcSpeaker"
+ "type": "PcSpeaker",
+ "i8254": "system.pc.south_bridge.pit"
},
"keyboard": {
+ "system": "system",
"command_port": 9223372036854775908,
"name": "keyboard",
"pio": {
@@ -933,7 +1006,8 @@
"name": "mouse_int_pin",
"cxx_class": "X86ISA::IntSourcePin"
},
- "pio_latency": 1.0000000000000001e-07,
+ "pio_latency": 100000,
+ "clk_domain": "system.clk_domain",
"keyboard_int_pin": {
"eventq_index": 0,
"path": "system.pc.south_bridge.keyboard.keyboard_int_pin",
@@ -954,6 +1028,7 @@
"peer": "system.iobus.master[8]",
"role": "SLAVE"
},
+ "pio_latency": 100000,
"int_pin": {
"eventq_index": 0,
"path": "system.pc.south_bridge.pit.int_pin",
@@ -961,7 +1036,8 @@
"name": "int_pin",
"cxx_class": "X86ISA::IntSourcePin"
},
- "pio_latency": 1.0000000000000001e-07,
+ "clk_domain": "system.clk_domain",
+ "system": "system",
"eventq_index": 0,
"cxx_class": "X86ISA::I8254",
"path": "system.pc.south_bridge.pit",
@@ -978,9 +1054,12 @@
"peer": "system.iobus.master[10]",
"role": "SLAVE"
},
- "pio_latency": 1.0000000000000001e-07,
+ "pio_latency": 100000,
+ "clk_domain": "system.clk_domain",
+ "external_int_pic": "system.pc.south_bridge.pic1",
+ "system": "system",
"apic_id": 1,
- "int_latency": 1e-09,
+ "int_latency": 1000,
"eventq_index": 0,
"cxx_class": "X86ISA::I82094AA",
"path": "system.pc.south_bridge.io_apic",
@@ -988,6 +1067,7 @@
"type": "I82094AA"
},
"pic1": {
+ "slave": "system.pc.south_bridge.pic2",
"name": "pic1",
"output": {
"eventq_index": 0,
@@ -1000,7 +1080,9 @@
"peer": "system.iobus.master[6]",
"role": "SLAVE"
},
- "pio_latency": 1.0000000000000001e-07,
+ "pio_latency": 100000,
+ "clk_domain": "system.clk_domain",
+ "system": "system",
"eventq_index": 0,
"mode": "I8259Master",
"cxx_class": "X86ISA::I8259",
@@ -1009,6 +1091,7 @@
"type": "I8259"
},
"pic2": {
+ "slave": null,
"name": "pic2",
"output": {
"eventq_index": 0,
@@ -1021,7 +1104,9 @@
"peer": "system.iobus.master[7]",
"role": "SLAVE"
},
- "pio_latency": 1.0000000000000001e-07,
+ "pio_latency": 100000,
+ "clk_domain": "system.clk_domain",
+ "system": "system",
"eventq_index": 0,
"mode": "I8259Slave",
"cxx_class": "X86ISA::I8259",
@@ -1029,13 +1114,16 @@
"pio_addr": 9223372036854775968,
"type": "I8259"
},
+ "platform": "system.pc",
"dma1": {
"name": "dma1",
"pio": {
"peer": "system.iobus.master[2]",
"role": "SLAVE"
},
- "pio_latency": 1.0000000000000001e-07,
+ "pio_latency": 100000,
+ "clk_domain": "system.clk_domain",
+ "system": "system",
"eventq_index": 0,
"cxx_class": "X86ISA::I8237",
"path": "system.pc.south_bridge.dma1",
@@ -1054,7 +1142,9 @@
"MSIXCAPNextCapability": 0,
"PXCAPLinkCtrl": 0,
"Revision": 0,
- "pio_latency": 3.0000000000000004e-08,
+ "LegacyIOBase": 9223372036854775808,
+ "pio_latency": 30000,
+ "platform": "system.pc",
"PXCAPLinkCap": 0,
"CapabilityPtr": 0,
"MSIXCAPBaseOffset": 0,
@@ -1078,21 +1168,23 @@
"image": {
"read_only": false,
"name": "image",
+ "cxx_class": "CowDiskImage",
+ "eventq_index": 0,
"child": {
"read_only": true,
"name": "child",
"eventq_index": 0,
"cxx_class": "RawDiskImage",
"path": "system.pc.south_bridge.ide.disks0.image.child",
+ "image_file": "/scratch/nilay/GEM5/system/disks/linux-x86.img",
"type": "RawDiskImage"
},
- "eventq_index": 0,
- "cxx_class": "CowDiskImage",
"path": "system.pc.south_bridge.ide.disks0.image",
- "table_size": 65536,
- "type": "CowDiskImage"
+ "image_file": "",
+ "type": "CowDiskImage",
+ "table_size": 65536
},
- "delay": 1e-06,
+ "delay": 1000000,
"eventq_index": 0,
"cxx_class": "IdeDisk",
"path": "system.pc.south_bridge.ide.disks0",
@@ -1104,21 +1196,23 @@
"image": {
"read_only": false,
"name": "image",
+ "cxx_class": "CowDiskImage",
+ "eventq_index": 0,
"child": {
"read_only": true,
"name": "child",
"eventq_index": 0,
"cxx_class": "RawDiskImage",
"path": "system.pc.south_bridge.ide.disks1.image.child",
+ "image_file": "/scratch/nilay/GEM5/system/disks/linux-bigswap2.img",
"type": "RawDiskImage"
},
- "eventq_index": 0,
- "cxx_class": "CowDiskImage",
"path": "system.pc.south_bridge.ide.disks1.image",
- "table_size": 65536,
- "type": "CowDiskImage"
+ "image_file": "",
+ "type": "CowDiskImage",
+ "table_size": 65536
},
- "delay": 1e-06,
+ "delay": 1000000,
"eventq_index": 0,
"cxx_class": "IdeDisk",
"path": "system.pc.south_bridge.ide.disks1",
@@ -1157,6 +1251,7 @@
"MinimumGrant": 0,
"Status": 640,
"BAR0Size": 8,
+ "system": "system",
"name": "ide",
"PXCAPNextCapability": 0,
"eventq_index": 0,
@@ -1171,7 +1266,7 @@
"role": "MASTER"
},
"PMCAPCapId": 0,
- "config_latency": 2e-08,
+ "config_latency": 20000,
"BAR1Size": 3,
"pio": {
"peer": "system.iobus.master[3]",
@@ -1180,6 +1275,7 @@
"pci_dev": 4,
"PMCAPCtrlStatus": 0,
"cxx_class": "IdeController",
+ "clk_domain": "system.clk_domain",
"SubsystemVendorID": 0,
"PMCAPBaseOffset": 0,
"config": {
@@ -1203,6 +1299,8 @@
"peer": "system.iobus.master[1]",
"role": "SLAVE"
},
+ "pio_latency": 100000,
+ "time": "Sun Jan 1 00:00:00 2012",
"int_pin": {
"eventq_index": 0,
"path": "system.pc.south_bridge.cmos.int_pin",
@@ -1210,8 +1308,8 @@
"name": "int_pin",
"cxx_class": "X86ISA::IntSourcePin"
},
- "time": "Sun Jan 1 00:00:00 2012",
- "pio_latency": 1.0000000000000001e-07,
+ "clk_domain": "system.clk_domain",
+ "system": "system",
"eventq_index": 0,
"cxx_class": "X86ISA::Cmos",
"path": "system.pc.south_bridge.cmos",
@@ -1220,14 +1318,17 @@
}
},
"fake_floppy": {
+ "system": "system",
"ret_data8": 255,
"name": "fake_floppy",
+ "warn_access": "",
"pio": {
"peer": "system.iobus.master[17]",
"role": "SLAVE"
},
"ret_bad_addr": false,
- "pio_latency": 1.0000000000000001e-07,
+ "pio_latency": 100000,
+ "clk_domain": "system.clk_domain",
"fake_mem": false,
"pio_size": 2,
"ret_data32": 4294967295,
@@ -1240,23 +1341,29 @@
"type": "IsaFake",
"ret_data16": 65535
},
+ "system": "system",
+ "intrctrl": "system.intrctrl",
"com_1": {
"name": "com_1",
"pio": {
"peer": "system.iobus.master[13]",
"role": "SLAVE"
},
- "pio_latency": 1.0000000000000001e-07,
+ "pio_latency": 100000,
+ "clk_domain": "system.clk_domain",
+ "system": "system",
"terminal": {
"name": "terminal",
"output": true,
"number": 0,
+ "intr_control": "system.intrctrl",
"eventq_index": 0,
"cxx_class": "Terminal",
"path": "system.pc.com_1.terminal",
"type": "Terminal",
"port": 3456
},
+ "platform": "system.pc",
"eventq_index": 0,
"cxx_class": "Uart8250",
"path": "system.pc.com_1",
@@ -1267,14 +1374,17 @@
"cxx_class": "Pc",
"path": "system.pc",
"behind_pci": {
+ "system": "system",
"ret_data8": 255,
"name": "behind_pci",
+ "warn_access": "",
"pio": {
"peer": "system.iobus.master[12]",
"role": "SLAVE"
},
"ret_bad_addr": false,
- "pio_latency": 1.0000000000000001e-07,
+ "pio_latency": 100000,
+ "clk_domain": "system.clk_domain",
"fake_mem": false,
"pio_size": 8,
"ret_data32": 4294967295,
@@ -1289,14 +1399,17 @@
},
"type": "Pc",
"i_dont_exist": {
+ "system": "system",
"ret_data8": 255,
"name": "i_dont_exist",
+ "warn_access": "",
"pio": {
"peer": "system.iobus.master[11]",
"role": "SLAVE"
},
"ret_bad_addr": false,
- "pio_latency": 1.0000000000000001e-07,
+ "pio_latency": 100000,
+ "clk_domain": "system.clk_domain",
"fake_mem": false,
"pio_size": 1,
"ret_data32": 4294967295,
@@ -1310,14 +1423,17 @@
"ret_data16": 65535
},
"fake_com_3": {
+ "system": "system",
"ret_data8": 255,
"name": "fake_com_3",
+ "warn_access": "",
"pio": {
"peer": "system.iobus.master[15]",
"role": "SLAVE"
},
"ret_bad_addr": false,
- "pio_latency": 1.0000000000000001e-07,
+ "pio_latency": 100000,
+ "clk_domain": "system.clk_domain",
"fake_mem": false,
"pio_size": 8,
"ret_data32": 4294967295,
@@ -1368,71 +1484,177 @@
"name": "entries2"
},
{
- "addr": 4294901760,
+ "addr": 134217728,
"range_type": 2,
"eventq_index": 0,
"cxx_class": "X86ISA::E820Entry",
"path": "system.e820_table.entries3",
- "size": 65536,
+ "size": 3087007744,
"type": "X86E820Entry",
"name": "entries3"
+ },
+ {
+ "addr": 4294901760,
+ "range_type": 2,
+ "eventq_index": 0,
+ "cxx_class": "X86ISA::E820Entry",
+ "path": "system.e820_table.entries4",
+ "size": 65536,
+ "type": "X86E820Entry",
+ "name": "entries4"
}
],
"path": "system.e820_table",
"type": "X86E820Table"
},
- "acpi_description_table_pointer": {
- "name": "acpi_description_table_pointer",
- "xsdt": {
- "name": "xsdt",
- "creator_revision": 0,
- "eventq_index": 0,
- "cxx_class": "X86ISA::ACPI::XSDT",
- "path": "system.acpi_description_table_pointer.xsdt",
- "oem_revision": 0,
- "type": "X86ACPIXSDT"
- },
+ "smbios_table": {
+ "name": "smbios_table",
+ "structures": [
+ {
+ "major": 0,
+ "vendor": "",
+ "name": "structures",
+ "characteristics": [],
+ "release_date": "06/08/2008",
+ "cxx_class": "X86ISA::SMBios::BiosInformation",
+ "emb_cont_firmware_major": 0,
+ "rom_size": 0,
+ "starting_addr_segment": 0,
+ "emb_cont_firmware_minor": 0,
+ "version": "",
+ "eventq_index": 0,
+ "characteristic_ext_bytes": [],
+ "path": "system.smbios_table.structures",
+ "type": "X86SMBiosBiosInformation",
+ "minor": 0
+ }
+ ],
+ "major_version": 2,
+ "minor_version": 5,
"eventq_index": 0,
- "cxx_class": "X86ISA::ACPI::RSDP",
- "path": "system.acpi_description_table_pointer",
- "type": "X86ACPIRSDP",
- "revision": 2
+ "cxx_class": "X86ISA::SMBios::SMBiosTable",
+ "path": "system.smbios_table",
+ "type": "X86SMBiosSMBiosTable"
},
"dvfs_handler": {
"enable": false,
"name": "dvfs_handler",
- "transition_latency": 9.999999999999999e-05,
+ "sys_clk_domain": "system.clk_domain",
+ "transition_latency": 100000000,
"eventq_index": 0,
"cxx_class": "DVFSHandler",
+ "domains": [],
"path": "system.dvfs_handler",
"type": "DVFSHandler"
},
"work_end_exit_count": 0,
"type": "LinuxX86System",
"voltage_domain": {
+ "name": "voltage_domain",
"eventq_index": 0,
+ "voltage": [
+ "1.0"
+ ],
+ "cxx_class": "VoltageDomain",
"path": "system.voltage_domain",
- "type": "VoltageDomain",
- "name": "voltage_domain",
- "cxx_class": "VoltageDomain"
+ "type": "VoltageDomain"
},
"cache_line_size": 64,
- "intel_mp_pointer": {
- "imcr_present": true,
- "name": "intel_mp_pointer",
- "spec_rev": 4,
- "eventq_index": 0,
- "cxx_class": "X86ISA::IntelMP::FloatingPointer",
- "path": "system.intel_mp_pointer",
- "type": "X86IntelMPFloatingPointer",
- "default_config": 0
- },
+ "boot_osflags": "earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1",
+ "physmem": [
+ {
+ "static_frontend_latency": 10000,
+ "tRFC": 260000,
+ "activation_limit": 4,
+ "in_addr_map": true,
+ "IDD3N2": "0.0",
+ "tWTR": 7500,
+ "IDD52": "0.0",
+ "clk_domain": "system.clk_domain",
+ "channels": 1,
+ "write_buffer_size": 64,
+ "device_bus_width": 8,
+ "VDD": "1.5",
+ "write_high_thresh_perc": 85,
+ "cxx_class": "DRAMCtrl",
+ "bank_groups_per_rank": 0,
+ "IDD2N2": "0.0",
+ "port": {
+ "peer": "system.membus.master[3]",
+ "role": "SLAVE"
+ },
+ "tCCD_L": 0,
+ "IDD2N": "0.05",
+ "null": false,
+ "IDD2P1": "0.0",
+ "eventq_index": 0,
+ "tRRD": 6000,
+ "tRTW": 2500,
+ "IDD4R": "0.187",
+ "burst_length": 8,
+ "tRTP": 7500,
+ "IDD4W": "0.165",
+ "tWR": 15000,
+ "banks_per_rank": 8,
+ "devices_per_rank": 8,
+ "IDD2P02": "0.0",
+ "IDD6": "0.0",
+ "IDD5": "0.22",
+ "tRCD": 13750,
+ "type": "DRAMCtrl",
+ "IDD3P02": "0.0",
+ "IDD0": "0.075",
+ "IDD62": "0.0",
+ "min_writes_per_switch": 16,
+ "mem_sched_policy": "frfcfs",
+ "IDD02": "0.0",
+ "IDD2P0": "0.0",
+ "ranks_per_channel": 2,
+ "page_policy": "open_adaptive",
+ "IDD4W2": "0.0",
+ "tCS": 2500,
+ "tCL": 13750,
+ "read_buffer_size": 32,
+ "conf_table_reported": true,
+ "tCK": 1250,
+ "tRAS": 35000,
+ "tRP": 13750,
+ "tBURST": 5000,
+ "path": "system.physmem",
+ "tXP": 0,
+ "tXS": 0,
+ "addr_mapping": "RoRaBaChCo",
+ "IDD3P0": "0.0",
+ "IDD3P1": "0.0",
+ "IDD3N": "0.057",
+ "name": "physmem",
+ "tXSDLL": 0,
+ "tXAW": 30000,
+ "dll": true,
+ "write_low_thresh_perc": 50,
+ "range": "0:134217727",
+ "VDD2": "0.0",
+ "IDD2P12": "0.0",
+ "tRRD_L": 0,
+ "tXPDLL": 0,
+ "IDD4R2": "0.0",
+ "device_rowbuffer_size": 1024,
+ "static_backend_latency": 10000,
+ "max_accesses_per_row": 16,
+ "IDD3P12": "0.0",
+ "tREFI": 7800000
+ }
+ ],
"work_cpus_ckpt_count": 0,
"work_begin_exit_count": 0,
"path": "system",
"cpu_clk_domain": {
"name": "cpu_clk_domain",
+ "clock": [
+ 500
+ ],
"init_perf_level": 0,
+ "voltage_domain": "system.voltage_domain",
"eventq_index": 0,
"cxx_class": "SrcClockDomain",
"path": "system.cpu_clk_domain",
@@ -1450,7 +1672,10 @@
"role": "SLAVE"
},
"name": "toL2Bus",
+ "snoop_filter": null,
+ "clk_domain": "system.cpu_clk_domain",
"header_cycles": 1,
+ "system": "system",
"width": 8,
"eventq_index": 0,
"master": {
@@ -1459,51 +1684,12 @@
],
"role": "MASTER"
},
- "cxx_class": "CoherentBus",
+ "cxx_class": "CoherentXBar",
"path": "system.toL2Bus",
- "type": "CoherentBus",
+ "type": "CoherentXBar",
"use_default_range": false
},
- "iocache": {
- "assoc": 8,
- "mem_side": {
- "peer": "system.membus.slave[4]",
- "role": "MASTER"
- },
- "cpu_side": {
- "peer": "system.iobus.master[18]",
- "role": "SLAVE"
- },
- "name": "iocache",
- "tags": {
- "name": "tags",
- "eventq_index": 0,
- "hit_latency": 50,
- "sequential_access": false,
- "assoc": 8,
- "cxx_class": "LRU",
- "path": "system.iocache.tags",
- "block_size": 64,
- "type": "LRU",
- "size": 1024
- },
- "hit_latency": 50,
- "mshrs": 20,
- "response_latency": 50,
- "is_top_level": true,
- "tgts_per_mshr": 12,
- "sequential_access": false,
- "max_miss_count": 0,
- "eventq_index": 0,
- "prefetch_on_access": false,
- "cxx_class": "BaseCache",
- "path": "system.iocache",
- "write_buffers": 8,
- "two_queue": false,
- "type": "BaseCache",
- "forward_snoops": false,
- "size": 1024
- },
+ "work_end_ckpt_count": 0,
"mem_mode": "atomic",
"name": "system",
"init_param": 0,
@@ -1514,7 +1700,6 @@
"load_addr_mask": 18446744073709551615,
"cpu": [
{
- "simpoint_interval": 100000000,
"do_statistics_insts": true,
"numThreads": 1,
"itb": {
@@ -1523,6 +1708,8 @@
"cxx_class": "X86ISA::TLB",
"walker": {
"name": "walker",
+ "clk_domain": "system.cpu_clk_domain",
+ "system": "system",
"eventq_index": 0,
"cxx_class": "X86ISA::Walker",
"path": "system.cpu0.itb.walker",
@@ -1537,47 +1724,48 @@
"type": "X86TLB",
"size": 64
},
+ "simulate_data_stalls": false,
"function_trace": false,
"do_checkpoint_insts": true,
"cxx_class": "AtomicSimpleCPU",
"max_loads_all_threads": 0,
+ "system": "system",
"apic_clk_domain": {
"name": "apic_clk_domain",
+ "clk_domain": "system.cpu_clk_domain",
"eventq_index": 0,
"cxx_class": "DerivedClockDomain",
"path": "system.cpu0.apic_clk_domain",
"type": "DerivedClockDomain",
"clk_divider": 16
},
- "simpoint_profile": false,
- "simulate_data_stalls": false,
+ "clk_domain": "system.cpu_clk_domain",
"function_trace_start": 0,
"cpu_id": 0,
"width": 1,
+ "checker": null,
"eventq_index": 0,
"do_quiesce": true,
"type": "AtomicSimpleCPU",
"fastmem": false,
- "profile": 0.0,
+ "profile": 0,
"icache_port": {
"peer": "system.cpu0.icache.cpu_side",
"role": "MASTER"
},
"icache": {
- "assoc": 1,
- "mem_side": {
- "peer": "system.toL2Bus.slave[0]",
- "role": "MASTER"
- },
- "cpu_side": {
- "peer": "system.cpu0.icache_port",
- "role": "SLAVE"
- },
- "name": "icache",
+ "is_top_level": true,
+ "prefetcher": null,
+ "clk_domain": "system.cpu_clk_domain",
+ "write_buffers": 8,
+ "response_latency": 2,
+ "cxx_class": "BaseCache",
+ "size": 32768,
"tags": {
"name": "tags",
"eventq_index": 0,
"hit_latency": 2,
+ "clk_domain": "system.cpu_clk_domain",
"sequential_access": false,
"assoc": 1,
"cxx_class": "LRU",
@@ -1586,22 +1774,31 @@
"type": "LRU",
"size": 32768
},
- "hit_latency": 2,
- "mshrs": 4,
- "response_latency": 2,
- "is_top_level": true,
- "tgts_per_mshr": 20,
- "sequential_access": false,
+ "system": "system",
"max_miss_count": 0,
"eventq_index": 0,
+ "mem_side": {
+ "peer": "system.toL2Bus.slave[0]",
+ "role": "MASTER"
+ },
+ "mshrs": 4,
+ "forward_snoops": true,
+ "hit_latency": 2,
+ "tgts_per_mshr": 20,
+ "addr_ranges": [
+ "0:18446744073709551615"
+ ],
+ "assoc": 1,
"prefetch_on_access": false,
- "cxx_class": "BaseCache",
"path": "system.cpu0.icache",
- "write_buffers": 8,
- "two_queue": false,
+ "name": "icache",
"type": "BaseCache",
- "forward_snoops": true,
- "size": 32768
+ "sequential_access": false,
+ "cpu_side": {
+ "peer": "system.cpu0.icache_port",
+ "role": "SLAVE"
+ },
+ "two_queue": false
},
"interrupts": {
"int_master": {
@@ -1613,31 +1810,30 @@
"peer": "system.membus.master[1]",
"role": "SLAVE"
},
- "pio_latency": 1.0000000000000001e-07,
"int_slave": {
"peer": "system.membus.master[2]",
"role": "SLAVE"
},
- "int_latency": 1e-09,
+ "pio_latency": 100000,
+ "clk_domain": "system.cpu0.apic_clk_domain",
+ "system": "system",
+ "int_latency": 1000,
"eventq_index": 0,
"cxx_class": "X86ISA::Interrupts",
"path": "system.cpu0.interrupts",
"pio_addr": 2305843009213693952,
"type": "X86LocalApic"
},
+ "dcache_port": {
+ "peer": "system.cpu0.dcache.cpu_side",
+ "role": "MASTER"
+ },
"socket_id": 0,
"max_insts_all_threads": 0,
"path": "system.cpu0",
- "isa": [
- {
- "eventq_index": 0,
- "path": "system.cpu0.isa",
- "type": "X86ISA",
- "name": "isa",
- "cxx_class": "X86ISA::ISA"
- }
- ],
+ "max_loads_any_thread": 0,
"switched_out": false,
+ "workload": [],
"name": "cpu0",
"dtb": {
"name": "dtb",
@@ -1645,6 +1841,8 @@
"cxx_class": "X86ISA::TLB",
"walker": {
"name": "walker",
+ "clk_domain": "system.cpu_clk_domain",
+ "system": "system",
"eventq_index": 0,
"cxx_class": "X86ISA::Walker",
"path": "system.cpu0.dtb.walker",
@@ -1659,28 +1857,24 @@
"type": "X86TLB",
"size": 64
},
+ "simpoint_start_insts": [],
"max_insts_any_thread": 0,
"simulate_inst_stalls": false,
- "progress_interval": 0.0,
- "dcache_port": {
- "peer": "system.cpu0.dcache.cpu_side",
- "role": "MASTER"
- },
+ "progress_interval": 0,
+ "branchPred": null,
"dcache": {
- "assoc": 4,
- "mem_side": {
- "peer": "system.toL2Bus.slave[1]",
- "role": "MASTER"
- },
- "cpu_side": {
- "peer": "system.cpu0.dcache_port",
- "role": "SLAVE"
- },
- "name": "dcache",
+ "is_top_level": true,
+ "prefetcher": null,
+ "clk_domain": "system.cpu_clk_domain",
+ "write_buffers": 8,
+ "response_latency": 2,
+ "cxx_class": "BaseCache",
+ "size": 32768,
"tags": {
"name": "tags",
"eventq_index": 0,
"hit_latency": 2,
+ "clk_domain": "system.cpu_clk_domain",
"sequential_access": false,
"assoc": 4,
"cxx_class": "LRU",
@@ -1689,24 +1883,41 @@
"type": "LRU",
"size": 32768
},
- "hit_latency": 2,
- "mshrs": 4,
- "response_latency": 2,
- "is_top_level": true,
- "tgts_per_mshr": 20,
- "sequential_access": false,
+ "system": "system",
"max_miss_count": 0,
"eventq_index": 0,
+ "mem_side": {
+ "peer": "system.toL2Bus.slave[1]",
+ "role": "MASTER"
+ },
+ "mshrs": 4,
+ "forward_snoops": true,
+ "hit_latency": 2,
+ "tgts_per_mshr": 20,
+ "addr_ranges": [
+ "0:18446744073709551615"
+ ],
+ "assoc": 4,
"prefetch_on_access": false,
- "cxx_class": "BaseCache",
"path": "system.cpu0.dcache",
- "write_buffers": 8,
- "two_queue": false,
+ "name": "dcache",
"type": "BaseCache",
- "forward_snoops": true,
- "size": 32768
+ "sequential_access": false,
+ "cpu_side": {
+ "peer": "system.cpu0.dcache_port",
+ "role": "SLAVE"
+ },
+ "two_queue": false
},
- "max_loads_any_thread": 0,
+ "isa": [
+ {
+ "eventq_index": 0,
+ "path": "system.cpu0.isa",
+ "type": "X86ISA",
+ "name": "isa",
+ "cxx_class": "X86ISA::ISA"
+ }
+ ],
"tracer": {
"eventq_index": 0,
"path": "system.cpu0.tracer",
@@ -1724,6 +1935,8 @@
"cxx_class": "X86ISA::TLB",
"walker": {
"name": "walker",
+ "clk_domain": "system.cpu_clk_domain",
+ "system": "system",
"eventq_index": 0,
"cxx_class": "X86ISA::Walker",
"path": "system.cpu1.itb.walker",
@@ -1734,29 +1947,26 @@
"type": "X86TLB",
"size": 64
},
+ "system": "system",
"function_trace": false,
"do_checkpoint_insts": true,
"cxx_class": "TimingSimpleCPU",
"max_loads_all_threads": 0,
+ "clk_domain": "system.cpu_clk_domain",
"function_trace_start": 0,
"cpu_id": 0,
+ "checker": null,
"eventq_index": 0,
"do_quiesce": true,
"type": "TimingSimpleCPU",
- "profile": 0.0,
+ "profile": 0,
+ "interrupts": null,
"socket_id": 0,
"max_insts_all_threads": 0,
"path": "system.cpu1",
- "isa": [
- {
- "eventq_index": 0,
- "path": "system.cpu1.isa",
- "type": "X86ISA",
- "name": "isa",
- "cxx_class": "X86ISA::ISA"
- }
- ],
+ "max_loads_any_thread": 0,
"switched_out": true,
+ "workload": [],
"name": "cpu1",
"dtb": {
"name": "dtb",
@@ -1764,6 +1974,8 @@
"cxx_class": "X86ISA::TLB",
"walker": {
"name": "walker",
+ "clk_domain": "system.cpu_clk_domain",
+ "system": "system",
"eventq_index": 0,
"cxx_class": "X86ISA::Walker",
"path": "system.cpu1.dtb.walker",
@@ -1774,9 +1986,19 @@
"type": "X86TLB",
"size": 64
},
+ "simpoint_start_insts": [],
"max_insts_any_thread": 0,
- "progress_interval": 0.0,
- "max_loads_any_thread": 0,
+ "progress_interval": 0,
+ "branchPred": null,
+ "isa": [
+ {
+ "eventq_index": 0,
+ "path": "system.cpu1.isa",
+ "type": "X86ISA",
+ "name": "isa",
+ "cxx_class": "X86ISA::ISA"
+ }
+ ],
"tracer": {
"eventq_index": 0,
"path": "system.cpu1.tracer",
@@ -1788,8 +2010,7 @@
{
"SQEntries": 32,
"smtLSQThreshold": 100,
- "do_statistics_insts": true,
- "dispatchWidth": 8,
+ "fetchTrapLatency": 1,
"iewToRenameDelay": 1,
"itb": {
"name": "itb",
@@ -1797,6 +2018,8 @@
"cxx_class": "X86ISA::TLB",
"walker": {
"name": "walker",
+ "clk_domain": "system.cpu_clk_domain",
+ "system": "system",
"eventq_index": 0,
"cxx_class": "X86ISA::Walker",
"path": "system.cpu2.itb.walker",
@@ -1807,26 +2030,39 @@
"type": "X86TLB",
"size": 64
},
- "wbWidth": 8,
- "squashWidth": 8,
- "forwardComSize": 5,
- "function_trace": false,
- "do_checkpoint_insts": true,
"fetchWidth": 8,
- "cxx_class": "DerivO3CPU",
- "backComSize": 5,
- "switched_out": true,
"max_loads_all_threads": 0,
- "numROBEntries": 192,
- "commitToIEWDelay": 1,
- "commitToDecodeDelay": 1,
- "decodeToRenameDelay": 1,
+ "cpu_id": 0,
"fetchToDecodeDelay": 1,
- "issueWidth": 8,
- "LSQCheckLoads": true,
- "commitToRenameDelay": 1,
"renameToDecodeDelay": 1,
- "wbDepth": 1,
+ "do_quiesce": true,
+ "renameToROBDelay": 1,
+ "max_insts_all_threads": 0,
+ "decodeWidth": 8,
+ "commitToFetchDelay": 1,
+ "needsTSO": true,
+ "smtIQThreshold": 100,
+ "workload": [],
+ "name": "cpu2",
+ "SSITSize": 1024,
+ "activity": 0,
+ "max_loads_any_thread": 0,
+ "tracer": {
+ "eventq_index": 0,
+ "path": "system.cpu2.tracer",
+ "type": "ExeTracer",
+ "name": "tracer",
+ "cxx_class": "Trace::ExeTracer"
+ },
+ "decodeToFetchDelay": 1,
+ "renameWidth": 8,
+ "numThreads": 1,
+ "squashWidth": 8,
+ "function_trace": false,
+ "backComSize": 5,
+ "decodeToRenameDelay": 1,
+ "store_set_clear_period": 250000,
+ "numPhysIntRegs": 256,
"fuPool": {
"name": "fuPool",
"FUList": [
@@ -2266,33 +2502,17 @@
"path": "system.cpu2.fuPool",
"type": "FUPool"
},
- "cachePorts": 200,
- "function_trace_start": 0,
- "cpu_id": 0,
- "store_set_clear_period": 250000,
- "numPhysFloatRegs": 256,
- "eventq_index": 0,
- "smtNumFetchingThreads": 1,
- "numThreads": 1,
- "numPhysIntRegs": 256,
- "do_quiesce": true,
- "type": "DerivO3CPU",
- "isa": [
- {
- "eventq_index": 0,
- "path": "system.cpu2.isa",
- "type": "X86ISA",
- "name": "isa",
- "cxx_class": "X86ISA::ISA"
- }
- ],
+ "socket_id": 0,
+ "renameToFetchDelay": 1,
+ "path": "system.cpu2",
+ "numRobs": 1,
+ "switched_out": true,
+ "smtLSQPolicy": "Partitioned",
+ "fetchBufferSize": 64,
+ "simpoint_start_insts": [],
+ "max_insts_any_thread": 0,
"smtROBThreshold": 100,
- "profile": 0.0,
- "renameToROBDelay": 1,
- "commitToFetchDelay": 1,
- "fetchTrapLatency": 1,
- "progress_interval": 0.0,
- "commitWidth": 8,
+ "numIQEntries": 64,
"branchPred": {
"choiceCtrBits": 2,
"name": "branchPred",
@@ -2309,32 +2529,47 @@
"path": "system.cpu2.branchPred",
"localPredictorSize": 2048,
"type": "BranchPredictor",
+ "predType": "tournament",
"RASSize": 16,
"globalPredictorSize": 8192
},
- "socket_id": 0,
- "numPhysCCRegs": 1280,
- "renameToFetchDelay": 1,
- "LSQDepCheckShift": 4,
- "decodeWidth": 8,
- "trapLatency": 13,
- "needsTSO": true,
- "renameWidth": 8,
- "path": "system.cpu2",
- "max_insts_all_threads": 0,
- "max_loads_any_thread": 0,
- "numRobs": 1,
- "iewToDecodeDelay": 1,
- "max_insts_any_thread": 0,
+ "LFSTSize": 1024,
+ "isa": [
+ {
+ "eventq_index": 0,
+ "path": "system.cpu2.isa",
+ "type": "X86ISA",
+ "name": "isa",
+ "cxx_class": "X86ISA::ISA"
+ }
+ ],
+ "smtROBPolicy": "Partitioned",
+ "iewToFetchDelay": 1,
+ "do_statistics_insts": true,
+ "dispatchWidth": 8,
+ "commitToDecodeDelay": 1,
+ "smtIQPolicy": "Partitioned",
+ "issueWidth": 8,
+ "LSQCheckLoads": true,
+ "commitToRenameDelay": 1,
+ "cachePorts": 200,
+ "system": "system",
+ "checker": null,
+ "numPhysFloatRegs": 256,
+ "eventq_index": 0,
+ "type": "DerivO3CPU",
+ "wbWidth": 8,
+ "interrupts": null,
+ "smtCommitPolicy": "RoundRobin",
"issueToExecuteDelay": 1,
- "name": "cpu2",
- "fetchBufferSize": 64,
"dtb": {
"name": "dtb",
"eventq_index": 0,
"cxx_class": "X86ISA::TLB",
"walker": {
"name": "walker",
+ "clk_domain": "system.cpu_clk_domain",
+ "system": "system",
"eventq_index": 0,
"cxx_class": "X86ISA::Walker",
"path": "system.cpu2.dtb.walker",
@@ -2345,39 +2580,44 @@
"type": "X86TLB",
"size": 64
},
- "SSITSize": 1024,
- "LQEntries": 32,
- "numIQEntries": 64,
- "activity": 0,
- "LFSTSize": 1024,
+ "numROBEntries": 192,
+ "fetchQueueSize": 32,
"iewToCommitDelay": 1,
+ "smtNumFetchingThreads": 1,
+ "forwardComSize": 5,
+ "do_checkpoint_insts": true,
+ "cxx_class": "DerivO3CPU",
+ "commitToIEWDelay": 1,
+ "commitWidth": 8,
+ "clk_domain": "system.cpu_clk_domain",
+ "function_trace_start": 0,
+ "smtFetchPolicy": "SingleThread",
+ "profile": 0,
+ "LSQDepCheckShift": 4,
+ "trapLatency": 13,
+ "iewToDecodeDelay": 1,
+ "numPhysCCRegs": 1280,
"renameToIEWDelay": 2,
- "iewToFetchDelay": 1,
- "tracer": {
- "eventq_index": 0,
- "path": "system.cpu2.tracer",
- "type": "ExeTracer",
- "name": "tracer",
- "cxx_class": "Trace::ExeTracer"
- },
- "decodeToFetchDelay": 1,
- "smtIQThreshold": 100
+ "progress_interval": 0,
+ "LQEntries": 32
}
],
"intrctrl": {
+ "name": "intrctrl",
+ "sys": "system",
"eventq_index": 0,
+ "cxx_class": "IntrControl",
"path": "system.intrctrl",
- "type": "IntrControl",
- "name": "intrctrl",
- "cxx_class": "IntrControl"
+ "type": "IntrControl"
},
- "num_work_ids": 16,
+ "work_begin_ckpt_count": 0,
+ "work_begin_cpu_id_exit": -1,
"work_item_id": -1,
- "work_begin_cpu_id_exit": -1
+ "num_work_ids": 16
},
- "time_sync_period": 0.1,
+ "time_sync_period": 100000000000,
"eventq_index": 0,
- "time_sync_spin_threshold": 9.999999999999999e-05,
+ "time_sync_spin_threshold": 100000000,
"cxx_class": "Root",
"path": "root",
"time_sync_enable": false,
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
index 9fd6d97ff..e53b3f285 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
@@ -1,150 +1,154 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 5.133872 # Number of seconds simulated
-sim_ticks 5133872107500 # Number of ticks simulated
-final_tick 5133872107500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.137752 # Number of seconds simulated
+sim_ticks 5137751757500 # Number of ticks simulated
+final_tick 5137751757500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 332026 # Simulator instruction rate (inst/s)
-host_op_rate 659988 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 6979227984 # Simulator tick rate (ticks/s)
-host_mem_usage 973372 # Number of bytes of host memory used
-host_seconds 735.59 # Real time elapsed on the host
-sim_insts 244235751 # Number of instructions simulated
-sim_ops 485482573 # Number of ops (including micro ops) simulated
+host_inst_rate 205879 # Simulator instruction rate (inst/s)
+host_op_rate 409313 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4343855741 # Simulator tick rate (ticks/s)
+host_mem_usage 976756 # Number of bytes of host memory used
+host_seconds 1182.76 # Real time elapsed on the host
+sim_insts 243506025 # Number of instructions simulated
+sim_ops 484120527 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 396736 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 5572928 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 164928 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 1639680 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker 2240 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 412864 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data 3220800 # Number of bytes read from this memory
-system.physmem.bytes_read::total 11438848 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 396736 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 164928 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 412864 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 974528 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 6205312 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 475328 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 5564736 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 130048 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 2113344 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker 2688 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 362880 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data 2752000 # Number of bytes read from this memory
+system.physmem.bytes_read::total 11429696 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 475328 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 130048 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 362880 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 968256 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 6180416 # Number of bytes written to this memory
system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9195392 # Number of bytes written to this memory
+system.physmem.bytes_written::total 9170496 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 6199 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 87077 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 2577 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 25620 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker 35 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 6451 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data 50325 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 178732 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 96958 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 7427 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 86949 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 2032 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 33021 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker 42 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 5670 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data 43000 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 178589 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 96569 # Number of write requests responded to by this memory
system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 143678 # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide 5523 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 77278 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 1085521 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 32125 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 319385 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker 436 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 80420 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 627363 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2228113 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 77278 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 32125 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 80420 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 189823 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1208700 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::pc.south_bridge.ide 582422 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1791122 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1208700 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 587945 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 77278 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 1085521 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 32125 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 319385 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker 436 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 80420 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 627363 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4019235 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 85451 # Number of read requests accepted
-system.physmem.writeReqs 85019 # Number of write requests accepted
-system.physmem.readBursts 85451 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 85019 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 5457024 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 11840 # Total number of bytes read from write queue
-system.physmem.bytesWritten 5440128 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 5468864 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 5441216 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 185 # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_writes::total 143289 # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide 5518 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 92517 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 1083107 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 12 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 25312 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 411336 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker 523 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 70630 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 535643 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2224649 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 92517 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 25312 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 70630 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 188459 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1202942 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::pc.south_bridge.ide 581982 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1784924 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1202942 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 587501 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 92517 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 1083107 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 12 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 25312 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 411336 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker 523 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 70630 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 535643 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4009573 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 84209 # Number of read requests accepted
+system.physmem.writeReqs 74716 # Number of write requests accepted
+system.physmem.readBursts 84209 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 74716 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 5376960 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 12416 # Total number of bytes read from write queue
+system.physmem.bytesWritten 4781824 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 5389376 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 4781824 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 194 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 868 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 5096 # Per bank write bursts
-system.physmem.perBankRdBursts::1 5035 # Per bank write bursts
-system.physmem.perBankRdBursts::2 5503 # Per bank write bursts
-system.physmem.perBankRdBursts::3 5713 # Per bank write bursts
-system.physmem.perBankRdBursts::4 5011 # Per bank write bursts
-system.physmem.perBankRdBursts::5 4756 # Per bank write bursts
-system.physmem.perBankRdBursts::6 4921 # Per bank write bursts
-system.physmem.perBankRdBursts::7 5413 # Per bank write bursts
-system.physmem.perBankRdBursts::8 5128 # Per bank write bursts
-system.physmem.perBankRdBursts::9 4999 # Per bank write bursts
-system.physmem.perBankRdBursts::10 4701 # Per bank write bursts
-system.physmem.perBankRdBursts::11 5348 # Per bank write bursts
-system.physmem.perBankRdBursts::12 5396 # Per bank write bursts
-system.physmem.perBankRdBursts::13 6167 # Per bank write bursts
-system.physmem.perBankRdBursts::14 6376 # Per bank write bursts
-system.physmem.perBankRdBursts::15 5703 # Per bank write bursts
-system.physmem.perBankWrBursts::0 5743 # Per bank write bursts
-system.physmem.perBankWrBursts::1 5870 # Per bank write bursts
-system.physmem.perBankWrBursts::2 5006 # Per bank write bursts
-system.physmem.perBankWrBursts::3 5323 # Per bank write bursts
-system.physmem.perBankWrBursts::4 4689 # Per bank write bursts
-system.physmem.perBankWrBursts::5 4481 # Per bank write bursts
-system.physmem.perBankWrBursts::6 5327 # Per bank write bursts
-system.physmem.perBankWrBursts::7 5300 # Per bank write bursts
-system.physmem.perBankWrBursts::8 5281 # Per bank write bursts
-system.physmem.perBankWrBursts::9 5131 # Per bank write bursts
-system.physmem.perBankWrBursts::10 5421 # Per bank write bursts
-system.physmem.perBankWrBursts::11 5658 # Per bank write bursts
-system.physmem.perBankWrBursts::12 5171 # Per bank write bursts
-system.physmem.perBankWrBursts::13 5597 # Per bank write bursts
-system.physmem.perBankWrBursts::14 5966 # Per bank write bursts
-system.physmem.perBankWrBursts::15 5038 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 805 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 5309 # Per bank write bursts
+system.physmem.perBankRdBursts::1 4164 # Per bank write bursts
+system.physmem.perBankRdBursts::2 4421 # Per bank write bursts
+system.physmem.perBankRdBursts::3 5747 # Per bank write bursts
+system.physmem.perBankRdBursts::4 5625 # Per bank write bursts
+system.physmem.perBankRdBursts::5 4848 # Per bank write bursts
+system.physmem.perBankRdBursts::6 4889 # Per bank write bursts
+system.physmem.perBankRdBursts::7 4803 # Per bank write bursts
+system.physmem.perBankRdBursts::8 5153 # Per bank write bursts
+system.physmem.perBankRdBursts::9 5288 # Per bank write bursts
+system.physmem.perBankRdBursts::10 4847 # Per bank write bursts
+system.physmem.perBankRdBursts::11 5280 # Per bank write bursts
+system.physmem.perBankRdBursts::12 5573 # Per bank write bursts
+system.physmem.perBankRdBursts::13 6540 # Per bank write bursts
+system.physmem.perBankRdBursts::14 6055 # Per bank write bursts
+system.physmem.perBankRdBursts::15 5473 # Per bank write bursts
+system.physmem.perBankWrBursts::0 4689 # Per bank write bursts
+system.physmem.perBankWrBursts::1 3818 # Per bank write bursts
+system.physmem.perBankWrBursts::2 3922 # Per bank write bursts
+system.physmem.perBankWrBursts::3 4862 # Per bank write bursts
+system.physmem.perBankWrBursts::4 4936 # Per bank write bursts
+system.physmem.perBankWrBursts::5 4229 # Per bank write bursts
+system.physmem.perBankWrBursts::6 4848 # Per bank write bursts
+system.physmem.perBankWrBursts::7 4482 # Per bank write bursts
+system.physmem.perBankWrBursts::8 4577 # Per bank write bursts
+system.physmem.perBankWrBursts::9 4853 # Per bank write bursts
+system.physmem.perBankWrBursts::10 4451 # Per bank write bursts
+system.physmem.perBankWrBursts::11 4689 # Per bank write bursts
+system.physmem.perBankWrBursts::12 4903 # Per bank write bursts
+system.physmem.perBankWrBursts::13 5464 # Per bank write bursts
+system.physmem.perBankWrBursts::14 5149 # Per bank write bursts
+system.physmem.perBankWrBursts::15 4844 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 5132871981000 # Total gap between requests
+system.physmem.totGap 5136577016500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 85451 # Read request sizes (log2)
+system.physmem.readPktSize::6 84209 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 85019 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 78990 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 4833 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 949 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 171 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 40 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 74716 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 79815 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 3315 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 428 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 133 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 41 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see
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-system.physmem.bytesPerActivate::1024-1151 3512 8.79% 100.00% # Bytes accessed per row activation
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-system.physmem.rdPerTurnAround::0-255 4095 99.76% 99.76% # Reads before turning the bus around for writes
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-system.physmem.wrPerTurnAround::20-23 49 1.19% 84.85% # Writes before turning the bus around for reads
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 30961.45 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1.06 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 1.06 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1.07 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 1.06 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 29710.99 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1.05 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 0.93 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.05 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 0.93 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 6.94 # Average write queue length when enqueuing
-system.physmem.readRowHits 67077 # Number of row buffer hits during reads
-system.physmem.writeRowHits 63228 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 78.67 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 74.37 # Row buffer hit rate for writes
-system.physmem.avgGap 30110118.97 # Average gap between requests
-system.physmem.pageHitRate 76.52 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 4938526642750 # Time in different power states
-system.physmem.memoryStateTime::REF 171431260000 # Time in different power states
+system.physmem.avgWrQLen 12.74 # Average write queue length when enqueuing
+system.physmem.readRowHits 66918 # Number of row buffer hits during reads
+system.physmem.writeRowHits 54576 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 79.65 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 73.04 # Row buffer hit rate for writes
+system.physmem.avgGap 32320761.47 # Average gap between requests
+system.physmem.pageHitRate 76.54 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 4942660463000 # Time in different power states
+system.physmem.memoryStateTime::REF 171560740000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 23914099250 # Time in different power states
+system.physmem.memoryStateTime::ACT 23528333250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem.actEnergy::0 145575360 # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1 156537360 # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0 79431000 # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1 85412250 # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0 323294400 # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1 341772600 # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0 270468720 # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1 280344240 # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0 335319544560 # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1 335319544560 # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0 122941148535 # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1 123404461065 # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0 2972480080500 # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1 2972073666000 # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0 3431559543075 # Total energy per rank (pJ)
-system.physmem.totalEnergy::1 3431661738075 # Total energy per rank (pJ)
-system.physmem.averagePower::0 668.415487 # Core power per rank (mW)
-system.physmem.averagePower::1 668.435393 # Core power per rank (mW)
-system.membus.trans_dist::ReadReq 5056260 # Transaction distribution
-system.membus.trans_dist::ReadResp 5056258 # Transaction distribution
-system.membus.trans_dist::WriteReq 13754 # Transaction distribution
-system.membus.trans_dist::WriteResp 13754 # Transaction distribution
-system.membus.trans_dist::Writeback 96958 # Transaction distribution
+system.physmem.actEnergy::0 135618840 # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1 145892880 # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0 73998375 # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1 79604250 # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0 310486800 # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1 344830200 # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0 231893280 # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1 252266400 # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0 335572807440 # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1 335572807440 # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0 122729524065 # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1 123386936985 # Energy for active background per rank (pJ)
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+system.physmem.preBackEnergy::1 2974415558250 # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0 3434046565050 # Total energy per rank (pJ)
+system.physmem.totalEnergy::1 3434197896405 # Total energy per rank (pJ)
+system.physmem.averagePower::0 668.395092 # Core power per rank (mW)
+system.physmem.averagePower::1 668.424547 # Core power per rank (mW)
+system.membus.trans_dist::ReadReq 5119571 # Transaction distribution
+system.membus.trans_dist::ReadResp 5119569 # Transaction distribution
+system.membus.trans_dist::WriteReq 13900 # Transaction distribution
+system.membus.trans_dist::WriteResp 13900 # Transaction distribution
+system.membus.trans_dist::Writeback 96569 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 1654 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 1654 # Transaction distribution
-system.membus.trans_dist::ReadExReq 129924 # Transaction distribution
-system.membus.trans_dist::ReadExResp 129924 # Transaction distribution
-system.membus.trans_dist::MessageReq 1664 # Transaction distribution
-system.membus.trans_dist::MessageResp 1664 # Transaction distribution
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+system.membus.trans_dist::ReadExResp 130179 # Transaction distribution
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+system.membus.trans_dist::MessageResp 1687 # Transaction distribution
system.membus.trans_dist::BadAddressError 2 # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3328 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total 3328 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7028524 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3012958 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 456844 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3374 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total 3374 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7129206 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 10498330 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94955 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 94955 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 10596613 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6656 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::total 6656 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3520458 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6025913 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17615808 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 27162179 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3029056 # Cumulative packet size per connected master and slave (bytes)
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-system.membus.pkt_size::total 30197891 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 297 # Total snoops (count)
-system.membus.snoop_fanout::samples 324529 # Request fanout histogram
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+system.membus.pkt_count::total 10723708 # Packet count per connected master and slave (bytes)
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+system.membus.pkt_size_system.apicbridge.master::total 6748 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3570760 # Cumulative packet size per connected master and slave (bytes)
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+system.membus.pkt_size::total 30268557 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 291 # Total snoops (count)
+system.membus.snoop_fanout::samples 323999 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 324529 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 323999 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 324529 # Request fanout histogram
-system.membus.reqLayer0.occupancy 165183000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 323999 # Request fanout histogram
+system.membus.reqLayer0.occupancy 162958500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 315920500 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 314938500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 1960000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 2254000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer3.occupancy 897247500 # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy 804193000 # Layer occupancy (ticks)
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks)
+system.membus.reqLayer4.occupancy 2000 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer0.occupancy 980000 # Layer occupancy (ticks)
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system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 1679098885 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 1664243698 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer4.occupancy 35042997 # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy 28678745 # Layer occupancy (ticks)
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.l2c.tags.replacements 105529 # number of replacements
-system.l2c.tags.tagsinuse 64826.632454 # Cycle average of tags in use
-system.l2c.tags.total_refs 3692969 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 169653 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 21.767779 # Average number of references to valid blocks.
+system.l2c.tags.replacements 104648 # number of replacements
+system.l2c.tags.tagsinuse 64825.327064 # Cycle average of tags in use
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+system.l2c.tags.sampled_refs 168821 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 21.865266 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 50921.041202 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 0.134275 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 1022.158767 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 3887.538850 # Average occupied blocks per requestor
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-system.l2c.tags.occ_blocks::cpu1.data 1563.161522 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker 13.370475 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst 1774.545144 # Average occupied blocks per requestor
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system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy
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system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits
system.l2c.WriteReq_hits::total 2 # number of WriteReq hits
-system.l2c.Writeback_hits::writebacks 1548978 # number of Writeback hits
-system.l2c.Writeback_hits::total 1548978 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 124 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 47 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data 90 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 261 # number of UpgradeReq hits
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-system.l2c.ReadExReq_hits::cpu1.data 37696 # number of ReadExReq hits
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-system.l2c.demand_hits::cpu0.dtb.walker 19672 # number of demand (read+write) hits
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-system.l2c.overall_hits::cpu0.dtb.walker 19672 # number of overall hits
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-system.l2c.overall_hits::total 2447866 # number of overall hits
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-system.l2c.ReadReq_misses::cpu0.data 12693 # number of ReadReq misses
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-system.l2c.ReadReq_misses::cpu1.data 4439 # number of ReadReq misses
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@@ -776,54 +796,54 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
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system.iocache.blocked_cycles::no_mshrs 471 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 39 # number of cycles access was blocked
@@ -832,38 +852,38 @@ system.iocache.avg_blocked_cycles::no_mshrs 12.076923 #
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 46720 # number of fast writes performed
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-system.iocache.overall_mshr_miss_latency::total 93698779 # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.816777 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total 0.816777 # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.607192 # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.607192 # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.816777 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total 0.816777 # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.816777 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total 0.816777 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 126619.971622 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 126619.971622 # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60568.435138 # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60568.435138 # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 126619.971622 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 126619.971622 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 126619.971622 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 126619.971622 # average overall mshr miss latency
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 734 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 734 # number of ReadReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 22056 # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total 22056 # number of WriteInvalidateReq MSHR misses
+system.iocache.demand_mshr_misses::pc.south_bridge.ide 734 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 734 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide 734 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 734 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 93740027 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 93740027 # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 1329860248 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 1329860248 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 93740027 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 93740027 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 93740027 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 93740027 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.811947 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total 0.811947 # mshr miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.472089 # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.472089 # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.811947 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total 0.811947 # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.811947 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total 0.811947 # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 127711.208447 # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60294.715633 # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60294.715633 # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 127711.208447 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 127711.208447 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
@@ -877,567 +897,563 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.toL2Bus.trans_dist::ReadReq 7367165 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 7366643 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 13756 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 13756 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 1548978 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq 28368 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 1663 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 1663 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 296632 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 296632 # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq 7431790 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 7431262 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 13902 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 13902 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 1547592 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 22056 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 1664 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 1664 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 291447 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 291447 # Transaction distribution
system.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1740682 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 14873990 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 71302 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 198555 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 16884529 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 55700736 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213654403 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 264160 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 728920 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 270348219 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 69633 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 4254339 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 3.011195 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.105211 # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1733856 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 14997138 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 72735 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 201275 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 17005004 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 55482624 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213567857 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 271280 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 749120 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 270070881 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 66934 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 4248687 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 3.011209 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.105278 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 4206713 98.88% 98.88% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 47626 1.12% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 4201063 98.88% 98.88% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 47624 1.12% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 4254339 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 5229007845 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 4248687 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 5247340592 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 990000 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 936000 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 2442789502 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 2425844552 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 4872933864 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 4872344858 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 24776404 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 24091410 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 82986153 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 80681637 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 3504325 # Transaction distribution
-system.iobus.trans_dist::ReadResp 3504325 # Transaction distribution
-system.iobus.trans_dist::WriteReq 57563 # Transaction distribution
-system.iobus.trans_dist::WriteResp 39211 # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp 18352 # Transaction distribution
-system.iobus.trans_dist::MessageReq 1664 # Transaction distribution
-system.iobus.trans_dist::MessageResp 1664 # Transaction distribution
+system.iobus.trans_dist::ReadReq 3554542 # Transaction distribution
+system.iobus.trans_dist::ReadResp 3554542 # Transaction distribution
+system.iobus.trans_dist::WriteReq 57685 # Transaction distribution
+system.iobus.trans_dist::WriteResp 33021 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp 24664 # Transaction distribution
+system.iobus.trans_dist::MessageReq 1687 # Transaction distribution
+system.iobus.trans_dist::MessageResp 1687 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 6984892 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1154 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7085054 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1126 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27280 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27782 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 7028524 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95252 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95252 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3328 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3328 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 7127104 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 7129206 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95248 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95248 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3374 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3374 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 7227828 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3492446 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2308 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3542527 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2252 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13640 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13891 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 3520458 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027792 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027792 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6656 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6656 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 6554906 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 2324808 # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::total 3570760 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027776 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027776 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6748 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6748 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 6605284 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 2693792 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 27000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 4000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 4502000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 4846000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy 4000 # Layer occupancy (ticks)
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-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32561.311943 # average WriteReq miss latency
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system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14794.396908 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17074.737561 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17958.421554 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17682.002602 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16136.757886 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17298.147148 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16940.202896 # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 1547592 # number of writebacks
+system.cpu0.dcache.writebacks::total 1547592 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 59 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 355847 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 355906 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1633 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 30941 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 32574 # number of WriteReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data 1692 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data 386788 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 388480 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data 1692 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data 386788 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 388480 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 164832 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 416190 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 581022 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 63496 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 95574 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 159070 # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 64293 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 186824 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total 251117 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data 228328 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data 511764 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 740092 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data 292621 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data 698588 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 991209 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1964999750 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5660700319 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7625700069 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2364352650 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3101755528 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5466108178 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 883443250 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2757990753 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 3641434003 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4329352400 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 8762455847 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 13091808247 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 5212795650 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11520446600 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 16733242250 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30452050000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 32985877000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63437927000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 577982500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 687759500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1265742000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31030032500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33673636500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64703669000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.059119 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.089108 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.045278 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033849 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.032789 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018926 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.858602 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.851553 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.538331 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.048955 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.067467 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.034849 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.061749 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.089507 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.045670 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11921.227371 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13601.240585 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13124.632233 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 37236.245590 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32453.967899 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34362.910530 # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13740.893254 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14762.507777 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14500.945786 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18961.110333 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17122.063777 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17689.433539 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17814.154316 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16491.045652 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16881.648825 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
@@ -1448,376 +1464,376 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.numCycles 2604021576 # number of cpu cycles simulated
+system.cpu1.numCycles 2606022983 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 35901808 # Number of instructions committed
-system.cpu1.committedOps 69778761 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 64893692 # Number of integer alu accesses
+system.cpu1.committedInsts 35939339 # Number of instructions committed
+system.cpu1.committedOps 69774923 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 64844483 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu1.num_func_calls 487874 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 6598396 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 64893692 # number of integer instructions
+system.cpu1.num_func_calls 499287 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 6580388 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 64844483 # number of integer instructions
system.cpu1.num_fp_insts 0 # number of float instructions
-system.cpu1.num_int_register_reads 119938204 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 55974127 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 120226227 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 55826198 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 36929560 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 27415142 # number of times the CC registers were written
-system.cpu1.num_mem_refs 4838216 # number of memory refs
-system.cpu1.num_load_insts 3070311 # Number of load instructions
-system.cpu1.num_store_insts 1767905 # Number of store instructions
-system.cpu1.num_idle_cycles 2474835372.874957 # Number of idle cycles
-system.cpu1.num_busy_cycles 129186203.125043 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.049610 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.950390 # Percentage of idle cycles
-system.cpu1.Branches 7267731 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 34873 0.05% 0.05% # Class of executed instruction
-system.cpu1.op_class::IntAlu 64849393 92.94% 92.99% # Class of executed instruction
-system.cpu1.op_class::IntMult 30804 0.04% 93.03% # Class of executed instruction
-system.cpu1.op_class::IntDiv 25762 0.04% 93.07% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::MemRead 3070311 4.40% 97.47% # Class of executed instruction
-system.cpu1.op_class::MemWrite 1767905 2.53% 100.00% # Class of executed instruction
+system.cpu1.num_cc_register_reads 36586824 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 27309791 # number of times the CC registers were written
+system.cpu1.num_mem_refs 4927873 # number of memory refs
+system.cpu1.num_load_insts 3050339 # Number of load instructions
+system.cpu1.num_store_insts 1877534 # Number of store instructions
+system.cpu1.num_idle_cycles 2477290986.248718 # Number of idle cycles
+system.cpu1.num_busy_cycles 128731996.751282 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.049398 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.950602 # Percentage of idle cycles
+system.cpu1.Branches 7259898 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 35461 0.05% 0.05% # Class of executed instruction
+system.cpu1.op_class::IntAlu 64754697 92.80% 92.86% # Class of executed instruction
+system.cpu1.op_class::IntMult 31756 0.05% 92.90% # Class of executed instruction
+system.cpu1.op_class::IntDiv 25505 0.04% 92.94% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::MemRead 3050339 4.37% 97.31% # Class of executed instruction
+system.cpu1.op_class::MemWrite 1877534 2.69% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 69779048 # Class of executed instruction
+system.cpu1.op_class::total 69775292 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu2.branchPred.lookups 29537500 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 29537500 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 323734 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 26929505 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 26224950 # Number of BTB hits
+system.cpu2.branchPred.lookups 29000272 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 29000272 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 311632 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 26370508 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 25723888 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 97.383706 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 595117 # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect 63666 # Number of incorrect RAS predictions.
-system.cpu2.numCycles 155672620 # number of cpu cycles simulated
+system.cpu2.branchPred.BTBHitPct 97.547943 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 573459 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect 63282 # Number of incorrect RAS predictions.
+system.cpu2.numCycles 153009050 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles 10607285 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 145694636 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 29537500 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 26820067 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 143529975 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 676631 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles 97153 # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.MiscStallCycles 5039 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles 8049 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles 56841 # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles 4424 # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles 421 # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines 3472431 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 167012 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes 3661 # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples 154646852 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.855079 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 3.032629 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles 10521285 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 142969715 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 29000272 # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches 26297347 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles 141031314 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 650011 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles 92984 # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.MiscStallCycles 4408 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles 9006 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles 47091 # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles 2529 # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles 579 # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines 3383247 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 163781 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes 3234 # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples 152033550 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.852472 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 3.031588 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 98720699 63.84% 63.84% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 840447 0.54% 64.38% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 23990695 15.51% 79.89% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 599923 0.39% 80.28% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 812589 0.53% 80.81% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 861055 0.56% 81.36% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 574182 0.37% 81.73% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 718315 0.46% 82.20% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 27528947 17.80% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 97124192 63.88% 63.88% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 819598 0.54% 64.42% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 23594190 15.52% 79.94% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 577537 0.38% 80.32% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 790978 0.52% 80.84% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 823076 0.54% 81.38% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 560198 0.37% 81.75% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 693420 0.46% 82.21% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 27050361 17.79% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 154646852 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.189741 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 0.935904 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 10277789 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 95381782 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 22559618 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 5904125 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 338966 # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts 283871353 # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles 338966 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 12885148 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 76664692 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 4829048 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 25619792 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 14124701 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 282624473 # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents 211024 # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents 6375709 # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents 73879 # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents 5159969 # Number of times rename has blocked due to SQ full
-system.cpu2.rename.RenamedOperands 337473501 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 616062521 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 378507156 # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups 50 # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps 325128635 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 12344864 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 162095 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 163797 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 28599466 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 6606628 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 3716011 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 425441 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 346966 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 280674873 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 430305 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 278581977 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 102725 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 8814114 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 13599788 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved 65362 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 154646852 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 1.801407 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 2.400759 # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total 152033550 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.189533 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 0.934387 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 9712542 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 92934302 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 23280371 # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles 5017317 # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles 325657 # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts 278875678 # Number of instructions handled by decode
+system.cpu2.rename.SquashCycles 325657 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 11857648 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 75889768 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 4419845 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 25919685 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 12857653 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 277706863 # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents 221466 # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents 5888159 # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents 42783 # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents 4808995 # Number of times rename has blocked due to SQ full
+system.cpu2.rename.RenamedOperands 331833488 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 605194394 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 371618079 # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups 36 # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps 320107208 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 11726280 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts 151218 # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts 152719 # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts 24489304 # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads 6338862 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 3553328 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 367719 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 319565 # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded 275826769 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded 413139 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued 273878584 # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued 98557 # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined 8364175 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 12972199 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved 61453 # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples 152033550 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 1.801435 # Number of insts issued each cycle
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system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 91425932 59.12% 59.12% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 5392264 3.49% 62.61% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 3912324 2.53% 65.14% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 4126244 2.67% 67.80% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 21795400 14.09% 81.90% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 3071037 1.99% 83.88% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 24235245 15.67% 99.55% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 469170 0.30% 99.86% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 219236 0.14% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 89826062 59.08% 59.08% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 5325607 3.50% 62.59% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 3883778 2.55% 65.14% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 3618974 2.38% 67.52% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 22318323 14.68% 82.20% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 2568868 1.69% 83.89% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 23837030 15.68% 99.57% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7 450577 0.30% 99.87% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8 204331 0.13% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 154646852 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 152033550 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 2310389 89.01% 89.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 246 0.01% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 223101 8.59% 97.61% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 62004 2.39% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu 1765790 86.71% 86.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult 6 0.00% 86.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv 95 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead 213483 10.48% 97.20% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite 57008 2.80% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass 76436 0.03% 0.03% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu 268041478 96.22% 96.24% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult 58746 0.02% 96.26% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv 49744 0.02% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 6933130 2.49% 98.77% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 3422443 1.23% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass 75484 0.03% 0.03% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu 263736524 96.30% 96.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult 54819 0.02% 96.34% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv 47031 0.02% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead 6686249 2.44% 98.80% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite 3278477 1.20% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 278581977 # Type of FU issued
-system.cpu2.iq.rate 1.789537 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 2595740 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.009318 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 714509188 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 289923619 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 276984093 # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads 82 # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes 98 # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses 18 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 281101244 # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses 37 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 733638 # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total 273878584 # Type of FU issued
+system.cpu2.iq.rate 1.789950 # Inst issue rate
+system.cpu2.iq.fu_busy_cnt 2036382 # FU busy when requested
+system.cpu2.iq.fu_busy_rate 0.007435 # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads 701925596 # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes 284608270 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses 272313229 # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads 61 # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes 68 # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses 275839453 # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses 29 # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads 685704 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 1227908 # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses 6601 # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation 5025 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 667461 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads 1161006 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses 6104 # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation 4803 # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores 634153 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads 754863 # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked 24022 # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads 755552 # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked 21313 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 338966 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 71689555 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 1628683 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 281105178 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 39439 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 6606628 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 3716011 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 250069 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents 194031 # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents 1131651 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents 5025 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 186633 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 188127 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 374760 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 278001109 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 6795315 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 530943 # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles 325657 # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles 70767994 # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles 1741893 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts 276239908 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts 40444 # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts 6338884 # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts 3553328 # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts 236248 # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents 194416 # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents 1250638 # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents 4803 # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect 177191 # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect 184398 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts 361589 # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts 273320009 # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts 6554812 # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts 510377 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
system.cpu2.iew.exec_nop 0 # number of nop insts executed
-system.cpu2.iew.exec_refs 10133053 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 28226522 # Number of branches executed
-system.cpu2.iew.exec_stores 3337738 # Number of stores executed
-system.cpu2.iew.exec_rate 1.785806 # Inst execution rate
-system.cpu2.iew.wb_sent 277806882 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 276984111 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 215977189 # num instructions producing a value
-system.cpu2.iew.wb_consumers 354208085 # num instructions consuming a value
+system.cpu2.iew.exec_refs 9748811 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 27755327 # Number of branches executed
+system.cpu2.iew.exec_stores 3193999 # Number of stores executed
+system.cpu2.iew.exec_rate 1.786300 # Inst execution rate
+system.cpu2.iew.wb_sent 273134840 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 272313245 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 212432379 # num instructions producing a value
+system.cpu2.iew.wb_consumers 348339663 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate 1.779273 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.609747 # average fanout of values written-back
+system.cpu2.iew.wb_rate 1.779720 # insts written-back per cycle
+system.cpu2.iew.wb_fanout 0.609843 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts 9156375 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 364943 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 326343 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 153280377 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 1.774187 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 2.653000 # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts 8691419 # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls 351686 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts 314047 # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples 150733678 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean 1.774964 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 2.652543 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 95267512 62.15% 62.15% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 4211429 2.75% 64.90% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 1288351 0.84% 65.74% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 24928908 16.26% 82.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 992667 0.65% 82.65% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 656859 0.43% 83.08% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 436979 0.29% 83.37% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 23484943 15.32% 98.69% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 2012729 1.31% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 93656646 62.13% 62.13% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 4148238 2.75% 64.89% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 1235888 0.82% 65.71% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 24514613 16.26% 81.97% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4 1002757 0.67% 82.63% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 665638 0.44% 83.08% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 467092 0.31% 83.39% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7 23101150 15.33% 98.71% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8 1941656 1.29% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 153280377 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 137795324 # Number of instructions committed
-system.cpu2.commit.committedOps 271948125 # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total 150733678 # Number of insts commited each cycle
+system.cpu2.commit.committedInsts 135526613 # Number of instructions committed
+system.cpu2.commit.committedOps 267546921 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 8427269 # Number of memory references committed
-system.cpu2.commit.loads 5378719 # Number of loads committed
-system.cpu2.commit.membars 165391 # Number of memory barriers committed
-system.cpu2.commit.branches 27813078 # Number of branches committed
+system.cpu2.commit.refs 8097053 # Number of memory references committed
+system.cpu2.commit.loads 5177878 # Number of loads committed
+system.cpu2.commit.membars 162019 # Number of memory barriers committed
+system.cpu2.commit.branches 27358633 # Number of branches committed
system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 248363308 # Number of committed integer instructions.
-system.cpu2.commit.function_calls 444774 # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass 44974 0.02% 0.02% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu 263371453 96.85% 96.86% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult 56553 0.02% 96.88% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv 47876 0.02% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead 5378719 1.98% 98.88% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite 3048550 1.12% 100.00% # Class of committed instruction
+system.cpu2.commit.int_insts 244351653 # Number of committed integer instructions.
+system.cpu2.commit.function_calls 425746 # Number of function calls committed.
+system.cpu2.commit.op_class_0::No_OpClass 44568 0.02% 0.02% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu 259307312 96.92% 96.94% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult 52493 0.02% 96.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv 45495 0.02% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead 5177878 1.94% 98.91% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite 2919175 1.09% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total 271948125 # Class of committed instruction
-system.cpu2.commit.bw_lim_events 2012729 # number cycles where commit BW limit reached
+system.cpu2.commit.op_class_0::total 267546921 # Class of committed instruction
+system.cpu2.commit.bw_lim_events 1941656 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads 432344700 # The number of ROB reads
-system.cpu2.rob.rob_writes 563581737 # The number of ROB writes
-system.cpu2.timesIdled 114304 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 1025768 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles 4904031691 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 137795324 # Number of Instructions Simulated
-system.cpu2.committedOps 271948125 # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi 1.129738 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 1.129738 # CPI: Total CPI of All Threads
-system.cpu2.ipc 0.885161 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 0.885161 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 370036745 # number of integer regfile reads
-system.cpu2.int_regfile_writes 221903617 # number of integer regfile writes
-system.cpu2.fp_regfile_reads 72874 # number of floating regfile reads
-system.cpu2.fp_regfile_writes 72912 # number of floating regfile writes
-system.cpu2.cc_regfile_reads 140867740 # number of cc regfile reads
-system.cpu2.cc_regfile_writes 108480868 # number of cc regfile writes
-system.cpu2.misc_regfile_reads 90412070 # number of misc regfile reads
-system.cpu2.misc_regfile_writes 138782 # number of misc regfile writes
+system.cpu2.rob.rob_reads 425004820 # The number of ROB reads
+system.cpu2.rob.rob_writes 553782312 # The number of ROB writes
+system.cpu2.timesIdled 113608 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles 975500 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles 4910108147 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts 135526613 # Number of Instructions Simulated
+system.cpu2.committedOps 267546921 # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi 1.128996 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 1.128996 # CPI: Total CPI of All Threads
+system.cpu2.ipc 0.885742 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 0.885742 # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads 363608614 # number of integer regfile reads
+system.cpu2.int_regfile_writes 218247524 # number of integer regfile writes
+system.cpu2.fp_regfile_reads 72984 # number of floating regfile reads
+system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes
+system.cpu2.cc_regfile_reads 138904210 # number of cc regfile reads
+system.cpu2.cc_regfile_writes 106846664 # number of cc regfile writes
+system.cpu2.misc_regfile_reads 88678814 # number of misc regfile reads
+system.cpu2.misc_regfile_writes 129757 # number of misc regfile writes
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal
index 72fbd3738..2c13ee133 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal
@@ -4,6 +4,7 @@ BIOS-provided physical RAM map:
BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
BIOS-e820: 000000000009fc00 - 0000000000100000 (reserved)
BIOS-e820: 0000000000100000 - 0000000008000000 (usable)
+ BIOS-e820: 0000000008000000 - 00000000c0000000 (reserved)
BIOS-e820: 00000000ffff0000 - 0000000100000000 (reserved)
end_pfn_map = 1048576
kernel direct mapping tables up to 100000000 @ 8000-d000
@@ -23,18 +24,18 @@ Setting APIC routing to flat
Processors: 1
swsusp: Registered nosave memory region: 000000000009f000 - 00000000000a0000
swsusp: Registered nosave memory region: 00000000000a0000 - 0000000000100000
-Allocating PCI resources starting at 10000000 (gap: 8000000:f7ff0000)
-Built 1 zonelists. Total pages: 30612
+Allocating PCI resources starting at c4000000 (gap: c0000000:3fff0000)
+Built 1 zonelists. Total pages: 30610
Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
Initializing CPU#0
PID hash table entries: 512 (order: 9, 4096 bytes)
-time.c: Detected 1999.986 MHz processor.
+time.c: Detected 2000.002 MHz processor.
Console: colour dummy device 80x25
console handover: boot [earlyser0] -> real [ttyS0]
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)
Checking aperture...
-Memory: 122184k/131072k available (3742k kernel code, 8464k reserved, 1874k data, 232k init)
+Memory: 122176k/131072k available (3742k kernel code, 8472k reserved, 1874k data, 232k init)
Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
Mount-cache hash table entries: 256
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
@@ -44,7 +45,7 @@ ACPI: Core revision 20070126
ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
ACPI: Unable to load the System Description Tables
Using local APIC timer interrupts.
-result 7812464
+result 7812527
Detected 7.812 MHz APIC timer.
NET: Registered protocol family 16
PCI: Using configuration type 1
@@ -56,6 +57,7 @@ usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
PCI: Probing PCI hardware
+PCI->APIC IRQ transform: 0000:00:04.0[A] -> IRQ 16
PCI-GART: No AMD northbridge found.
NET: Registered protocol family 2
Time: tsc clocksource has been installed.
diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
index ccf2bc154..12828101a 100644
--- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
+++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
@@ -16,10 +16,10 @@ cache_line_size=64
clk_domain=system.clk_domain
eventq_index=0
hypervisor_addr=1099243257856
-hypervisor_bin=/dist/m5/system/binaries/q_new.bin
+hypervisor_bin=/scratch/nilay/GEM5/system/binaries/q_new.bin
hypervisor_desc=system.hypervisor_desc
hypervisor_desc_addr=133446500352
-hypervisor_desc_bin=/dist/m5/system/binaries/1up-hv.bin
+hypervisor_desc_bin=/scratch/nilay/GEM5/system/binaries/1up-hv.bin
init_param=0
kernel=
kernel_addr_check=true
@@ -27,19 +27,19 @@ load_addr_mask=1099511627775
load_offset=0
mem_mode=atomic
mem_ranges=1048576:68157439 2147483648:2415919103
-memories=system.hypervisor_desc system.physmem1 system.partition_desc system.physmem0 system.rom system.nvram
+memories=system.nvram system.physmem1 system.hypervisor_desc system.partition_desc system.physmem0 system.rom
num_work_ids=16
nvram=system.nvram
nvram_addr=133429198848
-nvram_bin=/dist/m5/system/binaries/nvram1
+nvram_bin=/scratch/nilay/GEM5/system/binaries/nvram1
openboot_addr=1099243716608
-openboot_bin=/dist/m5/system/binaries/openboot_new.bin
+openboot_bin=/scratch/nilay/GEM5/system/binaries/openboot_new.bin
partition_desc=system.partition_desc
partition_desc_addr=133445976064
-partition_desc_bin=/dist/m5/system/binaries/1up-md.bin
-readfile=/z/stever/hg/gem5/tests/halt.sh
+partition_desc_bin=/scratch/nilay/GEM5/system/binaries/1up-md.bin
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
reset_addr=1099243192320
-reset_bin=/dist/m5/system/binaries/reset_new.bin
+reset_bin=/scratch/nilay/GEM5/system/binaries/reset_new.bin
rom=system.rom
symbolfile=
work_begin_ckpt_count=0
@@ -160,7 +160,7 @@ table_size=65536
[system.disk0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/m5/system/disks/disk.s10hw2
+image_file=/scratch/nilay/GEM5/system/disks/disk.s10hw2
read_only=true
[system.dvfs_handler]
diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json
index 300aaf6af..f3e5c9bf3 100644
--- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json
+++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json
@@ -471,7 +471,7 @@
}
},
"symbolfile": "",
- "readfile": "/z/stever/hg/gem5/tests/halt.sh",
+ "readfile": "/scratch/nilay/GEM5/gem5/tests/halt.sh",
"hypervisor_addr": 1099243257856,
"mem_ranges": [
"1048576:68157439",
@@ -479,17 +479,17 @@
],
"cxx_class": "SparcSystem",
"load_offset": 0,
- "reset_bin": "/dist/m5/system/binaries/reset_new.bin",
+ "reset_bin": "/scratch/nilay/GEM5/system/binaries/reset_new.bin",
"openboot_addr": 1099243716608,
"work_end_ckpt_count": 0,
"nvram_addr": 133429198848,
"memories": [
- "system.hypervisor_desc",
+ "system.nvram",
"system.physmem1",
+ "system.hypervisor_desc",
"system.partition_desc",
"system.physmem0",
- "system.rom",
- "system.nvram"
+ "system.rom"
],
"work_begin_ckpt_count": 0,
"partition_desc": {
@@ -639,8 +639,8 @@
"type": "DVFSHandler"
},
"work_end_exit_count": 0,
- "hypervisor_desc_bin": "/dist/m5/system/binaries/1up-hv.bin",
- "openboot_bin": "/dist/m5/system/binaries/openboot_new.bin",
+ "hypervisor_desc_bin": "/scratch/nilay/GEM5/system/binaries/1up-hv.bin",
+ "openboot_bin": "/scratch/nilay/GEM5/system/binaries/openboot_new.bin",
"voltage_domain": {
"name": "voltage_domain",
"eventq_index": 0,
@@ -700,7 +700,7 @@
"work_cpus_ckpt_count": 0,
"work_begin_exit_count": 0,
"path": "system",
- "hypervisor_bin": "/dist/m5/system/binaries/q_new.bin",
+ "hypervisor_bin": "/scratch/nilay/GEM5/system/binaries/q_new.bin",
"cpu_clk_domain": {
"name": "cpu_clk_domain",
"clock": [
@@ -714,12 +714,12 @@
"type": "SrcClockDomain",
"domain_id": -1
},
- "nvram_bin": "/dist/m5/system/binaries/nvram1",
+ "nvram_bin": "/scratch/nilay/GEM5/system/binaries/nvram1",
"mem_mode": "atomic",
"name": "system",
"init_param": 0,
"type": "SparcSystem",
- "partition_desc_bin": "/dist/m5/system/binaries/1up-md.bin",
+ "partition_desc_bin": "/scratch/nilay/GEM5/system/binaries/1up-md.bin",
"load_addr_mask": 1099511627775,
"cpu": {
"do_statistics_insts": true,
@@ -825,7 +825,7 @@
"eventq_index": 0,
"cxx_class": "RawDiskImage",
"path": "system.disk0.image.child",
- "image_file": "/dist/m5/system/disks/disk.s10hw2",
+ "image_file": "/scratch/nilay/GEM5/system/disks/disk.s10hw2",
"type": "RawDiskImage"
},
"path": "system.disk0.image",
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini
index 68be94d23..04ace1eeb 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini
@@ -730,10 +730,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -763,6 +764,7 @@ ppid=99
simpoint=55300000000
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -781,10 +783,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -793,8 +796,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -803,6 +831,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -816,19 +845,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
index 4a5a11c6e..8fe365c4e 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
@@ -47,10 +47,10 @@ voltage_domain=system.voltage_domain
type=DerivO3CPU
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
LFSTSize=1024
-LQEntries=32
+LQEntries=16
LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
+LSQDepCheckShift=0
+SQEntries=16
SSITSize=1024
activity=0
backComSize=5
@@ -65,19 +65,20 @@ commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-dispatchWidth=8
+decodeToRenameDelay=2
+decodeWidth=3
+dispatchWidth=6
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
-fetchBufferSize=64
-fetchToDecodeDelay=1
+fetchBufferSize=16
+fetchQueueSize=32
+fetchToDecodeDelay=3
fetchTrapLatency=1
-fetchWidth=8
+fetchWidth=3
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
@@ -97,20 +98,20 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
-numIQEntries=64
-numPhysCCRegs=0
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
+numIQEntries=32
+numPhysCCRegs=640
+numPhysFloatRegs=192
+numPhysIntRegs=128
+numROBEntries=40
numRobs=1
numThreads=1
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
-renameToIEWDelay=2
+renameToIEWDelay=1
renameToROBDelay=1
-renameWidth=8
+renameWidth=3
simpoint_start_insts=
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
@@ -128,7 +129,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -136,8 +136,8 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=BranchPredictor
-BTBEntries=4096
-BTBTagSize=16
+BTBEntries=2048
+BTBTagSize=18
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
@@ -149,7 +149,7 @@ localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
+predType=bi-mode
[system.cpu.dcache]
type=BaseCache
@@ -162,17 +162,17 @@ forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=4
+mshrs=6
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
-size=262144
+size=32768
system=system
tags=system.cpu.dcache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
two_queue=false
-write_buffers=8
+write_buffers=16
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@@ -184,7 +184,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=2
sequential_access=false
-size=262144
+size=32768
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@@ -229,14 +229,14 @@ port=system.cpu.toL2Bus.slave[3]
[system.cpu.fuPool]
type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+children=FUList0 FUList1 FUList2 FUList3 FUList4
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
eventq_index=0
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
-count=6
+count=2
eventq_index=0
opList=system.cpu.fuPool.FUList0.opList
@@ -249,10 +249,10 @@ opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
-children=opList0 opList1
-count=2
+children=opList0 opList1 opList2
+count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
@@ -264,275 +264,233 @@ opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
-issueLat=19
+issueLat=12
opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+opLat=12
-[system.cpu.fuPool.FUList2.opList0]
+[system.cpu.fuPool.FUList1.opList2]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=FloatAdd
-opLat=2
+opClass=IprAccess
+opLat=3
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList
+count=1
eventq_index=0
-issueLat=1
-opClass=FloatCmp
-opLat=2
+opList=system.cpu.fuPool.FUList2.opList
-[system.cpu.fuPool.FUList2.opList2]
+[system.cpu.fuPool.FUList2.opList]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=FloatCvt
+opClass=MemRead
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
-children=opList0 opList1 opList2
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
children=opList
-count=0
+count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList
+opList=system.cpu.fuPool.FUList3.opList
-[system.cpu.fuPool.FUList4.opList]
+[system.cpu.fuPool.FUList3.opList]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemRead
-opLat=1
+opClass=MemWrite
+opLat=2
-[system.cpu.fuPool.FUList5]
+[system.cpu.fuPool.FUList4]
type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+count=2
eventq_index=0
-opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
-[system.cpu.fuPool.FUList5.opList00]
+[system.cpu.fuPool.FUList4.opList00]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAdd
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList01]
+[system.cpu.fuPool.FUList4.opList01]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAddAcc
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList02]
+[system.cpu.fuPool.FUList4.opList02]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAlu
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList03]
+[system.cpu.fuPool.FUList4.opList03]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCmp
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList04]
+[system.cpu.fuPool.FUList4.opList04]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCvt
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList05]
+[system.cpu.fuPool.FUList4.opList05]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMisc
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList06]
+[system.cpu.fuPool.FUList4.opList06]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMult
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList07]
+[system.cpu.fuPool.FUList4.opList07]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMultAcc
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList08]
+[system.cpu.fuPool.FUList4.opList08]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShift
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList09]
+[system.cpu.fuPool.FUList4.opList09]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShiftAcc
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList10]
+[system.cpu.fuPool.FUList4.opList10]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdSqrt
-opLat=1
+opLat=9
-[system.cpu.fuPool.FUList5.opList11]
+[system.cpu.fuPool.FUList4.opList11]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAdd
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList12]
+[system.cpu.fuPool.FUList4.opList12]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAlu
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList13]
+[system.cpu.fuPool.FUList4.opList13]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCmp
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList14]
+[system.cpu.fuPool.FUList4.opList14]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCvt
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList15]
+[system.cpu.fuPool.FUList4.opList15]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatDiv
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList16]
+[system.cpu.fuPool.FUList4.opList16]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMisc
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList17]
+[system.cpu.fuPool.FUList4.opList17]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMult
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList18]
+[system.cpu.fuPool.FUList4.opList18]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
-[system.cpu.fuPool.FUList5.opList19]
+[system.cpu.fuPool.FUList4.opList19]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatSqrt
-opLat=1
+opLat=9
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList6.opList
-
-[system.cpu.fuPool.FUList6.opList]
+[system.cpu.fuPool.FUList4.opList20]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemWrite
-opLat=1
+opClass=FloatAdd
+opLat=5
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
+[system.cpu.fuPool.FUList4.opList21]
+type=OpDesc
eventq_index=0
-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+issueLat=1
+opClass=FloatCmp
+opLat=5
-[system.cpu.fuPool.FUList7.opList0]
+[system.cpu.fuPool.FUList4.opList22]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemRead
-opLat=1
+opClass=FloatCvt
+opLat=5
-[system.cpu.fuPool.FUList7.opList1]
+[system.cpu.fuPool.FUList4.opList23]
type=OpDesc
eventq_index=0
-issueLat=1
-opClass=MemWrite
-opLat=1
+issueLat=9
+opClass=FloatDiv
+opLat=9
-[system.cpu.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
+[system.cpu.fuPool.FUList4.opList24]
+type=OpDesc
eventq_index=0
-opList=system.cpu.fuPool.FUList8.opList
+issueLat=33
+opClass=FloatSqrt
+opLat=33
-[system.cpu.fuPool.FUList8.opList]
+[system.cpu.fuPool.FUList4.opList25]
type=OpDesc
eventq_index=0
-issueLat=3
-opClass=IprAccess
-opLat=3
+issueLat=1
+opClass=FloatMult
+opLat=4
[system.cpu.icache]
type=BaseCache
@@ -542,18 +500,18 @@ assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
-hit_latency=2
+hit_latency=1
is_top_level=true
max_miss_count=0
-mshrs=4
+mshrs=2
prefetch_on_access=false
prefetcher=Null
-response_latency=2
+response_latency=1
sequential_access=false
-size=131072
+size=32768
system=system
tags=system.cpu.icache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -565,9 +523,9 @@ assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
-hit_latency=2
+hit_latency=1
sequential_access=false
-size=131072
+size=32768
[system.cpu.interrupts]
type=ArmInterrupts
@@ -645,44 +603,62 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
-children=tags
+children=prefetcher tags
addr_ranges=0:18446744073709551615
-assoc=8
+assoc=16
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
-hit_latency=20
+hit_latency=12
is_top_level=false
max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu.l2cache.prefetcher
+response_latency=12
sequential_access=false
-size=2097152
+size=1048576
system=system
tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
+tgts_per_mshr=8
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
+[system.cpu.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
+type=RandomRepl
+assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
-hit_latency=20
+hit_latency=12
sequential_access=false
-size=2097152
+size=1048576
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -712,6 +688,7 @@ ppid=99
simpoint=55300000000
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -730,10 +707,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -742,8 +720,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -752,6 +755,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -765,19 +769,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
index 1ac296d57..392920ac8 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
@@ -70,9 +70,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -223,6 +220,7 @@ ppid=99
simpoint=55300000000
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -241,10 +239,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
index 091559190..e662df1f5 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
@@ -299,10 +299,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -332,6 +333,7 @@ ppid=99
simpoint=55300000000
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -350,10 +352,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
index 84ab5e292..5a8877655 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -124,6 +121,7 @@ ppid=99
simpoint=55300000000
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -142,10 +140,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
index b0f5cdf9b..e9a50bebb 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
@@ -200,10 +200,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -233,6 +234,7 @@ ppid=99
simpoint=55300000000
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -251,10 +253,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
index 098c34f79..c3e1a1978 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
@@ -74,6 +74,7 @@ do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -126,7 +127,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -614,10 +614,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -647,6 +648,7 @@ ppid=99
simpoint=55300000000
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -665,10 +667,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -677,8 +680,33 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -687,6 +715,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -700,19 +729,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
index d838f1c87..fbecda938 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -158,6 +155,7 @@ ppid=99
simpoint=55300000000
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -176,10 +174,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
index 31f143ff4..1e2ff91f9 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
@@ -234,10 +234,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -267,6 +268,7 @@ ppid=99
simpoint=55300000000
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -285,10 +287,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini
index a5f2c0f8e..956669942 100644
--- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini
@@ -632,10 +632,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -665,6 +666,7 @@ ppid=99
simpoint=114600000000
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -683,10 +685,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -695,8 +698,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -705,6 +733,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -718,19 +747,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini
index 35eb71fc6..2fe2a523a 100644
--- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini
@@ -730,10 +730,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -763,6 +764,7 @@ ppid=99
simpoint=114600000000
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -781,10 +783,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -793,8 +796,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -803,6 +831,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -816,19 +845,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
index 3e9c4c1da..8a55cdea8 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
@@ -47,10 +47,10 @@ voltage_domain=system.voltage_domain
type=DerivO3CPU
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
LFSTSize=1024
-LQEntries=32
+LQEntries=16
LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
+LSQDepCheckShift=0
+SQEntries=16
SSITSize=1024
activity=0
backComSize=5
@@ -65,19 +65,20 @@ commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-dispatchWidth=8
+decodeToRenameDelay=2
+decodeWidth=3
+dispatchWidth=6
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
-fetchBufferSize=64
-fetchToDecodeDelay=1
+fetchBufferSize=16
+fetchQueueSize=32
+fetchToDecodeDelay=3
fetchTrapLatency=1
-fetchWidth=8
+fetchWidth=3
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
@@ -97,20 +98,20 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
-numIQEntries=64
-numPhysCCRegs=0
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
+numIQEntries=32
+numPhysCCRegs=640
+numPhysFloatRegs=192
+numPhysIntRegs=128
+numROBEntries=40
numRobs=1
numThreads=1
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
-renameToIEWDelay=2
+renameToIEWDelay=1
renameToROBDelay=1
-renameWidth=8
+renameWidth=3
simpoint_start_insts=
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
@@ -128,7 +129,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -136,8 +136,8 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=BranchPredictor
-BTBEntries=4096
-BTBTagSize=16
+BTBEntries=2048
+BTBTagSize=18
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
@@ -149,7 +149,7 @@ localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
+predType=bi-mode
[system.cpu.dcache]
type=BaseCache
@@ -162,17 +162,17 @@ forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=4
+mshrs=6
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
-size=262144
+size=32768
system=system
tags=system.cpu.dcache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
two_queue=false
-write_buffers=8
+write_buffers=16
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@@ -184,7 +184,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=2
sequential_access=false
-size=262144
+size=32768
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@@ -229,14 +229,14 @@ port=system.cpu.toL2Bus.slave[3]
[system.cpu.fuPool]
type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+children=FUList0 FUList1 FUList2 FUList3 FUList4
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
eventq_index=0
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
-count=6
+count=2
eventq_index=0
opList=system.cpu.fuPool.FUList0.opList
@@ -249,10 +249,10 @@ opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
-children=opList0 opList1
-count=2
+children=opList0 opList1 opList2
+count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
@@ -264,275 +264,233 @@ opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
-issueLat=19
+issueLat=12
opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+opLat=12
-[system.cpu.fuPool.FUList2.opList0]
+[system.cpu.fuPool.FUList1.opList2]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=FloatAdd
-opLat=2
+opClass=IprAccess
+opLat=3
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList
+count=1
eventq_index=0
-issueLat=1
-opClass=FloatCmp
-opLat=2
+opList=system.cpu.fuPool.FUList2.opList
-[system.cpu.fuPool.FUList2.opList2]
+[system.cpu.fuPool.FUList2.opList]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=FloatCvt
+opClass=MemRead
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
-children=opList0 opList1 opList2
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
children=opList
-count=0
+count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList
+opList=system.cpu.fuPool.FUList3.opList
-[system.cpu.fuPool.FUList4.opList]
+[system.cpu.fuPool.FUList3.opList]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemRead
-opLat=1
+opClass=MemWrite
+opLat=2
-[system.cpu.fuPool.FUList5]
+[system.cpu.fuPool.FUList4]
type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+count=2
eventq_index=0
-opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
-[system.cpu.fuPool.FUList5.opList00]
+[system.cpu.fuPool.FUList4.opList00]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAdd
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList01]
+[system.cpu.fuPool.FUList4.opList01]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAddAcc
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList02]
+[system.cpu.fuPool.FUList4.opList02]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAlu
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList03]
+[system.cpu.fuPool.FUList4.opList03]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCmp
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList04]
+[system.cpu.fuPool.FUList4.opList04]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCvt
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList05]
+[system.cpu.fuPool.FUList4.opList05]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMisc
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList06]
+[system.cpu.fuPool.FUList4.opList06]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMult
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList07]
+[system.cpu.fuPool.FUList4.opList07]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMultAcc
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList08]
+[system.cpu.fuPool.FUList4.opList08]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShift
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList09]
+[system.cpu.fuPool.FUList4.opList09]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShiftAcc
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList10]
+[system.cpu.fuPool.FUList4.opList10]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdSqrt
-opLat=1
+opLat=9
-[system.cpu.fuPool.FUList5.opList11]
+[system.cpu.fuPool.FUList4.opList11]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAdd
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList12]
+[system.cpu.fuPool.FUList4.opList12]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAlu
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList13]
+[system.cpu.fuPool.FUList4.opList13]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCmp
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList14]
+[system.cpu.fuPool.FUList4.opList14]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCvt
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList15]
+[system.cpu.fuPool.FUList4.opList15]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatDiv
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList16]
+[system.cpu.fuPool.FUList4.opList16]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMisc
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList17]
+[system.cpu.fuPool.FUList4.opList17]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMult
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList18]
+[system.cpu.fuPool.FUList4.opList18]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
-[system.cpu.fuPool.FUList5.opList19]
+[system.cpu.fuPool.FUList4.opList19]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatSqrt
-opLat=1
+opLat=9
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList6.opList
-
-[system.cpu.fuPool.FUList6.opList]
+[system.cpu.fuPool.FUList4.opList20]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemWrite
-opLat=1
+opClass=FloatAdd
+opLat=5
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
+[system.cpu.fuPool.FUList4.opList21]
+type=OpDesc
eventq_index=0
-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+issueLat=1
+opClass=FloatCmp
+opLat=5
-[system.cpu.fuPool.FUList7.opList0]
+[system.cpu.fuPool.FUList4.opList22]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemRead
-opLat=1
+opClass=FloatCvt
+opLat=5
-[system.cpu.fuPool.FUList7.opList1]
+[system.cpu.fuPool.FUList4.opList23]
type=OpDesc
eventq_index=0
-issueLat=1
-opClass=MemWrite
-opLat=1
+issueLat=9
+opClass=FloatDiv
+opLat=9
-[system.cpu.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
+[system.cpu.fuPool.FUList4.opList24]
+type=OpDesc
eventq_index=0
-opList=system.cpu.fuPool.FUList8.opList
+issueLat=33
+opClass=FloatSqrt
+opLat=33
-[system.cpu.fuPool.FUList8.opList]
+[system.cpu.fuPool.FUList4.opList25]
type=OpDesc
eventq_index=0
-issueLat=3
-opClass=IprAccess
-opLat=3
+issueLat=1
+opClass=FloatMult
+opLat=4
[system.cpu.icache]
type=BaseCache
@@ -542,18 +500,18 @@ assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
-hit_latency=2
+hit_latency=1
is_top_level=true
max_miss_count=0
-mshrs=4
+mshrs=2
prefetch_on_access=false
prefetcher=Null
-response_latency=2
+response_latency=1
sequential_access=false
-size=131072
+size=32768
system=system
tags=system.cpu.icache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -565,9 +523,9 @@ assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
-hit_latency=2
+hit_latency=1
sequential_access=false
-size=131072
+size=32768
[system.cpu.interrupts]
type=ArmInterrupts
@@ -645,44 +603,62 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
-children=tags
+children=prefetcher tags
addr_ranges=0:18446744073709551615
-assoc=8
+assoc=16
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
-hit_latency=20
+hit_latency=12
is_top_level=false
max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu.l2cache.prefetcher
+response_latency=12
sequential_access=false
-size=2097152
+size=1048576
system=system
tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
+tgts_per_mshr=8
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
+[system.cpu.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
+type=RandomRepl
+assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
-hit_latency=20
+hit_latency=12
sequential_access=false
-size=2097152
+size=1048576
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -712,6 +688,7 @@ ppid=99
simpoint=114600000000
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -730,10 +707,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -742,8 +720,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -752,6 +755,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -765,19 +769,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
index 1b406eef6..0288139dc 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
@@ -70,9 +70,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -223,6 +220,7 @@ ppid=99
simpoint=114600000000
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -241,10 +239,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
index dd4a92786..abc8be573 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
@@ -299,10 +299,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -332,6 +333,7 @@ ppid=99
simpoint=114600000000
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -350,10 +352,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
index 5f45842db..9577cfdf6 100644
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
@@ -74,6 +74,7 @@ do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -126,7 +127,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -614,10 +614,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -647,6 +648,7 @@ ppid=99
simpoint=114600000000
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -665,10 +667,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -677,8 +680,33 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -687,6 +715,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -700,19 +729,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
index 8134f7b0e..156b7eda7 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -158,6 +155,7 @@ ppid=99
simpoint=114600000000
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -176,10 +174,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
index 2b0e6b6be..d1dba8bc2 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
@@ -234,10 +234,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -267,6 +268,7 @@ ppid=99
simpoint=114600000000
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -285,10 +287,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini
index 383c5c9aa..f0acfeb88 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini
@@ -632,10 +632,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -665,6 +666,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -683,10 +685,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -695,8 +698,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -705,6 +733,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -718,19 +747,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
index 536d6ad31..c0739097e 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
@@ -17,6 +17,7 @@ clk_domain=system.clk_domain
eventq_index=0
init_param=0
kernel=
+kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
@@ -73,6 +74,7 @@ do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -125,7 +127,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -580,10 +581,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -603,7 +605,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/eon
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
max_stack_size=67108864
@@ -613,6 +615,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -631,10 +634,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -643,8 +647,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -653,6 +682,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -666,19 +696,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
index 0aab988e5..44bc5cf02 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -125,6 +122,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -143,10 +141,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
index 5569f2848..601735401 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
@@ -201,10 +201,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -234,6 +235,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -252,10 +254,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini
index 3da78afde..c190aab09 100644
--- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini
@@ -730,10 +730,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -763,6 +764,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -781,10 +783,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -793,8 +796,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -803,6 +831,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -816,19 +845,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
index 521f5fb70..a21e90645 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
@@ -47,10 +47,10 @@ voltage_domain=system.voltage_domain
type=DerivO3CPU
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
LFSTSize=1024
-LQEntries=32
+LQEntries=16
LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
+LSQDepCheckShift=0
+SQEntries=16
SSITSize=1024
activity=0
backComSize=5
@@ -65,19 +65,20 @@ commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-dispatchWidth=8
+decodeToRenameDelay=2
+decodeWidth=3
+dispatchWidth=6
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
-fetchBufferSize=64
-fetchToDecodeDelay=1
+fetchBufferSize=16
+fetchQueueSize=32
+fetchToDecodeDelay=3
fetchTrapLatency=1
-fetchWidth=8
+fetchWidth=3
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
@@ -97,20 +98,20 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
-numIQEntries=64
-numPhysCCRegs=0
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
+numIQEntries=32
+numPhysCCRegs=640
+numPhysFloatRegs=192
+numPhysIntRegs=128
+numROBEntries=40
numRobs=1
numThreads=1
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
-renameToIEWDelay=2
+renameToIEWDelay=1
renameToROBDelay=1
-renameWidth=8
+renameWidth=3
simpoint_start_insts=
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
@@ -128,7 +129,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -136,8 +136,8 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=BranchPredictor
-BTBEntries=4096
-BTBTagSize=16
+BTBEntries=2048
+BTBTagSize=18
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
@@ -149,7 +149,7 @@ localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
+predType=bi-mode
[system.cpu.dcache]
type=BaseCache
@@ -162,17 +162,17 @@ forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=4
+mshrs=6
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
-size=262144
+size=32768
system=system
tags=system.cpu.dcache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
two_queue=false
-write_buffers=8
+write_buffers=16
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@@ -184,7 +184,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=2
sequential_access=false
-size=262144
+size=32768
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@@ -229,14 +229,14 @@ port=system.cpu.toL2Bus.slave[3]
[system.cpu.fuPool]
type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+children=FUList0 FUList1 FUList2 FUList3 FUList4
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
eventq_index=0
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
-count=6
+count=2
eventq_index=0
opList=system.cpu.fuPool.FUList0.opList
@@ -249,10 +249,10 @@ opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
-children=opList0 opList1
-count=2
+children=opList0 opList1 opList2
+count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
@@ -264,275 +264,233 @@ opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
-issueLat=19
+issueLat=12
opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+opLat=12
-[system.cpu.fuPool.FUList2.opList0]
+[system.cpu.fuPool.FUList1.opList2]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=FloatAdd
-opLat=2
+opClass=IprAccess
+opLat=3
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList
+count=1
eventq_index=0
-issueLat=1
-opClass=FloatCmp
-opLat=2
+opList=system.cpu.fuPool.FUList2.opList
-[system.cpu.fuPool.FUList2.opList2]
+[system.cpu.fuPool.FUList2.opList]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=FloatCvt
+opClass=MemRead
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
-children=opList0 opList1 opList2
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
children=opList
-count=0
+count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList
+opList=system.cpu.fuPool.FUList3.opList
-[system.cpu.fuPool.FUList4.opList]
+[system.cpu.fuPool.FUList3.opList]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemRead
-opLat=1
+opClass=MemWrite
+opLat=2
-[system.cpu.fuPool.FUList5]
+[system.cpu.fuPool.FUList4]
type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+count=2
eventq_index=0
-opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
-[system.cpu.fuPool.FUList5.opList00]
+[system.cpu.fuPool.FUList4.opList00]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAdd
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList01]
+[system.cpu.fuPool.FUList4.opList01]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAddAcc
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList02]
+[system.cpu.fuPool.FUList4.opList02]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAlu
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList03]
+[system.cpu.fuPool.FUList4.opList03]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCmp
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList04]
+[system.cpu.fuPool.FUList4.opList04]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCvt
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList05]
+[system.cpu.fuPool.FUList4.opList05]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMisc
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList06]
+[system.cpu.fuPool.FUList4.opList06]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMult
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList07]
+[system.cpu.fuPool.FUList4.opList07]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMultAcc
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList08]
+[system.cpu.fuPool.FUList4.opList08]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShift
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList09]
+[system.cpu.fuPool.FUList4.opList09]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShiftAcc
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList10]
+[system.cpu.fuPool.FUList4.opList10]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdSqrt
-opLat=1
+opLat=9
-[system.cpu.fuPool.FUList5.opList11]
+[system.cpu.fuPool.FUList4.opList11]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAdd
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList12]
+[system.cpu.fuPool.FUList4.opList12]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAlu
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList13]
+[system.cpu.fuPool.FUList4.opList13]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCmp
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList14]
+[system.cpu.fuPool.FUList4.opList14]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCvt
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList15]
+[system.cpu.fuPool.FUList4.opList15]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatDiv
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList16]
+[system.cpu.fuPool.FUList4.opList16]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMisc
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList17]
+[system.cpu.fuPool.FUList4.opList17]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMult
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList18]
+[system.cpu.fuPool.FUList4.opList18]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
-[system.cpu.fuPool.FUList5.opList19]
+[system.cpu.fuPool.FUList4.opList19]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatSqrt
-opLat=1
+opLat=9
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList6.opList
-
-[system.cpu.fuPool.FUList6.opList]
+[system.cpu.fuPool.FUList4.opList20]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemWrite
-opLat=1
+opClass=FloatAdd
+opLat=5
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
+[system.cpu.fuPool.FUList4.opList21]
+type=OpDesc
eventq_index=0
-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+issueLat=1
+opClass=FloatCmp
+opLat=5
-[system.cpu.fuPool.FUList7.opList0]
+[system.cpu.fuPool.FUList4.opList22]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemRead
-opLat=1
+opClass=FloatCvt
+opLat=5
-[system.cpu.fuPool.FUList7.opList1]
+[system.cpu.fuPool.FUList4.opList23]
type=OpDesc
eventq_index=0
-issueLat=1
-opClass=MemWrite
-opLat=1
+issueLat=9
+opClass=FloatDiv
+opLat=9
-[system.cpu.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
+[system.cpu.fuPool.FUList4.opList24]
+type=OpDesc
eventq_index=0
-opList=system.cpu.fuPool.FUList8.opList
+issueLat=33
+opClass=FloatSqrt
+opLat=33
-[system.cpu.fuPool.FUList8.opList]
+[system.cpu.fuPool.FUList4.opList25]
type=OpDesc
eventq_index=0
-issueLat=3
-opClass=IprAccess
-opLat=3
+issueLat=1
+opClass=FloatMult
+opLat=4
[system.cpu.icache]
type=BaseCache
@@ -542,18 +500,18 @@ assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
-hit_latency=2
+hit_latency=1
is_top_level=true
max_miss_count=0
-mshrs=4
+mshrs=2
prefetch_on_access=false
prefetcher=Null
-response_latency=2
+response_latency=1
sequential_access=false
-size=131072
+size=32768
system=system
tags=system.cpu.icache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -565,9 +523,9 @@ assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
-hit_latency=2
+hit_latency=1
sequential_access=false
-size=131072
+size=32768
[system.cpu.interrupts]
type=ArmInterrupts
@@ -645,44 +603,62 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
-children=tags
+children=prefetcher tags
addr_ranges=0:18446744073709551615
-assoc=8
+assoc=16
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
-hit_latency=20
+hit_latency=12
is_top_level=false
max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu.l2cache.prefetcher
+response_latency=12
sequential_access=false
-size=2097152
+size=1048576
system=system
tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
+tgts_per_mshr=8
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
+[system.cpu.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
+type=RandomRepl
+assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
-hit_latency=20
+hit_latency=12
sequential_access=false
-size=2097152
+size=1048576
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -712,6 +688,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -730,10 +707,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -742,8 +720,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -752,6 +755,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -765,19 +769,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini
index ea25a257f..a03e92cf3 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini
@@ -70,9 +70,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -223,6 +220,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -241,10 +239,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
index e7e094253..f7026168d 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
@@ -299,10 +299,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -332,6 +333,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -350,10 +352,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini
index acd11e636..503aa08b6 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini
@@ -632,10 +632,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -648,7 +649,7 @@ eventq_index=0
[system.cpu.workload]
type=LiveProcess
-cmd=perlbmk -I. -I lib lgred.makerand.pl
+cmd=perlbmk -I. -I lib mdred.makerand.pl
cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing
egid=100
env=
@@ -665,6 +666,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -683,10 +685,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -695,8 +698,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -705,6 +733,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -718,19 +747,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
index a624ec61c..3d200442c 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
@@ -17,6 +17,7 @@ clk_domain=system.clk_domain
eventq_index=0
init_param=0
kernel=
+kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
@@ -73,6 +74,7 @@ do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -125,7 +127,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -580,10 +581,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -596,14 +598,14 @@ eventq_index=0
[system.cpu.workload]
type=LiveProcess
-cmd=perlbmk -I. -I lib lgred.makerand.pl
+cmd=perlbmk -I. -I lib mdred.makerand.pl
cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
euid=100
eventq_index=0
-executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/perlbmk
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
gid=100
input=cin
max_stack_size=67108864
@@ -613,6 +615,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -631,10 +634,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -643,8 +647,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -653,6 +682,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -666,19 +696,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
index 7c82d017b..02a01f5db 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -108,7 +105,7 @@ eventq_index=0
[system.cpu.workload]
type=LiveProcess
-cmd=perlbmk -I. -I lib lgred.makerand.pl
+cmd=perlbmk -I. -I lib mdred.makerand.pl
cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic
egid=100
env=
@@ -125,6 +122,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -143,10 +141,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
index 354d6da6a..48df53b70 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
@@ -201,10 +201,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -217,7 +218,7 @@ eventq_index=0
[system.cpu.workload]
type=LiveProcess
-cmd=perlbmk -I. -I lib lgred.makerand.pl
+cmd=perlbmk -I. -I lib mdred.makerand.pl
cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing
egid=100
env=
@@ -234,6 +235,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -252,10 +254,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini
index 901264c7e..c01955b00 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini
@@ -730,10 +730,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -746,7 +747,7 @@ eventq_index=0
[system.cpu.workload]
type=LiveProcess
-cmd=perlbmk -I. -I lib lgred.makerand.pl
+cmd=perlbmk -I. -I lib mdred.makerand.pl
cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing
egid=100
env=
@@ -763,6 +764,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -781,10 +783,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -793,8 +796,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -803,6 +831,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -816,19 +845,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
index db65c79ef..3db3f48e9 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
@@ -47,10 +47,10 @@ voltage_domain=system.voltage_domain
type=DerivO3CPU
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
LFSTSize=1024
-LQEntries=32
+LQEntries=16
LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
+LSQDepCheckShift=0
+SQEntries=16
SSITSize=1024
activity=0
backComSize=5
@@ -65,19 +65,20 @@ commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-dispatchWidth=8
+decodeToRenameDelay=2
+decodeWidth=3
+dispatchWidth=6
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
-fetchBufferSize=64
-fetchToDecodeDelay=1
+fetchBufferSize=16
+fetchQueueSize=32
+fetchToDecodeDelay=3
fetchTrapLatency=1
-fetchWidth=8
+fetchWidth=3
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
@@ -97,20 +98,20 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
-numIQEntries=64
-numPhysCCRegs=0
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
+numIQEntries=32
+numPhysCCRegs=640
+numPhysFloatRegs=192
+numPhysIntRegs=128
+numROBEntries=40
numRobs=1
numThreads=1
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
-renameToIEWDelay=2
+renameToIEWDelay=1
renameToROBDelay=1
-renameWidth=8
+renameWidth=3
simpoint_start_insts=
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
@@ -128,7 +129,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -136,8 +136,8 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=BranchPredictor
-BTBEntries=4096
-BTBTagSize=16
+BTBEntries=2048
+BTBTagSize=18
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
@@ -149,7 +149,7 @@ localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
+predType=bi-mode
[system.cpu.dcache]
type=BaseCache
@@ -162,17 +162,17 @@ forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=4
+mshrs=6
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
-size=262144
+size=32768
system=system
tags=system.cpu.dcache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
two_queue=false
-write_buffers=8
+write_buffers=16
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@@ -184,7 +184,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=2
sequential_access=false
-size=262144
+size=32768
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@@ -229,14 +229,14 @@ port=system.cpu.toL2Bus.slave[3]
[system.cpu.fuPool]
type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+children=FUList0 FUList1 FUList2 FUList3 FUList4
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
eventq_index=0
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
-count=6
+count=2
eventq_index=0
opList=system.cpu.fuPool.FUList0.opList
@@ -249,10 +249,10 @@ opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
-children=opList0 opList1
-count=2
+children=opList0 opList1 opList2
+count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
@@ -264,275 +264,233 @@ opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
-issueLat=19
+issueLat=12
opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+opLat=12
-[system.cpu.fuPool.FUList2.opList0]
+[system.cpu.fuPool.FUList1.opList2]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=FloatAdd
-opLat=2
+opClass=IprAccess
+opLat=3
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList
+count=1
eventq_index=0
-issueLat=1
-opClass=FloatCmp
-opLat=2
+opList=system.cpu.fuPool.FUList2.opList
-[system.cpu.fuPool.FUList2.opList2]
+[system.cpu.fuPool.FUList2.opList]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=FloatCvt
+opClass=MemRead
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
-children=opList0 opList1 opList2
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
children=opList
-count=0
+count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList
+opList=system.cpu.fuPool.FUList3.opList
-[system.cpu.fuPool.FUList4.opList]
+[system.cpu.fuPool.FUList3.opList]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemRead
-opLat=1
+opClass=MemWrite
+opLat=2
-[system.cpu.fuPool.FUList5]
+[system.cpu.fuPool.FUList4]
type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+count=2
eventq_index=0
-opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
-[system.cpu.fuPool.FUList5.opList00]
+[system.cpu.fuPool.FUList4.opList00]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAdd
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList01]
+[system.cpu.fuPool.FUList4.opList01]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAddAcc
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList02]
+[system.cpu.fuPool.FUList4.opList02]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAlu
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList03]
+[system.cpu.fuPool.FUList4.opList03]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCmp
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList04]
+[system.cpu.fuPool.FUList4.opList04]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCvt
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList05]
+[system.cpu.fuPool.FUList4.opList05]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMisc
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList06]
+[system.cpu.fuPool.FUList4.opList06]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMult
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList07]
+[system.cpu.fuPool.FUList4.opList07]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMultAcc
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList08]
+[system.cpu.fuPool.FUList4.opList08]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShift
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList09]
+[system.cpu.fuPool.FUList4.opList09]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShiftAcc
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList10]
+[system.cpu.fuPool.FUList4.opList10]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdSqrt
-opLat=1
+opLat=9
-[system.cpu.fuPool.FUList5.opList11]
+[system.cpu.fuPool.FUList4.opList11]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAdd
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList12]
+[system.cpu.fuPool.FUList4.opList12]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAlu
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList13]
+[system.cpu.fuPool.FUList4.opList13]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCmp
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList14]
+[system.cpu.fuPool.FUList4.opList14]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCvt
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList15]
+[system.cpu.fuPool.FUList4.opList15]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatDiv
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList16]
+[system.cpu.fuPool.FUList4.opList16]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMisc
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList17]
+[system.cpu.fuPool.FUList4.opList17]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMult
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList18]
+[system.cpu.fuPool.FUList4.opList18]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
-[system.cpu.fuPool.FUList5.opList19]
+[system.cpu.fuPool.FUList4.opList19]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatSqrt
-opLat=1
+opLat=9
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList6.opList
-
-[system.cpu.fuPool.FUList6.opList]
+[system.cpu.fuPool.FUList4.opList20]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemWrite
-opLat=1
+opClass=FloatAdd
+opLat=5
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
+[system.cpu.fuPool.FUList4.opList21]
+type=OpDesc
eventq_index=0
-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+issueLat=1
+opClass=FloatCmp
+opLat=5
-[system.cpu.fuPool.FUList7.opList0]
+[system.cpu.fuPool.FUList4.opList22]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemRead
-opLat=1
+opClass=FloatCvt
+opLat=5
-[system.cpu.fuPool.FUList7.opList1]
+[system.cpu.fuPool.FUList4.opList23]
type=OpDesc
eventq_index=0
-issueLat=1
-opClass=MemWrite
-opLat=1
+issueLat=9
+opClass=FloatDiv
+opLat=9
-[system.cpu.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
+[system.cpu.fuPool.FUList4.opList24]
+type=OpDesc
eventq_index=0
-opList=system.cpu.fuPool.FUList8.opList
+issueLat=33
+opClass=FloatSqrt
+opLat=33
-[system.cpu.fuPool.FUList8.opList]
+[system.cpu.fuPool.FUList4.opList25]
type=OpDesc
eventq_index=0
-issueLat=3
-opClass=IprAccess
-opLat=3
+issueLat=1
+opClass=FloatMult
+opLat=4
[system.cpu.icache]
type=BaseCache
@@ -542,18 +500,18 @@ assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
-hit_latency=2
+hit_latency=1
is_top_level=true
max_miss_count=0
-mshrs=4
+mshrs=2
prefetch_on_access=false
prefetcher=Null
-response_latency=2
+response_latency=1
sequential_access=false
-size=131072
+size=32768
system=system
tags=system.cpu.icache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -565,9 +523,9 @@ assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
-hit_latency=2
+hit_latency=1
sequential_access=false
-size=131072
+size=32768
[system.cpu.interrupts]
type=ArmInterrupts
@@ -645,44 +603,62 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
-children=tags
+children=prefetcher tags
addr_ranges=0:18446744073709551615
-assoc=8
+assoc=16
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
-hit_latency=20
+hit_latency=12
is_top_level=false
max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu.l2cache.prefetcher
+response_latency=12
sequential_access=false
-size=2097152
+size=1048576
system=system
tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
+tgts_per_mshr=8
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
+[system.cpu.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
+type=RandomRepl
+assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
-hit_latency=20
+hit_latency=12
sequential_access=false
-size=2097152
+size=1048576
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -695,7 +671,7 @@ eventq_index=0
[system.cpu.workload]
type=LiveProcess
-cmd=perlbmk -I. -I lib lgred.makerand.pl
+cmd=perlbmk -I. -I lib mdred.makerand.pl
cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
egid=100
env=
@@ -712,6 +688,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -730,10 +707,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -742,8 +720,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -752,6 +755,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -765,19 +769,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
index 183fc2417..b27ae5a40 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.407884 # Nu
sim_ticks 407883784500 # Number of ticks simulated
final_tick 407883784500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 91837 # Simulator instruction rate (inst/s)
-host_op_rate 113063 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 58469822 # Simulator tick rate (ticks/s)
-host_mem_usage 2565440 # Number of bytes of host memory used
-host_seconds 6975.97 # Real time elapsed on the host
+host_inst_rate 65117 # Simulator instruction rate (inst/s)
+host_op_rate 80168 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 41458433 # Simulator tick rate (ticks/s)
+host_mem_usage 2600432 # Number of bytes of host memory used
+host_seconds 9838.38 # Real time elapsed on the host
sim_insts 640649298 # Number of instructions simulated
sim_ops 788724957 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -420,7 +420,7 @@ system.cpu.numCycles 815767570 # nu
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 84062545 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1200075863 # Number of instructions fetch has processed
+system.cpu.fetch.Insts 1200075862 # Number of instructions fetch has processed
system.cpu.fetch.Branches 233961455 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 133292629 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 716015819 # Number of cycles fetch has run and was not squashing or blocked
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
index b0a290b06..7eb73e466 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
@@ -70,9 +70,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -206,7 +203,7 @@ eventq_index=0
[system.cpu.workload]
type=LiveProcess
-cmd=perlbmk -I. -I lib lgred.makerand.pl
+cmd=perlbmk -I. -I lib mdred.makerand.pl
cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic
egid=100
env=
@@ -223,6 +220,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -241,10 +239,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
index e3c2da1c2..0c1f952a4 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
@@ -299,10 +299,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -315,7 +316,7 @@ eventq_index=0
[system.cpu.workload]
type=LiveProcess
-cmd=perlbmk -I. -I lib lgred.makerand.pl
+cmd=perlbmk -I. -I lib mdred.makerand.pl
cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing
egid=100
env=
@@ -332,6 +333,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -350,10 +352,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini
index d2cfbc574..e4bee3f35 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini
@@ -632,10 +632,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -665,6 +666,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -683,10 +685,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -695,8 +698,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -705,6 +733,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -718,19 +747,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
index e46a676eb..72bc50e35 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
@@ -17,6 +17,7 @@ clk_domain=system.clk_domain
eventq_index=0
init_param=0
kernel=
+kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
@@ -73,6 +74,7 @@ do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -125,7 +127,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -580,10 +581,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -603,7 +605,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/vortex
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
max_stack_size=67108864
@@ -613,6 +615,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -631,10 +634,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -643,8 +647,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -653,6 +682,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -666,19 +696,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
index 34c305ae5..bc26b879f 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -125,6 +122,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -143,10 +141,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
index d2c7c290f..5ccaad7e0 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
@@ -201,10 +201,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -234,6 +235,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -252,10 +254,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini
index 6ff93edf5..fd6ea1264 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini
@@ -730,10 +730,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -763,6 +764,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -781,10 +783,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -793,8 +796,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -803,6 +831,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -816,19 +845,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
index 11661d187..6bff9ac08 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
@@ -47,10 +47,10 @@ voltage_domain=system.voltage_domain
type=DerivO3CPU
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
LFSTSize=1024
-LQEntries=32
+LQEntries=16
LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
+LSQDepCheckShift=0
+SQEntries=16
SSITSize=1024
activity=0
backComSize=5
@@ -65,19 +65,20 @@ commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-dispatchWidth=8
+decodeToRenameDelay=2
+decodeWidth=3
+dispatchWidth=6
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
-fetchBufferSize=64
-fetchToDecodeDelay=1
+fetchBufferSize=16
+fetchQueueSize=32
+fetchToDecodeDelay=3
fetchTrapLatency=1
-fetchWidth=8
+fetchWidth=3
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
@@ -97,20 +98,20 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
-numIQEntries=64
-numPhysCCRegs=0
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
+numIQEntries=32
+numPhysCCRegs=640
+numPhysFloatRegs=192
+numPhysIntRegs=128
+numROBEntries=40
numRobs=1
numThreads=1
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
-renameToIEWDelay=2
+renameToIEWDelay=1
renameToROBDelay=1
-renameWidth=8
+renameWidth=3
simpoint_start_insts=
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
@@ -128,7 +129,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -136,8 +136,8 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=BranchPredictor
-BTBEntries=4096
-BTBTagSize=16
+BTBEntries=2048
+BTBTagSize=18
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
@@ -149,7 +149,7 @@ localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
+predType=bi-mode
[system.cpu.dcache]
type=BaseCache
@@ -162,17 +162,17 @@ forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=4
+mshrs=6
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
-size=262144
+size=32768
system=system
tags=system.cpu.dcache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
two_queue=false
-write_buffers=8
+write_buffers=16
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@@ -184,7 +184,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=2
sequential_access=false
-size=262144
+size=32768
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@@ -229,14 +229,14 @@ port=system.cpu.toL2Bus.slave[3]
[system.cpu.fuPool]
type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+children=FUList0 FUList1 FUList2 FUList3 FUList4
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
eventq_index=0
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
-count=6
+count=2
eventq_index=0
opList=system.cpu.fuPool.FUList0.opList
@@ -249,10 +249,10 @@ opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
-children=opList0 opList1
-count=2
+children=opList0 opList1 opList2
+count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
@@ -264,275 +264,233 @@ opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
-issueLat=19
+issueLat=12
opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+opLat=12
-[system.cpu.fuPool.FUList2.opList0]
+[system.cpu.fuPool.FUList1.opList2]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=FloatAdd
-opLat=2
+opClass=IprAccess
+opLat=3
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList
+count=1
eventq_index=0
-issueLat=1
-opClass=FloatCmp
-opLat=2
+opList=system.cpu.fuPool.FUList2.opList
-[system.cpu.fuPool.FUList2.opList2]
+[system.cpu.fuPool.FUList2.opList]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=FloatCvt
+opClass=MemRead
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
-children=opList0 opList1 opList2
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
children=opList
-count=0
+count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList
+opList=system.cpu.fuPool.FUList3.opList
-[system.cpu.fuPool.FUList4.opList]
+[system.cpu.fuPool.FUList3.opList]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemRead
-opLat=1
+opClass=MemWrite
+opLat=2
-[system.cpu.fuPool.FUList5]
+[system.cpu.fuPool.FUList4]
type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+count=2
eventq_index=0
-opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
-[system.cpu.fuPool.FUList5.opList00]
+[system.cpu.fuPool.FUList4.opList00]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAdd
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList01]
+[system.cpu.fuPool.FUList4.opList01]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAddAcc
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList02]
+[system.cpu.fuPool.FUList4.opList02]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAlu
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList03]
+[system.cpu.fuPool.FUList4.opList03]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCmp
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList04]
+[system.cpu.fuPool.FUList4.opList04]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCvt
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList05]
+[system.cpu.fuPool.FUList4.opList05]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMisc
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList06]
+[system.cpu.fuPool.FUList4.opList06]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMult
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList07]
+[system.cpu.fuPool.FUList4.opList07]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMultAcc
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList08]
+[system.cpu.fuPool.FUList4.opList08]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShift
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList09]
+[system.cpu.fuPool.FUList4.opList09]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShiftAcc
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList10]
+[system.cpu.fuPool.FUList4.opList10]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdSqrt
-opLat=1
+opLat=9
-[system.cpu.fuPool.FUList5.opList11]
+[system.cpu.fuPool.FUList4.opList11]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAdd
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList12]
+[system.cpu.fuPool.FUList4.opList12]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAlu
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList13]
+[system.cpu.fuPool.FUList4.opList13]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCmp
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList14]
+[system.cpu.fuPool.FUList4.opList14]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCvt
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList15]
+[system.cpu.fuPool.FUList4.opList15]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatDiv
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList16]
+[system.cpu.fuPool.FUList4.opList16]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMisc
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList17]
+[system.cpu.fuPool.FUList4.opList17]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMult
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList18]
+[system.cpu.fuPool.FUList4.opList18]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
-[system.cpu.fuPool.FUList5.opList19]
+[system.cpu.fuPool.FUList4.opList19]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatSqrt
-opLat=1
+opLat=9
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList6.opList
-
-[system.cpu.fuPool.FUList6.opList]
+[system.cpu.fuPool.FUList4.opList20]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemWrite
-opLat=1
+opClass=FloatAdd
+opLat=5
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
+[system.cpu.fuPool.FUList4.opList21]
+type=OpDesc
eventq_index=0
-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+issueLat=1
+opClass=FloatCmp
+opLat=5
-[system.cpu.fuPool.FUList7.opList0]
+[system.cpu.fuPool.FUList4.opList22]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemRead
-opLat=1
+opClass=FloatCvt
+opLat=5
-[system.cpu.fuPool.FUList7.opList1]
+[system.cpu.fuPool.FUList4.opList23]
type=OpDesc
eventq_index=0
-issueLat=1
-opClass=MemWrite
-opLat=1
+issueLat=9
+opClass=FloatDiv
+opLat=9
-[system.cpu.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
+[system.cpu.fuPool.FUList4.opList24]
+type=OpDesc
eventq_index=0
-opList=system.cpu.fuPool.FUList8.opList
+issueLat=33
+opClass=FloatSqrt
+opLat=33
-[system.cpu.fuPool.FUList8.opList]
+[system.cpu.fuPool.FUList4.opList25]
type=OpDesc
eventq_index=0
-issueLat=3
-opClass=IprAccess
-opLat=3
+issueLat=1
+opClass=FloatMult
+opLat=4
[system.cpu.icache]
type=BaseCache
@@ -542,18 +500,18 @@ assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
-hit_latency=2
+hit_latency=1
is_top_level=true
max_miss_count=0
-mshrs=4
+mshrs=2
prefetch_on_access=false
prefetcher=Null
-response_latency=2
+response_latency=1
sequential_access=false
-size=131072
+size=32768
system=system
tags=system.cpu.icache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -565,9 +523,9 @@ assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
-hit_latency=2
+hit_latency=1
sequential_access=false
-size=131072
+size=32768
[system.cpu.interrupts]
type=ArmInterrupts
@@ -645,44 +603,62 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
-children=tags
+children=prefetcher tags
addr_ranges=0:18446744073709551615
-assoc=8
+assoc=16
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
-hit_latency=20
+hit_latency=12
is_top_level=false
max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu.l2cache.prefetcher
+response_latency=12
sequential_access=false
-size=2097152
+size=1048576
system=system
tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
+tgts_per_mshr=8
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
+[system.cpu.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
+type=RandomRepl
+assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
-hit_latency=20
+hit_latency=12
sequential_access=false
-size=2097152
+size=1048576
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -712,6 +688,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -730,10 +707,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -742,8 +720,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -752,6 +755,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -765,19 +769,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
index 7a9144759..f73c6b128 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
@@ -70,9 +70,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -223,6 +220,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -241,10 +239,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
index 0709f1643..8d05feb2e 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
@@ -299,10 +299,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -332,6 +333,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -350,10 +352,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
index d88b9c728..5fee4647b 100644
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -124,6 +121,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -142,10 +140,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
index 0fe5ca901..5186e7456 100644
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
@@ -200,10 +200,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -233,6 +234,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -251,10 +253,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini
index 581902389..706f923dd 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini
@@ -632,10 +632,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -665,6 +666,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -683,10 +685,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -695,8 +698,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -705,6 +733,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -718,19 +747,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
index a124b2ba9..cfff7eb6d 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
@@ -17,6 +17,7 @@ clk_domain=system.clk_domain
eventq_index=0
init_param=0
kernel=
+kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
@@ -73,6 +74,7 @@ do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -125,7 +127,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -580,10 +581,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -603,7 +605,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/bzip2
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
max_stack_size=67108864
@@ -613,6 +615,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -631,10 +634,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -643,8 +647,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -653,6 +682,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -666,19 +696,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
index a048badbc..2e63bb33b 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -125,6 +122,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -143,10 +141,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
index d3adad404..fc2fe20b8 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
@@ -201,10 +201,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -234,6 +235,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -252,10 +254,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini
index 0d07c139d..55081d3ef 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini
@@ -730,10 +730,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -763,6 +764,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -781,10 +783,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -793,8 +796,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -803,6 +831,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -816,19 +845,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
index d2257e41a..d573e8898 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
@@ -47,10 +47,10 @@ voltage_domain=system.voltage_domain
type=DerivO3CPU
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
LFSTSize=1024
-LQEntries=32
+LQEntries=16
LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
+LSQDepCheckShift=0
+SQEntries=16
SSITSize=1024
activity=0
backComSize=5
@@ -65,19 +65,20 @@ commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-dispatchWidth=8
+decodeToRenameDelay=2
+decodeWidth=3
+dispatchWidth=6
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
-fetchBufferSize=64
-fetchToDecodeDelay=1
+fetchBufferSize=16
+fetchQueueSize=32
+fetchToDecodeDelay=3
fetchTrapLatency=1
-fetchWidth=8
+fetchWidth=3
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
@@ -97,20 +98,20 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
-numIQEntries=64
-numPhysCCRegs=0
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
+numIQEntries=32
+numPhysCCRegs=640
+numPhysFloatRegs=192
+numPhysIntRegs=128
+numROBEntries=40
numRobs=1
numThreads=1
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
-renameToIEWDelay=2
+renameToIEWDelay=1
renameToROBDelay=1
-renameWidth=8
+renameWidth=3
simpoint_start_insts=
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
@@ -128,7 +129,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -136,8 +136,8 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=BranchPredictor
-BTBEntries=4096
-BTBTagSize=16
+BTBEntries=2048
+BTBTagSize=18
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
@@ -149,7 +149,7 @@ localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
+predType=bi-mode
[system.cpu.dcache]
type=BaseCache
@@ -162,17 +162,17 @@ forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=4
+mshrs=6
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
-size=262144
+size=32768
system=system
tags=system.cpu.dcache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
two_queue=false
-write_buffers=8
+write_buffers=16
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@@ -184,7 +184,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=2
sequential_access=false
-size=262144
+size=32768
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@@ -229,14 +229,14 @@ port=system.cpu.toL2Bus.slave[3]
[system.cpu.fuPool]
type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+children=FUList0 FUList1 FUList2 FUList3 FUList4
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
eventq_index=0
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
-count=6
+count=2
eventq_index=0
opList=system.cpu.fuPool.FUList0.opList
@@ -249,10 +249,10 @@ opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
-children=opList0 opList1
-count=2
+children=opList0 opList1 opList2
+count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
@@ -264,275 +264,233 @@ opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
-issueLat=19
+issueLat=12
opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+opLat=12
-[system.cpu.fuPool.FUList2.opList0]
+[system.cpu.fuPool.FUList1.opList2]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=FloatAdd
-opLat=2
+opClass=IprAccess
+opLat=3
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList
+count=1
eventq_index=0
-issueLat=1
-opClass=FloatCmp
-opLat=2
+opList=system.cpu.fuPool.FUList2.opList
-[system.cpu.fuPool.FUList2.opList2]
+[system.cpu.fuPool.FUList2.opList]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=FloatCvt
+opClass=MemRead
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
-children=opList0 opList1 opList2
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
children=opList
-count=0
+count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList
+opList=system.cpu.fuPool.FUList3.opList
-[system.cpu.fuPool.FUList4.opList]
+[system.cpu.fuPool.FUList3.opList]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemRead
-opLat=1
+opClass=MemWrite
+opLat=2
-[system.cpu.fuPool.FUList5]
+[system.cpu.fuPool.FUList4]
type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+count=2
eventq_index=0
-opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
-[system.cpu.fuPool.FUList5.opList00]
+[system.cpu.fuPool.FUList4.opList00]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAdd
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList01]
+[system.cpu.fuPool.FUList4.opList01]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAddAcc
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList02]
+[system.cpu.fuPool.FUList4.opList02]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAlu
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList03]
+[system.cpu.fuPool.FUList4.opList03]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCmp
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList04]
+[system.cpu.fuPool.FUList4.opList04]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCvt
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList05]
+[system.cpu.fuPool.FUList4.opList05]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMisc
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList06]
+[system.cpu.fuPool.FUList4.opList06]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMult
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList07]
+[system.cpu.fuPool.FUList4.opList07]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMultAcc
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList08]
+[system.cpu.fuPool.FUList4.opList08]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShift
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList09]
+[system.cpu.fuPool.FUList4.opList09]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShiftAcc
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList10]
+[system.cpu.fuPool.FUList4.opList10]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdSqrt
-opLat=1
+opLat=9
-[system.cpu.fuPool.FUList5.opList11]
+[system.cpu.fuPool.FUList4.opList11]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAdd
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList12]
+[system.cpu.fuPool.FUList4.opList12]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAlu
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList13]
+[system.cpu.fuPool.FUList4.opList13]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCmp
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList14]
+[system.cpu.fuPool.FUList4.opList14]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCvt
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList15]
+[system.cpu.fuPool.FUList4.opList15]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatDiv
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList16]
+[system.cpu.fuPool.FUList4.opList16]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMisc
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList17]
+[system.cpu.fuPool.FUList4.opList17]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMult
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList18]
+[system.cpu.fuPool.FUList4.opList18]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
-[system.cpu.fuPool.FUList5.opList19]
+[system.cpu.fuPool.FUList4.opList19]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatSqrt
-opLat=1
+opLat=9
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList6.opList
-
-[system.cpu.fuPool.FUList6.opList]
+[system.cpu.fuPool.FUList4.opList20]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemWrite
-opLat=1
+opClass=FloatAdd
+opLat=5
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
+[system.cpu.fuPool.FUList4.opList21]
+type=OpDesc
eventq_index=0
-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+issueLat=1
+opClass=FloatCmp
+opLat=5
-[system.cpu.fuPool.FUList7.opList0]
+[system.cpu.fuPool.FUList4.opList22]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemRead
-opLat=1
+opClass=FloatCvt
+opLat=5
-[system.cpu.fuPool.FUList7.opList1]
+[system.cpu.fuPool.FUList4.opList23]
type=OpDesc
eventq_index=0
-issueLat=1
-opClass=MemWrite
-opLat=1
+issueLat=9
+opClass=FloatDiv
+opLat=9
-[system.cpu.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
+[system.cpu.fuPool.FUList4.opList24]
+type=OpDesc
eventq_index=0
-opList=system.cpu.fuPool.FUList8.opList
+issueLat=33
+opClass=FloatSqrt
+opLat=33
-[system.cpu.fuPool.FUList8.opList]
+[system.cpu.fuPool.FUList4.opList25]
type=OpDesc
eventq_index=0
-issueLat=3
-opClass=IprAccess
-opLat=3
+issueLat=1
+opClass=FloatMult
+opLat=4
[system.cpu.icache]
type=BaseCache
@@ -542,18 +500,18 @@ assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
-hit_latency=2
+hit_latency=1
is_top_level=true
max_miss_count=0
-mshrs=4
+mshrs=2
prefetch_on_access=false
prefetcher=Null
-response_latency=2
+response_latency=1
sequential_access=false
-size=131072
+size=32768
system=system
tags=system.cpu.icache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -565,9 +523,9 @@ assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
-hit_latency=2
+hit_latency=1
sequential_access=false
-size=131072
+size=32768
[system.cpu.interrupts]
type=ArmInterrupts
@@ -645,44 +603,62 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
-children=tags
+children=prefetcher tags
addr_ranges=0:18446744073709551615
-assoc=8
+assoc=16
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
-hit_latency=20
+hit_latency=12
is_top_level=false
max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu.l2cache.prefetcher
+response_latency=12
sequential_access=false
-size=2097152
+size=1048576
system=system
tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
+tgts_per_mshr=8
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
+[system.cpu.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
+type=RandomRepl
+assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
-hit_latency=20
+hit_latency=12
sequential_access=false
-size=2097152
+size=1048576
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -712,6 +688,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -730,10 +707,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -742,8 +720,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -752,6 +755,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -765,19 +769,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
index ec3a0574d..c5adbf84c 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
@@ -70,9 +70,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -223,6 +220,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -241,10 +239,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
index 3e6b06c13..3bcac58f7 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
@@ -299,10 +299,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -332,6 +333,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -350,10 +352,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
index abb41bc37..36079bdaf 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -158,6 +155,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -176,10 +174,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
index eedfe9da7..1cf904013 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
@@ -234,10 +234,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -267,6 +268,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -285,10 +287,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini
index 11027e0cc..250783f94 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini
@@ -632,10 +632,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -665,6 +666,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -683,10 +685,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -695,8 +698,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -705,6 +733,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -718,19 +747,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
index 91fb4fb7f..168018c03 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
@@ -17,6 +17,7 @@ clk_domain=system.clk_domain
eventq_index=0
init_param=0
kernel=
+kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
@@ -73,6 +74,7 @@ do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -125,7 +127,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -580,10 +581,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -603,7 +605,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
max_stack_size=67108864
@@ -613,6 +615,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -631,10 +634,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -643,8 +647,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -653,6 +682,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -666,19 +696,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
index 881006e7f..31653027e 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -125,6 +122,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -143,10 +141,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
index 896591c78..b930735f4 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
@@ -201,10 +201,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -234,6 +235,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -252,10 +254,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini
index e7e2c3de4..f2c2bbb56 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini
@@ -730,10 +730,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -763,6 +764,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -781,10 +783,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -793,8 +796,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -803,6 +831,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -816,19 +845,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simerr b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simerr
index 1a4f96712..1a4f96712 100644..100755
--- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simerr
+++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simerr
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout
index 6876fac87..6876fac87 100644..100755
--- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout
+++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
index d8488904a..963ba1258 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
@@ -47,10 +47,10 @@ voltage_domain=system.voltage_domain
type=DerivO3CPU
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
LFSTSize=1024
-LQEntries=32
+LQEntries=16
LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
+LSQDepCheckShift=0
+SQEntries=16
SSITSize=1024
activity=0
backComSize=5
@@ -65,19 +65,20 @@ commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-dispatchWidth=8
+decodeToRenameDelay=2
+decodeWidth=3
+dispatchWidth=6
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
-fetchBufferSize=64
-fetchToDecodeDelay=1
+fetchBufferSize=16
+fetchQueueSize=32
+fetchToDecodeDelay=3
fetchTrapLatency=1
-fetchWidth=8
+fetchWidth=3
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
@@ -97,20 +98,20 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
-numIQEntries=64
-numPhysCCRegs=0
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
+numIQEntries=32
+numPhysCCRegs=640
+numPhysFloatRegs=192
+numPhysIntRegs=128
+numROBEntries=40
numRobs=1
numThreads=1
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
-renameToIEWDelay=2
+renameToIEWDelay=1
renameToROBDelay=1
-renameWidth=8
+renameWidth=3
simpoint_start_insts=
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
@@ -128,7 +129,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -136,8 +136,8 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=BranchPredictor
-BTBEntries=4096
-BTBTagSize=16
+BTBEntries=2048
+BTBTagSize=18
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
@@ -149,7 +149,7 @@ localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
+predType=bi-mode
[system.cpu.dcache]
type=BaseCache
@@ -162,17 +162,17 @@ forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=4
+mshrs=6
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
-size=262144
+size=32768
system=system
tags=system.cpu.dcache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
two_queue=false
-write_buffers=8
+write_buffers=16
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@@ -184,7 +184,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=2
sequential_access=false
-size=262144
+size=32768
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@@ -229,14 +229,14 @@ port=system.cpu.toL2Bus.slave[3]
[system.cpu.fuPool]
type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+children=FUList0 FUList1 FUList2 FUList3 FUList4
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
eventq_index=0
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
-count=6
+count=2
eventq_index=0
opList=system.cpu.fuPool.FUList0.opList
@@ -249,10 +249,10 @@ opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
-children=opList0 opList1
-count=2
+children=opList0 opList1 opList2
+count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
@@ -264,275 +264,233 @@ opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
-issueLat=19
+issueLat=12
opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+opLat=12
-[system.cpu.fuPool.FUList2.opList0]
+[system.cpu.fuPool.FUList1.opList2]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=FloatAdd
-opLat=2
+opClass=IprAccess
+opLat=3
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList
+count=1
eventq_index=0
-issueLat=1
-opClass=FloatCmp
-opLat=2
+opList=system.cpu.fuPool.FUList2.opList
-[system.cpu.fuPool.FUList2.opList2]
+[system.cpu.fuPool.FUList2.opList]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=FloatCvt
+opClass=MemRead
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
-children=opList0 opList1 opList2
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
children=opList
-count=0
+count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList
+opList=system.cpu.fuPool.FUList3.opList
-[system.cpu.fuPool.FUList4.opList]
+[system.cpu.fuPool.FUList3.opList]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemRead
-opLat=1
+opClass=MemWrite
+opLat=2
-[system.cpu.fuPool.FUList5]
+[system.cpu.fuPool.FUList4]
type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+count=2
eventq_index=0
-opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
-[system.cpu.fuPool.FUList5.opList00]
+[system.cpu.fuPool.FUList4.opList00]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAdd
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList01]
+[system.cpu.fuPool.FUList4.opList01]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAddAcc
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList02]
+[system.cpu.fuPool.FUList4.opList02]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAlu
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList03]
+[system.cpu.fuPool.FUList4.opList03]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCmp
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList04]
+[system.cpu.fuPool.FUList4.opList04]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCvt
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList05]
+[system.cpu.fuPool.FUList4.opList05]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMisc
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList06]
+[system.cpu.fuPool.FUList4.opList06]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMult
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList07]
+[system.cpu.fuPool.FUList4.opList07]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMultAcc
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList08]
+[system.cpu.fuPool.FUList4.opList08]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShift
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList09]
+[system.cpu.fuPool.FUList4.opList09]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShiftAcc
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList10]
+[system.cpu.fuPool.FUList4.opList10]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdSqrt
-opLat=1
+opLat=9
-[system.cpu.fuPool.FUList5.opList11]
+[system.cpu.fuPool.FUList4.opList11]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAdd
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList12]
+[system.cpu.fuPool.FUList4.opList12]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAlu
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList13]
+[system.cpu.fuPool.FUList4.opList13]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCmp
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList14]
+[system.cpu.fuPool.FUList4.opList14]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCvt
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList15]
+[system.cpu.fuPool.FUList4.opList15]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatDiv
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList16]
+[system.cpu.fuPool.FUList4.opList16]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMisc
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList17]
+[system.cpu.fuPool.FUList4.opList17]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMult
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList18]
+[system.cpu.fuPool.FUList4.opList18]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
-[system.cpu.fuPool.FUList5.opList19]
+[system.cpu.fuPool.FUList4.opList19]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatSqrt
-opLat=1
+opLat=9
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList6.opList
-
-[system.cpu.fuPool.FUList6.opList]
+[system.cpu.fuPool.FUList4.opList20]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemWrite
-opLat=1
+opClass=FloatAdd
+opLat=5
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
+[system.cpu.fuPool.FUList4.opList21]
+type=OpDesc
eventq_index=0
-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+issueLat=1
+opClass=FloatCmp
+opLat=5
-[system.cpu.fuPool.FUList7.opList0]
+[system.cpu.fuPool.FUList4.opList22]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemRead
-opLat=1
+opClass=FloatCvt
+opLat=5
-[system.cpu.fuPool.FUList7.opList1]
+[system.cpu.fuPool.FUList4.opList23]
type=OpDesc
eventq_index=0
-issueLat=1
-opClass=MemWrite
-opLat=1
+issueLat=9
+opClass=FloatDiv
+opLat=9
-[system.cpu.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
+[system.cpu.fuPool.FUList4.opList24]
+type=OpDesc
eventq_index=0
-opList=system.cpu.fuPool.FUList8.opList
+issueLat=33
+opClass=FloatSqrt
+opLat=33
-[system.cpu.fuPool.FUList8.opList]
+[system.cpu.fuPool.FUList4.opList25]
type=OpDesc
eventq_index=0
-issueLat=3
-opClass=IprAccess
-opLat=3
+issueLat=1
+opClass=FloatMult
+opLat=4
[system.cpu.icache]
type=BaseCache
@@ -542,18 +500,18 @@ assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
-hit_latency=2
+hit_latency=1
is_top_level=true
max_miss_count=0
-mshrs=4
+mshrs=2
prefetch_on_access=false
prefetcher=Null
-response_latency=2
+response_latency=1
sequential_access=false
-size=131072
+size=32768
system=system
tags=system.cpu.icache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -565,9 +523,9 @@ assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
-hit_latency=2
+hit_latency=1
sequential_access=false
-size=131072
+size=32768
[system.cpu.interrupts]
type=ArmInterrupts
@@ -645,44 +603,62 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
-children=tags
+children=prefetcher tags
addr_ranges=0:18446744073709551615
-assoc=8
+assoc=16
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
-hit_latency=20
+hit_latency=12
is_top_level=false
max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu.l2cache.prefetcher
+response_latency=12
sequential_access=false
-size=2097152
+size=1048576
system=system
tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
+tgts_per_mshr=8
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
+[system.cpu.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
+type=RandomRepl
+assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
-hit_latency=20
+hit_latency=12
sequential_access=false
-size=2097152
+size=1048576
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -712,6 +688,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -730,10 +707,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -742,8 +720,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -752,6 +755,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -765,19 +769,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
index b37d84887..52b17d81d 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
@@ -70,9 +70,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -223,6 +220,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -241,10 +239,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
index 50fb5bed2..0035560c6 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
@@ -299,10 +299,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -332,6 +333,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -350,10 +352,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
index b76f802a9..fd6e14d22 100644
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -124,6 +121,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -142,10 +140,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
index fb7b292e6..fc5d4f341 100644
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
@@ -200,10 +200,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -233,6 +234,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -251,10 +253,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
index c83cd6a89..bfaee19bf 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
@@ -74,6 +74,7 @@ do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -126,7 +127,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -614,10 +614,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -647,6 +648,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -665,10 +667,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -677,8 +680,33 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -687,6 +715,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -700,19 +729,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
index 6e31ea4d2..26fe45507 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -158,6 +155,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -176,10 +174,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
index 3e9d33bf3..4909b25e3 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
@@ -234,10 +234,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -267,6 +268,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -285,10 +287,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8