diff options
Diffstat (limited to 'tests/long')
40 files changed, 708 insertions, 714 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt index 8e02b536f..4e08b47b3 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,37 +1,37 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 65718863 # Number of BTB hits -global.BPredUnit.BTBLookups 73181378 # Number of BTB lookups +global.BPredUnit.BTBHits 65718859 # Number of BTB hits +global.BPredUnit.BTBLookups 73181368 # Number of BTB lookups global.BPredUnit.RASInCorrect 198 # Number of incorrect RAS predictions. global.BPredUnit.condIncorrect 4206850 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 70112297 # Number of conditional branches predicted -global.BPredUnit.lookups 76039028 # Number of BP lookups +global.BPredUnit.condPredicted 70112287 # Number of conditional branches predicted +global.BPredUnit.lookups 76039018 # Number of BP lookups global.BPredUnit.usedRAS 1692219 # Number of times the RAS was used to get a target. -host_inst_rate 204243 # Simulator instruction rate (inst/s) -host_mem_usage 202188 # Number of bytes of host memory used -host_seconds 2769.01 # Real time elapsed on the host -host_tick_rate 60338522 # Simulator tick rate (ticks/s) +host_inst_rate 193677 # Simulator instruction rate (inst/s) +host_mem_usage 202220 # Number of bytes of host memory used +host_seconds 2920.07 # Real time elapsed on the host +host_tick_rate 57217081 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 19292303 # Number of conflicting loads. memdepunit.memDep.conflictingStores 14732751 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 126977207 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 126977202 # Number of loads inserted to the mem dependence unit. memdepunit.memDep.insertedStores 43223597 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated sim_seconds 0.167078 # Number of seconds simulated -sim_ticks 167078186500 # Number of ticks simulated +sim_ticks 167078146500 # Number of ticks simulated system.cpu.commit.COM:branches 62547159 # Number of branches committed system.cpu.commit.COM:bw_lim_events 17700250 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 322711309 +system.cpu.commit.COM:committed_per_cycle.samples 322711249 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 108088817 3349.40% + 0 108088757 3349.40% 1 100475751 3113.49% 2 37367184 1157.91% 3 9733028 301.60% 4 10676883 330.85% - 5 22147835 686.30% + 5 22147835 686.31% 6 13251874 410.64% 7 3269687 101.32% 8 17700250 548.49% @@ -46,22 +46,22 @@ system.cpu.commit.COM:swp_count 0 # Nu system.cpu.commit.branchMispredicts 4206223 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 61418223 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 61418165 # The number of squashed insts skipped by commit system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated system.cpu.cpi 0.590849 # CPI: Cycles Per Instruction system.cpu.cpi_total 0.590849 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 113146791 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 19647.218520 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7806.236909 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 112293702 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 16760826000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses 113146786 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 19647.173839 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7806.243845 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 112293703 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 16760670000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.007540 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 853089 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 636812 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1688309500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 853083 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 636806 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1688311000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001911 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 216277 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) @@ -77,36 +77,36 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.008549 # m system.cpu.dcache.WriteReq_mshr_misses 337278 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs 6922.723577 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets 21318.181818 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 317.179200 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 317.179202 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 123 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 11 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 851495 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 234500 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 152598112 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 29275.568696 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 24763.762399 # average overall mshr miss latency -system.cpu.dcache.demand_hits 149415338 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 93177518881 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 152598107 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 29275.574871 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 24763.765109 # average overall mshr miss latency +system.cpu.dcache.demand_hits 149415339 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 93177362881 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.020857 # miss rate for demand accesses -system.cpu.dcache.demand_misses 3182774 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2629219 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 13708104495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_misses 3182768 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2629213 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 13708105995 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.003628 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 553555 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 152598112 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 29275.568696 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 24763.762399 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 152598107 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 29275.574871 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 24763.765109 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 149415338 # number of overall hits -system.cpu.dcache.overall_miss_latency 93177518881 # number of overall miss cycles +system.cpu.dcache.overall_hits 149415339 # number of overall hits +system.cpu.dcache.overall_miss_latency 93177362881 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.020857 # miss rate for overall accesses -system.cpu.dcache.overall_misses 3182774 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2629219 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 13708104495 # number of overall MSHR miss cycles +system.cpu.dcache.overall_misses 3182768 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2629213 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 13708105995 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.003628 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 553555 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -123,99 +123,99 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 468828 # number of replacements system.cpu.dcache.sampled_refs 472924 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.202443 # Cycle average of tags in use -system.cpu.dcache.total_refs 150001656 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 126621000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tagsinuse 4094.203417 # Cycle average of tags in use +system.cpu.dcache.total_refs 150001657 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 126581000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 334123 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 49202535 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BlockedCycles 49202518 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 654 # Number of times decode detected a branch misprediction system.cpu.decode.DECODE:BranchResolved 4158991 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 689696251 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 144199512 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 123896072 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 9869869 # Number of cycles decode is squashing +system.cpu.decode.DECODE:DecodedInsts 689696194 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 144199483 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 123896058 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 9869862 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 2004 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:UnblockCycles 5413191 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 163077395 # DTB accesses +system.cpu.dtb.accesses 163077390 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 163013885 # DTB hits +system.cpu.dtb.hits 163013880 # DTB hits system.cpu.dtb.misses 63510 # DTB misses -system.cpu.dtb.read_accesses 122284114 # DTB read accesses +system.cpu.dtb.read_accesses 122284109 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 122260501 # DTB read hits +system.cpu.dtb.read_hits 122260496 # DTB read hits system.cpu.dtb.read_misses 23613 # DTB read misses system.cpu.dtb.write_accesses 40793281 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_hits 40753384 # DTB write hits system.cpu.dtb.write_misses 39897 # DTB write misses -system.cpu.fetch.Branches 76039028 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 66014416 # Number of cache lines fetched -system.cpu.fetch.Cycles 197129359 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Branches 76039018 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 66014406 # Number of cache lines fetched +system.cpu.fetch.Cycles 197129335 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 1352914 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 698864070 # Number of instructions fetch has processed +system.cpu.fetch.Insts 698864013 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 4233116 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.227555 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 66014416 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 67411082 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.091428 # Number of inst fetches per cycle +system.cpu.fetch.icacheStallCycles 66014406 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 67411078 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.091429 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 332581179 +system.cpu.fetch.rateDist.samples 332581112 system.cpu.fetch.rateDist.min_value 0 - 0 201466276 6057.66% - 1 10360751 311.53% - 2 15882086 477.54% + 0 201466223 6057.66% + 1 10360747 311.53% + 2 15882081 477.54% 3 14599006 438.96% 4 12362950 371.73% - 5 14822133 445.67% + 5 14822134 445.67% 6 6008311 180.66% 7 3307530 99.45% - 8 53772136 1616.81% + 8 53772130 1616.81% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 66014416 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 36203.165098 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35497.228381 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 66013247 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 42321500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 66014406 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 36214.713430 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35498.337029 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 66013237 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 42335000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 1169 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 267 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 32018500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 32019500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 902 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 73185.417960 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 73185.406874 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 66014416 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 36203.165098 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35497.228381 # average overall mshr miss latency -system.cpu.icache.demand_hits 66013247 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 42321500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 66014406 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 36214.713430 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35498.337029 # average overall mshr miss latency +system.cpu.icache.demand_hits 66013237 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 42335000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses system.cpu.icache.demand_misses 1169 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 267 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 32018500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 32019500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 902 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 66014416 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 36203.165098 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35497.228381 # average overall mshr miss latency +system.cpu.icache.overall_accesses 66014406 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 36214.713430 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35498.337029 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 66013247 # number of overall hits -system.cpu.icache.overall_miss_latency 42321500 # number of overall miss cycles +system.cpu.icache.overall_hits 66013237 # number of overall hits +system.cpu.icache.overall_miss_latency 42335000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses system.cpu.icache.overall_misses 1169 # number of overall misses system.cpu.icache.overall_mshr_hits 267 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 32018500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 32019500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 902 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -232,40 +232,40 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 34 # number of replacements system.cpu.icache.sampled_refs 902 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 769.803769 # Cycle average of tags in use -system.cpu.icache.total_refs 66013247 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 769.803945 # Cycle average of tags in use +system.cpu.icache.total_refs 66013237 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1575195 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 67316863 # Number of branches executed +system.cpu.idleCycles 1575182 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 67316859 # Number of branches executed system.cpu.iew.EXEC:nop 42997381 # number of nop insts executed system.cpu.iew.EXEC:rate 1.793347 # Inst execution rate -system.cpu.iew.EXEC:refs 164017998 # number of memory reference insts executed +system.cpu.iew.EXEC:refs 164017993 # number of memory reference insts executed system.cpu.iew.EXEC:stores 41189464 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 487237026 # num instructions consuming a value -system.cpu.iew.WB:count 596051181 # cumulative count of insts written-back +system.cpu.iew.WB:consumers 487237002 # num instructions consuming a value +system.cpu.iew.WB:count 596051147 # cumulative count of insts written-back system.cpu.iew.WB:fanout 0.811465 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 395375822 # num instructions producing a value -system.cpu.iew.WB:rate 1.783749 # insts written-back per cycle -system.cpu.iew.WB:sent 597227214 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 4671564 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 2251991 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 126977207 # Number of dispatched load instructions +system.cpu.iew.WB:producers 395375802 # num instructions producing a value +system.cpu.iew.WB:rate 1.783750 # insts written-back per cycle +system.cpu.iew.WB:sent 597227180 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 4671561 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 2251979 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 126977202 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispSquashedInsts 3270425 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispStoreInsts 43223597 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 663380014 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 122828534 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6459967 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 599258177 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 2444 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispatchedInsts 663379957 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 122828529 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6459968 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 599258144 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 2443 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 34441 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 9869869 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 84553 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 9869862 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 84552 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 207 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.forwLoads 9107751 # Number of loads that had data forwarded from stores @@ -274,17 +274,17 @@ system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Nu system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 29567 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 5881 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 11927697 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedLoads 11927692 # Number of loads squashed system.cpu.iew.lsq.thread.0.squashedStores 3411074 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 29567 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 540318 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 540315 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 4131246 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.692478 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.692478 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 605718144 # Type of FU issued +system.cpu.ipc 1.692479 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.692479 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 605718112 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued - IntAlu 438834867 72.45% # Type of FU issued + IntAlu 438834840 72.45% # Type of FU issued IntMult 6546 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 29 0.00% # Type of FU issued @@ -293,16 +293,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 4 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 124855458 20.61% # Type of FU issued + MemRead 124855453 20.61% # Type of FU issued MemWrite 42021230 6.94% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 7232327 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt 7232323 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.011940 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 5390835 74.54% # attempts to use FU when none available + IntAlu 5390831 74.54% # attempts to use FU when none available IntMult 67 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -317,31 +317,31 @@ system.cpu.iq.ISSUE:fu_full.start_dist InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 332581179 +system.cpu.iq.ISSUE:issued_per_cycle.samples 332581112 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 92203834 2772.37% - 1 67051351 2016.09% - 2 80133785 2409.45% - 3 36043476 1083.75% + 0 92203773 2772.37% + 1 67051353 2016.09% + 2 80133780 2409.45% + 3 36043478 1083.75% 4 30084945 904.59% 5 14579095 438.36% - 6 10850498 326.25% + 6 10850493 326.25% 7 1143008 34.37% 8 491187 14.77% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist system.cpu.iq.ISSUE:rate 1.812679 # Inst issue rate -system.cpu.iq.iqInstsAdded 620382610 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 605718144 # Number of instructions issued +system.cpu.iq.iqInstsAdded 620382553 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 605718112 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 53519343 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsExamined 53519286 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 12833 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 29313590 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 66014456 # ITB accesses +system.cpu.iq.iqSquashedOperandsExamined 29313548 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 66014446 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 66014416 # ITB hits +system.cpu.itb.hits 66014406 # ITB hits system.cpu.itb.misses 40 # ITB misses system.cpu.l2cache.ReadExReq_accesses 256647 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 34260.342026 # average ReadExReq miss latency @@ -353,13 +353,13 @@ system.cpu.l2cache.ReadExReq_mshr_miss_latency 7992382500 system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 256647 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 217179 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34303.958543 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31015.588334 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34303.986479 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31015.630238 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 181383 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1227944500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 1227945500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.164823 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 35796 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1110234000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1110235500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.164823 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 35796 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 80643 # number of UpgradeReq accesses(hits+misses) @@ -382,29 +382,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 396500 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 473826 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34265.680834 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31126.122014 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 34265.684253 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31126.127143 # average overall mshr miss latency system.cpu.l2cache.demand_hits 181383 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 10020758500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 10020759500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.617195 # miss rate for demand accesses system.cpu.l2cache.demand_misses 292443 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 9102616500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 9102618000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.617195 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 292443 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 473826 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34265.680834 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31126.122014 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 34265.684253 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31126.127143 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 181383 # number of overall hits -system.cpu.l2cache.overall_miss_latency 10020758500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 10020759500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.617195 # miss rate for overall accesses system.cpu.l2cache.overall_misses 292443 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 9102616500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 9102618000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.617195 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 292443 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -421,29 +421,29 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 85262 # number of replacements system.cpu.l2cache.sampled_refs 100888 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16333.158558 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 16333.162457 # Cycle average of tags in use system.cpu.l2cache.total_refs 375607 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 63236 # number of writebacks -system.cpu.numCycles 334156374 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 15214869 # Number of cycles rename is blocking +system.cpu.numCycles 334156294 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 15214853 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 31587364 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 151899466 # Number of cycles rename is idle +system.cpu.rename.RENAME:IQFullEvents 31587363 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 151899436 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 2286618 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:ROBFullEvents 131 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 896816435 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 680424801 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 519473844 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 116401000 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 9869869 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 39195269 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 55618955 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:RenameLookups 896816353 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 680424744 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 519473797 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 116400987 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 9869862 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 39195268 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 55618908 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:serializeStallCycles 706 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 28 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 77660301 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 77660298 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 26 # count of temporary serializing insts renamed -system.cpu.timesIdled 36535 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 36534 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout index 8133509b4..4ea4c0572 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 21:40:15 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:25:12 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt index c226b8d4c..96bd5579b 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3818661 # Simulator instruction rate (inst/s) -host_mem_usage 193720 # Number of bytes of host memory used -host_seconds 157.61 # Real time elapsed on the host -host_tick_rate 1909343313 # Simulator tick rate (ticks/s) +host_inst_rate 3417919 # Simulator instruction rate (inst/s) +host_mem_usage 193752 # Number of bytes of host memory used +host_seconds 176.09 # Real time elapsed on the host +host_tick_rate 1708971531 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated sim_seconds 0.300931 # Number of seconds simulated diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout index 63dd02070..4f98f10a9 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 19:05:35 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:47 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt index cf41fab83..5fbfd3d3d 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1993278 # Simulator instruction rate (inst/s) -host_mem_usage 201176 # Number of bytes of host memory used -host_seconds 301.94 # Real time elapsed on the host -host_tick_rate 2576653236 # Simulator tick rate (ticks/s) +host_inst_rate 1797646 # Simulator instruction rate (inst/s) +host_mem_usage 201208 # Number of bytes of host memory used +host_seconds 334.80 # Real time elapsed on the host +host_tick_rate 2323765799 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated sim_seconds 0.778004 # Number of seconds simulated @@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 24 # number of replacements system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 673.225224 # Cycle average of tags in use +system.cpu.icache.tagsinuse 673.225223 # Cycle average of tags in use system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout index 7bb6940cc..912067c8f 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 19:08:13 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:45 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/m5stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/m5stats.txt index c498474d4..cbdec272c 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/m5stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/m5stats.txt @@ -16,10 +16,10 @@ global.BPredUnit.lookups 10092697 # Nu global.BPredUnit.lookups 5530798 # Number of BP lookups global.BPredUnit.usedRAS 690318 # Number of times the RAS was used to get a target. global.BPredUnit.usedRAS 415111 # Number of times the RAS was used to get a target. -host_inst_rate 130617 # Simulator instruction rate (inst/s) -host_mem_usage 292856 # Number of bytes of host memory used -host_seconds 429.91 # Real time elapsed on the host -host_tick_rate 4437424208 # Simulator tick rate (ticks/s) +host_inst_rate 121094 # Simulator instruction rate (inst/s) +host_mem_usage 292872 # Number of bytes of host memory used +host_seconds 463.72 # Real time elapsed on the host +host_tick_rate 4113887240 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 2050196 # Number of conflicting loads. memdepunit.memDep.conflictingLoads 902547 # Number of conflicting loads. memdepunit.memDep.conflictingStores 1831551 # Number of conflicting stores. diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stdout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stdout index 3839b0231..bace1f0ca 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stdout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 22:27:11 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:30:16 +M5 compiled Dec 4 2008 21:30:58 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:35:52 M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/m5stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/m5stats.txt index 7b34dbd2c..4860b3f1d 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/m5stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 828381 # Nu global.BPredUnit.condPredicted 12127533 # Number of conditional branches predicted global.BPredUnit.lookups 14559443 # Number of BP lookups global.BPredUnit.usedRAS 1032470 # Number of times the RAS was used to get a target. -host_inst_rate 200905 # Simulator instruction rate (inst/s) -host_mem_usage 290800 # Number of bytes of host memory used -host_seconds 264.07 # Real time elapsed on the host -host_tick_rate 7071490969 # Simulator tick rate (ticks/s) +host_inst_rate 123231 # Simulator instruction rate (inst/s) +host_mem_usage 290820 # Number of bytes of host memory used +host_seconds 430.51 # Real time elapsed on the host +host_tick_rate 4337505567 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 3072758 # Number of conflicting loads. memdepunit.memDep.conflictingStores 2866670 # Number of conflicting stores. memdepunit.memDep.insertedLoads 11041732 # Number of loads inserted to the mem dependence unit. diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stdout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stdout index 4989a72b8..f6f2f7d37 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stdout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 22:27:11 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:28:27 +M5 compiled Dec 4 2008 21:30:58 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:31:00 M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt index 756f9cdc8..704dd86aa 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 5781170 # Nu global.BPredUnit.condPredicted 35418150 # Number of conditional branches predicted global.BPredUnit.lookups 62209737 # Number of BP lookups global.BPredUnit.usedRAS 12344504 # Number of times the RAS was used to get a target. -host_inst_rate 185748 # Simulator instruction rate (inst/s) -host_mem_usage 209620 # Number of bytes of host memory used -host_seconds 2021.96 # Real time elapsed on the host -host_tick_rate 66765374 # Simulator tick rate (ticks/s) +host_inst_rate 151728 # Simulator instruction rate (inst/s) +host_mem_usage 209656 # Number of bytes of host memory used +host_seconds 2475.31 # Real time elapsed on the host +host_tick_rate 54537175 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 73961217 # Number of conflicting loads. memdepunit.memDep.conflictingStores 54131405 # Number of conflicting stores. memdepunit.memDep.insertedLoads 124841223 # Number of loads inserted to the mem dependence unit. @@ -54,13 +54,13 @@ system.cpu.cpi_total 0.718880 # CP system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits system.cpu.dcache.ReadReq_accesses 95501309 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 33012.273524 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 33016.637478 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31966.971545 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 95499598 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 56484000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_hits 95499596 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 56557500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1711 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 727 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_misses 1713 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 729 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 31455500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 984 # number of ReadReq MSHR misses @@ -77,20 +77,20 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # m system.cpu.dcache.WriteReq_mshr_misses 3309 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs 3249.700000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 40460.273163 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 40460.272684 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 10 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 32497 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 169022038 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 30545.096938 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 30545.726047 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 35227.346145 # average overall mshr miss latency -system.cpu.dcache.demand_hits 169002314 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 602471492 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_hits 169002312 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 602544992 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000117 # miss rate for demand accesses -system.cpu.dcache.demand_misses 19724 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 15431 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_misses 19726 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 15433 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 151230997 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 4293 # number of demand (read+write) MSHR misses @@ -98,14 +98,14 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 169022038 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 30545.096938 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 30545.726047 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 35227.346145 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 169002314 # number of overall hits -system.cpu.dcache.overall_miss_latency 602471492 # number of overall miss cycles +system.cpu.dcache.overall_hits 169002312 # number of overall hits +system.cpu.dcache.overall_miss_latency 602544992 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000117 # miss rate for overall accesses -system.cpu.dcache.overall_misses 19724 # number of overall misses -system.cpu.dcache.overall_mshr_hits 15431 # number of overall MSHR hits +system.cpu.dcache.overall_misses 19726 # number of overall misses +system.cpu.dcache.overall_mshr_hits 15433 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 151230997 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 4293 # number of overall MSHR misses @@ -124,7 +124,7 @@ system.cpu.dcache.replacements 782 # nu system.cpu.dcache.sampled_refs 4177 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 3293.970402 # Cycle average of tags in use -system.cpu.dcache.total_refs 169002561 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 169002559 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 635 # number of writebacks system.cpu.decode.DECODE:BlockedCycles 18875032 # Number of cycles decode is blocked @@ -237,21 +237,21 @@ system.cpu.icache.total_refs 63861348 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 140725 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 50976852 # Number of branches executed +system.cpu.iew.EXEC:branches 50976851 # Number of branches executed system.cpu.iew.EXEC:nop 27164335 # number of nop insts executed system.cpu.iew.EXEC:rate 1.553144 # Inst execution rate system.cpu.iew.EXEC:refs 191842297 # number of memory reference insts executed system.cpu.iew.EXEC:stores 80676625 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 285463488 # num instructions consuming a value -system.cpu.iew.WB:count 415481244 # cumulative count of insts written-back +system.cpu.iew.WB:consumers 285463485 # num instructions consuming a value +system.cpu.iew.WB:count 415481237 # cumulative count of insts written-back system.cpu.iew.WB:fanout 0.703314 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 200770523 # num instructions producing a value +system.cpu.iew.WB:producers 200770520 # num instructions producing a value system.cpu.iew.WB:rate 1.538857 # insts written-back per cycle -system.cpu.iew.WB:sent 416287471 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 6390314 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:sent 416287464 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 6390313 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 2178518 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 124841223 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 239 # Number of dispatched non-speculative instructions @@ -259,8 +259,8 @@ system.cpu.iew.iewDispSquashedInsts 6302760 # Nu system.cpu.iew.iewDispStoreInsts 92324076 # Number of dispatched store instructions system.cpu.iew.iewDispatchedInsts 493447669 # Number of instructions dispatched to IQ system.cpu.iew.iewExecLoadInsts 111165672 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10261542 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 419338657 # Number of executed instructions +system.cpu.iew.iewExecSquashedInsts 10261544 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 419338652 # Number of executed instructions system.cpu.iew.iewIQFullEvents 25079 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 23746 # Number of times the LSQ has become full, causing a stall @@ -278,13 +278,13 @@ system.cpu.iew.lsq.thread.0.squashedLoads 24189228 # N system.cpu.iew.lsq.thread.0.squashedStores 18792674 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 436213 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 847804 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 5542510 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedTakenIncorrect 5542509 # Number of branches that were predicted taken incorrectly system.cpu.ipc 1.391052 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.391052 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 429600199 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0 429600196 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 33581 0.01% # Type of FU issued - IntAlu 166319017 38.71% # Type of FU issued + IntAlu 166319014 38.71% # Type of FU issued IntMult 2152935 0.50% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 35077566 8.17% # Type of FU issued @@ -321,11 +321,11 @@ system.cpu.iq.ISSUE:issued_per_cycle.samples 269852647 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 0 99465935 3685.94% 1 57766030 2140.65% - 2 39984555 1481.72% - 3 29664957 1099.30% - 4 23966119 888.12% - 5 10452564 387.34% - 6 5712017 211.67% + 2 39984554 1481.72% + 3 29664959 1099.30% + 4 23966120 888.12% + 5 10452563 387.34% + 6 5712016 211.67% 7 2252970 83.49% 8 587500 21.77% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 @@ -333,12 +333,12 @@ system.cpu.iq.ISSUE:issued_per_cycle.end_dist system.cpu.iq.ISSUE:rate 1.591151 # Inst issue rate system.cpu.iq.iqInstsAdded 466283095 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 429600199 # Number of instructions issued +system.cpu.iq.iqInstsIssued 429600196 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 239 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqSquashedInstsExamined 89615992 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 918381 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 68228106 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 68228113 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 63866476 # ITB accesses system.cpu.itb.acv 0 # ITB acv system.cpu.itb.hits 63866189 # ITB hits diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout index e6ff44d85..2bc3bdeed 100755 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 18:33:01 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:46 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt index 651cb243c..520bb514f 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3323718 # Simulator instruction rate (inst/s) -host_mem_usage 201288 # Number of bytes of host memory used -host_seconds 119.95 # Real time elapsed on the host -host_tick_rate 1661856596 # Simulator tick rate (ticks/s) +host_inst_rate 3407773 # Simulator instruction rate (inst/s) +host_mem_usage 201328 # Number of bytes of host memory used +host_seconds 116.99 # Real time elapsed on the host +host_tick_rate 1703884563 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 398664595 # Number of instructions simulated sim_seconds 0.199332 # Number of seconds simulated diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout index 913be9f23..bb141923e 100755 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 19:13:17 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:26:02 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/30.eon/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt index 3ff76c5f4..99f2593a9 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1753697 # Simulator instruction rate (inst/s) -host_mem_usage 208744 # Number of bytes of host memory used -host_seconds 227.33 # Real time elapsed on the host -host_tick_rate 2495737915 # Simulator tick rate (ticks/s) +host_inst_rate 1526276 # Simulator instruction rate (inst/s) +host_mem_usage 208780 # Number of bytes of host memory used +host_seconds 261.20 # Real time elapsed on the host +host_tick_rate 2172088412 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 398664609 # Number of instructions simulated sim_seconds 0.567352 # Number of seconds simulated diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout index caf805d08..c8c05bf7d 100755 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 18:58:04 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:22:18 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/30.eon/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/m5stats.txt index 9069620c7..2e0ae6799 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/m5stats.txt @@ -6,15 +6,15 @@ global.BPredUnit.BTBLookups 294213603 # Nu global.BPredUnit.RASInCorrect 3593 # Number of incorrect RAS predictions. global.BPredUnit.condIncorrect 29107758 # Number of conditional branches incorrect global.BPredUnit.condPredicted 233918302 # Number of conditional branches predicted -global.BPredUnit.lookups 349424732 # Number of BP lookups -global.BPredUnit.usedRAS 49888257 # Number of times the RAS was used to get a target. -host_inst_rate 250324 # Simulator instruction rate (inst/s) -host_mem_usage 209520 # Number of bytes of host memory used -host_seconds 7282.75 # Real time elapsed on the host -host_tick_rate 96826033 # Simulator tick rate (ticks/s) +global.BPredUnit.lookups 349424731 # Number of BP lookups +global.BPredUnit.usedRAS 49888256 # Number of times the RAS was used to get a target. +host_inst_rate 157306 # Simulator instruction rate (inst/s) +host_mem_usage 209560 # Number of bytes of host memory used +host_seconds 11589.17 # Real time elapsed on the host +host_tick_rate 60846406 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 118847053 # Number of conflicting loads. memdepunit.memDep.conflictingStores 21034746 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 655954744 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 655954745 # Number of loads inserted to the mem dependence unit. memdepunit.memDep.insertedStores 303651290 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1823043370 # Number of instructions simulated @@ -26,14 +26,14 @@ system.cpu.commit.COM:bw_limited 0 # nu system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle.samples 1310002800 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 603585598 4607.51% - 1 273587002 2088.45% + 0 603585596 4607.51% + 1 273587005 2088.45% 2 174037133 1328.52% - 3 65399709 499.23% - 4 48333002 368.95% - 5 34003109 259.57% - 6 18481317 141.08% - 7 23715686 181.04% + 3 65399708 499.23% + 4 48333001 368.95% + 5 34003110 259.57% + 6 18481318 141.08% + 7 23715685 181.04% 8 68860244 525.65% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -46,21 +46,21 @@ system.cpu.commit.COM:swp_count 0 # Nu system.cpu.commit.branchMispredicts 29095954 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 696013928 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 696013930 # The number of squashed insts skipped by commit system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated system.cpu.cpi 0.773607 # CPI: Cycles Per Instruction system.cpu.cpi_total 0.773607 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 6 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 6 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 465737270 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 37550.777258 # average ReadReq miss latency +system.cpu.dcache.ReadReq_accesses 465737269 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 37550.774879 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34829.991989 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 463802713 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 72644119000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_hits 463802710 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 72644189500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.004154 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1934557 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 475264 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_misses 1934559 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 475266 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 50827163500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.003133 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 1459293 # number of ReadReq MSHR misses @@ -77,35 +77,35 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.000355 # m system.cpu.dcache.WriteReq_mshr_misses 74781 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs 5124.928571 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets 18000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 440.284638 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 440.284636 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 28 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 1 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 143498 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 18000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 676532166 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 37782.431371 # average overall miss latency +system.cpu.dcache.demand_accesses 676532165 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 37782.429340 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 34912.605909 # average overall mshr miss latency -system.cpu.dcache.demand_hits 674038254 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 94226058985 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_hits 674038251 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 94226129485 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.003686 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2493912 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 959838 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_misses 2493914 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 959840 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 53558520998 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002268 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 1534074 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 676532166 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 37782.431371 # average overall miss latency +system.cpu.dcache.overall_accesses 676532165 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 37782.429340 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 34912.605909 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 674038254 # number of overall hits -system.cpu.dcache.overall_miss_latency 94226058985 # number of overall miss cycles +system.cpu.dcache.overall_hits 674038251 # number of overall hits +system.cpu.dcache.overall_miss_latency 94226129485 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.003686 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2493912 # number of overall misses -system.cpu.dcache.overall_mshr_hits 959838 # number of overall MSHR hits +system.cpu.dcache.overall_misses 2493914 # number of overall misses +system.cpu.dcache.overall_mshr_hits 959840 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 53558520998 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002268 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 1534074 # number of overall MSHR misses @@ -124,39 +124,39 @@ system.cpu.dcache.replacements 1526847 # nu system.cpu.dcache.sampled_refs 1530943 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 4095.104513 # Cycle average of tags in use -system.cpu.dcache.total_refs 674050685 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 674050682 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 274499000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 74589 # number of writebacks system.cpu.decode.DECODE:BlockedCycles 32190527 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 12129 # Number of times decode detected a branch misprediction system.cpu.decode.DECODE:BranchResolved 30585324 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 2936172394 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 716337475 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 561391035 # Number of cycles decode is running +system.cpu.decode.DECODE:DecodedInsts 2936172402 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 716337474 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 561391036 # Number of cycles decode is running system.cpu.decode.DECODE:SquashCycles 100159084 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 45706 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:UnblockCycles 83764 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 775959989 # DTB accesses +system.cpu.dtb.accesses 775959987 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 775335045 # DTB hits +system.cpu.dtb.hits 775335043 # DTB hits system.cpu.dtb.misses 624944 # DTB misses -system.cpu.dtb.read_accesses 516992086 # DTB read accesses +system.cpu.dtb.read_accesses 516992085 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 516404964 # DTB read hits +system.cpu.dtb.read_hits 516404963 # DTB read hits system.cpu.dtb.read_misses 587122 # DTB read misses -system.cpu.dtb.write_accesses 258967903 # DTB write accesses +system.cpu.dtb.write_accesses 258967902 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 258930081 # DTB write hits +system.cpu.dtb.write_hits 258930080 # DTB write hits system.cpu.dtb.write_misses 37822 # DTB write misses -system.cpu.fetch.Branches 349424732 # Number of branches that fetch encountered +system.cpu.fetch.Branches 349424731 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 348447899 # Number of cache lines fetched system.cpu.fetch.Cycles 928021937 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 4387629 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 3030218621 # Number of instructions fetch has processed +system.cpu.fetch.Insts 3030218619 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 29544622 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.247763 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 348447899 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 290350353 # Number of branches that fetch has predicted taken +system.cpu.fetch.predictedBranches 290350352 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 2.148605 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist.samples 1410161885 @@ -165,9 +165,9 @@ system.cpu.fetch.rateDist.min_value 0 1 53463106 379.13% 2 39766072 282.00% 3 63538024 450.57% - 4 121390718 860.83% + 4 121390719 860.83% 5 35256321 250.02% - 6 38761683 274.87% + 6 38761682 274.87% 7 6988644 49.56% 8 220409277 1563.01% system.cpu.fetch.rateDist.max_value 8 @@ -237,30 +237,30 @@ system.cpu.icache.total_refs 348437250 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 157025 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 274534146 # Number of branches executed +system.cpu.iew.EXEC:branches 274534145 # Number of branches executed system.cpu.iew.EXEC:nop 329178061 # number of nop insts executed system.cpu.iew.EXEC:rate 1.421117 # Inst execution rate -system.cpu.iew.EXEC:refs 776495505 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 258968901 # Number of stores executed +system.cpu.iew.EXEC:refs 776495503 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 258968900 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1631503181 # num instructions consuming a value -system.cpu.iew.WB:count 2002130592 # cumulative count of insts written-back +system.cpu.iew.WB:consumers 1631503179 # num instructions consuming a value +system.cpu.iew.WB:count 2002130585 # cumulative count of insts written-back system.cpu.iew.WB:fanout 0.696431 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1136229271 # num instructions producing a value +system.cpu.iew.WB:producers 1136229268 # num instructions producing a value system.cpu.iew.WB:rate 1.419630 # insts written-back per cycle -system.cpu.iew.WB:sent 2003425038 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 31680134 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:sent 2003425032 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 31680133 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 3459468 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 655954744 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 655954745 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 57 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 62125 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispSquashedInsts 62130 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispStoreInsts 303651290 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2715209776 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 517526604 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 85279851 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 2004227959 # Number of executed instructions +system.cpu.iew.iewDispatchedInsts 2715209778 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 517526603 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 85279852 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 2004227953 # Number of executed instructions system.cpu.iew.iewIQFullEvents 131519 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 3361 # Number of times the LSQ has become full, causing a stall @@ -274,17 +274,17 @@ system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Nu system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 3589 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 4102 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 144359442 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedLoads 144359443 # Number of loads squashed system.cpu.iew.lsq.thread.0.squashedStores 92856159 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 3589 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 816990 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 30863144 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedTakenIncorrect 30863143 # Number of branches that were predicted taken incorrectly system.cpu.ipc 1.292646 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.292646 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 2089507810 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0 2089507805 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 2752 0.00% # Type of FU issued - IntAlu 1204412682 57.64% # Type of FU issued + IntAlu 1204412678 57.64% # Type of FU issued IntMult 17591 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 27851349 1.33% # Type of FU issued @@ -294,11 +294,11 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued MemRead 557993260 26.70% # Type of FU issued - MemWrite 283770832 13.58% # Type of FU issued + MemWrite 283770831 13.58% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 37093549 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt 37093546 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.017752 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available @@ -311,34 +311,34 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 28032979 75.57% # attempts to use FU when none available - MemWrite 9052279 24.40% # attempts to use FU when none available + MemRead 28032977 75.57% # attempts to use FU when none available + MemWrite 9052278 24.40% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle.samples 1410161885 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 537278440 3810.05% - 1 285217725 2022.59% - 2 273546794 1939.83% - 3 154810622 1097.82% - 4 63341839 449.18% - 5 51438518 364.77% - 6 32491112 230.41% - 7 9036667 64.08% + 0 537278436 3810.05% + 1 285217724 2022.59% + 2 273546804 1939.83% + 3 154810620 1097.82% + 4 63341841 449.18% + 5 51438515 364.77% + 6 32491109 230.41% + 7 9036668 64.08% 8 3000168 21.28% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist system.cpu.iq.ISSUE:rate 1.481585 # Inst issue rate -system.cpu.iq.iqInstsAdded 2386031658 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 2089507810 # Number of instructions issued +system.cpu.iq.iqInstsAdded 2386031660 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 2089507805 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 562621265 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 12403595 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 562621267 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 12403599 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 18 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 516017441 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 516017454 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 348448092 # ITB accesses system.cpu.itb.acv 0 # ITB acv system.cpu.itb.hits 348447899 # ITB hits diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stdout b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stdout index 14154444a..7f7e7a869 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 19:15:35 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:45 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt index 841932c00..028814426 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 5368625 # Simulator instruction rate (inst/s) -host_mem_usage 200452 # Number of bytes of host memory used -host_seconds 374.21 # Real time elapsed on the host -host_tick_rate 2684890322 # Simulator tick rate (ticks/s) +host_inst_rate 3237524 # Simulator instruction rate (inst/s) +host_mem_usage 200500 # Number of bytes of host memory used +host_seconds 620.53 # Real time elapsed on the host +host_tick_rate 1619110797 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987605 # Number of instructions simulated sim_seconds 1.004711 # Number of seconds simulated diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout index 315befb59..30786b895 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 19:06:43 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:26:39 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/40.perlbmk/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt index 6e65ba05d..c24e3b046 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2795907 # Simulator instruction rate (inst/s) -host_mem_usage 207904 # Number of bytes of host memory used -host_seconds 718.55 # Real time elapsed on the host -host_tick_rate 3917565207 # Simulator tick rate (ticks/s) +host_inst_rate 1407375 # Simulator instruction rate (inst/s) +host_mem_usage 207960 # Number of bytes of host memory used +host_seconds 1427.47 # Real time elapsed on the host +host_tick_rate 1971983298 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987605 # Number of instructions simulated sim_seconds 2.814951 # Number of seconds simulated diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout index f4fff795a..5e421444e 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 21:28:15 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:44 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/40.perlbmk/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt index 60ec1554f..36c3049e3 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 8039248 # Number of BTB hits -global.BPredUnit.BTBLookups 14256738 # Number of BTB lookups +global.BPredUnit.BTBHits 8039250 # Number of BTB hits +global.BPredUnit.BTBLookups 14256744 # Number of BTB lookups global.BPredUnit.RASInCorrect 34579 # Number of incorrect RAS predictions. global.BPredUnit.condIncorrect 452707 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 10551562 # Number of conditional branches predicted -global.BPredUnit.lookups 16249458 # Number of BP lookups +global.BPredUnit.condPredicted 10551565 # Number of conditional branches predicted +global.BPredUnit.lookups 16249463 # Number of BP lookups global.BPredUnit.usedRAS 1941929 # Number of times the RAS was used to get a target. -host_inst_rate 272001 # Simulator instruction rate (inst/s) -host_mem_usage 212988 # Number of bytes of host memory used -host_seconds 292.62 # Real time elapsed on the host -host_tick_rate 92731689 # Simulator tick rate (ticks/s) +host_inst_rate 155507 # Simulator instruction rate (inst/s) +host_mem_usage 212996 # Number of bytes of host memory used +host_seconds 511.82 # Real time elapsed on the host +host_tick_rate 53016132 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 12835812 # Number of conflicting loads. memdepunit.memDep.conflictingStores 11558188 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 23001211 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 16328870 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 23001213 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 16328872 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 79591756 # Number of instructions simulated sim_seconds 0.027135 # Number of seconds simulated -sim_ticks 27134783500 # Number of ticks simulated +sim_ticks 27134794500 # Number of ticks simulated system.cpu.commit.COM:branches 13754477 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 3320893 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 3320894 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 51751153 +system.cpu.commit.COM:committed_per_cycle.samples 51751168 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 22506428 4348.97% - 1 11357580 2194.65% + 0 22506445 4348.97% + 1 11357579 2194.65% 2 5114502 988.29% 3 3560855 688.07% - 4 2552506 493.23% - 5 1532718 296.17% - 6 1008932 194.96% + 4 2552504 493.23% + 5 1532717 296.17% + 6 1008933 194.96% 7 796739 153.96% - 8 3320893 641.70% + 8 3320894 641.70% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -46,21 +46,21 @@ system.cpu.commit.COM:swp_count 0 # Nu system.cpu.commit.branchMispredicts 358406 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 8296832 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8296858 # The number of squashed insts skipped by commit system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated system.cpu.cpi 0.681849 # CPI: Cycles Per Instruction system.cpu.cpi_total 0.681849 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 43 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 20425511 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 30386.313820 # average ReadReq miss latency +system.cpu.dcache.ReadReq_accesses 20425513 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 30386.330224 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20952.491225 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 20275871 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4547008000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_hits 20275869 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4547132000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.007326 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 149640 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 88104 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_misses 149644 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 88108 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 1289332500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.003013 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 61536 # number of ReadReq MSHR misses @@ -77,35 +77,35 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # m system.cpu.dcache.WriteReq_mshr_misses 149789 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs 3166.333333 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets 27000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 165.103746 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 165.103737 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 6 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 1 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 18998 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 27000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 35038888 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 32023.264084 # average overall miss latency +system.cpu.dcache.demand_accesses 35038890 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 32023.260673 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency -system.cpu.dcache.demand_hits 33838927 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 38426667994 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_hits 33838925 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 38426791994 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.034247 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1199961 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 988636 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_misses 1199965 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 988640 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 6644392997 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.006031 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 211325 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 35038888 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 32023.264084 # average overall miss latency +system.cpu.dcache.overall_accesses 35038890 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 32023.260673 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 33838927 # number of overall hits -system.cpu.dcache.overall_miss_latency 38426667994 # number of overall miss cycles +system.cpu.dcache.overall_hits 33838925 # number of overall hits +system.cpu.dcache.overall_miss_latency 38426791994 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.034247 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1199961 # number of overall misses -system.cpu.dcache.overall_mshr_hits 988636 # number of overall MSHR hits +system.cpu.dcache.overall_misses 1199965 # number of overall misses +system.cpu.dcache.overall_mshr_hits 988640 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 6644392997 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.006031 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 211325 # number of overall MSHR misses @@ -123,83 +123,83 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 200933 # number of replacements system.cpu.dcache.sampled_refs 205029 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4077.325791 # Cycle average of tags in use -system.cpu.dcache.total_refs 33851056 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 183212000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tagsinuse 4077.324152 # Cycle average of tags in use +system.cpu.dcache.total_refs 33851054 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 183223000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 147760 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 3553972 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BlockedCycles 3553993 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 95125 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3655574 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 101758297 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 28531772 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 19520692 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1290098 # Number of cycles decode is squashing +system.cpu.decode.DECODE:BranchResolved 3655575 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 101758318 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 28531763 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 19520694 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1290101 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 284696 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 144718 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 36599686 # DTB accesses +system.cpu.decode.DECODE:UnblockCycles 144719 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 36599689 # DTB accesses system.cpu.dtb.acv 39 # DTB access violations -system.cpu.dtb.hits 36425478 # DTB hits +system.cpu.dtb.hits 36425481 # DTB hits system.cpu.dtb.misses 174208 # DTB misses -system.cpu.dtb.read_accesses 21541286 # DTB read accesses +system.cpu.dtb.read_accesses 21541288 # DTB read accesses system.cpu.dtb.read_acv 37 # DTB read access violations -system.cpu.dtb.read_hits 21383018 # DTB read hits +system.cpu.dtb.read_hits 21383020 # DTB read hits system.cpu.dtb.read_misses 158268 # DTB read misses -system.cpu.dtb.write_accesses 15058400 # DTB write accesses +system.cpu.dtb.write_accesses 15058401 # DTB write accesses system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_hits 15042460 # DTB write hits +system.cpu.dtb.write_hits 15042461 # DTB write hits system.cpu.dtb.write_misses 15940 # DTB write misses -system.cpu.fetch.Branches 16249458 # Number of branches that fetch encountered +system.cpu.fetch.Branches 16249463 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 13386072 # Number of cache lines fetched -system.cpu.fetch.Cycles 33247227 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 33247230 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 153162 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 103308047 # Number of instructions fetch has processed +system.cpu.fetch.Insts 103308065 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 567638 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.299421 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 13386072 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 9981177 # Number of branches that fetch has predicted taken +system.cpu.fetch.predictedBranches 9981179 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 1.903609 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 53041252 +system.cpu.fetch.rateDist.samples 53041270 system.cpu.fetch.rateDist.min_value 0 - 0 33206262 6260.46% + 0 33206277 6260.46% 1 1871594 352.86% 2 1529415 288.34% 3 1809626 341.17% 4 3985239 751.35% - 5 1867237 352.03% + 5 1867239 352.04% 6 695846 131.19% 7 1111736 209.60% - 8 6964297 1313.00% + 8 6964298 1313.00% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist system.cpu.icache.ReadReq_accesses 13386072 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 9527.365371 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency 9527.179672 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 6037.865388 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 13297365 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 845144000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_hits 13297366 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 845118000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.006627 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 88707 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 2771 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_misses 88706 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 2770 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_miss_latency 518870000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.006420 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 85936 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 154.737476 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 154.737488 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 13386072 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 9527.365371 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency 9527.179672 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency -system.cpu.icache.demand_hits 13297365 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 845144000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_hits 13297366 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 845118000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.006627 # miss rate for demand accesses -system.cpu.icache.demand_misses 88707 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 2771 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_misses 88706 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 2770 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 518870000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.006420 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 85936 # number of demand (read+write) MSHR misses @@ -207,14 +207,14 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 13386072 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 9527.365371 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 9527.179672 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 13297365 # number of overall hits -system.cpu.icache.overall_miss_latency 845144000 # number of overall miss cycles +system.cpu.icache.overall_hits 13297366 # number of overall hits +system.cpu.icache.overall_miss_latency 845118000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.006627 # miss rate for overall accesses -system.cpu.icache.overall_misses 88707 # number of overall misses -system.cpu.icache.overall_mshr_hits 2771 # number of overall MSHR hits +system.cpu.icache.overall_misses 88706 # number of overall misses +system.cpu.icache.overall_mshr_hits 2770 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 518870000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.006420 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 85936 # number of overall MSHR misses @@ -232,40 +232,40 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 83888 # number of replacements system.cpu.icache.sampled_refs 85935 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1916.994932 # Cycle average of tags in use -system.cpu.icache.total_refs 13297365 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1916.994169 # Cycle average of tags in use +system.cpu.icache.total_refs 13297366 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1228316 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 14745483 # Number of branches executed +system.cpu.idleCycles 1228320 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 14745486 # Number of branches executed system.cpu.iew.EXEC:nop 9395656 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.562958 # Inst execution rate -system.cpu.iew.EXEC:refs 36941990 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 15291391 # Number of stores executed +system.cpu.iew.EXEC:rate 1.562957 # Inst execution rate +system.cpu.iew.EXEC:refs 36941993 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 15291392 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 42302247 # num instructions consuming a value -system.cpu.iew.WB:count 84351843 # cumulative count of insts written-back +system.cpu.iew.WB:consumers 42302279 # num instructions consuming a value +system.cpu.iew.WB:count 84351875 # cumulative count of insts written-back system.cpu.iew.WB:fanout 0.765845 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 32396966 # num instructions producing a value +system.cpu.iew.WB:producers 32396987 # num instructions producing a value system.cpu.iew.WB:rate 1.554312 # insts written-back per cycle -system.cpu.iew.WB:sent 84585242 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent 84585274 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 398232 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 627280 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 23001211 # Number of dispatched load instructions +system.cpu.iew.iewBlockCycles 627293 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 23001213 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 5004 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispSquashedInsts 362338 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 16328870 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 98972071 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 21650599 # Number of load instructions executed +system.cpu.iew.iewDispStoreInsts 16328872 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 98972097 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 21650601 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 525286 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 84821030 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 84821059 # Number of executed instructions system.cpu.iew.iewIQFullEvents 11758 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 8922 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1290098 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 44030 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 1290101 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 44031 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 31 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.forwLoads 956127 # Number of loads that had data forwarded from stores @@ -274,17 +274,17 @@ system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Nu system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 16859 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1313 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 2621812 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1484251 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 2621814 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 1484253 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 16859 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 106828 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 291404 # Number of branches that were predicted taken incorrectly system.cpu.ipc 1.466600 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.466600 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 85346316 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0 85346345 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued - IntAlu 47898540 56.12% # Type of FU issued + IntAlu 47898565 56.12% # Type of FU issued IntMult 42953 0.05% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 121655 0.14% # Type of FU issued @@ -293,16 +293,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 53 0.00% # Type of FU issued FloatDiv 38535 0.05% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 21753620 25.49% # Type of FU issued - MemWrite 15368768 18.01% # Type of FU issued + MemRead 21753622 25.49% # Type of FU issued + MemWrite 15368770 18.01% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 979635 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt 979640 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.011478 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 97095 9.91% # attempts to use FU when none available + IntAlu 97100 9.91% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -317,28 +317,28 @@ system.cpu.iq.ISSUE:fu_full.start_dist InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 53041252 +system.cpu.iq.ISSUE:issued_per_cycle.samples 53041270 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 17563400 3311.27% - 1 13937997 2627.77% - 2 8266118 1558.43% - 3 4784811 902.09% - 4 4627571 872.45% - 5 2066742 389.65% - 6 1112371 209.72% - 7 454506 85.69% - 8 227736 42.94% + 0 17563410 3311.27% + 1 13937999 2627.76% + 2 8266125 1558.43% + 3 4784809 902.09% + 4 4627568 872.45% + 5 2066740 389.65% + 6 1112374 209.72% + 7 454507 85.69% + 8 227738 42.94% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist system.cpu.iq.ISSUE:rate 1.572637 # Inst issue rate -system.cpu.iq.iqInstsAdded 89571411 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 85346316 # Number of instructions issued +system.cpu.iq.iqInstsAdded 89571437 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 85346345 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 5004 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 9777285 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 49836 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 9777311 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 49841 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 421 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 6793888 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 6793875 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 13412237 # ITB accesses system.cpu.itb.acv 0 # ITB acv system.cpu.itb.hits 13386072 # ITB hits @@ -354,12 +354,12 @@ system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # system.cpu.l2cache.ReadExReq_mshr_misses 143494 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 147471 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 34138.973013 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31034.558180 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31034.569397 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 102894 # number of ReadReq hits system.cpu.l2cache.ReadReq_miss_latency 1521813000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.302276 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 44577 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1383427500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1383428000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.302276 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 44577 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 6344 # number of UpgradeReq accesses(hits+misses) @@ -383,13 +383,13 @@ system.cpu.l2cache.blocked_cycles_no_targets 0 system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 290965 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 34290.353106 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31186.312616 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31186.315275 # average overall mshr miss latency system.cpu.l2cache.demand_hits 102894 # number of demand (read+write) hits system.cpu.l2cache.demand_miss_latency 6449020999 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.646370 # miss rate for demand accesses system.cpu.l2cache.demand_misses 188071 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 5865241000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 5865241500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.646370 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 188071 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed @@ -397,14 +397,14 @@ system.cpu.l2cache.mshr_cap_events 0 # nu system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 290965 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34290.353106 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31186.312616 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31186.315275 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 102894 # number of overall hits system.cpu.l2cache.overall_miss_latency 6449020999 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.646370 # miss rate for overall accesses system.cpu.l2cache.overall_misses 188071 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 5865241000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 5865241500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.646370 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 188071 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -421,27 +421,27 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 148779 # number of replacements system.cpu.l2cache.sampled_refs 173998 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18483.932532 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 18483.925058 # Cycle average of tags in use system.cpu.l2cache.total_refs 118089 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 120647 # number of writebacks -system.cpu.numCycles 54269568 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 2047036 # Number of cycles rename is blocking +system.cpu.numCycles 54269590 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 2047052 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 64601 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 28934159 # Number of cycles rename is idle +system.cpu.rename.RENAME:IQFullEvents 64606 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 28934151 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 1281103 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:ROBFullEvents 21 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 121625281 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 100952073 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 60736821 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 19265133 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1290098 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 1421425 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 8189940 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:RenameLookups 121625306 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 100952091 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 60736832 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 19265135 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1290101 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1421430 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 8189951 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:serializeStallCycles 83401 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 5265 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 2801985 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 2801993 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 5263 # count of temporary serializing insts renamed system.cpu.timesIdled 42538 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout index 61aa77324..305b9e178 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 18:42:31 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:27:20 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt index fba592412..7b2d6e4f7 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 5277091 # Simulator instruction rate (inst/s) -host_mem_usage 203864 # Number of bytes of host memory used -host_seconds 16.74 # Real time elapsed on the host -host_tick_rate 2641544350 # Simulator tick rate (ticks/s) +host_inst_rate 3156054 # Simulator instruction rate (inst/s) +host_mem_usage 203904 # Number of bytes of host memory used +host_seconds 27.99 # Real time elapsed on the host +host_tick_rate 1579824710 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated sim_seconds 0.044221 # Number of seconds simulated diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout index a2c31ed4b..f78544a3c 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 19:13:00 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:24:43 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt index 828a42be2..4078e993e 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,23 +1,23 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1704355 # Simulator instruction rate (inst/s) -host_mem_usage 211324 # Number of bytes of host memory used -host_seconds 51.83 # Real time elapsed on the host -host_tick_rate 2607795037 # Simulator tick rate (ticks/s) +host_inst_rate 1655989 # Simulator instruction rate (inst/s) +host_mem_usage 211348 # Number of bytes of host memory used +host_seconds 53.35 # Real time elapsed on the host +host_tick_rate 2533794438 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated sim_seconds 0.135169 # Number of seconds simulated -sim_ticks 135168711000 # Number of ticks simulated +sim_ticks 135168766000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 37874.302641 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34874.302641 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 20215873 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2301432000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_avg_miss_latency 37874.600928 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34874.600928 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 20215872 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 2301488000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 60765 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2119137000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 60766 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 2119190000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 60765 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 60766 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 55999.752992 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.752992 # average WriteReq mshr miss latency @@ -30,38 +30,38 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # m system.cpu.dcache.WriteReq_mshr_misses 149793 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 169.742404 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 50768.923527 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 47768.923527 # average overall mshr miss latency -system.cpu.dcache.demand_hits 34679457 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10689803000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_avg_miss_latency 50768.948371 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 47768.948371 # average overall mshr miss latency +system.cpu.dcache.demand_hits 34679456 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 10689859000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.006035 # miss rate for demand accesses -system.cpu.dcache.demand_misses 210558 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 210559 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 10058129000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 10058182000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.006035 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 210558 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 210559 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 50768.923527 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 47768.923527 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 50768.948371 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 47768.948371 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 34679457 # number of overall hits -system.cpu.dcache.overall_miss_latency 10689803000 # number of overall miss cycles +system.cpu.dcache.overall_hits 34679456 # number of overall hits +system.cpu.dcache.overall_miss_latency 10689859000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.006035 # miss rate for overall accesses -system.cpu.dcache.overall_misses 210558 # number of overall misses +system.cpu.dcache.overall_misses 210559 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 10058129000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 10058182000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.006035 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 210558 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 210559 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -73,12 +73,12 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 200247 # number of replacements -system.cpu.dcache.sampled_refs 204343 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 200248 # number of replacements +system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4078.869222 # Cycle average of tags in use -system.cpu.dcache.total_refs 34685672 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 947580000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tagsinuse 4078.872537 # Cycle average of tags in use +system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 947635000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 147714 # number of writebacks system.cpu.dtb.accesses 34987415 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations @@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 74391 # number of replacements system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1871.769418 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1871.768668 # Cycle average of tags in use system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -168,16 +168,16 @@ system.cpu.l2cache.ReadExReq_misses 143578 # nu system.cpu.l2cache.ReadExReq_mshr_miss_latency 5743120000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 143578 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 137201 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses 137202 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 93905 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 2251392000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.315566 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 43296 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1731840000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.315566 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 43296 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 2251444000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.315571 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 43297 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1731880000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.315571 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 43297 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 6215 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 51690.426388 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency @@ -191,38 +191,38 @@ system.cpu.l2cache.Writeback_accesses 147714 # nu system.cpu.l2cache.Writeback_hits 147714 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.630834 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.630830 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 280779 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 280780 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 93905 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9717448000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.665555 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 186874 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 9717500000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.665557 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 186875 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 7474960000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.665555 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 186874 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 7475000000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.665557 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 186875 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 280779 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 280780 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 93905 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9717448000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.665555 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 186874 # number of overall misses +system.cpu.l2cache.overall_miss_latency 9717500000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.665557 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 186875 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 7474960000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.665555 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 186874 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 7475000000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.665557 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 186875 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -234,15 +234,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 147560 # number of replacements -system.cpu.l2cache.sampled_refs 172765 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 147561 # number of replacements +system.cpu.l2cache.sampled_refs 172766 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18255.753819 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 18255.825674 # Cycle average of tags in use system.cpu.l2cache.total_refs 108986 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 120634 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 270337422 # number of cpu cycles simulated +system.cpu.numCycles 270337532 # number of cpu cycles simulated system.cpu.num_insts 88340673 # Number of instructions executed system.cpu.num_refs 35321418 # Number of memory references system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout index 8bed4881a..7c7d8426c 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 21:27:23 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:28:00 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt index 2aa5eaaa5..2cba4195f 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 19647325 # Nu global.BPredUnit.condPredicted 266741494 # Number of conditional branches predicted global.BPredUnit.lookups 345502589 # Number of BP lookups global.BPredUnit.usedRAS 23750300 # Number of times the RAS was used to get a target. -host_inst_rate 152874 # Simulator instruction rate (inst/s) -host_mem_usage 201972 # Number of bytes of host memory used -host_seconds 11356.03 # Real time elapsed on the host -host_tick_rate 65366964 # Simulator tick rate (ticks/s) +host_inst_rate 178472 # Simulator instruction rate (inst/s) +host_mem_usage 202004 # Number of bytes of host memory used +host_seconds 9727.25 # Real time elapsed on the host +host_tick_rate 76312348 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 127392983 # Number of conflicting loads. memdepunit.memDep.conflictingStores 67515291 # Number of conflicting stores. memdepunit.memDep.insertedLoads 621608435 # Number of loads inserted to the mem dependence unit. diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout index bf92c70e1..46c21a733 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 19:13:16 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:46 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt index c3eb995b5..a74bbb7e5 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3454414 # Simulator instruction rate (inst/s) -host_mem_usage 193640 # Number of bytes of host memory used -host_seconds 526.80 # Real time elapsed on the host -host_tick_rate 1733469179 # Simulator tick rate (ticks/s) +host_inst_rate 3337847 # Simulator instruction rate (inst/s) +host_mem_usage 193672 # Number of bytes of host memory used +host_seconds 545.20 # Real time elapsed on the host +host_tick_rate 1674974438 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780127 # Number of instructions simulated sim_seconds 0.913189 # Number of seconds simulated diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout index 2550b2dca..6c0c37f87 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 18:32:56 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:45 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt index 65a250806..027e53548 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2843037 # Simulator instruction rate (inst/s) -host_mem_usage 201092 # Number of bytes of host memory used -host_seconds 640.08 # Real time elapsed on the host -host_tick_rate 4261930074 # Simulator tick rate (ticks/s) +host_inst_rate 1294592 # Simulator instruction rate (inst/s) +host_mem_usage 201124 # Number of bytes of host memory used +host_seconds 1405.68 # Real time elapsed on the host +host_tick_rate 1940692275 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780127 # Number of instructions simulated sim_seconds 2.727991 # Number of seconds simulated diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout index e112321fe..15467090e 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 18:47:24 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:45 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt index 8c4b78811..bf979a603 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 1946248 # Nu global.BPredUnit.condPredicted 14605230 # Number of conditional branches predicted global.BPredUnit.lookups 19468548 # Number of BP lookups global.BPredUnit.usedRAS 1719783 # Number of times the RAS was used to get a target. -host_inst_rate 134854 # Simulator instruction rate (inst/s) -host_mem_usage 207240 # Number of bytes of host memory used -host_seconds 624.23 # Real time elapsed on the host -host_tick_rate 65390701 # Simulator tick rate (ticks/s) +host_inst_rate 123995 # Simulator instruction rate (inst/s) +host_mem_usage 207276 # Number of bytes of host memory used +host_seconds 678.90 # Real time elapsed on the host +host_tick_rate 60124800 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 17216078 # Number of conflicting loads. memdepunit.memDep.conflictingStores 5041116 # Number of conflicting stores. memdepunit.memDep.insertedLoads 33976826 # Number of loads inserted to the mem dependence unit. @@ -21,20 +21,20 @@ sim_insts 84179709 # Nu sim_seconds 0.040819 # Number of seconds simulated sim_ticks 40818658500 # Number of ticks simulated system.cpu.commit.COM:branches 10240685 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 2855803 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 2855802 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 73457195 +system.cpu.commit.COM:committed_per_cycle.samples 73457196 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 36278942 4938.79% - 1 18156305 2471.69% - 2 7455514 1014.95% - 3 3880418 528.26% + 0 36278941 4938.79% + 1 18156304 2471.68% + 2 7455517 1014.95% + 3 3880419 528.26% 4 2046448 278.59% 5 1301140 177.13% 6 721823 98.26% 7 760802 103.57% - 8 2855803 388.77% + 8 2855802 388.77% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -54,14 +54,14 @@ system.cpu.cpi_total 0.969798 # CP system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits system.cpu.dcache.ReadReq_accesses 23402422 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 30625.144175 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32084.980237 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 30623.414072 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32082.015810 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 23401555 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 26552000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 26550500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000037 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 867 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 361 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 16235000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 16233500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 506 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) @@ -84,29 +84,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 26497 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 29903525 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 35255.478247 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35297.410692 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 35255.314688 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35296.774289 # average overall mshr miss latency system.cpu.dcache.demand_hits 29894354 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 323327991 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 323326491 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000307 # miss rate for demand accesses system.cpu.dcache.demand_misses 9171 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 6814 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 83195997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 83194497 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000079 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 2357 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 29903525 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 35255.478247 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35297.410692 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 35255.314688 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35296.774289 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 29894354 # number of overall hits -system.cpu.dcache.overall_miss_latency 323327991 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 323326491 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000307 # miss rate for overall accesses system.cpu.dcache.overall_misses 9171 # number of overall misses system.cpu.dcache.overall_mshr_hits 6814 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 83195997 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 83194497 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000079 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 2357 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -123,7 +123,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 159 # number of replacements system.cpu.dcache.sampled_refs 2240 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1458.381237 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1458.398369 # Cycle average of tags in use system.cpu.dcache.total_refs 29894629 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 105 # number of writebacks @@ -131,7 +131,7 @@ system.cpu.decode.DECODE:BlockedCycles 3781084 # Nu system.cpu.decode.DECODE:BranchMispred 12597 # Number of times decode detected a branch misprediction system.cpu.decode.DECODE:BranchResolved 3039308 # Number of times decode resolved a branch system.cpu.decode.DECODE:DecodedInsts 162679523 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 39569073 # Number of cycles decode is idle +system.cpu.decode.DECODE:IdleCycles 39569074 # Number of cycles decode is idle system.cpu.decode.DECODE:RunCycles 29917869 # Number of cycles decode is running system.cpu.decode.DECODE:SquashCycles 8071146 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 45156 # Number of squashed instructions handled by decode @@ -159,9 +159,9 @@ system.cpu.fetch.icacheStallCycles 19230003 # Nu system.cpu.fetch.predictedBranches 14728574 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 2.052430 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 81528342 +system.cpu.fetch.rateDist.samples 81528343 system.cpu.fetch.rateDist.min_value 0 - 0 50560377 6201.57% + 0 50560378 6201.57% 1 3114212 381.98% 2 2012618 246.86% 3 3505366 429.96% @@ -236,19 +236,19 @@ system.cpu.icache.tagsinuse 1543.991602 # Cy system.cpu.icache.total_refs 19218965 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 108976 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 108975 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.EXEC:branches 12812003 # Number of branches executed system.cpu.iew.EXEC:nop 12599027 # number of nop insts executed system.cpu.iew.EXEC:rate 1.247521 # Inst execution rate system.cpu.iew.EXEC:refs 31962516 # number of memory reference insts executed system.cpu.iew.EXEC:stores 7194632 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 90937299 # num instructions consuming a value +system.cpu.iew.WB:consumers 90937302 # num instructions consuming a value system.cpu.iew.WB:count 99943821 # cumulative count of insts written-back system.cpu.iew.WB:fanout 0.723990 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 65837671 # num instructions producing a value +system.cpu.iew.WB:producers 65837672 # num instructions producing a value system.cpu.iew.WB:rate 1.224242 # insts written-back per cycle system.cpu.iew.WB:sent 100859242 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 2125730 # Number of branch mispredicts detected at execute @@ -317,11 +317,11 @@ system.cpu.iq.ISSUE:fu_full.start_dist InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 81528342 +system.cpu.iq.ISSUE:issued_per_cycle.samples 81528343 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 0 35305774 4330.49% - 1 18904883 2318.81% - 2 11574998 1419.75% + 1 18904885 2318.81% + 2 11574997 1419.75% 3 6762756 829.50% 4 5075415 622.53% 5 2394533 293.71% @@ -353,13 +353,13 @@ system.cpu.l2cache.ReadExReq_mshr_miss_latency 54690500 system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 1735 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 10561 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34278.518519 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31080.296296 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34278.222222 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31080 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 7186 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 115690000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 115689000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.319572 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 3375 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 104896000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 104895000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.319572 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 3375 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 123 # number of UpgradeReq accesses(hits+misses) @@ -382,29 +382,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 3000 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 12296 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34416.634051 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31230.234834 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 34416.438356 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31230.039139 # average overall mshr miss latency system.cpu.l2cache.demand_hits 7186 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 175869000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 175868000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.415582 # miss rate for demand accesses system.cpu.l2cache.demand_misses 5110 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 159586500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 159585500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.415582 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 5110 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 12296 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34416.634051 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31230.234834 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 34416.438356 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31230.039139 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 7186 # number of overall hits -system.cpu.l2cache.overall_miss_latency 175869000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 175868000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.415582 # miss rate for overall accesses system.cpu.l2cache.overall_misses 5110 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 159586500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 159585500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.415582 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 5110 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -421,7 +421,7 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 3331 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2244.752447 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2244.769579 # Cycle average of tags in use system.cpu.l2cache.total_refs 7171 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks @@ -429,7 +429,7 @@ system.cpu.numCycles 81637318 # nu system.cpu.rename.RENAME:BlockCycles 1761024 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 964182 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 40833182 # Number of cycles rename is idle +system.cpu.rename.RENAME:IdleCycles 40833183 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 973065 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:RenameLookups 202958583 # Number of register rename lookups that rename has made system.cpu.rename.RENAME:RenamedInsts 157334532 # Number of instructions processed by rename diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout index 7f155cd9b..4aef79cf1 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout @@ -5,14 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 21:16:59 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:29:52 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/alpha/tru64/o3-timing -Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav -Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt index f322d0c86..fd63e8611 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 5620505 # Simulator instruction rate (inst/s) -host_mem_usage 198560 # Number of bytes of host memory used -host_seconds 16.35 # Real time elapsed on the host -host_tick_rate 2810224606 # Simulator tick rate (ticks/s) +host_inst_rate 2797283 # Simulator instruction rate (inst/s) +host_mem_usage 198592 # Number of bytes of host memory used +host_seconds 32.85 # Real time elapsed on the host +host_tick_rate 1398634763 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated sim_seconds 0.045952 # Number of seconds simulated diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout index e5e1bfe2b..17a346373 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout @@ -5,14 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 19:15:18 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:45 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/alpha/tru64/simple-atomic -Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sav -Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt index e6e809818..3b3e2ccb7 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,23 +1,23 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1922347 # Simulator instruction rate (inst/s) -host_mem_usage 206016 # Number of bytes of host memory used -host_seconds 47.81 # Real time elapsed on the host -host_tick_rate 2483835101 # Simulator tick rate (ticks/s) +host_inst_rate 1637033 # Simulator instruction rate (inst/s) +host_mem_usage 206044 # Number of bytes of host memory used +host_seconds 56.14 # Real time elapsed on the host +host_tick_rate 2115189911 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated sim_seconds 0.118747 # Number of seconds simulated -sim_ticks 118747191000 # Number of ticks simulated +sim_ticks 118747246000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 51303.797468 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48303.797468 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 19995724 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 24318000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_avg_miss_latency 51313.684211 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48313.684211 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 19995723 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 24374000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 474 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 22896000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 475 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 22949000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 474 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency @@ -30,38 +30,38 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.000286 # m system.cpu.dcache.WriteReq_mshr_misses 1859 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11923.977948 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 55045.863695 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52045.863695 # average overall mshr miss latency -system.cpu.dcache.demand_hits 26494968 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 128422000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_avg_miss_latency 55046.272494 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 52046.272494 # average overall mshr miss latency +system.cpu.dcache.demand_hits 26494967 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 128478000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000088 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2333 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 2334 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 121423000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 121476000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000088 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2333 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 2334 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 55045.863695 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 52045.863695 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 55046.272494 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 52046.272494 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 26494968 # number of overall hits -system.cpu.dcache.overall_miss_latency 128422000 # number of overall miss cycles +system.cpu.dcache.overall_hits 26494967 # number of overall hits +system.cpu.dcache.overall_miss_latency 128478000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000088 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2333 # number of overall misses +system.cpu.dcache.overall_misses 2334 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 121423000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 121476000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000088 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2333 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 2334 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -74,10 +74,10 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.sampled_refs 2222 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1441.023190 # Cycle average of tags in use -system.cpu.dcache.total_refs 26495079 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1442.022508 # Cycle average of tags in use +system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 104 # number of writebacks system.cpu.dtb.accesses 26497334 # DTB accesses @@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 6681 # number of replacements system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1418.026644 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1418.025998 # Cycle average of tags in use system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -168,16 +168,16 @@ system.cpu.l2cache.ReadExReq_misses 1748 # nu system.cpu.l2cache.ReadExReq_mshr_miss_latency 69920000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 1748 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 8984 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses 8985 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 5942 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 158184000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.338602 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 3042 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 121680000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338602 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 3042 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 158236000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.338676 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 3043 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 121720000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338676 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 3043 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 111 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency @@ -191,38 +191,38 @@ system.cpu.l2cache.Writeback_accesses 104 # nu system.cpu.l2cache.Writeback_hits 104 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.970090 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.969435 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 10732 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 10733 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 5942 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 249080000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.446329 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 4790 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 249132000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.446380 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 4791 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 191600000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.446329 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 4790 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 191640000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.446380 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 4791 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 10732 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 10733 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 5942 # number of overall hits -system.cpu.l2cache.overall_miss_latency 249080000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.446329 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 4790 # number of overall misses +system.cpu.l2cache.overall_miss_latency 249132000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.446380 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 4791 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 191600000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.446329 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 4790 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 191640000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.446380 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 4791 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -235,14 +235,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 3009 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 3010 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2021.060296 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2022.059349 # Cycle average of tags in use system.cpu.l2cache.total_refs 5928 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 237494382 # number of cpu cycles simulated +system.cpu.numCycles 237494492 # number of cpu cycles simulated system.cpu.num_insts 91903056 # Number of instructions executed system.cpu.num_refs 26537141 # Number of memory references system.cpu.workload.PROG:num_syscalls 389 # Number of system calls diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout index 50f9ae74a..a43a9ad37 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout @@ -5,14 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 18:30:06 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 18:41:43 +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:28:54 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/alpha/tru64/simple-timing -Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sav -Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... |