diff options
Diffstat (limited to 'tests/long')
19 files changed, 322 insertions, 305 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout index e75420ce2..8cfa09dc6 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 12 2010 01:43:39 -M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip -M5 started May 12 2010 01:52:49 +M5 compiled Jun 6 2010 03:04:38 +M5 revision ba1a0193c050 7448 default tip +M5 started Jun 6 2010 03:24:00 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 319df7c1b..eda9ea869 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 206060 # Simulator instruction rate (inst/s) -host_mem_usage 206972 # Number of bytes of host memory used -host_seconds 2744.60 # Real time elapsed on the host -host_tick_rate 61062862 # Simulator tick rate (ticks/s) +host_inst_rate 217525 # Simulator instruction rate (inst/s) +host_mem_usage 207124 # Number of bytes of host memory used +host_seconds 2599.94 # Real time elapsed on the host +host_tick_rate 64460403 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated sim_seconds 0.167593 # Number of seconds simulated @@ -23,14 +23,14 @@ system.cpu.commit.COM:committed_per_cycle::samples 323575021 system.cpu.commit.COM:committed_per_cycle::mean 1.860023 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::stdev 2.297815 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 107931872 33.36% 33.36% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 101513205 31.37% 64.73% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 37265964 11.52% 76.25% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 10166735 3.14% 79.39% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 11290718 3.49% 82.88% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 21721468 6.71% 89.59% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 12702626 3.93% 93.52% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 2533807 0.78% 94.30% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 107931872 33.36% 33.36% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 101513205 31.37% 64.73% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 37265964 11.52% 76.25% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 10166735 3.14% 79.39% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 11290718 3.49% 82.88% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 21721468 6.71% 89.59% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 12702626 3.93% 93.52% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 2533807 0.78% 94.30% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::8 18448626 5.70% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle @@ -157,14 +157,14 @@ system.cpu.fetch.rateDist::samples 333428374 # Nu system.cpu.fetch.rateDist::mean 2.096612 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.077342 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 203214688 60.95% 60.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 10311898 3.09% 64.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 15894466 4.77% 68.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 13958250 4.19% 72.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 12033268 3.61% 76.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 13973782 4.19% 80.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 5916300 1.77% 82.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 3411105 1.02% 83.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 203214688 60.95% 60.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 10311898 3.09% 64.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 15894466 4.77% 68.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 13958250 4.19% 72.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 12033268 3.61% 76.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 13973782 4.19% 80.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5916300 1.77% 82.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3411105 1.02% 83.59% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 54714617 16.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) @@ -306,14 +306,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::samples 333428374 system.cpu.iq.ISSUE:issued_per_cycle::mean 1.816052 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.661323 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 91844434 27.55% 27.55% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 66796624 20.03% 47.58% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 82026036 24.60% 72.18% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 37142853 11.14% 83.32% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 29318508 8.79% 92.11% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 13804488 4.14% 96.25% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 11015283 3.30% 99.56% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 983503 0.29% 99.85% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 91844434 27.55% 27.55% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 66796624 20.03% 47.58% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 82026036 24.60% 72.18% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 37142853 11.14% 83.32% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 29318508 8.79% 92.11% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 13804488 4.14% 96.25% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 11015283 3.30% 99.56% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 983503 0.29% 99.85% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::8 496645 0.15% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout index 0c73642e7..ed5277c40 100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing/simout +Redirecting stderr to build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 12 2010 02:45:56 -M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip -M5 started May 12 2010 02:48:22 +M5 compiled Jun 6 2010 04:01:36 +M5 revision ba1a0193c050 7448 default tip +M5 started Jun 6 2010 04:02:01 M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 74618889d..57777fec7 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 141900 # Simulator instruction rate (inst/s) -host_mem_usage 208776 # Number of bytes of host memory used -host_seconds 9905.67 # Real time elapsed on the host -host_tick_rate 109908342 # Simulator tick rate (ticks/s) +host_inst_rate 109148 # Simulator instruction rate (inst/s) +host_mem_usage 208820 # Number of bytes of host memory used +host_seconds 12878.07 # Real time elapsed on the host +host_tick_rate 84540245 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1405618369 # Number of instructions simulated sim_seconds 1.088715 # Number of seconds simulated @@ -23,14 +23,14 @@ system.cpu.commit.COM:committed_per_cycle::samples 1942378796 system.cpu.commit.COM:committed_per_cycle::mean 0.766863 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::stdev 1.200662 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 1072972593 55.24% 55.24% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 568760584 29.28% 84.52% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 118179777 6.08% 90.61% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 122167717 6.29% 96.90% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 27965504 1.44% 98.34% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 8603273 0.44% 98.78% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 11084471 0.57% 99.35% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 4630000 0.24% 99.59% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 1072972593 55.24% 55.24% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 568760584 29.28% 84.52% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 118179777 6.08% 90.61% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 122167717 6.29% 96.90% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 27965504 1.44% 98.34% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 8603273 0.44% 98.78% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 11084471 0.57% 99.35% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 4630000 0.24% 99.59% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::8 8014877 0.41% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle @@ -146,14 +146,14 @@ system.cpu.fetch.rateDist::samples 2175919229 # Nu system.cpu.fetch.rateDist::mean 1.693886 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 2.844671 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 1350521444 62.07% 62.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 247724506 11.38% 73.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 78785496 3.62% 77.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 36714251 1.69% 78.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 82505145 3.79% 82.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 39097939 1.80% 84.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 30045371 1.38% 85.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 19662444 0.90% 86.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1350521444 62.07% 62.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 247724506 11.38% 73.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 78785496 3.62% 77.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 36714251 1.69% 78.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 82505145 3.79% 82.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 39097939 1.80% 84.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 30045371 1.38% 85.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 19662444 0.90% 86.63% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 290862633 13.37% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) @@ -295,14 +295,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::samples 2175919229 system.cpu.iq.ISSUE:issued_per_cycle::mean 0.909807 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.157368 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 1068255963 49.09% 49.09% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 579314637 26.62% 75.72% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 292421261 13.44% 89.16% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 161809686 7.44% 96.59% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 50369072 2.31% 98.91% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 14937591 0.69% 99.60% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 7897011 0.36% 99.96% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 777368 0.04% 99.99% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 1068255963 49.09% 49.09% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 579314637 26.62% 75.72% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 292421261 13.44% 89.16% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 161809686 7.44% 96.59% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 50369072 2.31% 98.91% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 14937591 0.69% 99.60% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 7897011 0.36% 99.96% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 777368 0.04% 99.99% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::8 136640 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr index cde3a8c1f..83c71fc5c 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr @@ -2,6 +2,4 @@ warn: Sockets disabled, not accepting terminal connections For more information see: http://www.m5sim.org/warn/8742226b warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: 125751000: Trying to launch CPU number 1! -For more information see: http://www.m5sim.org/warn/8f7d2563 hack: be nice to actually delete the event here diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index fa47c5c0e..a7674462a 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual/simout +Redirecting stderr to build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,12 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 12 2010 02:36:15 -M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip -M5 started May 12 2010 02:36:17 +M5 compiled Jun 6 2010 03:50:36 +M5 revision ba1a0193c050 7448 default tip +M5 started Jun 6 2010 03:50:38 M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... +info: Launching CPU 1 @ 125751000 Exiting @ tick 1907689250500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 3e4d779fa..a30544a1e 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 123563 # Simulator instruction rate (inst/s) -host_mem_usage 293920 # Number of bytes of host memory used -host_seconds 454.60 # Real time elapsed on the host -host_tick_rate 4196424819 # Simulator tick rate (ticks/s) +host_inst_rate 140959 # Simulator instruction rate (inst/s) +host_mem_usage 294084 # Number of bytes of host memory used +host_seconds 398.50 # Real time elapsed on the host +host_tick_rate 4787234846 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 56171530 # Number of instructions simulated sim_seconds 1.907689 # Number of seconds simulated @@ -23,14 +23,14 @@ system.cpu0.commit.COM:committed_per_cycle::samples 73665183 system.cpu0.commit.COM:committed_per_cycle::mean 0.571097 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::stdev 1.330919 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::0-1 55454240 75.28% 75.28% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::1-2 8064036 10.95% 86.23% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::2-3 4660922 6.33% 92.55% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::3-4 2129949 2.89% 95.44% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::4-5 1559149 2.12% 97.56% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::5-6 477103 0.65% 98.21% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::6-7 293859 0.40% 98.61% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::7-8 298455 0.41% 99.01% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::0 55454240 75.28% 75.28% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::1 8064036 10.95% 86.23% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::2 4660922 6.33% 92.55% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::3 2129949 2.89% 95.44% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::4 1559149 2.12% 97.56% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::5 477103 0.65% 98.21% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::6 293859 0.40% 98.61% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::7 298455 0.41% 99.01% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::8 727470 0.99% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle @@ -233,14 +233,14 @@ system.cpu0.fetch.rateDist::samples 74812186 # Nu system.cpu0.fetch.rateDist::mean 0.732846 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::stdev 2.023907 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0-1 64104390 85.69% 85.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1-2 792685 1.06% 86.75% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2-3 1475450 1.97% 88.72% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3-4 663490 0.89% 89.61% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4-5 2416214 3.23% 92.84% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5-6 489674 0.65% 93.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6-7 557514 0.75% 94.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7-8 868698 1.16% 95.40% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 64104390 85.69% 85.69% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 792685 1.06% 86.75% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1475450 1.97% 88.72% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 663490 0.89% 89.61% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2416214 3.23% 92.84% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 489674 0.65% 93.49% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 557514 0.75% 94.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 868698 1.16% 95.40% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::8 3444071 4.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) @@ -413,14 +413,14 @@ system.cpu0.iq.ISSUE:issued_per_cycle::samples 74812186 system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.578231 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.135171 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::0-1 52955077 70.78% 70.78% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::1-2 11074556 14.80% 85.59% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::2-3 4848896 6.48% 92.07% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::3-4 2948908 3.94% 96.01% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::4-5 1827398 2.44% 98.45% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::5-6 727506 0.97% 99.43% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::6-7 332197 0.44% 99.87% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::7-8 81828 0.11% 99.98% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::0 52955077 70.78% 70.78% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::1 11074556 14.80% 85.59% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::2 4848896 6.48% 92.07% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::3 2948908 3.94% 96.01% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::4 1827398 2.44% 98.45% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::5 727506 0.97% 99.43% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::6 332197 0.44% 99.87% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::7 81828 0.11% 99.98% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::8 15820 0.02% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle @@ -576,14 +576,14 @@ system.cpu1.commit.COM:committed_per_cycle::samples 33118489 system.cpu1.commit.COM:committed_per_cycle::mean 0.526612 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::stdev 1.338198 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::0-1 25969028 78.41% 78.41% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::1-2 3179753 9.60% 88.01% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::2-3 1522948 4.60% 92.61% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::3-4 936064 2.83% 95.44% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::4-5 628296 1.90% 97.34% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::5-6 237537 0.72% 98.05% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::6-7 164527 0.50% 98.55% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::7-8 123974 0.37% 98.92% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::0 25969028 78.41% 78.41% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::1 3179753 9.60% 88.01% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::2 1522948 4.60% 92.61% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::3 936064 2.83% 95.44% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::4 628296 1.90% 97.34% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::5 237537 0.72% 98.05% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::6 164527 0.50% 98.55% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::7 123974 0.37% 98.92% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::8 356362 1.08% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle @@ -786,14 +786,14 @@ system.cpu1.fetch.rateDist::samples 33684585 # Nu system.cpu1.fetch.rateDist::mean 0.705985 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::stdev 2.028331 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0-1 29238127 86.80% 86.80% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1-2 297283 0.88% 87.68% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2-3 597287 1.77% 89.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3-4 350001 1.04% 90.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4-5 693611 2.06% 92.55% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5-6 228580 0.68% 93.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6-7 280979 0.83% 94.07% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7-8 354019 1.05% 95.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 29238127 86.80% 86.80% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 297283 0.88% 87.68% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 597287 1.77% 89.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 350001 1.04% 90.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 693611 2.06% 92.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 228580 0.68% 93.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 280979 0.83% 94.07% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 354019 1.05% 95.12% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::8 1644698 4.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) @@ -966,14 +966,14 @@ system.cpu1.iq.ISSUE:issued_per_cycle::samples 33684585 system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.541162 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.162170 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::0-1 25088136 74.48% 74.48% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::1-2 4124812 12.25% 86.72% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::2-3 1756786 5.22% 91.94% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::3-4 1209447 3.59% 95.53% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::4-5 865609 2.57% 98.10% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::5-6 413218 1.23% 99.33% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::6-7 164057 0.49% 99.81% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::7-8 50935 0.15% 99.97% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::0 25088136 74.48% 74.48% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::1 4124812 12.25% 86.72% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::2 1756786 5.22% 91.94% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::3 1209447 3.59% 95.53% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::4 865609 2.57% 98.10% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::5 413218 1.23% 99.33% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::6 164057 0.49% 99.81% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::7 50935 0.15% 99.97% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::8 11585 0.03% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index f6482ad23..6a353dabf 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3/simout +Redirecting stderr to build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 12 2010 02:36:15 -M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip -M5 started May 12 2010 02:37:22 +M5 compiled Jun 6 2010 03:50:36 +M5 revision ba1a0193c050 7448 default tip +M5 started Jun 6 2010 03:51:37 M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 6ec7aca0a..867b96dc0 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 154746 # Simulator instruction rate (inst/s) -host_mem_usage 291744 # Number of bytes of host memory used -host_seconds 343.04 # Real time elapsed on the host -host_tick_rate 5443609822 # Simulator tick rate (ticks/s) +host_inst_rate 146942 # Simulator instruction rate (inst/s) +host_mem_usage 291780 # Number of bytes of host memory used +host_seconds 361.25 # Real time elapsed on the host +host_tick_rate 5169110276 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 53083414 # Number of instructions simulated sim_seconds 1.867360 # Number of seconds simulated @@ -23,14 +23,14 @@ system.cpu.commit.COM:committed_per_cycle::samples 100508484 system.cpu.commit.COM:committed_per_cycle::mean 0.559927 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::stdev 1.327303 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 76371825 75.99% 75.99% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 10652369 10.60% 86.58% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 5995069 5.96% 92.55% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 2948172 2.93% 95.48% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 2094039 2.08% 97.57% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 649751 0.65% 98.21% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 415244 0.41% 98.62% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 382142 0.38% 99.01% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 76371825 75.99% 75.99% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 10652369 10.60% 86.58% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 5995069 5.96% 92.55% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 2948172 2.93% 95.48% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 2094039 2.08% 97.57% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 649751 0.65% 98.21% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 415244 0.41% 98.62% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 382142 0.38% 99.01% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::8 999873 0.99% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle @@ -235,14 +235,14 @@ system.cpu.fetch.rateDist::samples 102147731 # Nu system.cpu.fetch.rateDist::mean 0.727155 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 2.025450 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 87794438 85.95% 85.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 1023092 1.00% 86.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 1967534 1.93% 88.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 960313 0.94% 89.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 2993138 2.93% 92.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 661201 0.65% 93.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 802863 0.79% 94.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 1218814 1.19% 95.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 87794438 85.95% 85.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1023092 1.00% 86.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1967534 1.93% 88.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 960313 0.94% 89.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2993138 2.93% 92.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 661201 0.65% 93.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 802863 0.79% 94.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1218814 1.19% 95.37% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 4726338 4.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) @@ -415,14 +415,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::samples 102147731 system.cpu.iq.ISSUE:issued_per_cycle::mean 0.569292 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.137713 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 73060847 71.52% 71.52% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 14641510 14.33% 85.86% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 6377407 6.24% 92.10% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 3918998 3.84% 95.94% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 2506307 2.45% 98.39% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 1046173 1.02% 99.42% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 456673 0.45% 99.86% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 116088 0.11% 99.98% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 73060847 71.52% 71.52% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 14641510 14.33% 85.86% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 6377407 6.24% 92.10% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 3918998 3.84% 95.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 2506307 2.45% 98.39% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 1046173 1.02% 99.42% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 456673 0.45% 99.86% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 116088 0.11% 99.98% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::8 23728 0.02% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout index d81198635..a08242399 100755 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 12 2010 01:43:39 -M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip -M5 started May 12 2010 01:43:41 +M5 compiled Jun 6 2010 03:04:38 +M5 revision ba1a0193c050 7448 default tip +M5 started Jun 6 2010 03:04:42 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt index ca20bd45c..f61637969 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 229808 # Simulator instruction rate (inst/s) -host_mem_usage 213388 # Number of bytes of host memory used -host_seconds 1634.30 # Real time elapsed on the host -host_tick_rate 82387662 # Simulator tick rate (ticks/s) +host_inst_rate 242260 # Simulator instruction rate (inst/s) +host_mem_usage 213404 # Number of bytes of host memory used +host_seconds 1550.30 # Real time elapsed on the host +host_tick_rate 86851686 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 375574819 # Number of instructions simulated sim_seconds 0.134646 # Number of seconds simulated @@ -23,14 +23,14 @@ system.cpu.commit.COM:committed_per_cycle::samples 253935739 system.cpu.commit.COM:committed_per_cycle::mean 1.569943 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::stdev 2.243237 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 122688628 48.31% 48.31% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 50190176 19.76% 68.08% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 18710011 7.37% 75.45% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 19547996 7.70% 83.15% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 12735073 5.02% 88.16% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 8256826 3.25% 91.41% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 5486679 2.16% 93.57% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 3296888 1.30% 94.87% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 122688628 48.31% 48.31% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 50190176 19.76% 68.08% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 18710011 7.37% 75.45% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 19547996 7.70% 83.15% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 12735073 5.02% 88.16% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 8256826 3.25% 91.41% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 5486679 2.16% 93.57% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 3296888 1.30% 94.87% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::8 13023462 5.13% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle @@ -157,14 +157,14 @@ system.cpu.fetch.rateDist::samples 269151403 # Nu system.cpu.fetch.rateDist::mean 2.021852 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.019136 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 165698966 61.56% 61.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 11106934 4.13% 65.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 11530416 4.28% 69.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 6307474 2.34% 72.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 14437862 5.36% 77.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 9686725 3.60% 81.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 7134176 2.65% 83.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 3886825 1.44% 85.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 165698966 61.56% 61.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 11106934 4.13% 65.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 11530416 4.28% 69.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6307474 2.34% 72.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 14437862 5.36% 77.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9686725 3.60% 81.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 7134176 2.65% 83.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3886825 1.44% 85.38% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 39362025 14.62% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) @@ -306,14 +306,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::samples 269151403 system.cpu.iq.ISSUE:issued_per_cycle::mean 1.593279 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.717169 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 98731931 36.68% 36.68% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 57661044 21.42% 58.11% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 40586976 15.08% 73.19% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 29421704 10.93% 84.12% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 23908046 8.88% 93.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 10239078 3.80% 96.80% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 5871323 2.18% 98.99% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 2172785 0.81% 99.79% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 98731931 36.68% 36.68% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 57661044 21.42% 58.11% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 40586976 15.08% 73.19% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 29421704 10.93% 84.12% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 23908046 8.88% 93.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 10239078 3.80% 96.80% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 5871323 2.18% 98.99% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 2172785 0.81% 99.79% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::8 558516 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout index 4e9d17041..c04d8ba25 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 12 2010 01:43:39 -M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip -M5 started May 12 2010 01:44:11 +M5 compiled Jun 6 2010 03:04:38 +M5 revision ba1a0193c050 7448 default tip +M5 started Jun 6 2010 03:07:52 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 88b7dc5dd..b9fdde085 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 173583 # Simulator instruction rate (inst/s) -host_mem_usage 213764 # Number of bytes of host memory used -host_seconds 10502.41 # Real time elapsed on the host -host_tick_rate 66694888 # Simulator tick rate (ticks/s) +host_inst_rate 150652 # Simulator instruction rate (inst/s) +host_mem_usage 214040 # Number of bytes of host memory used +host_seconds 12101.02 # Real time elapsed on the host +host_tick_rate 57884111 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1823043370 # Number of instructions simulated sim_seconds 0.700457 # Number of seconds simulated @@ -23,14 +23,14 @@ system.cpu.commit.COM:committed_per_cycle::samples 1302157693 system.cpu.commit.COM:committed_per_cycle::mean 1.542814 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::stdev 2.203929 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 596380613 45.80% 45.80% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 273242120 20.98% 66.78% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 173533589 13.33% 80.11% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 65306568 5.02% 85.13% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 48690140 3.74% 88.86% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 33944722 2.61% 91.47% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 18456166 1.42% 92.89% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 23292764 1.79% 94.68% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 596380613 45.80% 45.80% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 273242120 20.98% 66.78% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 173533589 13.33% 80.11% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 65306568 5.02% 85.13% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 48690140 3.74% 88.86% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 33944722 2.61% 91.47% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 18456166 1.42% 92.89% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 23292764 1.79% 94.68% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::8 69311011 5.32% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle @@ -157,14 +157,14 @@ system.cpu.fetch.rateDist::samples 1400755789 # Nu system.cpu.fetch.rateDist::mean 2.153055 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.032526 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 824834992 58.88% 58.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 53206817 3.80% 62.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 38924738 2.78% 65.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 62366133 4.45% 69.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 120532729 8.60% 78.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 35808657 2.56% 81.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 38526871 2.75% 83.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 7024237 0.50% 84.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 824834992 58.88% 58.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 53206817 3.80% 62.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 38924738 2.78% 65.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 62366133 4.45% 69.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 120532729 8.60% 78.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 35808657 2.56% 81.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38526871 2.75% 83.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7024237 0.50% 84.33% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 219530615 15.67% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) @@ -306,14 +306,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::samples 1400755789 system.cpu.iq.ISSUE:issued_per_cycle::mean 1.487303 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.636763 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 530170444 37.85% 37.85% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 284246633 20.29% 58.14% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 272843485 19.48% 77.62% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 155156600 11.08% 88.70% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 63055400 4.50% 93.20% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 50914622 3.63% 96.83% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 32393130 2.31% 99.15% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 9012045 0.64% 99.79% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 530170444 37.85% 37.85% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 284246633 20.29% 58.14% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 272843485 19.48% 77.62% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 155156600 11.08% 88.70% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 63055400 4.50% 93.20% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 50914622 3.63% 96.83% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 32393130 2.31% 99.15% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 9012045 0.64% 99.79% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::8 2963430 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout index 361003678..409031e84 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 12 2010 01:43:39 -M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip -M5 started May 12 2010 01:52:23 +M5 compiled Jun 6 2010 03:04:38 +M5 revision ba1a0193c050 7448 default tip +M5 started Jun 6 2010 03:07:19 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 182c67d63..7506a8fb6 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 184348 # Simulator instruction rate (inst/s) -host_mem_usage 216288 # Number of bytes of host memory used -host_seconds 431.75 # Real time elapsed on the host -host_tick_rate 62947203 # Simulator tick rate (ticks/s) +host_inst_rate 172331 # Simulator instruction rate (inst/s) +host_mem_usage 216300 # Number of bytes of host memory used +host_seconds 461.86 # Real time elapsed on the host +host_tick_rate 58843672 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 79591756 # Number of instructions simulated sim_seconds 0.027177 # Number of seconds simulated @@ -23,14 +23,14 @@ system.cpu.commit.COM:committed_per_cycle::samples 51827032 system.cpu.commit.COM:committed_per_cycle::mean 1.704529 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::stdev 2.326613 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 22597378 43.60% 43.60% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 11350095 21.90% 65.50% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 5102840 9.85% 75.35% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 3559000 6.87% 82.21% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 2567186 4.95% 87.17% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 1515845 2.92% 90.09% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 1002832 1.93% 92.03% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 811912 1.57% 93.59% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 22597378 43.60% 43.60% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 11350095 21.90% 65.50% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 5102840 9.85% 75.35% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 3559000 6.87% 82.21% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 2567186 4.95% 87.17% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 1515845 2.92% 90.09% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 1002832 1.93% 92.03% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 811912 1.57% 93.59% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::8 3319944 6.41% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle @@ -157,14 +157,14 @@ system.cpu.fetch.rateDist::samples 53133675 # Nu system.cpu.fetch.rateDist::mean 1.946813 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 2.939021 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 33232285 62.54% 62.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 1906283 3.59% 66.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 1507954 2.84% 68.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 1896878 3.57% 72.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 3940139 7.42% 79.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 1882924 3.54% 83.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 690153 1.30% 84.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 1104079 2.08% 86.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 33232285 62.54% 62.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1906283 3.59% 66.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1507954 2.84% 68.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1896878 3.57% 72.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3940139 7.42% 79.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1882924 3.54% 83.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 690153 1.30% 84.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1104079 2.08% 86.88% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 6972980 13.12% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) @@ -306,14 +306,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::samples 53133675 system.cpu.iq.ISSUE:issued_per_cycle::mean 1.608151 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.716289 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 17599811 33.12% 33.12% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 14135768 26.60% 59.73% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 8101815 15.25% 74.98% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 4767583 8.97% 83.95% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 4587960 8.63% 92.58% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 2114458 3.98% 96.56% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 1132800 2.13% 98.69% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 463918 0.87% 99.57% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 17599811 33.12% 33.12% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 14135768 26.60% 59.73% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 8101815 15.25% 74.98% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 4767583 8.97% 83.95% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 4587960 8.63% 92.58% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 2114458 3.98% 96.56% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 1132800 2.13% 98.69% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 463918 0.87% 99.57% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::8 229562 0.43% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout index d2c3c175b..0be7bd3b3 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 16 2010 18:46:51 -M5 revision 38e5c8a73ea9 7084 default tip -M5 started May 16 2010 18:46:55 +M5 compiled Jun 6 2010 03:04:38 +M5 revision ba1a0193c050 7448 default tip +M5 started Jun 6 2010 03:30:51 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 2b683dcfe..93a32f882 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 144441 # Simulator instruction rate (inst/s) -host_mem_usage 206960 # Number of bytes of host memory used -host_seconds 12019.07 # Real time elapsed on the host -host_tick_rate 61604184 # Simulator tick rate (ticks/s) +host_inst_rate 192033 # Simulator instruction rate (inst/s) +host_mem_usage 206980 # Number of bytes of host memory used +host_seconds 9040.35 # Real time elapsed on the host +host_tick_rate 81902195 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1736043781 # Number of instructions simulated sim_seconds 0.740425 # Number of seconds simulated @@ -23,14 +23,14 @@ system.cpu.commit.COM:committed_per_cycle::samples 1374695730 system.cpu.commit.COM:committed_per_cycle::mean 1.323769 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::stdev 2.099460 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 733755921 53.38% 53.38% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 260590847 18.96% 72.33% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 127148586 9.25% 81.58% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 73808717 5.37% 86.95% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 48837558 3.55% 90.50% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 32392808 2.36% 92.86% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 24165844 1.76% 94.62% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 10806972 0.79% 95.40% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 733755921 53.38% 53.38% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 260590847 18.96% 72.33% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 127148586 9.25% 81.58% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 73808717 5.37% 86.95% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 48837558 3.55% 90.50% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 32392808 2.36% 92.86% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 24165844 1.76% 94.62% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 10806972 0.79% 95.40% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::8 63188477 4.60% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle @@ -167,14 +167,14 @@ system.cpu.fetch.rateDist::samples 1468602609 # Nu system.cpu.fetch.rateDist::mean 1.955835 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 2.862588 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 907478951 61.79% 61.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 48285594 3.29% 65.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 31293098 2.13% 67.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 51463172 3.50% 70.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 124103039 8.45% 79.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 68291233 4.65% 83.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 47448055 3.23% 87.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 37389871 2.55% 89.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 907478951 61.79% 61.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 48285594 3.29% 65.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31293098 2.13% 67.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 51463172 3.50% 70.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 124103039 8.45% 79.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 68291233 4.65% 83.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 47448055 3.23% 87.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 37389871 2.55% 89.59% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 152849596 10.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) @@ -316,14 +316,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::samples 1468602609 system.cpu.iq.ISSUE:issued_per_cycle::mean 1.582741 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.758662 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 577211692 39.30% 39.30% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 268561729 18.29% 57.59% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 245516096 16.72% 74.31% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 137351239 9.35% 83.66% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 112900190 7.69% 91.35% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 73000831 4.97% 96.32% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 43951863 2.99% 99.31% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 8418123 0.57% 99.88% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 577211692 39.30% 39.30% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 268561729 18.29% 57.59% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 245516096 16.72% 74.31% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 137351239 9.35% 83.66% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 112900190 7.69% 91.35% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 73000831 4.97% 96.32% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 43951863 2.99% 99.31% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 8418123 0.57% 99.88% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::8 1690846 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout index 6a7caf9b4..adb770d42 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 12 2010 01:43:39 -M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip -M5 started May 12 2010 01:45:37 +M5 compiled Jun 6 2010 03:04:38 +M5 revision ba1a0193c050 7448 default tip +M5 started Jun 6 2010 03:04:41 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 92d71f0ba..317b399da 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 153450 # Simulator instruction rate (inst/s) -host_mem_usage 210984 # Number of bytes of host memory used -host_seconds 548.58 # Real time elapsed on the host -host_tick_rate 73456175 # Simulator tick rate (ticks/s) +host_inst_rate 133236 # Simulator instruction rate (inst/s) +host_mem_usage 211268 # Number of bytes of host memory used +host_seconds 631.81 # Real time elapsed on the host +host_tick_rate 63779599 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 84179709 # Number of instructions simulated sim_seconds 0.040297 # Number of seconds simulated @@ -23,14 +23,14 @@ system.cpu.commit.COM:committed_per_cycle::samples 72454759 system.cpu.commit.COM:committed_per_cycle::mean 1.268420 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::stdev 1.963909 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 35335976 48.77% 48.77% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 18219580 25.15% 73.92% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 7350657 10.15% 84.06% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 3843959 5.31% 89.37% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 2026400 2.80% 92.16% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 1285963 1.77% 93.94% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 738665 1.02% 94.96% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 745593 1.03% 95.99% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 35335976 48.77% 48.77% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 18219580 25.15% 73.92% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 7350657 10.15% 84.06% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 3843959 5.31% 89.37% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 2026400 2.80% 92.16% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 1285963 1.77% 93.94% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 738665 1.02% 94.96% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 745593 1.03% 95.99% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::8 2907966 4.01% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle @@ -157,14 +157,14 @@ system.cpu.fetch.rateDist::samples 80484719 # Nu system.cpu.fetch.rateDist::mean 2.076420 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.094224 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 50001427 62.13% 62.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 3132178 3.89% 66.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 1884597 2.34% 68.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 3228306 4.01% 72.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 4370184 5.43% 77.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 1507606 1.87% 79.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 1854945 2.30% 81.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 1658454 2.06% 84.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 50001427 62.13% 62.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3132178 3.89% 66.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1884597 2.34% 68.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3228306 4.01% 72.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4370184 5.43% 77.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1507606 1.87% 79.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1854945 2.30% 81.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1658454 2.06% 84.04% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 12847022 15.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) @@ -306,14 +306,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::samples 80484719 system.cpu.iq.ISSUE:issued_per_cycle::mean 1.291184 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.543424 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 34420666 42.77% 42.77% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 18632497 23.15% 65.92% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 11734091 14.58% 80.50% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 6720766 8.35% 88.85% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 5079668 6.31% 95.16% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 2378591 2.96% 98.11% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 1227784 1.53% 99.64% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 245969 0.31% 99.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 34420666 42.77% 42.77% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 18632497 23.15% 65.92% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 11734091 14.58% 80.50% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 6720766 8.35% 88.85% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 5079668 6.31% 95.16% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 2378591 2.96% 98.11% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 1227784 1.53% 99.64% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 245969 0.31% 99.94% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::8 44687 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle |