diff options
Diffstat (limited to 'tests/long')
205 files changed, 4750 insertions, 4688 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini index 85d434144..23a53cd4f 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini @@ -86,6 +86,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +122,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -156,6 +158,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout index 8f9b1263d..ff066f3a4 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 23 2011 05:47:47 -M5 revision Unknown -M5 started Feb 23 2011 05:49:05 -M5 executing on m55-001.pool +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 11:58:24 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index 97f36d33a..74577bc37 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,37 +1,25 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 145740 # Simulator instruction rate (inst/s) -host_mem_usage 390376 # Number of bytes of host memory used -host_seconds 4129.65 # Real time elapsed on the host -host_tick_rate 63356930 # Simulator tick rate (ticks/s) +host_inst_rate 209357 # Simulator instruction rate (inst/s) +host_mem_usage 403360 # Number of bytes of host memory used +host_seconds 2874.78 # Real time elapsed on the host +host_tick_rate 91012809 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated sim_seconds 0.261642 # Number of seconds simulated sim_ticks 261641972500 # Number of ticks simulated -system.cpu.AGEN-Unit.agens 155868116 # Number of Address Generations -system.cpu.Branch-Predictor.BTBHitPct 90.344266 # BTB Hit Percentage -system.cpu.Branch-Predictor.BTBHits 29143677 # Number of BTB hits -system.cpu.Branch-Predictor.BTBLookups 32258469 # Number of BTB lookups -system.cpu.Branch-Predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.Branch-Predictor.condIncorrect 22153653 # Number of conditional branches incorrect -system.cpu.Branch-Predictor.condPredicted 59309256 # Number of conditional branches predicted -system.cpu.Branch-Predictor.lookups 64114012 # Number of BP lookups -system.cpu.Branch-Predictor.predictedNotTaken 31921338 # Number of Branches Predicted As Not Taken (False). -system.cpu.Branch-Predictor.predictedTaken 32192674 # Number of Branches Predicted As Taken (True). -system.cpu.Branch-Predictor.usedRAS 1197609 # Number of times the RAS was used to get a target. -system.cpu.Execution-Unit.executions 419011350 # Number of Instructions Executed. -system.cpu.Execution-Unit.mispredictPct 35.419120 # Percentage of Incorrect Branches Predicts -system.cpu.Execution-Unit.mispredicted 22153653 # Number of Branches Incorrectly Predicted -system.cpu.Execution-Unit.predicted 40393506 # Number of Branches Incorrectly Predicted -system.cpu.Execution-Unit.predictedNotTakenIncorrect 19275234 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.Execution-Unit.predictedTakenIncorrect 2878419 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed -system.cpu.Mult-Div-Unit.multiplies 6482 # Number of Multipy Operations Executed -system.cpu.RegFile-Manager.regFileAccesses 1022190210 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.RegFile-Manager.regFileReads 558335321 # Number of Reads from Register File -system.cpu.RegFile-Manager.regFileWrites 463854889 # Number of Writes to Register File -system.cpu.RegFile-Manager.regForwards 256259728 # Number of Registers Read Through Forwarding Logic system.cpu.activity 88.058146 # Percentage of cycles cpu is active +system.cpu.agen_unit.agens 155868116 # Number of Address Generations +system.cpu.branch_predictor.BTBHitPct 90.344266 # BTB Hit Percentage +system.cpu.branch_predictor.BTBHits 29143677 # Number of BTB hits +system.cpu.branch_predictor.BTBLookups 32258469 # Number of BTB lookups +system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.condIncorrect 22153653 # Number of conditional branches incorrect +system.cpu.branch_predictor.condPredicted 59309256 # Number of conditional branches predicted +system.cpu.branch_predictor.lookups 64114012 # Number of BP lookups +system.cpu.branch_predictor.predictedNotTaken 31921338 # Number of Branches Predicted As Not Taken (False). +system.cpu.branch_predictor.predictedTaken 32192674 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target. system.cpu.comBranches 62547159 # Number of Branches instructions committed system.cpu.comFloats 24 # Number of Floating Point instructions committed system.cpu.comInts 349039879 # Number of Integer instructions committed @@ -88,8 +76,8 @@ system.cpu.dcache.demand_mshr_misses 455395 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.998946 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4091.682212 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.998946 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 21854.685324 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 19449.234181 # average overall mshr miss latency @@ -127,6 +115,12 @@ system.cpu.dtb.write_accesses 39453623 # DT system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_hits 39451321 # DTB write hits system.cpu.dtb.write_misses 2302 # DTB write misses +system.cpu.execution_unit.executions 419011350 # Number of Instructions Executed. +system.cpu.execution_unit.mispredictPct 35.419120 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.mispredicted 22153653 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 40393506 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predictedNotTakenIncorrect 19275234 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.predictedTakenIncorrect 2878419 # Number of Branches Incorrectly Predicted As Taken. system.cpu.icache.ReadReq_accesses 25645163 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 55761.178862 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53508.177570 # average ReadReq mshr miss latency @@ -160,8 +154,8 @@ system.cpu.icache.demand_mshr_misses 856 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.355592 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 728.253324 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.355592 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 25645163 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55761.178862 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53508.177570 # average overall mshr miss latency @@ -246,10 +240,10 @@ system.cpu.l2cache.demand_mshr_misses 92098 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.050363 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.487947 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 1650.286010 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 15989.036396 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.050363 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.487947 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 456251 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52157.973029 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40004.212904 # average overall mshr miss latency @@ -271,31 +265,37 @@ system.cpu.l2cache.tagsinuse 17639.322406 # Cy system.cpu.l2cache.total_refs 445702 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 59346 # number of writebacks +system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed +system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed system.cpu.numCycles 523283946 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.regfile_manager.regFileAccesses 1022190210 # Number of Total Accesses (Read+Write) to the Register File +system.cpu.regfile_manager.regFileReads 558335321 # Number of Reads from Register File +system.cpu.regfile_manager.regFileWrites 463854889 # Number of Writes to Register File +system.cpu.regfile_manager.regForwards 256259728 # Number of Registers Read Through Forwarding Logic system.cpu.runCycles 460794140 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 186436323 # Number of cycles 0 instructions are processed. -system.cpu.stage-0.runCycles 336847623 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 64.371863 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 209154116 # Number of cycles 0 instructions are processed. -system.cpu.stage-1.runCycles 314129830 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 60.030473 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 197582511 # Number of cycles 0 instructions are processed. -system.cpu.stage-2.runCycles 325701435 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 62.241817 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 410314498 # Number of cycles 0 instructions are processed. -system.cpu.stage-3.runCycles 112969448 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 21.588556 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 180086100 # Number of cycles 0 instructions are processed. -system.cpu.stage-4.runCycles 343197846 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 65.585396 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage0.idleCycles 186436323 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 336847623 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 64.371863 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 209154116 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 314129830 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 60.030473 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 197582511 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 325701435 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 62.241817 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 410314498 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 112969448 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.588556 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 180086100 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 343197846 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 65.585396 # Percentage of cycles stage was utilized (processing insts). system.cpu.threadCycles 508404874 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.timesIdled 455729 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls +system.cpu.workload.num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini index 8d44452f2..2c97093b4 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -25,6 +25,8 @@ BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout index 6c138b362..10e34acb3 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 17 2011 21:44:37 -M5 started Mar 17 2011 22:44:08 -M5 executing on zizzer +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 12:05:54 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 93acfbb63..bb82434d0 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 243015 # Simulator instruction rate (inst/s) -host_mem_usage 208616 # Number of bytes of host memory used -host_seconds 2327.23 # Real time elapsed on the host -host_tick_rate 69757618 # Simulator tick rate (ticks/s) +host_inst_rate 385051 # Simulator instruction rate (inst/s) +host_mem_usage 204468 # Number of bytes of host memory used +host_seconds 1468.77 # Real time elapsed on the host +host_tick_rate 110529153 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated sim_seconds 0.162342 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 4119052 # Nu system.cpu.BPredUnit.condPredicted 70244988 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 76158972 # Number of BP lookups system.cpu.BPredUnit.usedRAS 1672188 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 62547159 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 20370282 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 315015358 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.910564 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.344745 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 102187516 32.44% 32.44% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 100337503 31.85% 64.29% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 36333939 11.53% 75.82% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 9834278 3.12% 78.95% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 9585018 3.04% 81.99% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 21675104 6.88% 88.87% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 13171126 4.18% 93.05% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 1520592 0.48% 93.53% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 20370282 6.47% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 315015358 # Number of insts commited each cycle -system.cpu.commit.COM:count 601856963 # Number of instructions committed -system.cpu.commit.COM:fp_insts 1520 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 1197610 # Number of function calls committed. -system.cpu.commit.COM:int_insts 563954763 # Number of committed integer instructions. -system.cpu.commit.COM:loads 114514042 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 153965363 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 4118243 # The number of times a branch was mispredicted +system.cpu.commit.branches 62547159 # Number of branches committed +system.cpu.commit.bw_lim_events 20370282 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 59876142 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 315015358 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.910564 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.344745 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 102187516 32.44% 32.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 100337503 31.85% 64.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 36333939 11.53% 75.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9834278 3.12% 78.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 9585018 3.04% 81.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 21675104 6.88% 88.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 13171126 4.18% 93.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1520592 0.48% 93.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 20370282 6.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 315015358 # Number of insts commited each cycle +system.cpu.commit.count 601856963 # Number of instructions committed +system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. +system.cpu.commit.function_calls 1197610 # Number of function calls committed. +system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. +system.cpu.commit.loads 114514042 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.refs 153965363 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated system.cpu.cpi 0.574101 # CPI: Cycles Per Instruction @@ -98,8 +98,8 @@ system.cpu.dcache.demand_mshr_misses 475134 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999549 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4094.151824 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999549 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 151655852 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 14624.181040 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 9493.104038 # average overall mshr miss latency @@ -121,15 +121,15 @@ system.cpu.dcache.tagsinuse 4094.151824 # Cy system.cpu.dcache.total_refs 149582206 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 126677000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 423176 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 44833716 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 844 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 4163323 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 687863087 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 142213399 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 122593858 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 9601978 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 3402 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 5374385 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 44833716 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 844 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 4163323 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 687863087 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 142213399 # Number of cycles decode is idle +system.cpu.decode.RunCycles 122593858 # Number of cycles decode is running +system.cpu.decode.SquashCycles 9601978 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 3402 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 5374385 # Number of cycles decode is unblocking system.cpu.dtb.data_accesses 163150258 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 163097305 # DTB hits @@ -209,8 +209,8 @@ system.cpu.icache.demand_mshr_misses 909 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.378270 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 774.695980 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.378270 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 65447834 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 36501.303215 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35511.551155 # average overall mshr miss latency @@ -233,21 +233,13 @@ system.cpu.icache.total_refs 65446683 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 67100 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 67449018 # Number of branches executed -system.cpu.iew.EXEC:nop 43212719 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.845435 # Inst execution rate -system.cpu.iew.EXEC:refs 163178153 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 40932468 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 486897348 # num instructions consuming a value -system.cpu.iew.WB:count 595948678 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.812979 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 395837342 # num instructions producing a value -system.cpu.iew.WB:rate 1.835470 # insts written-back per cycle -system.cpu.iew.WB:sent 597097102 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 4605504 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 67449018 # Number of branches executed +system.cpu.iew.exec_nop 43212719 # number of nop insts executed +system.cpu.iew.exec_rate 1.845435 # Inst execution rate +system.cpu.iew.exec_refs 163178153 # number of memory reference insts executed +system.cpu.iew.exec_stores 40932468 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 1354512 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 125962189 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions @@ -275,103 +267,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 3134413 # system.cpu.iew.memOrderViolationEvents 24101 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 952315 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 3653189 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 486897348 # num instructions consuming a value +system.cpu.iew.wb_count 595948678 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.812979 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 395837342 # num instructions producing a value +system.cpu.iew.wb_rate 1.835470 # insts written-back per cycle +system.cpu.iew.wb_sent 597097102 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 844972523 # number of integer regfile reads system.cpu.int_regfile_writes 489243634 # number of integer regfile writes system.cpu.ipc 1.741853 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.741853 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 439577743 72.58% 72.58% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 6656 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 30 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 5 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 5 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 124281005 20.52% 93.11% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 41743673 6.89% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 605609121 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 5929666 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.009791 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 5228922 88.18% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 48 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 403247 6.80% 94.98% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 297449 5.02% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 324617336 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.865609 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.727719 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 90473429 27.87% 27.87% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 62743019 19.33% 47.20% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 78570143 24.20% 71.40% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 32526937 10.02% 81.42% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 31455135 9.69% 91.11% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 13029774 4.01% 95.13% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 14124566 4.35% 99.48% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 1126465 0.35% 99.83% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 567868 0.17% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 324617336 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.865224 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 439577743 72.58% 72.58% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6656 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 30 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 124281005 20.52% 93.11% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 41743673 6.89% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 605609121 # Type of FU issued system.cpu.iq.fp_alu_accesses 1669 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 3317 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 1594 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 1802 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 5929666 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009791 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5228922 88.18% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 48 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 403247 6.80% 94.98% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 297449 5.02% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 611537118 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 1541773318 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 595947084 # Number of integer instruction queue wakeup accesses @@ -383,6 +365,24 @@ system.cpu.iq.iqSquashedInstsExamined 51673321 # Nu system.cpu.iq.iqSquashedInstsIssued 11391 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 26894119 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 324617336 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.865609 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.727719 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 90473429 27.87% 27.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 62743019 19.33% 47.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 78570143 24.20% 71.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 32526937 10.02% 81.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31455135 9.69% 91.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 13029774 4.01% 95.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 14124566 4.35% 99.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1126465 0.35% 99.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 567868 0.17% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 324617336 # Number of insts issued each cycle +system.cpu.iq.rate 1.865224 # Inst issue rate system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits @@ -443,10 +443,10 @@ system.cpu.l2cache.demand_mshr_misses 92757 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.052925 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.487884 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 1734.245593 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 15986.969370 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.052925 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.487884 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 476043 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34447.863773 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31236.300225 # average overall mshr miss latency @@ -477,28 +477,28 @@ system.cpu.misc_regfile_writes 1 # nu system.cpu.numCycles 324684436 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 12564419 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 31522766 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 149604933 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 659383 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 101 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 894089158 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 678776451 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 517767610 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 115293181 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 9601978 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 37552130 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 53912721 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 1965 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 894087193 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 695 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 31 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 73444449 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 30 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 12564419 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 31522766 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 149604933 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 659383 # Number of times rename has blocked due to LSQ full +system.cpu.rename.ROBFullEvents 101 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 894089158 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 678776451 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 517767610 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 115293181 # Number of cycles rename is running +system.cpu.rename.SquashCycles 9601978 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 37552130 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 53912721 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 1965 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 894087193 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 695 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 31 # count of serializing insts renamed +system.cpu.rename.skidInsts 73444449 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 30 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 956313792 # The number of ROB reads system.cpu.rob.rob_writes 1333072216 # The number of ROB writes system.cpu.timesIdled 2037 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls +system.cpu.workload.num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout index b96d561c3..87e51a8e2 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:37 -M5 executing on burrito +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 11:58:35 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt index 4dfa82a45..fdb2e2919 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1697811 # Simulator instruction rate (inst/s) -host_mem_usage 218112 # Number of bytes of host memory used -host_seconds 354.49 # Real time elapsed on the host -host_tick_rate 848911876 # Simulator tick rate (ticks/s) +host_inst_rate 6401056 # Simulator instruction rate (inst/s) +host_mem_usage 195828 # Number of bytes of host memory used +host_seconds 94.02 # Real time elapsed on the host +host_tick_rate 3200547989 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated sim_seconds 0.300931 # Number of seconds simulated @@ -61,6 +61,6 @@ system.cpu.num_int_register_writes 463854847 # nu system.cpu.num_load_insts 114516673 # Number of load instructions system.cpu.num_mem_refs 153970296 # number of memory refs system.cpu.num_store_insts 39453623 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls +system.cpu.workload.num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini index 5dbdc6426..50ef6266f 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -51,6 +51,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -86,6 +87,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +123,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout index 5133de4f2..dc72f58cf 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:36 -M5 executing on burrito +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 11:58:24 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt index 0f44a109b..f9d483c5d 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 591495 # Simulator instruction rate (inst/s) -host_mem_usage 225828 # Number of bytes of host memory used -host_seconds 1017.52 # Real time elapsed on the host -host_tick_rate 752441266 # Simulator tick rate (ticks/s) +host_inst_rate 2829112 # Simulator instruction rate (inst/s) +host_mem_usage 203572 # Number of bytes of host memory used +host_seconds 212.74 # Real time elapsed on the host +host_tick_rate 3598913072 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated sim_seconds 0.765623 # Number of seconds simulated @@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses 455395 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999553 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4094.170317 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999553 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 22414.479737 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 19414.479737 # average overall mshr miss latency @@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 795 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.328778 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 673.337154 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.328778 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 601861898 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -205,10 +205,10 @@ system.cpu.l2cache.demand_mshr_misses 92031 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.052565 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.491366 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 1722.436058 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 16101.078831 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.052565 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.491366 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 456190 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -250,6 +250,6 @@ system.cpu.num_int_register_writes 463854847 # nu system.cpu.num_load_insts 114516673 # Number of load instructions system.cpu.num_mem_refs 153970296 # number of memory refs system.cpu.num_store_insts 39453623 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls +system.cpu.workload.num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini index d12448d3c..07f2d92be 100644 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini @@ -498,7 +498,7 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/alisai01/dist/cpu2000/binaries/arm/linux/gzip +executable=/dist/m5/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout index 0ab77604f..facf2b9b0 100755 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 17:54:33 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 12:47:12 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt index a5940d4c5..5fb65989e 100644 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 238408 # Simulator instruction rate (inst/s) -host_mem_usage 258640 # Number of bytes of host memory used -host_seconds 2526.59 # Real time elapsed on the host -host_tick_rate 77778012 # Simulator tick rate (ticks/s) +host_inst_rate 283332 # Simulator instruction rate (inst/s) +host_mem_usage 214996 # Number of bytes of host memory used +host_seconds 2125.99 # Real time elapsed on the host +host_tick_rate 92433779 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 602359865 # Number of instructions simulated sim_seconds 0.196513 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 3832102 # Nu system.cpu.BPredUnit.condPredicted 81880205 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 88398894 # Number of BP lookups system.cpu.BPredUnit.usedRAS 1393010 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 70828614 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 7897771 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 379244728 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.588315 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.904338 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 123478650 32.56% 32.56% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 123013107 32.44% 65.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 59170888 15.60% 80.60% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 18488020 4.87% 85.47% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 17225820 4.54% 90.01% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 14373715 3.79% 93.80% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 7590349 2.00% 95.81% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 8006408 2.11% 97.92% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 7897771 2.08% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 379244728 # Number of insts commited each cycle -system.cpu.commit.COM:count 602359916 # Number of instructions committed -system.cpu.commit.COM:fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 997573 # Number of function calls committed. -system.cpu.commit.COM:int_insts 533522691 # Number of committed integer instructions. -system.cpu.commit.COM:loads 148952607 # Number of loads committed -system.cpu.commit.COM:membars 1328 # Number of memory barriers committed -system.cpu.commit.COM:refs 219173633 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 3891220 # The number of times a branch was mispredicted +system.cpu.commit.branches 70828614 # Number of branches committed +system.cpu.commit.bw_lim_events 7897771 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 602359916 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 6310 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 86859726 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 379244728 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.588315 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.904338 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 123478650 32.56% 32.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 123013107 32.44% 65.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 59170888 15.60% 80.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18488020 4.87% 85.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 17225820 4.54% 90.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14373715 3.79% 93.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7590349 2.00% 95.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8006408 2.11% 97.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7897771 2.08% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 379244728 # Number of insts commited each cycle +system.cpu.commit.count 602359916 # Number of instructions committed +system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. +system.cpu.commit.function_calls 997573 # Number of function calls committed. +system.cpu.commit.int_insts 533522691 # Number of committed integer instructions. +system.cpu.commit.loads 148952607 # Number of loads committed +system.cpu.commit.membars 1328 # Number of memory barriers committed +system.cpu.commit.refs 219173633 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 602359865 # Number of Instructions Simulated system.cpu.committedInsts_total 602359865 # Number of Instructions Simulated system.cpu.cpi 0.652478 # CPI: Cycles Per Instruction @@ -105,8 +105,8 @@ system.cpu.dcache.demand_mshr_misses 443820 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999719 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4094.849519 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999719 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 208812765 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 17229.974009 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 9270.687452 # average overall mshr miss latency @@ -128,15 +128,15 @@ system.cpu.dcache.tagsinuse 4094.849519 # Cy system.cpu.dcache.total_refs 207082021 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 89315000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 394264 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 64227537 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 1274 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 5983982 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 722350979 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 163737957 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 138388023 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 12871984 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 4747 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 12891210 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 64227537 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 1274 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 5983982 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 722350979 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 163737957 # Number of cycles decode is idle +system.cpu.decode.RunCycles 138388023 # Number of cycles decode is running +system.cpu.decode.SquashCycles 12871984 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 4747 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 12891210 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -220,8 +220,8 @@ system.cpu.icache.demand_mshr_misses 722 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.307172 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 629.087764 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.307172 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 71395519 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 35429.359823 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 34341.412742 # average overall mshr miss latency @@ -244,21 +244,13 @@ system.cpu.icache.total_refs 71394613 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 909571 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 73704412 # Number of branches executed -system.cpu.iew.EXEC:nop 61098 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.622472 # Inst execution rate -system.cpu.iew.EXEC:refs 239165331 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 73423365 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 736448308 # num instructions consuming a value -system.cpu.iew.WB:count 631945179 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.594878 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 438096934 # num instructions producing a value -system.cpu.iew.WB:rate 1.607895 # insts written-back per cycle -system.cpu.iew.WB:sent 632881856 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 4305441 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 73704412 # Number of branches executed +system.cpu.iew.exec_nop 61098 # number of nop insts executed +system.cpu.iew.exec_rate 1.622472 # Inst execution rate +system.cpu.iew.exec_refs 239165331 # number of memory reference insts executed +system.cpu.iew.exec_stores 73423365 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 811047 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 176106355 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 5819 # Number of dispatched non-speculative instructions @@ -286,103 +278,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 11966835 # system.cpu.iew.memOrderViolationEvents 611520 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 628522 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 3676919 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 736448308 # num instructions consuming a value +system.cpu.iew.wb_count 631945179 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.594878 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 438096934 # num instructions producing a value +system.cpu.iew.wb_rate 1.607895 # insts written-back per cycle +system.cpu.iew.wb_sent 632881856 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 1724767298 # number of integer regfile reads system.cpu.int_regfile_writes 495432851 # number of integer regfile writes system.cpu.ipc 1.532620 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.532620 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 400863775 62.26% 62.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 6585 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 3 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 168265891 26.14% 88.40% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 74671891 11.60% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 643808145 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 3945011 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.006128 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 107679 2.73% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 3407280 86.37% 89.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 430052 10.90% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 392116711 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.641879 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.551770 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 108904518 27.77% 27.77% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 107421508 27.40% 55.17% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 76290088 19.46% 74.62% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 48454562 12.36% 86.98% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 26882762 6.86% 93.84% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 16851716 4.30% 98.14% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 5414053 1.38% 99.52% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 1011203 0.26% 99.77% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 886301 0.23% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 392116711 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.638079 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 400863775 62.26% 62.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6585 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 168265891 26.14% 88.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 74671891 11.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 643808145 # Type of FU issued system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 3945011 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006128 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 107679 2.73% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3407280 86.37% 89.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 430052 10.90% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 647753136 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 1684034505 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 631945163 # Number of integer instruction queue wakeup accesses @@ -394,6 +376,24 @@ system.cpu.iq.iqSquashedInstsExamined 86496318 # Nu system.cpu.iq.iqSquashedInstsIssued 356529 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 850 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 162226931 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 392116711 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.641879 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.551770 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 108904518 27.77% 27.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 107421508 27.40% 55.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 76290088 19.46% 74.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 48454562 12.36% 86.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 26882762 6.86% 93.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16851716 4.30% 98.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5414053 1.38% 99.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1011203 0.26% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 886301 0.23% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 392116711 # Number of insts issued each cycle +system.cpu.iq.rate 1.638079 # Inst issue rate system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -468,10 +468,10 @@ system.cpu.l2cache.demand_mshr_misses 91150 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.057260 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.487109 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 1876.282231 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 15961.603623 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.057260 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.487109 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 444538 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34340.043442 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31188.047175 # average overall mshr miss latency @@ -502,27 +502,27 @@ system.cpu.misc_regfile_writes 2682 # nu system.cpu.numCycles 393026282 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 9628088 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 471021820 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 50048668 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 176696020 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1915065 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 2034394520 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 711291370 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 553214444 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 138291459 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 12871984 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 54521168 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 82192621 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 96 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 2034394424 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 107992 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 6480 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 91409775 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 6477 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 9628088 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 471021820 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 50048668 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 176696020 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 1915065 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenameLookups 2034394520 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 711291370 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 553214444 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 138291459 # Number of cycles rename is running +system.cpu.rename.SquashCycles 12871984 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 54521168 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 82192621 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 96 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 2034394424 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 107992 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 6480 # count of serializing insts renamed +system.cpu.rename.skidInsts 91409775 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 6477 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 1060565987 # The number of ROB reads system.cpu.rob.rob_writes 1391311417 # The number of ROB writes system.cpu.timesIdled 36947 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 48 # Number of system calls +system.cpu.workload.num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini index b07d285b7..17d38a039 100644 --- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini @@ -61,12 +61,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip +executable=/dist/m5/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout index d9332d696..ceb1053f2 100755 --- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout +++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 17:54:33 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 12:47:58 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt index f0089af03..3089a85c4 100644 --- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1048186 # Simulator instruction rate (inst/s) -host_mem_usage 246964 # Number of bytes of host memory used -host_seconds 574.67 # Real time elapsed on the host -host_tick_rate 524112689 # Simulator tick rate (ticks/s) +host_inst_rate 4079554 # Simulator instruction rate (inst/s) +host_mem_usage 206080 # Number of bytes of host memory used +host_seconds 147.65 # Real time elapsed on the host +host_tick_rate 2039852029 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 602359851 # Number of instructions simulated sim_seconds 0.301191 # Number of seconds simulated @@ -71,6 +71,6 @@ system.cpu.num_int_register_writes 458076290 # nu system.cpu.num_load_insts 148952594 # Number of load instructions system.cpu.num_mem_refs 219173607 # number of memory refs system.cpu.num_store_insts 70221013 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 48 # Number of system calls +system.cpu.workload.num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini index 5a251a60a..f2a118cfd 100644 --- a/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini @@ -164,12 +164,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing +cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip +executable=/dist/m5/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/simout b/tests/long/00.gzip/ref/arm/linux/simple-timing/simout index 9680f68d5..99cb1ccc7 100755 --- a/tests/long/00.gzip/ref/arm/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 17:54:33 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 12:48:29 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt index 9997800cb..e356c348b 100644 --- a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 590565 # Simulator instruction rate (inst/s) -host_mem_usage 254684 # Number of bytes of host memory used -host_seconds 1016.65 # Real time elapsed on the host -host_tick_rate 783712761 # Simulator tick rate (ticks/s) +host_inst_rate 2132031 # Simulator instruction rate (inst/s) +host_mem_usage 213820 # Number of bytes of host memory used +host_seconds 281.61 # Real time elapsed on the host +host_tick_rate 2829324901 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 600398281 # Number of instructions simulated sim_seconds 0.796763 # Number of seconds simulated @@ -54,8 +54,8 @@ system.cpu.dcache.demand_mshr_misses 437564 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999566 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4094.222434 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999566 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 217209383 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 22578.841038 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 19578.841038 # average overall mshr miss latency @@ -130,8 +130,8 @@ system.cpu.icache.demand_mshr_misses 643 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.282094 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 577.728532 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.282094 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 570074535 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 54236.391913 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 51236.391913 # average overall mshr miss latency @@ -219,10 +219,10 @@ system.cpu.l2cache.demand_mshr_misses 89992 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.053777 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.492610 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 1762.179345 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 16141.835335 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.053777 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.492610 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 438207 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -264,6 +264,6 @@ system.cpu.num_int_register_writes 458076290 # nu system.cpu.num_load_insts 148952594 # Number of load instructions system.cpu.num_mem_refs 219173607 # number of memory refs system.cpu.num_store_insts 70221013 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 48 # Number of system calls +system.cpu.workload.num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini index 2c96b363d..3ff1381e0 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -25,6 +25,8 @@ BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout index bc6585d4f..9d435e3a3 100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 17 2011 23:04:27 -M5 started Mar 17 2011 23:11:57 -M5 executing on zizzer +M5 compiled Apr 19 2011 12:19:46 +M5 started Apr 19 2011 12:20:08 +M5 executing on maize command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 0f4eafb7d..04c8a25b6 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 165963 # Simulator instruction rate (inst/s) -host_mem_usage 210376 # Number of bytes of host memory used -host_seconds 8469.40 # Real time elapsed on the host -host_tick_rate 68767363 # Simulator tick rate (ticks/s) +host_inst_rate 280029 # Simulator instruction rate (inst/s) +host_mem_usage 206320 # Number of bytes of host memory used +host_seconds 5019.49 # Real time elapsed on the host +host_tick_rate 116031336 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1405604152 # Number of instructions simulated sim_seconds 0.582418 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 5339067 # Nu system.cpu.BPredUnit.condPredicted 103713551 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 103713551 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 86248929 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 26710610 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1136580592 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.310530 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.747403 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 402922453 35.45% 35.45% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 477569543 42.02% 77.47% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 55697713 4.90% 82.37% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 97088718 8.54% 90.91% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 32658945 2.87% 93.78% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 8438570 0.74% 94.53% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 25679618 2.26% 96.79% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 9814422 0.86% 97.65% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 26710610 2.35% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1136580592 # Number of insts commited each cycle -system.cpu.commit.COM:count 1489523295 # Number of instructions committed -system.cpu.commit.COM:fp_insts 8452036 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 0 # Number of function calls committed. -system.cpu.commit.COM:int_insts 1319476388 # Number of committed integer instructions. -system.cpu.commit.COM:loads 402512844 # Number of loads committed -system.cpu.commit.COM:membars 51356 # Number of memory barriers committed -system.cpu.commit.COM:refs 569360986 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 5339067 # The number of times a branch was mispredicted +system.cpu.commit.branches 86248929 # Number of branches committed +system.cpu.commit.bw_lim_events 26710610 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 1489523295 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 199490556 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 1136580592 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.310530 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.747403 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 402922453 35.45% 35.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 477569543 42.02% 77.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 55697713 4.90% 82.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 97088718 8.54% 90.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 32658945 2.87% 93.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 8438570 0.74% 94.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 25679618 2.26% 96.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9814422 0.86% 97.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 26710610 2.35% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1136580592 # Number of insts commited each cycle +system.cpu.commit.count 1489523295 # Number of instructions committed +system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. +system.cpu.commit.function_calls 0 # Number of function calls committed. +system.cpu.commit.int_insts 1319476388 # Number of committed integer instructions. +system.cpu.commit.loads 402512844 # Number of loads committed +system.cpu.commit.membars 51356 # Number of memory barriers committed +system.cpu.commit.refs 569360986 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 1405604152 # Number of Instructions Simulated system.cpu.committedInsts_total 1405604152 # Number of Instructions Simulated system.cpu.cpi 0.828709 # CPI: Cycles Per Instruction @@ -106,8 +106,8 @@ system.cpu.dcache.demand_mshr_misses 481375 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999855 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4095.405595 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999855 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 458308294 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 15159.332747 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 10578.009334 # average overall mshr miss latency @@ -129,12 +129,12 @@ system.cpu.dcache.tagsinuse 4095.405595 # Cy system.cpu.dcache.total_refs 455672050 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 132278000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 428224 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 373408138 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 1727466392 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 394807577 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 348667632 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 27885594 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 19696634 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 373408138 # Number of cycles decode is blocked +system.cpu.decode.DecodedInsts 1727466392 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 394807577 # Number of cycles decode is idle +system.cpu.decode.RunCycles 348667632 # Number of cycles decode is running +system.cpu.decode.SquashCycles 27885594 # Number of cycles decode is squashing +system.cpu.decode.UnblockCycles 19696634 # Number of cycles decode is unblocking system.cpu.fetch.Branches 103713551 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 170870865 # Number of cache lines fetched system.cpu.fetch.Cycles 370648133 # Number of cycles fetch has run and was not squashing or blocked @@ -198,8 +198,8 @@ system.cpu.icache.demand_mshr_misses 1297 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.511535 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1047.623620 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.511535 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 170870865 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 35272.495756 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35056.283732 # average overall mshr miss latency @@ -222,21 +222,13 @@ system.cpu.icache.total_refs 170869098 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 370544 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 89603944 # Number of branches executed -system.cpu.iew.EXEC:nop 100373819 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.267070 # Inst execution rate -system.cpu.iew.EXEC:refs 591399205 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 170154785 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1209973999 # num instructions consuming a value -system.cpu.iew.WB:count 1473173854 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.961076 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1162877329 # num instructions producing a value -system.cpu.iew.WB:rate 1.264705 # insts written-back per cycle -system.cpu.iew.WB:sent 1474297623 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 5675287 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 89603944 # Number of branches executed +system.cpu.iew.exec_nop 100373819 # number of nop insts executed +system.cpu.iew.exec_rate 1.267070 # Inst execution rate +system.cpu.iew.exec_refs 591399205 # number of memory reference insts executed +system.cpu.iew.exec_stores 170154785 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 2507924 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 461157302 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 2999936 # Number of dispatched non-speculative instructions @@ -264,103 +256,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 20174020 # system.cpu.iew.memOrderViolationEvents 460365 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 670427 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 5004860 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1209973999 # num instructions consuming a value +system.cpu.iew.wb_count 1473173854 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.961076 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 1162877329 # num instructions producing a value +system.cpu.iew.wb_rate 1.264705 # insts written-back per cycle +system.cpu.iew.wb_sent 1474297623 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 1997794756 # number of integer regfile reads system.cpu.int_regfile_writes 1296594839 # number of integer regfile writes system.cpu.ipc 1.206697 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.206697 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 883945189 59.64% 59.64% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 59.64% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 59.64% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2631981 0.18% 59.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 424001958 28.61% 88.42% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 171668003 11.58% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 1482247131 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 3391020 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.002288 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 214212 6.32% 6.32% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 6.32% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 6.32% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 187778 5.54% 11.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 11.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 11.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 11.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 11.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 11.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 11.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 11.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 11.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 11.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 11.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 11.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 11.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 11.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 11.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 11.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 11.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 11.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 11.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 11.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 11.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 11.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 11.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 11.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 11.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 2748667 81.06% 92.91% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 240363 7.09% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 1164465575 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.272899 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.148641 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 309298241 26.56% 26.56% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 465738905 40.00% 66.56% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 229121985 19.68% 86.23% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 104115000 8.94% 95.17% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 41467759 3.56% 98.74% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 8912842 0.77% 99.50% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 5349281 0.46% 99.96% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 304172 0.03% 99.99% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 157390 0.01% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 1164465575 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.272494 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 883945189 59.64% 59.64% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.64% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2631981 0.18% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 424001958 28.61% 88.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 171668003 11.58% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1482247131 # Type of FU issued system.cpu.iq.fp_alu_accesses 9142959 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 17762219 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 8523024 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 9165283 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 3391020 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.002288 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 214212 6.32% 6.32% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.32% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 187778 5.54% 11.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2748667 81.06% 92.91% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 240363 7.09% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 1476495192 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 4114870575 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 1464650830 # Number of integer instruction queue wakeup accesses @@ -372,6 +354,24 @@ system.cpu.iq.iqSquashedInstsExamined 182705519 # Nu system.cpu.iq.iqSquashedInstsIssued 281937 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 855886 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 240684944 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 1164465575 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.272899 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.148641 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 309298241 26.56% 26.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 465738905 40.00% 66.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 229121985 19.68% 86.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 104115000 8.94% 95.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 41467759 3.56% 98.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8912842 0.77% 99.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5349281 0.46% 99.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 304172 0.03% 99.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 157390 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1164465575 # Number of insts issued each cycle +system.cpu.iq.rate 1.272494 # Inst issue rate system.cpu.l2cache.ReadExReq_accesses 268051 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 34407.834444 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31320.706026 # average ReadExReq mshr miss latency @@ -416,10 +416,10 @@ system.cpu.l2cache.demand_mshr_misses 94147 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.059800 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.479227 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 1959.521413 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 15703.307498 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.059800 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.479227 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 482679 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34275.266339 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31207.701786 # average overall mshr miss latency @@ -450,28 +450,28 @@ system.cpu.misc_regfile_writes 2258933 # nu system.cpu.numCycles 1164836119 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 115497905 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 1244770452 # Number of HB maps that are committed -system.cpu.rename.RENAME:FullRegisterEvents 28107626 # Number of times there has been no free registers -system.cpu.rename.RENAME:IQFullEvents 128337052 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 433132347 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 40459205 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 2887426636 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 1709740875 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 1426816340 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 325737783 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 27885594 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 209164686 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 182045888 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 33660518 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 2853766118 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 53047260 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 3085415 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 378977297 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 3085429 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 115497905 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1244770452 # Number of HB maps that are committed +system.cpu.rename.FullRegisterEvents 28107626 # Number of times there has been no free registers +system.cpu.rename.IQFullEvents 128337052 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 433132347 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 40459205 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenameLookups 2887426636 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1709740875 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1426816340 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 325737783 # Number of cycles rename is running +system.cpu.rename.SquashCycles 27885594 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 209164686 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 182045888 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 33660518 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 2853766118 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 53047260 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 3085415 # count of serializing insts renamed +system.cpu.rename.skidInsts 378977297 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 3085429 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 2798818963 # The number of ROB reads system.cpu.rob.rob_writes 3405946340 # The number of ROB writes system.cpu.timesIdled 11499 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 49 # Number of system calls +system.cpu.workload.num_syscalls 49 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout index 4748a164d..6bfdef722 100755 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:13:30 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:14:57 -M5 executing on burrito +M5 compiled Apr 19 2011 12:19:46 +M5 started Apr 19 2011 12:21:44 +M5 executing on maize command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt index 16c920737..d5fea60de 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1524596 # Simulator instruction rate (inst/s) -host_mem_usage 219684 # Number of bytes of host memory used -host_seconds 977.00 # Real time elapsed on the host -host_tick_rate 762300416 # Simulator tick rate (ticks/s) +host_inst_rate 4954155 # Simulator instruction rate (inst/s) +host_mem_usage 197572 # Number of bytes of host memory used +host_seconds 300.66 # Real time elapsed on the host +host_tick_rate 2477084432 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489523295 # Number of instructions simulated sim_seconds 0.744764 # Number of seconds simulated @@ -29,6 +29,6 @@ system.cpu.num_int_register_writes 1234411208 # nu system.cpu.num_load_insts 402515346 # Number of load instructions system.cpu.num_mem_refs 569365767 # number of memory refs system.cpu.num_store_insts 166850421 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 49 # Number of system calls +system.cpu.workload.num_syscalls 49 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini index 9789f7d05..d8d6cf280 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -51,6 +51,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -86,6 +87,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +123,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout index f2b4b3e16..e55df7545 100755 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:13:30 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:13:36 -M5 executing on burrito +M5 compiled Apr 19 2011 12:19:46 +M5 started Apr 19 2011 12:20:53 +M5 executing on maize command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt index 8bc8178fc..6356f769a 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 594721 # Simulator instruction rate (inst/s) -host_mem_usage 227400 # Number of bytes of host memory used -host_seconds 2504.58 # Real time elapsed on the host -host_tick_rate 824195004 # Simulator tick rate (ticks/s) +host_inst_rate 2608442 # Simulator instruction rate (inst/s) +host_mem_usage 205324 # Number of bytes of host memory used +host_seconds 571.04 # Real time elapsed on the host +host_tick_rate 3614912787 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489523295 # Number of instructions simulated sim_seconds 2.064259 # Number of seconds simulated @@ -60,8 +60,8 @@ system.cpu.dcache.demand_mshr_misses 453214 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999811 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4095.226955 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999811 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 569359660 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 22454.694692 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 19454.694692 # average overall mshr miss latency @@ -115,8 +115,8 @@ system.cpu.icache.demand_mshr_misses 1107 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.442603 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 906.450625 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.442603 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 1485113012 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55848.238482 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency @@ -183,10 +183,10 @@ system.cpu.l2cache.demand_mshr_misses 92343 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.057187 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.483685 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 1873.919591 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 15849.385934 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.057187 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.483685 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 454328 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -228,6 +228,6 @@ system.cpu.num_int_register_writes 1234411207 # nu system.cpu.num_load_insts 402515346 # Number of load instructions system.cpu.num_mem_refs 569365767 # number of memory refs system.cpu.num_store_insts 166850421 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 49 # Number of system calls +system.cpu.workload.num_syscalls 49 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini index 2af9a6819..21fe896ca 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini @@ -25,6 +25,8 @@ BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout index f0ec00748..f0ad86715 100755 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 18 2011 20:12:06 -M5 started Mar 18 2011 20:12:27 -M5 executing on zizzer +M5 compiled Apr 19 2011 12:22:33 +M5 started Apr 19 2011 12:31:00 +M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt index 3726448fa..99a6b6318 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 151077 # Simulator instruction rate (inst/s) -host_mem_usage 216016 # Number of bytes of host memory used -host_seconds 10732.89 # Real time elapsed on the host -host_tick_rate 69979188 # Simulator tick rate (ticks/s) +host_inst_rate 229365 # Simulator instruction rate (inst/s) +host_mem_usage 211952 # Number of bytes of host memory used +host_seconds 7069.49 # Real time elapsed on the host +host_tick_rate 106242349 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1621493982 # Number of instructions simulated sim_seconds 0.751079 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 8971423 # Nu system.cpu.BPredUnit.condPredicted 179993455 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 179993455 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 107161579 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 11445860 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1402522347 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.156127 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.381739 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 522037324 37.22% 37.22% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 531767209 37.92% 75.14% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 125147036 8.92% 84.06% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 139348503 9.94% 93.99% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 42559094 3.03% 97.03% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 23457685 1.67% 98.70% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 5021941 0.36% 99.06% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 1737695 0.12% 99.18% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 11445860 0.82% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1402522347 # Number of insts commited each cycle -system.cpu.commit.COM:count 1621493982 # Number of instructions committed -system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 0 # Number of function calls committed. -system.cpu.commit.COM:int_insts 1621354492 # Number of committed integer instructions. -system.cpu.commit.COM:loads 419042125 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 607228182 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 8971450 # The number of times a branch was mispredicted +system.cpu.commit.branches 107161579 # Number of branches committed +system.cpu.commit.bw_lim_events 11445860 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 1621493982 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 721713449 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 1402522347 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.156127 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.381739 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 522037324 37.22% 37.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 531767209 37.92% 75.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 125147036 8.92% 84.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 139348503 9.94% 93.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 42559094 3.03% 97.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 23457685 1.67% 98.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5021941 0.36% 99.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1737695 0.12% 99.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11445860 0.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1402522347 # Number of insts commited each cycle +system.cpu.commit.count 1621493982 # Number of instructions committed +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 0 # Number of function calls committed. +system.cpu.commit.int_insts 1621354492 # Number of committed integer instructions. +system.cpu.commit.loads 419042125 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.refs 607228182 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 1621493982 # Number of Instructions Simulated system.cpu.committedInsts_total 1621493982 # Number of Instructions Simulated system.cpu.cpi 0.926404 # CPI: Cycles Per Instruction @@ -96,8 +96,8 @@ system.cpu.dcache.demand_mshr_misses 465016 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999792 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4095.146726 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999792 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 513587988 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 18150.803874 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 8690.812783 # average overall mshr miss latency @@ -119,12 +119,12 @@ system.cpu.dcache.tagsinuse 4095.146726 # Cy system.cpu.dcache.total_refs 512136646 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 317706000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 411408 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 587921420 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 2472731706 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 429893143 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 331529130 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 99378480 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 53178654 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 587921420 # Number of cycles decode is blocked +system.cpu.decode.DecodedInsts 2472731706 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 429893143 # Number of cycles decode is idle +system.cpu.decode.RunCycles 331529130 # Number of cycles decode is running +system.cpu.decode.SquashCycles 99378480 # Number of cycles decode is squashing +system.cpu.decode.UnblockCycles 53178654 # Number of cycles decode is unblocking system.cpu.fetch.Branches 179993455 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 170058043 # Number of cache lines fetched system.cpu.fetch.Cycles 400227143 # Number of cycles fetch has run and was not squashing or blocked @@ -187,8 +187,8 @@ system.cpu.icache.demand_mshr_misses 869 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.387535 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 793.670730 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.387535 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 170058043 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 35240.756303 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35321.058688 # average overall mshr miss latency @@ -211,21 +211,13 @@ system.cpu.icache.total_refs 170056853 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 257635 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 111429178 # Number of branches executed -system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.227514 # Inst execution rate -system.cpu.iew.EXEC:refs 636597814 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 191695864 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 2082700302 # num instructions consuming a value -system.cpu.iew.WB:count 1838995466 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.683970 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1424504384 # num instructions producing a value -system.cpu.iew.WB:rate 1.224235 # insts written-back per cycle -system.cpu.iew.WB:sent 1842743630 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 9107858 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 111429178 # Number of branches executed +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_rate 1.227514 # Inst execution rate +system.cpu.iew.exec_refs 636597814 # number of memory reference insts executed +system.cpu.iew.exec_stores 191695864 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 1395305 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 615851374 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 81 # Number of dispatched non-speculative instructions @@ -253,103 +245,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 62612798 # system.cpu.iew.memOrderViolationEvents 6399400 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 4677718 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 4430140 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 2082700302 # num instructions consuming a value +system.cpu.iew.wb_count 1838995466 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.683970 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 1424504384 # num instructions producing a value +system.cpu.iew.wb_rate 1.224235 # insts written-back per cycle +system.cpu.iew.wb_sent 1842743630 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 3236941415 # number of integer regfile reads system.cpu.int_regfile_writes 1831971139 # number of integer regfile writes system.cpu.ipc 1.079443 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.079443 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 28079218 1.51% 1.51% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1185434411 63.84% 65.35% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 451340139 24.30% 89.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 192134588 10.35% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 1856988356 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 4273878 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.002302 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 161807 3.79% 3.79% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 3493887 81.75% 85.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 618184 14.46% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 1501900827 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.236425 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.221094 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 463034659 30.83% 30.83% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 580779168 38.67% 69.50% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 218589752 14.55% 84.05% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 151066938 10.06% 94.11% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 63504112 4.23% 98.34% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 18859628 1.26% 99.60% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 5092601 0.34% 99.94% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 833076 0.06% 99.99% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 140893 0.01% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 1501900827 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.236213 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 28079218 1.51% 1.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1185434411 63.84% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 451340139 24.30% 89.65% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 192134588 10.35% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1856988356 # Type of FU issued system.cpu.iq.fp_alu_accesses 19 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 35 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 32 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 4273878 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.002302 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 161807 3.79% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3493887 81.75% 85.54% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 618184 14.46% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 1833182997 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 5220358647 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 1838995454 # Number of integer instruction queue wakeup accesses @@ -361,6 +343,24 @@ system.cpu.iq.iqSquashedInstsExamined 721564206 # Nu system.cpu.iq.iqSquashedInstsIssued 207265 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 31 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 1518322063 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 1501900827 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.236425 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.221094 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 463034659 30.83% 30.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 580779168 38.67% 69.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 218589752 14.55% 84.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 151066938 10.06% 94.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 63504112 4.23% 98.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 18859628 1.26% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5092601 0.34% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 833076 0.06% 99.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 140893 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1501900827 # Number of insts issued each cycle +system.cpu.iq.rate 1.236213 # Inst issue rate system.cpu.l2cache.ReadExReq_accesses 250113 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 34407.651379 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31155.730459 # average ReadExReq mshr miss latency @@ -405,10 +405,10 @@ system.cpu.l2cache.demand_mshr_misses 91933 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.058491 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.491164 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 1916.626475 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 16094.448281 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.058491 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.491164 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 465885 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34310.106273 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31101.889419 # average overall mshr miss latency @@ -438,28 +438,28 @@ system.cpu.misc_regfile_reads 931071836 # nu system.cpu.numCycles 1502158462 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 169288978 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 1617994650 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 298516669 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 493321936 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 107168100 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 70 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 5808956116 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 2397077126 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 2395694665 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 310095488 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 99378480 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 429812969 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 777700015 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 64 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 5808956052 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 2976 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 89 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 706930007 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 89 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 169288978 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1617994650 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 298516669 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 493321936 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 107168100 # Number of times rename has blocked due to LSQ full +system.cpu.rename.ROBFullEvents 70 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 5808956116 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 2397077126 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 2395694665 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 310095488 # Number of cycles rename is running +system.cpu.rename.SquashCycles 99378480 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 429812969 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 777700015 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 64 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 5808956052 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 2976 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 89 # count of serializing insts renamed +system.cpu.rename.skidInsts 706930007 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 89 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 3734283918 # The number of ROB reads system.cpu.rob.rob_writes 4785794667 # The number of ROB writes system.cpu.timesIdled 45615 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 48 # Number of system calls +system.cpu.workload.num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout index bb6395625..b229bc589 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 8 2011 00:58:32 -M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip -M5 started Feb 8 2011 00:58:34 -M5 executing on burrito +M5 compiled Apr 19 2011 12:22:33 +M5 started Apr 19 2011 12:22:36 +M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt index 5b839ec88..f6fa9ef1e 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2470310 # Simulator instruction rate (inst/s) -host_mem_usage 224012 # Number of bytes of host memory used -host_seconds 656.39 # Real time elapsed on the host -host_tick_rate 1468620897 # Simulator tick rate (ticks/s) +host_inst_rate 3280168 # Simulator instruction rate (inst/s) +host_mem_usage 202508 # Number of bytes of host memory used +host_seconds 494.33 # Real time elapsed on the host +host_tick_rate 1950088412 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1621493983 # Number of instructions simulated sim_seconds 0.963993 # Number of seconds simulated @@ -29,6 +29,6 @@ system.cpu.num_int_register_writes 1617994650 # nu system.cpu.num_load_insts 419042125 # Number of load instructions system.cpu.num_mem_refs 607228182 # number of memory refs system.cpu.num_store_insts 188186057 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 48 # Number of system calls +system.cpu.workload.num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini index 967d3d328..fa700a969 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini @@ -51,6 +51,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -86,6 +87,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +123,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout index 920574653..eb8442791 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 8 2011 00:58:32 -M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip -M5 started Feb 8 2011 00:58:34 -M5 executing on burrito +M5 compiled Apr 19 2011 12:22:33 +M5 started Apr 19 2011 12:23:09 +M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt index 120240c59..1cc5290ea 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1667736 # Simulator instruction rate (inst/s) -host_mem_usage 231728 # Number of bytes of host memory used -host_seconds 972.27 # Real time elapsed on the host -host_tick_rate 1854683738 # Simulator tick rate (ticks/s) +host_inst_rate 2023797 # Simulator instruction rate (inst/s) +host_mem_usage 210248 # Number of bytes of host memory used +host_seconds 801.21 # Real time elapsed on the host +host_tick_rate 2250658484 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1621493983 # Number of instructions simulated sim_seconds 1.803259 # Number of seconds simulated @@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses 442048 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999731 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4094.896939 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999731 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 607228182 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 22431.962140 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 19431.962140 # average overall mshr miss latency @@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses 722 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.322357 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 660.186297 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.322357 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 1186516740 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -173,10 +173,10 @@ system.cpu.l2cache.demand_mshr_misses 89468 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.057043 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.494010 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 1869.199731 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 16187.723361 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.057043 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.494010 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 442770 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -218,6 +218,6 @@ system.cpu.num_int_register_writes 1617994650 # nu system.cpu.num_load_insts 419042125 # Number of load instructions system.cpu.num_mem_refs 607228182 # number of memory refs system.cpu.num_store_insts 188186057 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 48 # Number of system calls +system.cpu.workload.num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index 1b7aa47b5..674bf0325 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -50,6 +50,8 @@ BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 @@ -483,6 +485,8 @@ BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index c0c960a9c..9ebdcf06b 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 17 2011 22:48:41 -M5 started Mar 17 2011 22:50:14 -M5 executing on zizzer +M5 compiled Apr 19 2011 12:17:36 +M5 started Apr 19 2011 12:17:43 +M5 executing on maize command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 1aa5f5dbb..31187c584 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 127019 # Simulator instruction rate (inst/s) -host_mem_usage 296760 # Number of bytes of host memory used -host_seconds 449.39 # Real time elapsed on the host -host_tick_rate 4231820542 # Simulator tick rate (ticks/s) +host_inst_rate 245660 # Simulator instruction rate (inst/s) +host_mem_usage 294304 # Number of bytes of host memory used +host_seconds 232.36 # Real time elapsed on the host +host_tick_rate 8184534150 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 57080594 # Number of instructions simulated sim_seconds 1.901725 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu0.BPredUnit.condIncorrect 455851 # Nu system.cpu0.BPredUnit.condPredicted 9912652 # Number of conditional branches predicted system.cpu0.BPredUnit.lookups 11764241 # Number of BP lookups system.cpu0.BPredUnit.usedRAS 785162 # Number of times the RAS was used to get a target. -system.cpu0.commit.COM:branches 7026012 # Number of branches committed -system.cpu0.commit.COM:bw_lim_events 938799 # number cycles where commit BW limit reached -system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.commit.COM:committed_per_cycle::samples 72953049 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::mean 0.644604 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::stdev 1.459058 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::0 53597246 73.47% 73.47% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::1 8417746 11.54% 85.01% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::2 4840163 6.63% 91.64% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::3 2111570 2.89% 94.54% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::4 1587453 2.18% 96.71% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::5 575078 0.79% 97.50% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::6 337488 0.46% 97.96% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::7 547506 0.75% 98.71% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::8 938799 1.29% 100.00% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::total 72953049 # Number of insts commited each cycle -system.cpu0.commit.COM:count 47025846 # Number of instructions committed -system.cpu0.commit.COM:fp_insts 287589 # Number of committed floating point instructions. -system.cpu0.commit.COM:function_calls 606692 # Number of function calls committed. -system.cpu0.commit.COM:int_insts 43528406 # Number of committed integer instructions. -system.cpu0.commit.COM:loads 7569996 # Number of loads committed -system.cpu0.commit.COM:membars 198353 # Number of memory barriers committed -system.cpu0.commit.COM:refs 12959088 # Number of memory references committed -system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu0.commit.branchMispredicts 606344 # The number of times a branch was mispredicted +system.cpu0.commit.branches 7026012 # Number of branches committed +system.cpu0.commit.bw_lim_events 938799 # number cycles where commit BW limit reached +system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu0.commit.commitCommittedInsts 47025846 # The number of committed instructions system.cpu0.commit.commitNonSpecStalls 585526 # The number of times commit has been forced to stall to communicate backwards system.cpu0.commit.commitSquashedInsts 5969393 # The number of squashed insts skipped by commit +system.cpu0.commit.committed_per_cycle::samples 72953049 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.644604 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.459058 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 53597246 73.47% 73.47% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 8417746 11.54% 85.01% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4840163 6.63% 91.64% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2111570 2.89% 94.54% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1587453 2.18% 96.71% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 575078 0.79% 97.50% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 337488 0.46% 97.96% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 547506 0.75% 98.71% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 938799 1.29% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::total 72953049 # Number of insts commited each cycle +system.cpu0.commit.count 47025846 # Number of instructions committed +system.cpu0.commit.fp_insts 287589 # Number of committed floating point instructions. +system.cpu0.commit.function_calls 606692 # Number of function calls committed. +system.cpu0.commit.int_insts 43528406 # Number of committed integer instructions. +system.cpu0.commit.loads 7569996 # Number of loads committed +system.cpu0.commit.membars 198353 # Number of memory barriers committed +system.cpu0.commit.refs 12959088 # Number of memory references committed +system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed system.cpu0.committedInsts 44336308 # Number of Instructions Simulated system.cpu0.committedInsts_total 44336308 # Number of Instructions Simulated system.cpu0.cpi 2.365714 # CPI: Cycles Per Instruction @@ -161,10 +161,10 @@ system.cpu0.dcache.demand_mshr_misses 1044131 # nu system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.occ_%::0 0.956764 # Average percentage of cache occupancy -system.cpu0.dcache.occ_%::1 -0.001953 # Average percentage of cache occupancy system.cpu0.dcache.occ_blocks::0 489.863061 # Average occupied blocks per context system.cpu0.dcache.occ_blocks::1 -1.000000 # Average occupied blocks per context +system.cpu0.dcache.occ_percent::0 0.956764 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::1 -0.001953 # Average percentage of cache occupancy system.cpu0.dcache.overall_accesses::0 12748257 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 12748257 # number of overall (read+write) accesses @@ -198,15 +198,15 @@ system.cpu0.dcache.tagsinuse 488.863062 # Cy system.cpu0.dcache.total_refs 10250942 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.dcache.writebacks 532971 # number of writebacks -system.cpu0.decode.DECODE:BlockedCycles 30335443 # Number of cycles decode is blocked -system.cpu0.decode.DECODE:BranchMispred 32433 # Number of times decode detected a branch misprediction -system.cpu0.decode.DECODE:BranchResolved 467445 # Number of times decode resolved a branch -system.cpu0.decode.DECODE:DecodedInsts 58302731 # Number of instructions handled by decode -system.cpu0.decode.DECODE:IdleCycles 31236137 # Number of cycles decode is idle -system.cpu0.decode.DECODE:RunCycles 10506640 # Number of cycles decode is running -system.cpu0.decode.DECODE:SquashCycles 1085015 # Number of cycles decode is squashing -system.cpu0.decode.DECODE:SquashedInsts 96992 # Number of squashed instructions handled by decode -system.cpu0.decode.DECODE:UnblockCycles 874828 # Number of cycles decode is unblocking +system.cpu0.decode.BlockedCycles 30335443 # Number of cycles decode is blocked +system.cpu0.decode.BranchMispred 32433 # Number of times decode detected a branch misprediction +system.cpu0.decode.BranchResolved 467445 # Number of times decode resolved a branch +system.cpu0.decode.DecodedInsts 58302731 # Number of instructions handled by decode +system.cpu0.decode.IdleCycles 31236137 # Number of cycles decode is idle +system.cpu0.decode.RunCycles 10506640 # Number of cycles decode is running +system.cpu0.decode.SquashCycles 1085015 # Number of cycles decode is squashing +system.cpu0.decode.SquashedInsts 96992 # Number of squashed instructions handled by decode +system.cpu0.decode.UnblockCycles 874828 # Number of cycles decode is unblocking system.cpu0.dtb.data_accesses 755162 # DTB accesses system.cpu0.dtb.data_acv 768 # DTB access violations system.cpu0.dtb.data_hits 13777358 # DTB hits @@ -305,8 +305,8 @@ system.cpu0.icache.demand_mshr_misses 839121 # nu system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.occ_%::0 0.995851 # Average percentage of cache occupancy system.cpu0.icache.occ_blocks::0 509.875783 # Average occupied blocks per context +system.cpu0.icache.occ_percent::0 0.995851 # Average percentage of cache occupancy system.cpu0.icache.overall_accesses::0 7276849 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 7276849 # number of overall (read+write) accesses @@ -341,21 +341,13 @@ system.cpu0.icache.total_refs 6407354 # To system.cpu0.icache.warmup_cycle 23816238000 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 147 # number of writebacks system.cpu0.idleCycles 30848962 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.iew.EXEC:branches 7463719 # Number of branches executed -system.cpu0.iew.EXEC:nop 2952874 # number of nop insts executed -system.cpu0.iew.EXEC:rate 0.449724 # Inst execution rate -system.cpu0.iew.EXEC:refs 13848442 # number of memory reference insts executed -system.cpu0.iew.EXEC:stores 5542976 # Number of stores executed -system.cpu0.iew.EXEC:swp 0 # number of swp insts executed -system.cpu0.iew.WB:consumers 29600256 # num instructions consuming a value -system.cpu0.iew.WB:count 46794498 # cumulative count of insts written-back -system.cpu0.iew.WB:fanout 0.755402 # average fanout of values written-back -system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.iew.WB:producers 22360092 # num instructions producing a value -system.cpu0.iew.WB:rate 0.446142 # insts written-back per cycle -system.cpu0.iew.WB:sent 46875004 # cumulative count of insts sent to commit system.cpu0.iew.branchMispredicts 654991 # Number of branch mispredicts detected at execute +system.cpu0.iew.exec_branches 7463719 # Number of branches executed +system.cpu0.iew.exec_nop 2952874 # number of nop insts executed +system.cpu0.iew.exec_rate 0.449724 # Inst execution rate +system.cpu0.iew.exec_refs 13848442 # number of memory reference insts executed +system.cpu0.iew.exec_stores 5542976 # Number of stores executed +system.cpu0.iew.exec_swp 0 # number of swp insts executed system.cpu0.iew.iewBlockCycles 7417251 # Number of cycles IEW is blocking system.cpu0.iew.iewDispLoadInsts 8574378 # Number of dispatched load instructions system.cpu0.iew.iewDispNonSpecInsts 1551984 # Number of dispatched non-speculative instructions @@ -383,103 +375,93 @@ system.cpu0.iew.lsq.thread.0.squashedStores 318301 # system.cpu0.iew.memOrderViolationEvents 14768 # Number of memory order violations system.cpu0.iew.predictedNotTakenIncorrect 331464 # Number of branches that were predicted not taken incorrectly system.cpu0.iew.predictedTakenIncorrect 323527 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.wb_consumers 29600256 # num instructions consuming a value +system.cpu0.iew.wb_count 46794498 # cumulative count of insts written-back +system.cpu0.iew.wb_fanout 0.755402 # average fanout of values written-back +system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu0.iew.wb_producers 22360092 # num instructions producing a value +system.cpu0.iew.wb_rate 0.446142 # insts written-back per cycle +system.cpu0.iew.wb_sent 46875004 # cumulative count of insts sent to commit system.cpu0.int_regfile_reads 61873527 # number of integer regfile reads system.cpu0.int_regfile_writes 33807346 # number of integer regfile writes system.cpu0.ipc 0.422705 # IPC: Instructions Per Cycle system.cpu0.ipc_total 0.422705 # IPC: Total IPC of All Threads -system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 3310 0.01% 0.01% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntAlu 32518161 68.37% 68.38% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntMult 52150 0.11% 68.49% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.49% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 15557 0.03% 68.52% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 1653 0.00% 68.52% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemRead 8591465 18.06% 86.59% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemWrite 5582440 11.74% 98.32% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IprAccess 797481 1.68% 100.00% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::total 47562217 # Type of FU issued -system.cpu0.iq.ISSUE:fu_busy_cnt 465945 # FU busy when requested -system.cpu0.iq.ISSUE:fu_busy_rate 0.009797 # FU busy rate (busy events/executed inst) -system.cpu0.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntAlu 32168 6.90% 6.90% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdAdd 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdAlu 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdCmp 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdCvt 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdMisc 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdMult 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdShift 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemRead 239318 51.36% 58.27% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemWrite 194459 41.73% 100.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:issued_per_cycle::samples 74038064 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.642402 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.245120 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::0 51535584 69.61% 69.61% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::1 10789742 14.57% 84.18% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::2 4855288 6.56% 90.74% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::3 3076859 4.16% 94.89% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::4 2068166 2.79% 97.69% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::5 951116 1.28% 98.97% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::6 576531 0.78% 99.75% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::7 134332 0.18% 99.93% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::8 50446 0.07% 100.00% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::total 74038064 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:rate 0.453461 # Inst issue rate +system.cpu0.iq.FU_type_0::No_OpClass 3310 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 32518161 68.37% 68.38% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 52150 0.11% 68.49% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.49% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 15557 0.03% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1653 0.00% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 8591465 18.06% 86.59% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5582440 11.74% 98.32% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 797481 1.68% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::total 47562217 # Type of FU issued system.cpu0.iq.fp_alu_accesses 318343 # Number of floating point alu accesses system.cpu0.iq.fp_inst_queue_reads 608219 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_wakeup_accesses 289004 # Number of floating instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_writes 292979 # Number of floating instruction queue writes +system.cpu0.iq.fu_busy_cnt 465945 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.009797 # FU busy rate (busy events/executed inst) +system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 32168 6.90% 6.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 6.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 239318 51.36% 58.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 194459 41.73% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.int_alu_accesses 47706509 # Number of integer alu accesses system.cpu0.iq.int_inst_queue_reads 169046393 # Number of integer instruction queue reads system.cpu0.iq.int_inst_queue_wakeup_accesses 46505494 # Number of integer instruction queue wakeup accesses @@ -491,6 +473,24 @@ system.cpu0.iq.iqSquashedInstsExamined 5493402 # Nu system.cpu0.iq.iqSquashedInstsIssued 26169 # Number of squashed instructions issued system.cpu0.iq.iqSquashedNonSpecRemoved 1178887 # Number of squashed non-spec instructions that were removed system.cpu0.iq.iqSquashedOperandsExamined 2580822 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.issued_per_cycle::samples 74038064 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.642402 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.245120 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 51535584 69.61% 69.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10789742 14.57% 84.18% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4855288 6.56% 90.74% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3076859 4.16% 94.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2068166 2.79% 97.69% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 951116 1.28% 98.97% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 576531 0.78% 99.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 134332 0.18% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 50446 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 74038064 # Number of insts issued each cycle +system.cpu0.iq.rate 0.453461 # Inst issue rate system.cpu0.itb.data_accesses 0 # DTB accesses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_hits 0 # DTB hits @@ -604,25 +604,25 @@ system.cpu0.misc_regfile_writes 822223 # nu system.cpu0.numCycles 104887026 # number of cpu cycles simulated system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.rename.RENAME:BlockCycles 10226952 # Number of cycles rename is blocking -system.cpu0.rename.RENAME:CommittedMaps 32010277 # Number of HB maps that are committed -system.cpu0.rename.RENAME:IQFullEvents 742771 # Number of times rename has blocked due to IQ full -system.cpu0.rename.RENAME:IdleCycles 32554760 # Number of cycles rename is idle -system.cpu0.rename.RENAME:LSQFullEvents 1133948 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RENAME:ROBFullEvents 1272 # Number of times rename has blocked due to ROB full -system.cpu0.rename.RENAME:RenameLookups 67011150 # Number of register rename lookups that rename has made -system.cpu0.rename.RENAME:RenamedInsts 55116446 # Number of instructions processed by rename -system.cpu0.rename.RENAME:RenamedOperands 36911598 # Number of destination operands rename has renamed -system.cpu0.rename.RENAME:RunCycles 10340148 # Number of cycles rename is running -system.cpu0.rename.RENAME:SquashCycles 1085015 # Number of cycles rename is squashing -system.cpu0.rename.RENAME:UnblockCycles 3374476 # Number of cycles rename is unblocking -system.cpu0.rename.RENAME:UndoneMaps 4901321 # Number of HB maps that are undone due to squashing -system.cpu0.rename.RENAME:fp_rename_lookups 420638 # Number of floating rename lookups -system.cpu0.rename.RENAME:int_rename_lookups 66590512 # Number of integer rename lookups -system.cpu0.rename.RENAME:serializeStallCycles 16456711 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RENAME:serializingInsts 1432211 # count of serializing insts renamed -system.cpu0.rename.RENAME:skidInsts 8924178 # count of insts added to the skid buffer -system.cpu0.rename.RENAME:tempSerializingInsts 217463 # count of temporary serializing insts renamed +system.cpu0.rename.BlockCycles 10226952 # Number of cycles rename is blocking +system.cpu0.rename.CommittedMaps 32010277 # Number of HB maps that are committed +system.cpu0.rename.IQFullEvents 742771 # Number of times rename has blocked due to IQ full +system.cpu0.rename.IdleCycles 32554760 # Number of cycles rename is idle +system.cpu0.rename.LSQFullEvents 1133948 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.ROBFullEvents 1272 # Number of times rename has blocked due to ROB full +system.cpu0.rename.RenameLookups 67011150 # Number of register rename lookups that rename has made +system.cpu0.rename.RenamedInsts 55116446 # Number of instructions processed by rename +system.cpu0.rename.RenamedOperands 36911598 # Number of destination operands rename has renamed +system.cpu0.rename.RunCycles 10340148 # Number of cycles rename is running +system.cpu0.rename.SquashCycles 1085015 # Number of cycles rename is squashing +system.cpu0.rename.UnblockCycles 3374476 # Number of cycles rename is unblocking +system.cpu0.rename.UndoneMaps 4901321 # Number of HB maps that are undone due to squashing +system.cpu0.rename.fp_rename_lookups 420638 # Number of floating rename lookups +system.cpu0.rename.int_rename_lookups 66590512 # Number of integer rename lookups +system.cpu0.rename.serializeStallCycles 16456711 # count of cycles rename stalled for serializing inst +system.cpu0.rename.serializingInsts 1432211 # count of serializing insts renamed +system.cpu0.rename.skidInsts 8924178 # count of insts added to the skid buffer +system.cpu0.rename.tempSerializingInsts 217463 # count of temporary serializing insts renamed system.cpu0.rob.rob_reads 124831913 # The number of ROB reads system.cpu0.rob.rob_writes 107074537 # The number of ROB writes system.cpu0.timesIdled 1083848 # Number of times that the entire CPU went into an idle state and unscheduled itself @@ -634,38 +634,38 @@ system.cpu1.BPredUnit.condIncorrect 156935 # Nu system.cpu1.BPredUnit.condPredicted 2982175 # Number of conditional branches predicted system.cpu1.BPredUnit.lookups 3622579 # Number of BP lookups system.cpu1.BPredUnit.usedRAS 265553 # Number of times the RAS was used to get a target. -system.cpu1.commit.COM:branches 2030517 # Number of branches committed -system.cpu1.commit.COM:bw_lim_events 301379 # number cycles where commit BW limit reached -system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.commit.COM:committed_per_cycle::samples 21012360 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::mean 0.640018 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::stdev 1.474919 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::0 15563519 74.07% 74.07% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::1 2436778 11.60% 85.67% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::2 1200178 5.71% 91.38% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::3 640529 3.05% 94.43% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::4 421093 2.00% 96.43% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::5 209093 1.00% 97.42% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::6 129842 0.62% 98.04% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::7 109949 0.52% 98.57% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::8 301379 1.43% 100.00% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::total 21012360 # Number of insts commited each cycle -system.cpu1.commit.COM:count 13448285 # Number of instructions committed -system.cpu1.commit.COM:fp_insts 77652 # Number of committed floating point instructions. -system.cpu1.commit.COM:function_calls 196980 # Number of function calls committed. -system.cpu1.commit.COM:int_insts 12472477 # Number of committed integer instructions. -system.cpu1.commit.COM:loads 2329401 # Number of loads committed -system.cpu1.commit.COM:membars 46552 # Number of memory barriers committed -system.cpu1.commit.COM:refs 3759357 # Number of memory references committed -system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu1.commit.branchMispredicts 207236 # The number of times a branch was mispredicted +system.cpu1.commit.branches 2030517 # Number of branches committed +system.cpu1.commit.bw_lim_events 301379 # number cycles where commit BW limit reached +system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu1.commit.commitCommittedInsts 13448285 # The number of committed instructions system.cpu1.commit.commitNonSpecStalls 143621 # The number of times commit has been forced to stall to communicate backwards system.cpu1.commit.commitSquashedInsts 2329974 # The number of squashed insts skipped by commit +system.cpu1.commit.committed_per_cycle::samples 21012360 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.640018 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.474919 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 15563519 74.07% 74.07% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 2436778 11.60% 85.67% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1200178 5.71% 91.38% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 640529 3.05% 94.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 421093 2.00% 96.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 209093 1.00% 97.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 129842 0.62% 98.04% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 109949 0.52% 98.57% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 301379 1.43% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::total 21012360 # Number of insts commited each cycle +system.cpu1.commit.count 13448285 # Number of instructions committed +system.cpu1.commit.fp_insts 77652 # Number of committed floating point instructions. +system.cpu1.commit.function_calls 196980 # Number of function calls committed. +system.cpu1.commit.int_insts 12472477 # Number of committed integer instructions. +system.cpu1.commit.loads 2329401 # Number of loads committed +system.cpu1.commit.membars 46552 # Number of memory barriers committed +system.cpu1.commit.refs 3759357 # Number of memory references committed +system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed system.cpu1.committedInsts 12744286 # Number of Instructions Simulated system.cpu1.committedInsts_total 12744286 # Number of Instructions Simulated system.cpu1.cpi 1.922547 # CPI: Cycles Per Instruction @@ -779,8 +779,8 @@ system.cpu1.dcache.demand_mshr_misses 332240 # nu system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.occ_%::0 0.934780 # Average percentage of cache occupancy system.cpu1.dcache.occ_blocks::0 478.607338 # Average occupied blocks per context +system.cpu1.dcache.occ_percent::0 0.934780 # Average percentage of cache occupancy system.cpu1.dcache.overall_accesses::0 3867599 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 3867599 # number of overall (read+write) accesses @@ -814,15 +814,15 @@ system.cpu1.dcache.tagsinuse 478.607338 # Cy system.cpu1.dcache.total_refs 3201172 # Total number of references to valid blocks. system.cpu1.dcache.warmup_cycle 38945924000 # Cycle when the warmup percentage was hit. system.cpu1.dcache.writebacks 258747 # number of writebacks -system.cpu1.decode.DECODE:BlockedCycles 8810954 # Number of cycles decode is blocked -system.cpu1.decode.DECODE:BranchMispred 10399 # Number of times decode detected a branch misprediction -system.cpu1.decode.DECODE:BranchResolved 165542 # Number of times decode resolved a branch -system.cpu1.decode.DECODE:DecodedInsts 17654641 # Number of instructions handled by decode -system.cpu1.decode.DECODE:IdleCycles 8825966 # Number of cycles decode is idle -system.cpu1.decode.DECODE:RunCycles 3267842 # Number of cycles decode is running -system.cpu1.decode.DECODE:SquashCycles 401676 # Number of cycles decode is squashing -system.cpu1.decode.DECODE:SquashedInsts 25654 # Number of squashed instructions handled by decode -system.cpu1.decode.DECODE:UnblockCycles 107597 # Number of cycles decode is unblocking +system.cpu1.decode.BlockedCycles 8810954 # Number of cycles decode is blocked +system.cpu1.decode.BranchMispred 10399 # Number of times decode detected a branch misprediction +system.cpu1.decode.BranchResolved 165542 # Number of times decode resolved a branch +system.cpu1.decode.DecodedInsts 17654641 # Number of instructions handled by decode +system.cpu1.decode.IdleCycles 8825966 # Number of cycles decode is idle +system.cpu1.decode.RunCycles 3267842 # Number of cycles decode is running +system.cpu1.decode.SquashCycles 401676 # Number of cycles decode is squashing +system.cpu1.decode.SquashedInsts 25654 # Number of squashed instructions handled by decode +system.cpu1.decode.UnblockCycles 107597 # Number of cycles decode is unblocking system.cpu1.dtb.data_accesses 513633 # DTB accesses system.cpu1.dtb.data_acv 185 # DTB access violations system.cpu1.dtb.data_hits 4112878 # DTB hits @@ -921,8 +921,8 @@ system.cpu1.icache.demand_mshr_misses 233675 # nu system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.occ_%::0 0.980042 # Average percentage of cache occupancy system.cpu1.icache.occ_blocks::0 501.781584 # Average occupied blocks per context +system.cpu1.icache.occ_percent::0 0.980042 # Average percentage of cache occupancy system.cpu1.icache.overall_accesses::0 2099932 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 2099932 # number of overall (read+write) accesses @@ -957,21 +957,13 @@ system.cpu1.icache.total_refs 1856598 # To system.cpu1.icache.warmup_cycle 1710247615000 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 27 # number of writebacks system.cpu1.idleCycles 3087450 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.iew.EXEC:branches 2215124 # Number of branches executed -system.cpu1.iew.EXEC:nop 807214 # number of nop insts executed -system.cpu1.iew.EXEC:rate 0.568172 # Inst execution rate -system.cpu1.iew.EXEC:refs 4143059 # number of memory reference insts executed -system.cpu1.iew.EXEC:stores 1503378 # Number of stores executed -system.cpu1.iew.EXEC:swp 0 # number of swp insts executed -system.cpu1.iew.WB:consumers 9185033 # num instructions consuming a value -system.cpu1.iew.WB:count 13765716 # cumulative count of insts written-back -system.cpu1.iew.WB:fanout 0.723664 # average fanout of values written-back -system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.iew.WB:producers 6646874 # num instructions producing a value -system.cpu1.iew.WB:rate 0.561832 # insts written-back per cycle -system.cpu1.iew.WB:sent 13802747 # cumulative count of insts sent to commit system.cpu1.iew.branchMispredicts 229368 # Number of branch mispredicts detected at execute +system.cpu1.iew.exec_branches 2215124 # Number of branches executed +system.cpu1.iew.exec_nop 807214 # number of nop insts executed +system.cpu1.iew.exec_rate 0.568172 # Inst execution rate +system.cpu1.iew.exec_refs 4143059 # number of memory reference insts executed +system.cpu1.iew.exec_stores 1503378 # Number of stores executed +system.cpu1.iew.exec_swp 0 # number of swp insts executed system.cpu1.iew.iewBlockCycles 1971298 # Number of cycles IEW is blocking system.cpu1.iew.iewDispLoadInsts 2745592 # Number of dispatched load instructions system.cpu1.iew.iewDispNonSpecInsts 455487 # Number of dispatched non-speculative instructions @@ -999,103 +991,93 @@ system.cpu1.iew.lsq.thread.0.squashedStores 148395 # system.cpu1.iew.memOrderViolationEvents 4299 # Number of memory order violations system.cpu1.iew.predictedNotTakenIncorrect 105547 # Number of branches that were predicted not taken incorrectly system.cpu1.iew.predictedTakenIncorrect 123821 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.wb_consumers 9185033 # num instructions consuming a value +system.cpu1.iew.wb_count 13765716 # cumulative count of insts written-back +system.cpu1.iew.wb_fanout 0.723664 # average fanout of values written-back +system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu1.iew.wb_producers 6646874 # num instructions producing a value +system.cpu1.iew.wb_rate 0.561832 # insts written-back per cycle +system.cpu1.iew.wb_sent 13802747 # cumulative count of insts sent to commit system.cpu1.int_regfile_reads 18282773 # number of integer regfile reads system.cpu1.int_regfile_writes 9947337 # number of integer regfile writes system.cpu1.ipc 0.520143 # IPC: Instructions Per Cycle system.cpu1.ipc_total 0.520143 # IPC: Total IPC of All Threads -system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 3979 0.03% 0.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntAlu 9510353 67.51% 67.54% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntMult 21826 0.15% 67.69% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.69% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 11300 0.08% 67.77% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.77% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.77% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.77% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 1989 0.01% 67.79% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemRead 2724274 19.34% 87.13% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemWrite 1523321 10.81% 97.94% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IprAccess 290281 2.06% 100.00% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::total 14087323 # Type of FU issued -system.cpu1.iq.ISSUE:fu_busy_cnt 199599 # FU busy when requested -system.cpu1.iq.ISSUE:fu_busy_rate 0.014169 # FU busy rate (busy events/executed inst) -system.cpu1.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntAlu 10735 5.38% 5.38% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdAdd 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdAlu 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdCmp 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdCvt 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdMisc 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdMult 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdShift 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::MemRead 110682 55.45% 60.83% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::MemWrite 78182 39.17% 100.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:issued_per_cycle::samples 21414036 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.657855 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.314285 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::0 15246065 71.20% 71.20% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::1 2762432 12.90% 84.10% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::2 1149877 5.37% 89.47% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::3 942390 4.40% 93.87% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::4 699267 3.27% 97.13% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::5 379191 1.77% 98.90% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::6 160390 0.75% 99.65% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::7 52788 0.25% 99.90% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::8 21636 0.10% 100.00% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::total 21414036 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:rate 0.574958 # Inst issue rate +system.cpu1.iq.FU_type_0::No_OpClass 3979 0.03% 0.03% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 9510353 67.51% 67.54% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 21826 0.15% 67.69% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.69% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 11300 0.08% 67.77% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.77% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.77% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.77% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1989 0.01% 67.79% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.79% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2724274 19.34% 87.13% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1523321 10.81% 97.94% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 290281 2.06% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::total 14087323 # Type of FU issued system.cpu1.iq.fp_alu_accesses 84267 # Number of floating point alu accesses system.cpu1.iq.fp_inst_queue_reads 163543 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_wakeup_accesses 78913 # Number of floating instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_writes 80927 # Number of floating instruction queue writes +system.cpu1.iq.fu_busy_cnt 199599 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.014169 # FU busy rate (busy events/executed inst) +system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 10735 5.38% 5.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 110682 55.45% 60.83% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 78182 39.17% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.int_alu_accesses 14198676 # Number of integer alu accesses system.cpu1.iq.int_inst_queue_reads 49640351 # Number of integer instruction queue reads system.cpu1.iq.int_inst_queue_wakeup_accesses 13686803 # Number of integer instruction queue wakeup accesses @@ -1107,6 +1089,24 @@ system.cpu1.iq.iqSquashedInstsExamined 2199611 # Nu system.cpu1.iq.iqSquashedInstsIssued 15615 # Number of squashed instructions issued system.cpu1.iq.iqSquashedNonSpecRemoved 360700 # Number of squashed non-spec instructions that were removed system.cpu1.iq.iqSquashedOperandsExamined 1165068 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.issued_per_cycle::samples 21414036 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.657855 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.314285 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 15246065 71.20% 71.20% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 2762432 12.90% 84.10% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 1149877 5.37% 89.47% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 942390 4.40% 93.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 699267 3.27% 97.13% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 379191 1.77% 98.90% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 160390 0.75% 99.65% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 52788 0.25% 99.90% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 21636 0.10% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 21414036 # Number of insts issued each cycle +system.cpu1.iq.rate 0.574958 # Inst issue rate system.cpu1.itb.data_accesses 0 # DTB accesses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_hits 0 # DTB hits @@ -1209,25 +1209,25 @@ system.cpu1.misc_regfile_writes 221749 # nu system.cpu1.numCycles 24501486 # number of cpu cycles simulated system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.rename.RENAME:BlockCycles 2575160 # Number of cycles rename is blocking -system.cpu1.rename.RENAME:CommittedMaps 9194083 # Number of HB maps that are committed -system.cpu1.rename.RENAME:IQFullEvents 253610 # Number of times rename has blocked due to IQ full -system.cpu1.rename.RENAME:IdleCycles 9125188 # Number of cycles rename is idle -system.cpu1.rename.RENAME:LSQFullEvents 96900 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RENAME:ROBFullEvents 103 # Number of times rename has blocked due to ROB full -system.cpu1.rename.RENAME:RenameLookups 20382349 # Number of register rename lookups that rename has made -system.cpu1.rename.RENAME:RenamedInsts 16583054 # Number of instructions processed by rename -system.cpu1.rename.RENAME:RenamedOperands 11154403 # Number of destination operands rename has renamed -system.cpu1.rename.RENAME:RunCycles 2970670 # Number of cycles rename is running -system.cpu1.rename.RENAME:SquashCycles 401676 # Number of cycles rename is squashing -system.cpu1.rename.RENAME:UnblockCycles 911632 # Number of cycles rename is unblocking -system.cpu1.rename.RENAME:UndoneMaps 1960318 # Number of HB maps that are undone due to squashing -system.cpu1.rename.RENAME:fp_rename_lookups 113596 # Number of floating rename lookups -system.cpu1.rename.RENAME:int_rename_lookups 20268753 # Number of integer rename lookups -system.cpu1.rename.RENAME:serializeStallCycles 5429708 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RENAME:serializingInsts 475094 # count of serializing insts renamed -system.cpu1.rename.RENAME:skidInsts 2839642 # count of insts added to the skid buffer -system.cpu1.rename.RENAME:tempSerializingInsts 40509 # count of temporary serializing insts renamed +system.cpu1.rename.BlockCycles 2575160 # Number of cycles rename is blocking +system.cpu1.rename.CommittedMaps 9194083 # Number of HB maps that are committed +system.cpu1.rename.IQFullEvents 253610 # Number of times rename has blocked due to IQ full +system.cpu1.rename.IdleCycles 9125188 # Number of cycles rename is idle +system.cpu1.rename.LSQFullEvents 96900 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.ROBFullEvents 103 # Number of times rename has blocked due to ROB full +system.cpu1.rename.RenameLookups 20382349 # Number of register rename lookups that rename has made +system.cpu1.rename.RenamedInsts 16583054 # Number of instructions processed by rename +system.cpu1.rename.RenamedOperands 11154403 # Number of destination operands rename has renamed +system.cpu1.rename.RunCycles 2970670 # Number of cycles rename is running +system.cpu1.rename.SquashCycles 401676 # Number of cycles rename is squashing +system.cpu1.rename.UnblockCycles 911632 # Number of cycles rename is unblocking +system.cpu1.rename.UndoneMaps 1960318 # Number of HB maps that are undone due to squashing +system.cpu1.rename.fp_rename_lookups 113596 # Number of floating rename lookups +system.cpu1.rename.int_rename_lookups 20268753 # Number of integer rename lookups +system.cpu1.rename.serializeStallCycles 5429708 # count of cycles rename stalled for serializing inst +system.cpu1.rename.serializingInsts 475094 # count of serializing insts renamed +system.cpu1.rename.skidInsts 2839642 # count of insts added to the skid buffer +system.cpu1.rename.tempSerializingInsts 40509 # count of temporary serializing insts renamed system.cpu1.rob.rob_reads 36377887 # The number of ROB reads system.cpu1.rob.rob_writes 31956605 # The number of ROB writes system.cpu1.timesIdled 286877 # Number of times that the entire CPU went into an idle state and unscheduled itself @@ -1307,8 +1307,8 @@ system.iocache.demand_mshr_misses 41727 # nu system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_%::1 0.012954 # Average percentage of cache occupancy system.iocache.occ_blocks::1 0.207263 # Average occupied blocks per context +system.iocache.occ_percent::1 0.012954 # Average percentage of cache occupancy system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses system.iocache.overall_accesses::1 41727 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses @@ -1483,12 +1483,12 @@ system.l2c.demand_mshr_misses 434897 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.158827 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.036596 # Average percentage of cache occupancy -system.l2c.occ_%::2 0.351892 # Average percentage of cache occupancy system.l2c.occ_blocks::0 10408.866153 # Average occupied blocks per context system.l2c.occ_blocks::1 2398.359333 # Average occupied blocks per context system.l2c.occ_blocks::2 23061.577659 # Average occupied blocks per context +system.l2c.occ_percent::0 0.158827 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.036596 # Average percentage of cache occupancy +system.l2c.occ_percent::2 0.351892 # Average percentage of cache occupancy system.l2c.overall_accesses::0 1877438 # number of overall (read+write) accesses system.l2c.overall_accesses::1 550694 # number of overall (read+write) accesses system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index 3773b1a35..2121232b8 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -50,6 +50,8 @@ BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index b2f6462f2..4d6dea231 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 17 2011 22:48:41 -M5 started Mar 17 2011 22:50:11 -M5 executing on zizzer +M5 compiled Apr 19 2011 12:17:36 +M5 started Apr 19 2011 12:17:43 +M5 executing on maize command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index dddaa888b..3f1d069d1 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 125213 # Simulator instruction rate (inst/s) -host_mem_usage 294244 # Number of bytes of host memory used -host_seconds 424.00 # Real time elapsed on the host -host_tick_rate 4395569700 # Simulator tick rate (ticks/s) +host_inst_rate 247292 # Simulator instruction rate (inst/s) +host_mem_usage 292024 # Number of bytes of host memory used +host_seconds 214.68 # Real time elapsed on the host +host_tick_rate 8681128138 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 53089625 # Number of instructions simulated sim_seconds 1.863702 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 599479 # Nu system.cpu.BPredUnit.condPredicted 11925971 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 14248722 # Number of BP lookups system.cpu.BPredUnit.usedRAS 975192 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 8461745 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 1125976 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 87254730 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.645057 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.459520 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 64129239 73.50% 73.50% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 10001511 11.46% 84.96% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 5794569 6.64% 91.60% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 2584226 2.96% 94.56% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 1856466 2.13% 96.69% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 706744 0.81% 97.50% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 418456 0.48% 97.98% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 637543 0.73% 98.71% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 1125976 1.29% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 87254730 # Number of insts commited each cycle -system.cpu.commit.COM:count 56284256 # Number of instructions committed -system.cpu.commit.COM:fp_insts 324451 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 744594 # Number of function calls committed. -system.cpu.commit.COM:int_insts 52122555 # Number of committed integer instructions. -system.cpu.commit.COM:loads 9113387 # Number of loads committed -system.cpu.commit.COM:membars 227959 # Number of memory barriers committed -system.cpu.commit.COM:refs 15505823 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 769874 # The number of times a branch was mispredicted +system.cpu.commit.branches 8461745 # Number of branches committed +system.cpu.commit.bw_lim_events 1125976 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 56284256 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 667734 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 8032073 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 87254730 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.645057 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.459520 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 64129239 73.50% 73.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 10001511 11.46% 84.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 5794569 6.64% 91.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2584226 2.96% 94.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1856466 2.13% 96.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 706744 0.81% 97.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 418456 0.48% 97.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 637543 0.73% 98.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1125976 1.29% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 87254730 # Number of insts commited each cycle +system.cpu.commit.count 56284256 # Number of instructions committed +system.cpu.commit.fp_insts 324451 # Number of committed floating point instructions. +system.cpu.commit.function_calls 744594 # Number of function calls committed. +system.cpu.commit.int_insts 52122555 # Number of committed integer instructions. +system.cpu.commit.loads 9113387 # Number of loads committed +system.cpu.commit.membars 227959 # Number of memory barriers committed +system.cpu.commit.refs 15505823 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 53089625 # Number of Instructions Simulated system.cpu.committedInsts_total 53089625 # Number of Instructions Simulated system.cpu.cpi 2.304358 # CPI: Cycles Per Instruction @@ -161,8 +161,8 @@ system.cpu.dcache.demand_mshr_misses 1384507 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999992 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 511.995879 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999992 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses::0 15419136 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 15419136 # number of overall (read+write) accesses @@ -196,15 +196,15 @@ system.cpu.dcache.tagsinuse 511.995879 # Cy system.cpu.dcache.total_refs 12121656 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 19670000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 833416 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 36259760 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 44553 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 598925 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 70789187 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 37160222 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 12840041 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1435065 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 134914 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 994706 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 36259760 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 44553 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 598925 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 70789187 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 37160222 # Number of cycles decode is idle +system.cpu.decode.RunCycles 12840041 # Number of cycles decode is running +system.cpu.decode.SquashCycles 1435065 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 134914 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 994706 # Number of cycles decode is unblocking system.cpu.dtb.data_accesses 1263492 # DTB accesses system.cpu.dtb.data_acv 894 # DTB access violations system.cpu.dtb.data_hits 16635681 # DTB hits @@ -303,8 +303,8 @@ system.cpu.icache.demand_mshr_misses 993440 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.995757 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 509.827441 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.995757 # Average percentage of cache occupancy system.cpu.icache.overall_accesses::0 8770990 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 8770990 # number of overall (read+write) accesses @@ -339,21 +339,13 @@ system.cpu.icache.total_refs 7733869 # To system.cpu.icache.warmup_cycle 23815676000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 201 # number of writebacks system.cpu.idleCycles 33647698 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 9077931 # Number of branches executed -system.cpu.iew.EXEC:nop 3561617 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.466022 # Inst execution rate -system.cpu.iew.EXEC:refs 16730349 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 6619936 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 36206464 # num instructions consuming a value -system.cpu.iew.WB:count 56518708 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.749991 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 27154531 # num instructions producing a value -system.cpu.iew.WB:rate 0.461990 # insts written-back per cycle -system.cpu.iew.WB:sent 56632372 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 834392 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 9077931 # Number of branches executed +system.cpu.iew.exec_nop 3561617 # number of nop insts executed +system.cpu.iew.exec_rate 0.466022 # Inst execution rate +system.cpu.iew.exec_refs 16730349 # number of memory reference insts executed +system.cpu.iew.exec_stores 6619936 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 9479709 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 10494692 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 1785178 # Number of dispatched non-speculative instructions @@ -381,103 +373,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 456751 # system.cpu.iew.memOrderViolationEvents 18985 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 404859 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 429533 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 36206464 # num instructions consuming a value +system.cpu.iew.wb_count 56518708 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.749991 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 27154531 # num instructions producing a value +system.cpu.iew.wb_rate 0.461990 # insts written-back per cycle +system.cpu.iew.wb_sent 56632372 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 74751539 # number of integer regfile reads system.cpu.int_regfile_writes 40782350 # number of integer regfile writes system.cpu.ipc 0.433960 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.433960 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 39349401 68.40% 68.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 62002 0.11% 68.52% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.52% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 25611 0.04% 68.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 3636 0.01% 68.57% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 10457735 18.18% 86.75% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 6670425 11.59% 98.34% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 952735 1.66% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 57528826 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 549270 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.009548 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 45293 8.25% 8.25% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 2 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 291133 53.00% 61.25% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 212842 38.75% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 88689795 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.648652 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.255048 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 61727681 69.60% 69.60% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 12782826 14.41% 84.01% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 5739308 6.47% 90.48% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 3779668 4.26% 94.75% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 2566031 2.89% 97.64% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 1197199 1.35% 98.99% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 667320 0.75% 99.74% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 163755 0.18% 99.93% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 66007 0.07% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 88689795 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.470247 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39349401 68.40% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 62002 0.11% 68.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25611 0.04% 68.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10457735 18.18% 86.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6670425 11.59% 98.34% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 952735 1.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 57528826 # Type of FU issued system.cpu.iq.fp_alu_accesses 358048 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 686320 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 327228 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 333627 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 549270 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009548 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 45293 8.25% 8.25% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.25% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 291133 53.00% 61.25% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 212842 38.75% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 57712767 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 203646640 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 56191480 # Number of integer instruction queue wakeup accesses @@ -489,6 +471,24 @@ system.cpu.iq.iqSquashedInstsExamined 7361535 # Nu system.cpu.iq.iqSquashedInstsIssued 36245 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 1361667 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 3591759 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 88689795 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.648652 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.255048 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 61727681 69.60% 69.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 12782826 14.41% 84.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5739308 6.47% 90.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3779668 4.26% 94.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2566031 2.89% 97.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1197199 1.35% 98.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 667320 0.75% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 163755 0.18% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 66007 0.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 88689795 # Number of insts issued each cycle +system.cpu.iq.rate 0.470247 # Inst issue rate system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits @@ -598,25 +598,25 @@ system.cpu.misc_regfile_writes 949727 # nu system.cpu.numCycles 122337493 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 12932543 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 38258765 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1039474 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 38708983 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1241691 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 1519 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 81518808 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 66985432 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 44869849 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 12449033 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1435065 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 4145083 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 6611082 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 474213 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 81044595 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 19019086 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 1691185 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 11218533 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 244825 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 12932543 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 38258765 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 1039474 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 38708983 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 1241691 # Number of times rename has blocked due to LSQ full +system.cpu.rename.ROBFullEvents 1519 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 81518808 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 66985432 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 44869849 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 12449033 # Number of cycles rename is running +system.cpu.rename.SquashCycles 1435065 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 4145083 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 6611082 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 474213 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 81044595 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 19019086 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 1691185 # count of serializing insts renamed +system.cpu.rename.skidInsts 11218533 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 244825 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 150193940 # The number of ROB reads system.cpu.rob.rob_writes 130068170 # The number of ROB writes system.cpu.timesIdled 1318957 # Number of times that the entire CPU went into an idle state and unscheduled itself @@ -696,8 +696,8 @@ system.iocache.demand_mshr_misses 41725 # nu system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_%::1 0.080564 # Average percentage of cache occupancy system.iocache.occ_blocks::1 1.289021 # Average occupied blocks per context +system.iocache.occ_percent::1 0.080564 # Average percentage of cache occupancy system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses @@ -838,10 +838,10 @@ system.l2c.demand_mshr_misses 424680 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.185866 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.343812 # Average percentage of cache occupancy system.l2c.occ_blocks::0 12180.929780 # Average occupied blocks per context system.l2c.occ_blocks::1 22532.084945 # Average occupied blocks per context +system.l2c.occ_percent::0 0.185866 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.343812 # Average percentage of cache occupancy system.l2c.overall_accesses::0 2395045 # number of overall (read+write) accesses system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses system.l2c.overall_accesses::total 2395045 # number of overall (read+write) accesses diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini index 083bb5627..98177ee67 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -11,7 +11,7 @@ children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview t boot_cpu_frequency=500 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- root=/dev/mtdblock0 init_param=0 -kernel=/chips/pd/randd/dist/binaries/vmlinux.arm +kernel=/dist/m5/system/binaries/vmlinux.arm load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -495,7 +495,7 @@ type=ExeTracer [system.diskmem] type=PhysicalMemory -file=/chips/pd/randd/dist/disks/ael-arm.ext2 +file=/dist/m5/system/disks/ael-arm.ext2 latency=30000 latency_var=0 null=false diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout index 83f702085..7cdd9066f 100755 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 4 2011 11:17:23 -M5 started Apr 4 2011 11:17:27 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_FS/m5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 +M5 compiled Apr 19 2011 13:41:05 +M5 started Apr 19 2011 13:41:08 +M5 executing on maize +command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm info: Entering event queue @ 0. Starting simulation... Exiting @ tick 82662490500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index edd79728c..4fdec7dfb 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 92348 # Simulator instruction rate (inst/s) -host_mem_usage 389996 # Number of bytes of host memory used -host_seconds 562.86 # Real time elapsed on the host -host_tick_rate 146862568 # Simulator tick rate (ticks/s) +host_inst_rate 182620 # Simulator instruction rate (inst/s) +host_mem_usage 341656 # Number of bytes of host memory used +host_seconds 284.63 # Real time elapsed on the host +host_tick_rate 290422658 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 51978682 # Number of instructions simulated sim_seconds 0.082662 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 665245 # Nu system.cpu.BPredUnit.condPredicted 11246732 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 13229511 # Number of BP lookups system.cpu.BPredUnit.usedRAS 787550 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 8445621 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 801383 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 93507712 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.557193 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.351787 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 71892468 76.88% 76.88% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 10568988 11.30% 88.19% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 3427833 3.67% 91.85% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 1711600 1.83% 93.68% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 3527395 3.77% 97.46% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 741726 0.79% 98.25% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 541099 0.58% 98.83% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 295220 0.32% 99.14% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 801383 0.86% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 93507712 # Number of insts commited each cycle -system.cpu.commit.COM:count 52101862 # Number of instructions committed -system.cpu.commit.COM:fp_insts 6017 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 529734 # Number of function calls committed. -system.cpu.commit.COM:int_insts 42509491 # Number of committed integer instructions. -system.cpu.commit.COM:loads 9207015 # Number of loads committed -system.cpu.commit.COM:membars 3 # Number of memory barriers committed -system.cpu.commit.COM:refs 16293738 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 641726 # The number of times a branch was mispredicted +system.cpu.commit.branches 8445621 # Number of branches committed +system.cpu.commit.bw_lim_events 801383 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 52101862 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 2963383 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 16147201 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 93507712 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.557193 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.351787 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 71892468 76.88% 76.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 10568988 11.30% 88.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3427833 3.67% 91.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1711600 1.83% 93.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3527395 3.77% 97.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 741726 0.79% 98.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 541099 0.58% 98.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 295220 0.32% 99.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 801383 0.86% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 93507712 # Number of insts commited each cycle +system.cpu.commit.count 52101862 # Number of instructions committed +system.cpu.commit.fp_insts 6017 # Number of committed floating point instructions. +system.cpu.commit.function_calls 529734 # Number of function calls committed. +system.cpu.commit.int_insts 42509491 # Number of committed integer instructions. +system.cpu.commit.loads 9207015 # Number of loads committed +system.cpu.commit.membars 3 # Number of memory barriers committed +system.cpu.commit.refs 16293738 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 51978682 # Number of Instructions Simulated system.cpu.committedInsts_total 51978682 # Number of Instructions Simulated system.cpu.cpi 3.180631 # CPI: Cycles Per Instruction @@ -148,8 +148,8 @@ system.cpu.dcache.demand_mshr_misses 419458 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999513 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 511.750765 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999513 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses::0 16095916 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 16095916 # number of overall (read+write) accesses @@ -183,15 +183,15 @@ system.cpu.dcache.tagsinuse 511.750765 # Cy system.cpu.dcache.total_refs 13775411 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 48224000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 391506 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 53936622 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 70601 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 1224137 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 76419738 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 23948605 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 14435253 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 2568567 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 235986 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1187204 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 53936622 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 70601 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 1224137 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 76419738 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 23948605 # Number of cycles decode is idle +system.cpu.decode.RunCycles 14435253 # Number of cycles decode is running +system.cpu.decode.SquashCycles 2568567 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 235986 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 1187204 # Number of cycles decode is unblocking system.cpu.dtb.accesses 35246983 # DTB accesses system.cpu.dtb.align_faults 1461 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -299,8 +299,8 @@ system.cpu.icache.demand_mshr_misses 502982 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.970025 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 496.652768 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.970025 # Average percentage of cache occupancy system.cpu.icache.overall_accesses::0 6553557 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 6553557 # number of overall (read+write) accesses @@ -335,21 +335,13 @@ system.cpu.icache.total_refs 6005950 # To system.cpu.icache.warmup_cycle 6210686000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 41369 # number of writebacks system.cpu.idleCycles 69248731 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 10230019 # Number of branches executed -system.cpu.iew.EXEC:nop 166886 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.475904 # Inst execution rate -system.cpu.iew.EXEC:refs 35985354 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 7801149 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 62345618 # num instructions consuming a value -system.cpu.iew.WB:count 60884415 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.509768 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 31781773 # num instructions producing a value -system.cpu.iew.WB:rate 0.368271 # insts written-back per cycle -system.cpu.iew.WB:sent 78152559 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 711242 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 10230019 # Number of branches executed +system.cpu.iew.exec_nop 166886 # number of nop insts executed +system.cpu.iew.exec_rate 0.475904 # Inst execution rate +system.cpu.iew.exec_refs 35985354 # number of memory reference insts executed +system.cpu.iew.exec_stores 7801149 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 21406073 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 12848037 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 4002488 # Number of dispatched non-speculative instructions @@ -377,103 +369,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 1649637 # system.cpu.iew.memOrderViolationEvents 280540 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 186102 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 525140 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 62345618 # num instructions consuming a value +system.cpu.iew.wb_count 60884415 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.509768 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 31781773 # num instructions producing a value +system.cpu.iew.wb_rate 0.368271 # insts written-back per cycle +system.cpu.iew.wb_sent 78152559 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 182840055 # number of integer regfile reads system.cpu.int_regfile_writes 43911822 # number of integer regfile writes system.cpu.ipc 0.314403 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.314403 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2393207 3.00% 3.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 40767716 51.13% 54.13% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 71906 0.09% 54.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 10 0.00% 54.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 6 0.00% 54.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 895 0.00% 54.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 6 0.00% 54.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 28538408 35.79% 90.01% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 7966700 9.99% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 79738854 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 4821847 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.060470 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 5252 0.11% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 1 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 4503965 93.41% 93.52% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 312629 6.48% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 96076251 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.829954 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.379344 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 59918658 62.37% 62.37% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 16598524 17.28% 79.64% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 7253913 7.55% 87.19% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 4126106 4.29% 91.49% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 5947858 6.19% 97.68% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 1304063 1.36% 99.04% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 619735 0.65% 99.68% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 235123 0.24% 99.92% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 72271 0.08% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 96076251 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.482316 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 2393207 3.00% 3.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 40767716 51.13% 54.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 71906 0.09% 54.22% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 10 0.00% 54.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 54.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 895 0.00% 54.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 54.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28538408 35.79% 90.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7966700 9.99% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 79738854 # Type of FU issued system.cpu.iq.fp_alu_accesses 8555 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 16356 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 6330 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 9324 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 4821847 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.060470 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5252 0.11% 0.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 4503965 93.41% 93.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 312629 6.48% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 82158939 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 260560114 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 60878085 # Number of integer instruction queue wakeup accesses @@ -485,6 +467,24 @@ system.cpu.iq.iqSquashedInstsExamined 17660461 # Nu system.cpu.iq.iqSquashedInstsIssued 127886 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 1069030 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 22275203 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 96076251 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.829954 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.379344 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 59918658 62.37% 62.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 16598524 17.28% 79.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7253913 7.55% 87.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4126106 4.29% 91.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5947858 6.19% 97.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1304063 1.36% 99.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 619735 0.65% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 235123 0.24% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 72271 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 96076251 # Number of insts issued each cycle +system.cpu.iq.rate 0.482316 # Inst issue rate system.cpu.itb.accesses 6566505 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -517,25 +517,25 @@ system.cpu.misc_regfile_writes 505947 # nu system.cpu.numCycles 165324982 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 33112132 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 36741742 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 775024 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 25585942 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2464411 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 439406 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 190546426 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 73652077 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 53332963 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 13017560 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 2568567 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 5444932 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 16591220 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 49319 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 190497107 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 16347118 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 812559 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 14268469 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 662925 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 33112132 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 36741742 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 775024 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 25585942 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 2464411 # Number of times rename has blocked due to LSQ full +system.cpu.rename.ROBFullEvents 439406 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 190546426 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 73652077 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 53332963 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 13017560 # Number of cycles rename is running +system.cpu.rename.SquashCycles 2568567 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 5444932 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 16591220 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 49319 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 190497107 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 16347118 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 812559 # count of serializing insts renamed +system.cpu.rename.skidInsts 14268469 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 662925 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 160015001 # The number of ROB reads system.cpu.rob.rob_writes 139111158 # The number of ROB writes system.cpu.timesIdled 1092841 # Number of times that the entire CPU went into an idle state and unscheduled itself @@ -705,10 +705,10 @@ system.l2c.demand_mshr_misses 128445 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.099470 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.481649 # Average percentage of cache occupancy system.l2c.occ_blocks::0 6518.840874 # Average occupied blocks per context system.l2c.occ_blocks::1 31565.358061 # Average occupied blocks per context +system.l2c.occ_percent::0 0.099470 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.481649 # Average percentage of cache occupancy system.l2c.overall_accesses::0 923785 # number of overall (read+write) accesses system.l2c.overall_accesses::1 102462 # number of overall (read+write) accesses system.l2c.overall_accesses::total 1026247 # number of overall (read+write) accesses diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/status b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/status index cffda2d37..f27ebe211 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/status +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/status @@ -1 +1 @@ -build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 FAILED! +build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 FAILED! diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini index f89b48399..049d7897c 100644 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -498,9 +498,9 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/alisai01/dist/cpu2000/binaries/arm/linux/mcf +executable=/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 -input=/arm/scratch/alisai01/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout index 9a7a71365..6a4d20d87 100755 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 17:54:33 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 12:49:23 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt index 365ff8ea3..9f9cc3407 100644 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 190258 # Simulator instruction rate (inst/s) -host_mem_usage 391364 # Number of bytes of host memory used -host_seconds 479.61 # Real time elapsed on the host -host_tick_rate 93397782 # Simulator tick rate (ticks/s) +host_inst_rate 230945 # Simulator instruction rate (inst/s) +host_mem_usage 347768 # Number of bytes of host memory used +host_seconds 395.11 # Real time elapsed on the host +host_tick_rate 113371387 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91249905 # Number of instructions simulated sim_seconds 0.044795 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 1596208 # Nu system.cpu.BPredUnit.condPredicted 23792873 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 29586235 # Number of BP lookups system.cpu.BPredUnit.usedRAS 63032 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 18722470 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 671558 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 84101876 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.085142 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.487392 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 39810013 47.34% 47.34% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 21942954 26.09% 73.43% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 9544341 11.35% 84.77% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 7643789 9.09% 93.86% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 2702545 3.21% 97.08% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 240327 0.29% 97.36% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 909211 1.08% 98.44% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 637138 0.76% 99.20% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 671558 0.80% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 84101876 # Number of insts commited each cycle -system.cpu.commit.COM:count 91262514 # Number of instructions committed -system.cpu.commit.COM:fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 56148 # Number of function calls committed. -system.cpu.commit.COM:int_insts 72533318 # Number of committed integer instructions. -system.cpu.commit.COM:loads 22575876 # Number of loads committed -system.cpu.commit.COM:membars 3888 # Number of memory barriers committed -system.cpu.commit.COM:refs 27322629 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 1599456 # The number of times a branch was mispredicted +system.cpu.commit.branches 18722470 # Number of branches committed +system.cpu.commit.bw_lim_events 671558 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 91262514 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 554406 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 37771309 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 84101876 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.085142 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.487392 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 39810013 47.34% 47.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 21942954 26.09% 73.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 9544341 11.35% 84.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7643789 9.09% 93.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2702545 3.21% 97.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 240327 0.29% 97.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 909211 1.08% 98.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 637138 0.76% 99.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 671558 0.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 84101876 # Number of insts commited each cycle +system.cpu.commit.count 91262514 # Number of instructions committed +system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. +system.cpu.commit.function_calls 56148 # Number of function calls committed. +system.cpu.commit.int_insts 72533318 # Number of committed integer instructions. +system.cpu.commit.loads 22575876 # Number of loads committed +system.cpu.commit.membars 3888 # Number of memory barriers committed +system.cpu.commit.refs 27322629 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 91249905 # Number of Instructions Simulated system.cpu.committedInsts_total 91249905 # Number of Instructions Simulated system.cpu.cpi 0.981803 # CPI: Cycles Per Instruction @@ -105,8 +105,8 @@ system.cpu.dcache.demand_mshr_misses 950233 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.852828 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 3493.184851 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.852828 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 29231190 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 8180.869220 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 3273.127173 # average overall mshr miss latency @@ -128,15 +128,15 @@ system.cpu.dcache.tagsinuse 3493.184851 # Cy system.cpu.dcache.total_refs 28069666 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 18896443000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 943153 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 17588781 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 9537 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 4762375 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 139874563 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 32956661 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 32742845 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 5457924 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 30438 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 813588 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 17588781 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 9537 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 4762375 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 139874563 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 32956661 # Number of cycles decode is idle +system.cpu.decode.RunCycles 32742845 # Number of cycles decode is running +system.cpu.decode.SquashCycles 5457924 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 30438 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 813588 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -221,8 +221,8 @@ system.cpu.icache.demand_mshr_misses 674 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.277518 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 568.356083 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.277518 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 15336543 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 35886.138614 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 34397.626113 # average overall mshr miss latency @@ -245,21 +245,13 @@ system.cpu.icache.total_refs 15335735 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 29674 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 20951910 # Number of branches executed -system.cpu.iew.EXEC:nop 39919 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.157669 # Inst execution rate -system.cpu.iew.EXEC:refs 30258239 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 5196792 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 127150055 # num instructions consuming a value -system.cpu.iew.WB:count 102173263 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.489247 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 62207806 # num instructions producing a value -system.cpu.iew.WB:rate 1.140461 # insts written-back per cycle -system.cpu.iew.WB:sent 102563540 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 1809783 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 20951910 # Number of branches executed +system.cpu.iew.exec_nop 39919 # number of nop insts executed +system.cpu.iew.exec_rate 1.157669 # Inst execution rate +system.cpu.iew.exec_refs 30258239 # number of memory reference insts executed +system.cpu.iew.exec_stores 5196792 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 316819 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 31496278 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 689079 # Number of dispatched non-speculative instructions @@ -287,103 +279,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 1867594 # system.cpu.iew.memOrderViolationEvents 14224 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 282853 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 1526930 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 127150055 # num instructions consuming a value +system.cpu.iew.wb_count 102173263 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.489247 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 62207806 # num instructions producing a value +system.cpu.iew.wb_rate 1.140461 # insts written-back per cycle +system.cpu.iew.wb_sent 102563540 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 259728905 # number of integer regfile reads system.cpu.int_regfile_writes 80595212 # number of integer regfile writes system.cpu.ipc 1.018534 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.018534 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 74250134 70.21% 70.21% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 10532 0.01% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 1 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 27 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 46 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 5 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 26236363 24.81% 95.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 5264077 4.98% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 105761185 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 177153 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.001675 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 40759 23.01% 23.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 27 0.02% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 78448 44.28% 67.31% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 57919 32.69% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 89559799 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.180900 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.457109 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 38412400 42.89% 42.89% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 23501864 26.24% 69.13% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 14299372 15.97% 85.10% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 6452092 7.20% 92.30% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 2377583 2.65% 94.96% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 2675567 2.99% 97.94% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 1597319 1.78% 99.73% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 116596 0.13% 99.86% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 127006 0.14% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 89559799 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.180509 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74250134 70.21% 70.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10532 0.01% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 27 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 46 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26236363 24.81% 95.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5264077 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 105761185 # Type of FU issued system.cpu.iq.fp_alu_accesses 110 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 216 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 99 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 196 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 177153 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001675 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 40759 23.01% 23.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.02% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 78448 44.28% 67.31% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 57919 32.69% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 105938228 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 301287282 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 102173164 # Number of integer instruction queue wakeup accesses @@ -395,6 +377,24 @@ system.cpu.iq.iqSquashedInstsExamined 37472339 # Nu system.cpu.iq.iqSquashedInstsIssued 28176 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 139525 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 69343981 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 89559799 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.180900 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.457109 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 38412400 42.89% 42.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23501864 26.24% 69.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 14299372 15.97% 85.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6452092 7.20% 92.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2377583 2.65% 94.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2675567 2.99% 97.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1597319 1.78% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 116596 0.13% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 127006 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 89559799 # Number of insts issued each cycle +system.cpu.iq.rate 1.180509 # Inst issue rate system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -468,10 +468,10 @@ system.cpu.l2cache.demand_mshr_misses 15537 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.012381 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.250026 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 405.690928 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 8192.856570 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.012381 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.250026 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 950905 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34233.211115 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31042.833237 # average overall mshr miss latency @@ -502,28 +502,28 @@ system.cpu.misc_regfile_writes 11602 # nu system.cpu.numCycles 89589473 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 2558009 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 71576967 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 2891853 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 35560664 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1952065 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 58 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 350271207 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 135568411 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 105865304 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 30904016 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 5457924 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 5891977 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 34288334 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 787 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 350270420 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 9187209 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 701223 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 13035103 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 702184 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 2558009 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 71576967 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 2891853 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 35560664 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 1952065 # Number of times rename has blocked due to LSQ full +system.cpu.rename.ROBFullEvents 58 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 350271207 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 135568411 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 105865304 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 30904016 # Number of cycles rename is running +system.cpu.rename.SquashCycles 5457924 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 5891977 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 34288334 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 787 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 350270420 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 9187209 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 701223 # count of serializing insts renamed +system.cpu.rename.skidInsts 13035103 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 702184 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 212458407 # The number of ROB reads system.cpu.rob.rob_writes 263525841 # The number of ROB writes system.cpu.timesIdled 1433 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 442 # Number of system calls +system.cpu.workload.num_syscalls 442 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini index 2f887d410..a584d29ed 100644 --- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini @@ -61,14 +61,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf +executable=/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 -input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout index d4df9bd55..778a5635d 100755 --- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout +++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 17:54:34 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 12:50:38 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt index 4aa89302d..857cf86ba 100644 --- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 950960 # Simulator instruction rate (inst/s) -host_mem_usage 379668 # Number of bytes of host memory used -host_seconds 95.96 # Real time elapsed on the host -host_tick_rate 565248287 # Simulator tick rate (ticks/s) +host_inst_rate 3623403 # Simulator instruction rate (inst/s) +host_mem_usage 338784 # Number of bytes of host memory used +host_seconds 25.18 # Real time elapsed on the host +host_tick_rate 2153732946 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91252969 # Number of instructions simulated sim_seconds 0.054241 # Number of seconds simulated @@ -71,6 +71,6 @@ system.cpu.num_int_register_writes 70993656 # nu system.cpu.num_load_insts 22573967 # Number of load instructions system.cpu.num_mem_refs 27318811 # number of memory refs system.cpu.num_store_insts 4744844 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 442 # Number of system calls +system.cpu.workload.num_syscalls 442 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini index 9fe66a752..b43580bea 100644 --- a/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini @@ -164,14 +164,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing +cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf +executable=/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 -input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/10.mcf/ref/arm/linux/simple-timing/simout index 4622f4ee0..ce41a8bab 100755 --- a/tests/long/10.mcf/ref/arm/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 17:54:34 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 12:51:14 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt index 389bae1e3..6b71bf251 100644 --- a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 492863 # Simulator instruction rate (inst/s) -host_mem_usage 387392 # Number of bytes of host memory used -host_seconds 185.09 # Real time elapsed on the host -host_tick_rate 800055292 # Simulator tick rate (ticks/s) +host_inst_rate 2007081 # Simulator instruction rate (inst/s) +host_mem_usage 346528 # Number of bytes of host memory used +host_seconds 45.45 # Real time elapsed on the host +host_tick_rate 3258049978 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91226321 # Number of instructions simulated sim_seconds 0.148086 # Number of seconds simulated @@ -54,8 +54,8 @@ system.cpu.dcache.demand_mshr_misses 946798 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.871228 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 3568.549501 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.871228 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 27284389 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 14657.859438 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 11657.859438 # average overall mshr miss latency @@ -130,8 +130,8 @@ system.cpu.icache.demand_mshr_misses 599 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.249187 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 510.335448 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.249187 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 107830780 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 54527.545910 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 51527.545910 # average overall mshr miss latency @@ -219,10 +219,10 @@ system.cpu.l2cache.demand_mshr_misses 15408 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.009921 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.271918 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 325.097811 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 8910.209882 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.009921 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.271918 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 947397 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -264,6 +264,6 @@ system.cpu.num_int_register_writes 70993656 # nu system.cpu.num_load_insts 22573967 # Number of load instructions system.cpu.num_mem_refs 27318811 # number of memory refs system.cpu.num_store_insts 4744844 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 442 # Number of system calls +system.cpu.workload.num_syscalls 442 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout index a011c886e..a5435dfc1 100755 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:13:30 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:14:01 -M5 executing on burrito +M5 compiled Apr 19 2011 12:19:46 +M5 started Apr 19 2011 12:20:18 +M5 executing on maize command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt index 282686242..5f734ed46 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1159873 # Simulator instruction rate (inst/s) -host_mem_usage 351876 # Number of bytes of host memory used -host_seconds 210.23 # Real time elapsed on the host -host_tick_rate 581353978 # Simulator tick rate (ticks/s) +host_inst_rate 4484533 # Simulator instruction rate (inst/s) +host_mem_usage 329760 # Number of bytes of host memory used +host_seconds 54.37 # Real time elapsed on the host +host_tick_rate 2247743371 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 243835278 # Number of instructions simulated sim_seconds 0.122216 # Number of seconds simulated @@ -29,6 +29,6 @@ system.cpu.num_int_register_writes 215451609 # nu system.cpu.num_load_insts 82803522 # Number of load instructions system.cpu.num_mem_refs 105711442 # number of memory refs system.cpu.num_store_insts 22907920 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 443 # Number of system calls +system.cpu.workload.num_syscalls 443 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini index dd7acffe5..a1bafa0cb 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini @@ -51,6 +51,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -86,6 +87,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +123,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout index 280cd1a31..e8a8f1145 100755 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:13:30 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:13:48 -M5 executing on burrito +M5 compiled Apr 19 2011 12:19:46 +M5 started Apr 19 2011 12:19:52 +M5 executing on maize command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 1b0d7fe21..3eb9bf1a6 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 483058 # Simulator instruction rate (inst/s) -host_mem_usage 359588 # Number of bytes of host memory used -host_seconds 504.77 # Real time elapsed on the host -host_tick_rate 718005180 # Simulator tick rate (ticks/s) +host_inst_rate 2305909 # Simulator instruction rate (inst/s) +host_mem_usage 337512 # Number of bytes of host memory used +host_seconds 105.74 # Real time elapsed on the host +host_tick_rate 3427441926 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 243835278 # Number of instructions simulated sim_seconds 0.362431 # Number of seconds simulated @@ -60,8 +60,8 @@ system.cpu.dcache.demand_mshr_misses 939567 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.870074 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 3563.824259 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.870074 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 105122385 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 14660.150899 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 11660.150899 # average overall mshr miss latency @@ -115,8 +115,8 @@ system.cpu.icache.demand_mshr_misses 882 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.354281 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 725.567632 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.354281 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 244421512 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55857.142857 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52857.142857 # average overall mshr miss latency @@ -183,10 +183,10 @@ system.cpu.l2cache.demand_mshr_misses 15648 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.011460 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.270424 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 375.506440 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 8861.245791 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.011460 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.270424 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 940453 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -228,6 +228,6 @@ system.cpu.num_int_register_writes 215451608 # nu system.cpu.num_load_insts 82803522 # Number of load instructions system.cpu.num_mem_refs 105711442 # number of memory refs system.cpu.num_store_insts 22907920 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 443 # Number of system calls +system.cpu.workload.num_syscalls 443 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini index 1f2e75864..de48f92fd 100644 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -25,6 +25,8 @@ BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout index 2b45d7376..c33237447 100755 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 18 2011 20:12:06 -M5 started Mar 18 2011 20:12:16 -M5 executing on zizzer +M5 compiled Apr 19 2011 12:22:33 +M5 started Apr 19 2011 12:30:19 +M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt index 2d839c8d9..6bc8ba293 100644 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 173311 # Simulator instruction rate (inst/s) -host_mem_usage 350460 # Number of bytes of host memory used -host_seconds 1605.16 # Real time elapsed on the host -host_tick_rate 50708988 # Simulator tick rate (ticks/s) +host_inst_rate 265187 # Simulator instruction rate (inst/s) +host_mem_usage 346300 # Number of bytes of host memory used +host_seconds 1049.04 # Real time elapsed on the host +host_tick_rate 77591071 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 278192519 # Number of instructions simulated sim_seconds 0.081396 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 2465320 # Nu system.cpu.BPredUnit.condPredicted 43504790 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 43504790 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 29309710 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 13548841 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 149131695 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.865415 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.481905 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 63516016 42.59% 42.59% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 27005826 18.11% 60.70% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 19486009 13.07% 73.77% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 13132636 8.81% 82.57% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 4245933 2.85% 85.42% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 3434891 2.30% 87.72% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 3062949 2.05% 89.78% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 1698594 1.14% 90.91% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 13548841 9.09% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 149131695 # Number of insts commited each cycle -system.cpu.commit.COM:count 278192519 # Number of instructions committed -system.cpu.commit.COM:fp_insts 40 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 0 # Number of function calls committed. -system.cpu.commit.COM:int_insts 278186227 # Number of committed integer instructions. -system.cpu.commit.COM:loads 90779388 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 122219139 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 2465329 # The number of times a branch was mispredicted +system.cpu.commit.branches 29309710 # Number of branches committed +system.cpu.commit.bw_lim_events 13548841 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 278192519 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 88842299 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 149131695 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.865415 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.481905 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 63516016 42.59% 42.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 27005826 18.11% 60.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 19486009 13.07% 73.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13132636 8.81% 82.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4245933 2.85% 85.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3434891 2.30% 87.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3062949 2.05% 89.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1698594 1.14% 90.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 13548841 9.09% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 149131695 # Number of insts commited each cycle +system.cpu.commit.count 278192519 # Number of instructions committed +system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. +system.cpu.commit.function_calls 0 # Number of function calls committed. +system.cpu.commit.int_insts 278186227 # Number of committed integer instructions. +system.cpu.commit.loads 90779388 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.refs 122219139 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 278192519 # Number of Instructions Simulated system.cpu.committedInsts_total 278192519 # Number of Instructions Simulated system.cpu.cpi 0.585179 # CPI: Cycles Per Instruction @@ -96,8 +96,8 @@ system.cpu.dcache.demand_mshr_misses 2078004 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.994940 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4075.274681 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.994940 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 94785588 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 7490.439865 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 3562.354617 # average overall mshr miss latency @@ -119,12 +119,12 @@ system.cpu.dcache.tagsinuse 4075.274681 # Cy system.cpu.dcache.total_refs 92329423 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 30396735000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 1448011 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 13645155 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 390459172 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 68124952 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 66154578 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 12492114 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 1207010 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 13645155 # Number of cycles decode is blocked +system.cpu.decode.DecodedInsts 390459172 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 68124952 # Number of cycles decode is idle +system.cpu.decode.RunCycles 66154578 # Number of cycles decode is running +system.cpu.decode.SquashCycles 12492114 # Number of cycles decode is squashing +system.cpu.decode.UnblockCycles 1207010 # Number of cycles decode is unblocking system.cpu.fetch.Branches 43504790 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 30855910 # Number of cache lines fetched system.cpu.fetch.Cycles 71218247 # Number of cycles fetch has run and was not squashing or blocked @@ -188,8 +188,8 @@ system.cpu.icache.demand_mshr_misses 1013 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.396500 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 812.031019 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.396500 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 30855910 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 36182.458888 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35209.772952 # average overall mshr miss latency @@ -212,21 +212,13 @@ system.cpu.icache.total_refs 30854633 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 1168640 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 32808514 # Number of branches executed -system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 2.009454 # Inst execution rate -system.cpu.iew.EXEC:refs 141715314 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 34352421 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 330470543 # num instructions consuming a value -system.cpu.iew.WB:count 324204287 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.735351 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 243011799 # num instructions producing a value -system.cpu.iew.WB:rate 1.991519 # insts written-back per cycle -system.cpu.iew.WB:sent 325408414 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 2866285 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 32808514 # Number of branches executed +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_rate 2.009454 # Inst execution rate +system.cpu.iew.exec_refs 141715314 # number of memory reference insts executed +system.cpu.iew.exec_stores 34352421 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 739357 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 121527888 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions @@ -254,103 +246,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 8203432 # system.cpu.iew.memOrderViolationEvents 237293 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 582972 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 2283313 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 330470543 # num instructions consuming a value +system.cpu.iew.wb_count 324204287 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.735351 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 243011799 # num instructions producing a value +system.cpu.iew.wb_rate 1.991519 # insts written-back per cycle +system.cpu.iew.wb_sent 325408414 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 572686347 # number of integer regfile reads system.cpu.int_regfile_writes 291536884 # number of integer regfile writes system.cpu.ipc 1.708879 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.708879 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 16703 0.01% 0.01% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 188329198 56.76% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 16 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 108641887 32.74% 89.51% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 34821337 10.49% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 331809141 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 1744992 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.005259 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 20475 1.17% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 1576903 90.37% 91.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 147614 8.46% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 161623809 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 2.052972 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.792191 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 44438080 27.49% 27.49% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 26560474 16.43% 43.93% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 27560184 17.05% 60.98% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 26726118 16.54% 77.52% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 19530475 12.08% 89.60% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 11104171 6.87% 96.47% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 3863575 2.39% 98.86% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 1600116 0.99% 99.85% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 240616 0.15% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 161623809 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 2.038234 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 16703 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 188329198 56.76% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 16 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 108641887 32.74% 89.51% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 34821337 10.49% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 331809141 # Type of FU issued system.cpu.iq.fp_alu_accesses 101 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 208 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 80 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 238 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 1744992 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005259 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 20475 1.17% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1576903 90.37% 91.54% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 147614 8.46% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 333537329 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 827162429 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 324204207 # Number of integer instruction queue wakeup accesses @@ -362,6 +344,24 @@ system.cpu.iq.iqSquashedInstsExamined 88592670 # Nu system.cpu.iq.iqSquashedInstsIssued 175554 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 19 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 124945161 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 161623809 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.052972 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.792191 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 44438080 27.49% 27.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 26560474 16.43% 43.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 27560184 17.05% 60.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 26726118 16.54% 77.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 19530475 12.08% 89.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 11104171 6.87% 96.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3863575 2.39% 98.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1600116 0.99% 99.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 240616 0.15% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 161623809 # Number of insts issued each cycle +system.cpu.iq.rate 2.038234 # Inst issue rate system.cpu.l2cache.ReadExReq_accesses 106011 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 34192.017786 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31115.893095 # average ReadExReq mshr miss latency @@ -413,10 +413,10 @@ system.cpu.l2cache.demand_mshr_misses 76519 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.196368 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.354446 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 6434.571377 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 11614.477696 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.196368 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.354446 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 2079015 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34202.596741 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31074.223395 # average overall mshr miss latency @@ -446,28 +446,28 @@ system.cpu.misc_regfile_reads 211169577 # nu system.cpu.numCycles 162792449 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 3023364 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 248344192 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 130274 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 72054036 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 9710787 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 12 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 941229334 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 383108308 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 343773743 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 63044913 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 12492114 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 11002939 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 95429551 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 586 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 941228748 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 6443 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 468 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 25868384 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 462 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 3023364 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 248344192 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 130274 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 72054036 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 9710787 # Number of times rename has blocked due to LSQ full +system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 941229334 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 383108308 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 343773743 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 63044913 # Number of cycles rename is running +system.cpu.rename.SquashCycles 12492114 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 11002939 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 95429551 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 586 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 941228748 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 6443 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 468 # count of serializing insts renamed +system.cpu.rename.skidInsts 25868384 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 462 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 502617672 # The number of ROB reads system.cpu.rob.rob_writes 746575877 # The number of ROB writes system.cpu.timesIdled 40062 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 444 # Number of system calls +system.cpu.workload.num_syscalls 444 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout index 2aa2852be..0d61b002c 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 8 2011 00:58:32 -M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip -M5 started Feb 8 2011 00:58:34 -M5 executing on burrito +M5 compiled Apr 19 2011 12:22:33 +M5 started Apr 19 2011 12:39:34 +M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt index aacdb2309..ed3183ec3 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1568972 # Simulator instruction rate (inst/s) -host_mem_usage 358500 # Number of bytes of host memory used -host_seconds 177.31 # Real time elapsed on the host -host_tick_rate 952856596 # Simulator tick rate (ticks/s) +host_inst_rate 3107267 # Simulator instruction rate (inst/s) +host_mem_usage 337076 # Number of bytes of host memory used +host_seconds 89.53 # Real time elapsed on the host +host_tick_rate 1887081425 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 278192520 # Number of instructions simulated sim_seconds 0.168950 # Number of seconds simulated @@ -29,6 +29,6 @@ system.cpu.num_int_register_writes 248344166 # nu system.cpu.num_load_insts 90779388 # Number of load instructions system.cpu.num_mem_refs 122219139 # number of memory refs system.cpu.num_store_insts 31439751 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 444 # Number of system calls +system.cpu.workload.num_syscalls 444 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini index 12f3ad44d..2184f1531 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini @@ -51,6 +51,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -86,6 +87,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +123,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout index 56b5fe9df..1d6e35c6c 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 8 2011 00:58:32 -M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip -M5 started Feb 8 2011 00:58:34 -M5 executing on burrito +M5 compiled Apr 19 2011 12:22:33 +M5 started Apr 19 2011 12:41:14 +M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt index e90dea7b7..e994cf670 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1018906 # Simulator instruction rate (inst/s) -host_mem_usage 366224 # Number of bytes of host memory used -host_seconds 273.03 # Real time elapsed on the host -host_tick_rate 1355197592 # Simulator tick rate (ticks/s) +host_inst_rate 1776708 # Simulator instruction rate (inst/s) +host_mem_usage 344820 # Number of bytes of host memory used +host_seconds 156.58 # Real time elapsed on the host +host_tick_rate 2363113199 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 278192520 # Number of instructions simulated sim_seconds 0.370011 # Number of seconds simulated @@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses 2066829 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.995279 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4076.661903 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.995279 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 122219201 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 15539.675029 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 12539.674303 # average overall mshr miss latency @@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses 808 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.325289 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 666.191948 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.325289 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 217696209 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -173,10 +173,10 @@ system.cpu.l2cache.demand_mshr_misses 76575 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.199945 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.368128 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 6551.798271 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 12062.804989 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.199945 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.368128 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 2067637 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000.385243 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -218,6 +218,6 @@ system.cpu.num_int_register_writes 248344166 # nu system.cpu.num_load_insts 90779388 # Number of load instructions system.cpu.num_mem_refs 122219139 # number of memory refs system.cpu.num_store_insts 31439751 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 444 # Number of system calls +system.cpu.workload.num_syscalls 444 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini index 4b915cedf..91e8c0469 100644 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini @@ -498,9 +498,9 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/alisai01/dist/cpu2000/binaries/arm/linux/parser +executable=/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 -input=/arm/scratch/alisai01/dist/cpu2000/data/parser/mdred/input/parser.in +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/20.parser/ref/arm/linux/o3-timing/simout index ce3065a66..092b47dee 100755 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 17:54:34 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 12:52:10 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt index a263a0962..8a2f1e243 100644 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 134709 # Simulator instruction rate (inst/s) -host_mem_usage 264692 # Number of bytes of host memory used -host_seconds 4256.17 # Real time elapsed on the host -host_tick_rate 78176241 # Simulator tick rate (ticks/s) +host_inst_rate 191028 # Simulator instruction rate (inst/s) +host_mem_usage 221120 # Number of bytes of host memory used +host_seconds 3001.36 # Real time elapsed on the host +host_tick_rate 110860138 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 573342397 # Number of instructions simulated sim_seconds 0.332731 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 18809964 # Nu system.cpu.BPredUnit.condPredicted 186338321 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 233659814 # Number of BP lookups system.cpu.BPredUnit.usedRAS 11860569 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 120192362 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 6858146 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 603587786 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.952117 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.448029 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 310030081 51.36% 51.36% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 161983498 26.84% 78.20% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 68757792 11.39% 89.59% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 25709435 4.26% 93.85% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 17326011 2.87% 96.72% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 5210197 0.86% 97.59% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 6149685 1.02% 98.60% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 1562941 0.26% 98.86% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 6858146 1.14% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 603587786 # Number of insts commited each cycle -system.cpu.commit.COM:count 574686281 # Number of instructions committed -system.cpu.commit.COM:fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 9757362 # Number of function calls committed. -system.cpu.commit.COM:int_insts 473702185 # Number of committed integer instructions. -system.cpu.commit.COM:loads 126773177 # Number of loads committed -system.cpu.commit.COM:membars 1488542 # Number of memory barriers committed -system.cpu.commit.COM:refs 184377275 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 20926821 # The number of times a branch was mispredicted +system.cpu.commit.branches 120192362 # Number of branches committed +system.cpu.commit.bw_lim_events 6858146 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 574686281 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 3877893 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 381923221 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 603587786 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.952117 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.448029 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 310030081 51.36% 51.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 161983498 26.84% 78.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 68757792 11.39% 89.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 25709435 4.26% 93.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 17326011 2.87% 96.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5210197 0.86% 97.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6149685 1.02% 98.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1562941 0.26% 98.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6858146 1.14% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 603587786 # Number of insts commited each cycle +system.cpu.commit.count 574686281 # Number of instructions committed +system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. +system.cpu.commit.function_calls 9757362 # Number of function calls committed. +system.cpu.commit.int_insts 473702185 # Number of committed integer instructions. +system.cpu.commit.loads 126773177 # Number of loads committed +system.cpu.commit.membars 1488542 # Number of memory barriers committed +system.cpu.commit.refs 184377275 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 573342397 # Number of Instructions Simulated system.cpu.committedInsts_total 573342397 # Number of Instructions Simulated system.cpu.cpi 1.160672 # CPI: Cycles Per Instruction @@ -105,8 +105,8 @@ system.cpu.dcache.demand_mshr_misses 1195995 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.991470 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4061.060335 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.991470 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 197693380 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 13396.562604 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 8735.502239 # average overall mshr miss latency @@ -128,15 +128,15 @@ system.cpu.dcache.tagsinuse 4061.060335 # Cy system.cpu.dcache.total_refs 200083704 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 6358781000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 1064793 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 85842380 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 76871 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 34367828 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 1126968144 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 277630014 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 236143765 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 57332647 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 218235 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 3971626 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 85842380 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 76871 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 34367828 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1126968144 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 277630014 # Number of cycles decode is idle +system.cpu.decode.RunCycles 236143765 # Number of cycles decode is running +system.cpu.decode.SquashCycles 57332647 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 218235 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 3971626 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -220,8 +220,8 @@ system.cpu.icache.demand_mshr_misses 13895 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.514415 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1053.520934 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.514415 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 132169265 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 14331.781024 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 10612.450522 # average overall mshr miss latency @@ -244,21 +244,13 @@ system.cpu.icache.total_refs 132154335 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 4 # number of writebacks system.cpu.idleCycles 4542007 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 142399885 # Number of branches executed -system.cpu.iew.EXEC:nop 9420990 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.051214 # Inst execution rate -system.cpu.iew.EXEC:refs 220838036 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 66554903 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 782273717 # num instructions consuming a value -system.cpu.iew.WB:count 680637923 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.486169 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 380317186 # num instructions producing a value -system.cpu.iew.WB:rate 1.022804 # insts written-back per cycle -system.cpu.iew.WB:sent 691183006 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 25100140 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 142399885 # Number of branches executed +system.cpu.iew.exec_nop 9420990 # number of nop insts executed +system.cpu.iew.exec_rate 1.051214 # Inst execution rate +system.cpu.iew.exec_refs 220838036 # number of memory reference insts executed +system.cpu.iew.exec_stores 66554903 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 2947924 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 196892006 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 2816035 # Number of dispatched non-speculative instructions @@ -286,103 +278,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 56769769 # system.cpu.iew.memOrderViolationEvents 241250 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 6965983 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 18134157 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 782273717 # num instructions consuming a value +system.cpu.iew.wb_count 680637923 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.486169 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 380317186 # num instructions producing a value +system.cpu.iew.wb_rate 1.022804 # insts written-back per cycle +system.cpu.iew.wb_sent 691183006 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 1609052037 # number of integer regfile reads system.cpu.int_regfile_writes 524399004 # number of integer regfile writes system.cpu.ipc 0.861570 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.861570 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 491156775 67.76% 67.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 386013 0.05% 67.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 106 0.00% 67.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 3 0.00% 67.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 162458896 22.41% 90.23% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 70842385 9.77% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 724844178 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 8619148 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011891 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 25536 0.30% 0.30% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 5445227 63.18% 63.47% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 3148385 36.53% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 660920432 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.096719 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.355430 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 305964281 46.29% 46.29% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 148313904 22.44% 68.73% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 112740957 17.06% 85.79% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 49799071 7.53% 93.33% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 29063149 4.40% 97.72% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 8262993 1.25% 98.97% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 4169807 0.63% 99.61% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 1785416 0.27% 99.88% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 820854 0.12% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 660920432 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.089234 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 491156775 67.76% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 386013 0.05% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 106 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 162458896 22.41% 90.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 70842385 9.77% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 724844178 # Type of FU issued system.cpu.iq.fp_alu_accesses 126 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 248 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 340 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 8619148 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011891 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 25536 0.30% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5445227 63.18% 63.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3148385 36.53% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 733463200 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 2121563604 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 680637907 # Number of integer instruction queue wakeup accesses @@ -394,6 +376,24 @@ system.cpu.iq.iqSquashedInstsExamined 371760121 # Nu system.cpu.iq.iqSquashedInstsIssued 2335916 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 799068 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 680735331 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 660920432 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.096719 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.355430 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 305964281 46.29% 46.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 148313904 22.44% 68.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 112740957 17.06% 85.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 49799071 7.53% 93.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 29063149 4.40% 97.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8262993 1.25% 98.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4169807 0.63% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1785416 0.27% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 820854 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 660920432 # Number of insts issued each cycle +system.cpu.iq.rate 1.089234 # Inst issue rate system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -470,10 +470,10 @@ system.cpu.l2cache.demand_mshr_misses 236073 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.216648 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.421153 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 7099.133966 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 13800.334539 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.216648 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.421153 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 1209222 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34216.723072 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31016.778708 # average overall mshr miss latency @@ -504,28 +504,28 @@ system.cpu.misc_regfile_writes 4464326 # nu system.cpu.numCycles 665462439 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 11783884 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 448493735 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 9081964 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 293899856 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 10512591 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 133 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 2673538298 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 1068521543 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 798521782 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 223635059 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 57332647 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 24492193 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 350028044 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 1141 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 2673537157 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 49776793 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 2837350 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 62579735 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 2837280 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 11783884 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 448493735 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 9081964 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 293899856 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 10512591 # Number of times rename has blocked due to LSQ full +system.cpu.rename.ROBFullEvents 133 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 2673538298 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1068521543 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 798521782 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 223635059 # Number of cycles rename is running +system.cpu.rename.SquashCycles 57332647 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 24492193 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 350028044 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 1141 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 2673537157 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 49776793 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 2837350 # count of serializing insts renamed +system.cpu.rename.skidInsts 62579735 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 2837280 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 1553332004 # The number of ROB reads system.cpu.rob.rob_writes 1970603439 # The number of ROB writes system.cpu.timesIdled 108463 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 548 # Number of system calls +system.cpu.workload.num_syscalls 548 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini index 2b400c946..8b55eca4f 100644 --- a/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini @@ -61,14 +61,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser +executable=/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 -input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/simout b/tests/long/20.parser/ref/arm/linux/simple-atomic/simout index 1ad3a878c..7da122073 100755 --- a/tests/long/20.parser/ref/arm/linux/simple-atomic/simout +++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 17:56:20 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 12:53:21 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt index 818f8fd56..0d8c76b6a 100644 --- a/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1096990 # Simulator instruction rate (inst/s) -host_mem_usage 250472 # Number of bytes of host memory used -host_seconds 520.49 # Real time elapsed on the host -host_tick_rate 558129819 # Simulator tick rate (ticks/s) +host_inst_rate 4059400 # Simulator instruction rate (inst/s) +host_mem_usage 209588 # Number of bytes of host memory used +host_seconds 140.65 # Real time elapsed on the host +host_tick_rate 2065351773 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 570968176 # Number of instructions simulated sim_seconds 0.290499 # Number of seconds simulated @@ -71,6 +71,6 @@ system.cpu.num_int_register_writes 425113002 # nu system.cpu.num_load_insts 126029556 # Number of load instructions system.cpu.num_mem_refs 182890035 # number of memory refs system.cpu.num_store_insts 56860479 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 548 # Number of system calls +system.cpu.workload.num_syscalls 548 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini index 75a3e24c1..1771ad8e9 100644 --- a/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini @@ -164,14 +164,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing +cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser +executable=/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 -input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/20.parser/ref/arm/linux/simple-timing/simout index 697084dd6..3ee3b4f05 100755 --- a/tests/long/20.parser/ref/arm/linux/simple-timing/simout +++ b/tests/long/20.parser/ref/arm/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 17:57:49 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 12:55:52 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt index 3b54b12a7..218238666 100644 --- a/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 577686 # Simulator instruction rate (inst/s) -host_mem_usage 258200 # Number of bytes of host memory used -host_seconds 985.02 # Real time elapsed on the host -host_tick_rate 733214267 # Simulator tick rate (ticks/s) +host_inst_rate 2210994 # Simulator instruction rate (inst/s) +host_mem_usage 217324 # Number of bytes of host memory used +host_seconds 257.37 # Real time elapsed on the host +host_tick_rate 2806251427 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 569034848 # Number of instructions simulated sim_seconds 0.722234 # Number of seconds simulated @@ -54,8 +54,8 @@ system.cpu.dcache.demand_mshr_misses 1138918 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.992551 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4065.490059 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.992551 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 177979623 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 22417.457622 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 19417.457622 # average overall mshr miss latency @@ -130,8 +130,8 @@ system.cpu.icache.demand_mshr_misses 11521 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.480677 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 984.426148 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.480677 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 516611385 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 24743.338252 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency @@ -219,10 +219,10 @@ system.cpu.l2cache.demand_mshr_misses 231204 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.178502 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.445374 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 5849.157602 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 14594.006011 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.178502 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.445374 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 1150439 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -264,6 +264,6 @@ system.cpu.num_int_register_writes 425113002 # nu system.cpu.num_load_insts 126029556 # Number of load instructions system.cpu.num_mem_refs 182890035 # number of memory refs system.cpu.num_store_insts 56860479 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 548 # Number of system calls +system.cpu.workload.num_syscalls 548 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini index e87680710..523530b80 100644 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini @@ -25,6 +25,8 @@ BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/20.parser/ref/x86/linux/o3-timing/simout index 06f1587f3..22653279f 100755 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 18 2011 20:12:06 -M5 started Mar 18 2011 20:27:45 -M5 executing on zizzer +M5 compiled Apr 19 2011 12:22:33 +M5 started Apr 19 2011 12:32:37 +M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt index 0fc55f229..6f1b3f3b0 100644 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 135575 # Simulator instruction rate (inst/s) -host_mem_usage 259672 # Number of bytes of host memory used -host_seconds 11277.84 # Real time elapsed on the host -host_tick_rate 51792019 # Simulator tick rate (ticks/s) +host_inst_rate 233996 # Simulator instruction rate (inst/s) +host_mem_usage 255168 # Number of bytes of host memory used +host_seconds 6534.25 # Real time elapsed on the host +host_tick_rate 89390880 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1528988756 # Number of instructions simulated sim_seconds 0.584102 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 16731555 # Nu system.cpu.BPredUnit.condPredicted 252612909 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 252612909 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 149758588 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 41097639 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1035309655 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.476842 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.993609 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 433213212 41.84% 41.84% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 271303976 26.21% 68.05% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 102660477 9.92% 77.96% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 102477093 9.90% 87.86% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 38291141 3.70% 91.56% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 25044351 2.42% 93.98% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 10787246 1.04% 95.02% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 10434520 1.01% 96.03% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 41097639 3.97% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1035309655 # Number of insts commited each cycle -system.cpu.commit.COM:count 1528988756 # Number of instructions committed -system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 0 # Number of function calls committed. -system.cpu.commit.COM:int_insts 1528317614 # Number of committed integer instructions. -system.cpu.commit.COM:loads 384102160 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 533262345 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 16763223 # The number of times a branch was mispredicted +system.cpu.commit.branches 149758588 # Number of branches committed +system.cpu.commit.bw_lim_events 41097639 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 795955462 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 1035309655 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.476842 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.993609 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 433213212 41.84% 41.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 271303976 26.21% 68.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 102660477 9.92% 77.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 102477093 9.90% 87.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 38291141 3.70% 91.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 25044351 2.42% 93.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10787246 1.04% 95.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10434520 1.01% 96.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 41097639 3.97% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1035309655 # Number of insts commited each cycle +system.cpu.commit.count 1528988756 # Number of instructions committed +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 0 # Number of function calls committed. +system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions. +system.cpu.commit.loads 384102160 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.refs 533262345 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 1528988756 # Number of Instructions Simulated system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated system.cpu.cpi 0.764037 # CPI: Cycles Per Instruction @@ -96,8 +96,8 @@ system.cpu.dcache.demand_mshr_misses 2775377 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.998173 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4088.515779 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.998173 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 472799393 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 18648.960228 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 11951.477943 # average overall mshr miss latency @@ -119,12 +119,12 @@ system.cpu.dcache.tagsinuse 4088.515779 # Cy system.cpu.dcache.total_refs 469490463 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 2268948000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 2231104 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 187291575 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 2489806075 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 422005844 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 404270583 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 108207267 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 21741653 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 187291575 # Number of cycles decode is blocked +system.cpu.decode.DecodedInsts 2489806075 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 422005844 # Number of cycles decode is idle +system.cpu.decode.RunCycles 404270583 # Number of cycles decode is running +system.cpu.decode.SquashCycles 108207267 # Number of cycles decode is squashing +system.cpu.decode.UnblockCycles 21741653 # Number of cycles decode is unblocking system.cpu.fetch.Branches 252612909 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 188594062 # Number of cache lines fetched system.cpu.fetch.Cycles 440470513 # Number of cycles fetch has run and was not squashing or blocked @@ -187,8 +187,8 @@ system.cpu.icache.demand_mshr_misses 256130 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.469099 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 960.715295 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.469099 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 188594062 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 6510.591789 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 3406.338578 # average overall mshr miss latency @@ -211,21 +211,13 @@ system.cpu.icache.total_refs 188329447 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 6 # number of writebacks system.cpu.idleCycles 24687157 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 173444431 # Number of branches executed -system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.602205 # Inst execution rate -system.cpu.iew.EXEC:refs 612750445 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 165978925 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 2110704618 # num instructions consuming a value -system.cpu.iew.WB:count 1858331416 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.678632 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1432391344 # num instructions producing a value -system.cpu.iew.WB:rate 1.590759 # insts written-back per cycle -system.cpu.iew.WB:sent 1864643959 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 18167511 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 173444431 # Number of branches executed +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_rate 1.602205 # Inst execution rate +system.cpu.iew.exec_refs 612750445 # number of memory reference insts executed +system.cpu.iew.exec_stores 165978925 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 9685611 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 586119276 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 9659 # Number of dispatched non-speculative instructions @@ -253,103 +245,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 73925179 # system.cpu.iew.memOrderViolationEvents 2443893 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 2771097 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 15396414 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 2110704618 # num instructions consuming a value +system.cpu.iew.wb_count 1858331416 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.678632 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 1432391344 # num instructions producing a value +system.cpu.iew.wb_rate 1.590759 # insts written-back per cycle +system.cpu.iew.wb_sent 1864643959 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 3111234049 # number of integer regfile reads system.cpu.int_regfile_writes 1733847214 # number of integer regfile writes system.cpu.ipc 1.308837 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.308837 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2348064 0.12% 0.12% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1272739342 66.91% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 456676516 24.01% 91.05% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 170264562 8.95% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 1902028484 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 11137895 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.005856 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 1120921 10.06% 10.06% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 7318318 65.71% 75.77% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 2698656 24.23% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 1143516922 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.663315 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.649679 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 363234856 31.76% 31.76% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 268152711 23.45% 55.21% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 190268701 16.64% 71.85% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 150184864 13.13% 84.99% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 96042571 8.40% 93.39% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 45507451 3.98% 97.37% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 20662852 1.81% 99.17% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 8604200 0.75% 99.92% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 858716 0.08% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 1143516922 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.628165 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 2348064 0.12% 0.12% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1272739342 66.91% 67.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 456676516 24.01% 91.05% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 170264562 8.95% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1902028484 # Type of FU issued system.cpu.iq.fp_alu_accesses 77 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 156 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 40 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 7351 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 11137895 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005856 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1120921 10.06% 10.06% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7318318 65.71% 75.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2698656 24.23% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 1910818238 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 4959453857 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 1858331376 # Number of integer instruction queue wakeup accesses @@ -361,6 +343,24 @@ system.cpu.iq.iqSquashedInstsExamined 793159883 # Nu system.cpu.iq.iqSquashedInstsIssued 742228 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 9106 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 1353359987 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 1143516922 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.663315 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.649679 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 363234856 31.76% 31.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 268152711 23.45% 55.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 190268701 16.64% 71.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 150184864 13.13% 84.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 96042571 8.40% 93.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 45507451 3.98% 97.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 20662852 1.81% 99.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 8604200 0.75% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 858716 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1143516922 # Number of insts issued each cycle +system.cpu.iq.rate 1.628165 # Inst issue rate system.cpu.l2cache.ReadExReq_accesses 775816 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 34258.394889 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31002.535640 # average ReadExReq mshr miss latency @@ -415,10 +415,10 @@ system.cpu.l2cache.demand_mshr_misses 586530 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.236559 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.418198 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 7751.549385 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 13703.522900 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.236559 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.418198 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 2544473 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34201.394643 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31004.134486 # average overall mshr miss latency @@ -448,28 +448,28 @@ system.cpu.misc_regfile_reads 1024751398 # nu system.cpu.numCycles 1168204079 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 50725953 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 1427299027 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 53866080 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 461056510 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 71664979 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 8215 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 5693696762 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 2424853504 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 2263021553 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 385257729 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 108207267 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 138255029 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 835722526 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 18042 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 5693678720 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 14434 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 2322 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 301380597 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 2286 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 50725953 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1427299027 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 53866080 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 461056510 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 71664979 # Number of times rename has blocked due to LSQ full +system.cpu.rename.ROBFullEvents 8215 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 5693696762 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 2424853504 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 2263021553 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 385257729 # Number of cycles rename is running +system.cpu.rename.SquashCycles 108207267 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 138255029 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 835722526 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 18042 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 5693678720 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 14434 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 2322 # count of serializing insts renamed +system.cpu.rename.skidInsts 301380597 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 2286 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 3319156234 # The number of ROB reads system.cpu.rob.rob_writes 4758159890 # The number of ROB writes system.cpu.timesIdled 639156 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 551 # Number of system calls +system.cpu.workload.num_syscalls 551 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini index adfcd9b98..fdc891c59 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini @@ -61,7 +61,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic +cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout index e27ac87ea..190029619 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout @@ -5,11 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 11 2011 23:35:10 -M5 revision c3deaa585dd3 7949 default qtip resforflagsstats.patch tip -M5 started Feb 11 2011 23:35:13 -M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic +M5 compiled Apr 19 2011 12:22:33 +M5 started Apr 19 2011 12:30:34 +M5 executing on maize +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt index afe5ef235..3cf669902 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1866600 # Simulator instruction rate (inst/s) -host_mem_usage 231212 # Number of bytes of host memory used -host_seconds 819.13 # Real time elapsed on the host -host_tick_rate 1080693863 # Simulator tick rate (ticks/s) +host_inst_rate 3416660 # Simulator instruction rate (inst/s) +host_mem_usage 206360 # Number of bytes of host memory used +host_seconds 447.51 # Real time elapsed on the host +host_tick_rate 1978121798 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1528988757 # Number of instructions simulated sim_seconds 0.885229 # Number of seconds simulated @@ -29,6 +29,6 @@ system.cpu.num_int_register_writes 1427299027 # nu system.cpu.num_load_insts 384102160 # Number of load instructions system.cpu.num_mem_refs 533262345 # number of memory refs system.cpu.num_store_insts 149160185 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 551 # Number of system calls +system.cpu.workload.num_syscalls 551 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini index 00b5b00f6..330cf56d3 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini @@ -51,6 +51,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -86,6 +87,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +123,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 @@ -161,7 +164,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing +cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/20.parser/ref/x86/linux/simple-timing/simout index 1e739aa16..b7abf2775 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simout @@ -5,11 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 11 2011 23:35:10 -M5 revision c3deaa585dd3 7949 default qtip resforflagsstats.patch tip -M5 started Feb 11 2011 23:35:13 -M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing +M5 compiled Apr 19 2011 12:22:33 +M5 started Apr 19 2011 12:27:05 +M5 executing on maize +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt index dbe8c165b..9224e99d3 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1188316 # Simulator instruction rate (inst/s) -host_mem_usage 238940 # Number of bytes of host memory used -host_seconds 1286.69 # Real time elapsed on the host -host_tick_rate 1289149200 # Simulator tick rate (ticks/s) +host_inst_rate 2070048 # Simulator instruction rate (inst/s) +host_mem_usage 214112 # Number of bytes of host memory used +host_seconds 738.62 # Real time elapsed on the host +host_tick_rate 2245699490 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1528988757 # Number of instructions simulated sim_seconds 1.658730 # Number of seconds simulated @@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses 2518458 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.997674 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4086.472055 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.997674 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 533262390 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 23627.363053 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 20627.360075 # average overall mshr miss latency @@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses 2814 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.430777 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 882.231489 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.430777 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 1068347110 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 48641.791045 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 45641.791045 # average overall mshr miss latency @@ -173,10 +173,10 @@ system.cpu.l2cache.demand_mshr_misses 579609 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.230381 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.417452 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 7549.128601 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 13679.064710 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.230381 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.417452 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 2521272 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000.010352 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -218,6 +218,6 @@ system.cpu.num_int_register_writes 1427299027 # nu system.cpu.num_load_insts 384102160 # Number of load instructions system.cpu.num_mem_refs 533262345 # number of memory refs system.cpu.num_store_insts 149160185 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 551 # Number of system calls +system.cpu.workload.num_syscalls 551 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini index 26196c984..b5728d762 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -25,6 +25,8 @@ BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout index 3643d6c6d..caf1c0c92 100755 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 17 2011 21:44:37 -M5 started Mar 17 2011 21:58:43 -M5 executing on zizzer +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 11:58:24 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 388ace0a5..4140bf39e 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 169900 # Simulator instruction rate (inst/s) -host_mem_usage 215004 # Number of bytes of host memory used -host_seconds 2210.56 # Real time elapsed on the host -host_tick_rate 51124064 # Simulator tick rate (ticks/s) +host_inst_rate 334419 # Simulator instruction rate (inst/s) +host_mem_usage 210864 # Number of bytes of host memory used +host_seconds 1123.07 # Real time elapsed on the host +host_tick_rate 100628798 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 375574812 # Number of instructions simulated sim_seconds 0.113013 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 5223677 # Nu system.cpu.BPredUnit.condPredicted 31927422 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 56786170 # Number of BP lookups system.cpu.BPredUnit.usedRAS 11422526 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 44587533 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 16035403 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 216073988 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.845037 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.480996 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 99774969 46.18% 46.18% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 35667629 16.51% 62.68% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 19281907 8.92% 71.61% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 16238513 7.52% 79.12% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 11569134 5.35% 84.48% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 7732170 3.58% 88.06% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 5922846 2.74% 90.80% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 3851417 1.78% 92.58% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 16035403 7.42% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 216073988 # Number of insts commited each cycle -system.cpu.commit.COM:count 398664587 # Number of instructions committed -system.cpu.commit.COM:fp_insts 155295106 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 8007752 # Number of function calls committed. -system.cpu.commit.COM:int_insts 316365844 # Number of committed integer instructions. -system.cpu.commit.COM:loads 94754489 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 168275218 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 5219312 # The number of times a branch was mispredicted +system.cpu.commit.branches 44587533 # Number of branches committed +system.cpu.commit.bw_lim_events 16035403 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 398664587 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 56265161 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 216073988 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.845037 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.480996 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 99774969 46.18% 46.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 35667629 16.51% 62.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 19281907 8.92% 71.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 16238513 7.52% 79.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 11569134 5.35% 84.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7732170 3.58% 88.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5922846 2.74% 90.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3851417 1.78% 92.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 16035403 7.42% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 216073988 # Number of insts commited each cycle +system.cpu.commit.count 398664587 # Number of instructions committed +system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. +system.cpu.commit.function_calls 8007752 # Number of function calls committed. +system.cpu.commit.int_insts 316365844 # Number of committed integer instructions. +system.cpu.commit.loads 94754489 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.refs 168275218 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 375574812 # Number of Instructions Simulated system.cpu.committedInsts_total 375574812 # Number of Instructions Simulated system.cpu.cpi 0.601812 # CPI: Cycles Per Instruction @@ -98,8 +98,8 @@ system.cpu.dcache.demand_mshr_misses 4182 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.803985 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 3293.121210 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.803985 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 166720564 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 30468.976321 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 34627.570540 # average overall mshr miss latency @@ -121,15 +121,15 @@ system.cpu.dcache.tagsinuse 3293.121210 # Cy system.cpu.dcache.total_refs 166701099 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 664 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 5613634 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 4438 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 10679460 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 490538381 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 118863884 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 90994213 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 9813191 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 13275 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 602257 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 5613634 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 4438 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 10679460 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 490538381 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 118863884 # Number of cycles decode is idle +system.cpu.decode.RunCycles 90994213 # Number of cycles decode is running +system.cpu.decode.SquashCycles 9813191 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 13275 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 602257 # Number of cycles decode is unblocking system.cpu.dtb.data_accesses 183645342 # DTB accesses system.cpu.dtb.data_acv 48603 # DTB access violations system.cpu.dtb.data_hits 183566296 # DTB hits @@ -209,8 +209,8 @@ system.cpu.icache.demand_mshr_misses 3907 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.890605 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1823.959859 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.890605 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 58423687 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 32309.424084 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 30830.816483 # average overall mshr miss latency @@ -233,21 +233,13 @@ system.cpu.icache.total_refs 58418912 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 138291 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 48687009 # Number of branches executed -system.cpu.iew.EXEC:nop 26082950 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.805331 # Inst execution rate -system.cpu.iew.EXEC:refs 183693980 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 79967080 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 258989364 # num instructions consuming a value -system.cpu.iew.WB:count 404042671 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.726642 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 188192474 # num instructions producing a value -system.cpu.iew.WB:rate 1.787598 # insts written-back per cycle -system.cpu.iew.WB:sent 405020447 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 5625617 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 48687009 # Number of branches executed +system.cpu.iew.exec_nop 26082950 # number of nop insts executed +system.cpu.iew.exec_rate 1.805331 # Inst execution rate +system.cpu.iew.exec_refs 183693980 # number of memory reference insts executed +system.cpu.iew.exec_stores 79967080 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 1911401 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 106982646 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 239 # Number of dispatched non-speculative instructions @@ -275,103 +267,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 12856211 # system.cpu.iew.memOrderViolationEvents 5629 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 886790 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 4738827 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 258989364 # num instructions consuming a value +system.cpu.iew.wb_count 404042671 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.726642 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 188192474 # num instructions producing a value +system.cpu.iew.wb_rate 1.787598 # insts written-back per cycle +system.cpu.iew.wb_sent 405020447 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 406883956 # number of integer regfile reads system.cpu.int_regfile_writes 173490032 # number of integer regfile writes system.cpu.ipc 1.661648 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.661648 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 165161738 39.53% 39.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 2124398 0.51% 40.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 40.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 33524704 8.02% 48.07% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 7711996 1.85% 49.91% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2967896 0.71% 50.62% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 16674434 3.99% 54.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 1571336 0.38% 54.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 105669831 25.29% 80.28% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 82413056 19.72% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 417852970 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 10358398 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.024790 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 4298 0.04% 0.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 768 0.01% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 7 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 10130 0.10% 0.15% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 1743113 16.83% 16.97% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 627758 6.06% 23.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 5427565 52.40% 75.43% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 2544759 24.57% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 225887179 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.849830 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.928832 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 80384230 35.59% 35.59% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 40475639 17.92% 53.50% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 30160734 13.35% 66.86% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 26305410 11.65% 78.50% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 21278104 9.42% 87.92% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 14868616 6.58% 94.50% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 9130443 4.04% 98.55% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 2370545 1.05% 99.60% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 913458 0.40% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 225887179 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.848699 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 165161738 39.53% 39.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2124398 0.51% 40.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 40.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 33524704 8.02% 48.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7711996 1.85% 49.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2967896 0.71% 50.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16674434 3.99% 54.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1571336 0.38% 54.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.99% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 105669831 25.29% 80.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 82413056 19.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 417852970 # Type of FU issued system.cpu.iq.fp_alu_accesses 175354000 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 344883249 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 164390765 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 192579711 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 10358398 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.024790 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4298 0.04% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 768 0.01% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 7 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 10130 0.10% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 1743113 16.83% 16.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 627758 6.06% 23.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 23.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 23.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 23.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 23.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 23.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 23.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 23.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 23.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 23.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 23.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 23.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 23.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 23.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 23.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 23.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 23.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 23.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 23.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 23.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 23.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5427565 52.40% 75.43% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2544759 24.57% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 252823787 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 727796795 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 239651906 # Number of integer instruction queue wakeup accesses @@ -383,6 +365,24 @@ system.cpu.iq.iqSquashedInstsExamined 47599271 # Nu system.cpu.iq.iqSquashedInstsIssued 728527 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 28893091 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 225887179 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.849830 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.928832 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 80384230 35.59% 35.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 40475639 17.92% 53.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 30160734 13.35% 66.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 26305410 11.65% 78.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21278104 9.42% 87.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 14868616 6.58% 94.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9130443 4.04% 98.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2370545 1.05% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 913458 0.40% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 225887179 # Number of insts issued each cycle +system.cpu.iq.rate 1.848699 # Inst issue rate system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits @@ -443,10 +443,10 @@ system.cpu.l2cache.demand_mshr_misses 7364 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.108576 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.011590 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 3557.826949 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 379.777727 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.108576 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.011590 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 8089 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34457.903313 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31289.109180 # average overall mshr miss latency @@ -477,28 +477,28 @@ system.cpu.misc_regfile_writes 1 # nu system.cpu.numCycles 226025470 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 3360184 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 259532333 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 311 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 122116498 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1529212 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 625408393 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 477751875 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 306658733 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 88296359 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 9813191 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 1960754 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 47126400 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 292973848 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 332434545 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 340193 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 36156 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 5383709 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 253 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 3360184 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 259532333 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 311 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 122116498 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 1529212 # Number of times rename has blocked due to LSQ full +system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 625408393 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 477751875 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 306658733 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 88296359 # Number of cycles rename is running +system.cpu.rename.SquashCycles 9813191 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 1960754 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 47126400 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 292973848 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 332434545 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 340193 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 36156 # count of serializing insts renamed +system.cpu.rename.skidInsts 5383709 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 253 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 654965356 # The number of ROB reads system.cpu.rob.rob_writes 919674888 # The number of ROB writes system.cpu.timesIdled 3011 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 215 # Number of system calls +system.cpu.workload.num_syscalls 215 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout index 96b5bf3c9..0fd1f360f 100755 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:38 -M5 executing on burrito +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 12:03:34 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt index 6fcc67a34..6655c3650 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1382202 # Simulator instruction rate (inst/s) -host_mem_usage 224632 # Number of bytes of host memory used -host_seconds 288.43 # Real time elapsed on the host -host_tick_rate 691100750 # Simulator tick rate (ticks/s) +host_inst_rate 5567399 # Simulator instruction rate (inst/s) +host_mem_usage 202284 # Number of bytes of host memory used +host_seconds 71.61 # Real time elapsed on the host +host_tick_rate 2783694716 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 398664595 # Number of instructions simulated sim_seconds 0.199332 # Number of seconds simulated @@ -61,6 +61,6 @@ system.cpu.num_int_register_writes 159335860 # nu system.cpu.num_load_insts 94754510 # Number of load instructions system.cpu.num_mem_refs 168275274 # number of memory refs system.cpu.num_store_insts 73520764 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 215 # Number of system calls +system.cpu.workload.num_syscalls 215 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini index 91f994c0c..c222d6133 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini @@ -51,6 +51,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -86,6 +87,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +123,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout index 4f3149cad..2be6be9ef 100755 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:38 -M5 executing on burrito +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 12:04:03 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt index 31ad19d58..94a73b71f 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 531142 # Simulator instruction rate (inst/s) -host_mem_usage 232344 # Number of bytes of host memory used -host_seconds 750.58 # Real time elapsed on the host -host_tick_rate 755872580 # Simulator tick rate (ticks/s) +host_inst_rate 2583171 # Simulator instruction rate (inst/s) +host_mem_usage 210032 # Number of bytes of host memory used +host_seconds 154.33 # Real time elapsed on the host +host_tick_rate 3676130341 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 398664609 # Number of instructions simulated sim_seconds 0.567343 # Number of seconds simulated @@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses 4152 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.802957 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 3288.912598 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.802957 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 168275220 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 54209.537572 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 51209.537572 # average overall mshr miss latency @@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 3673 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.876529 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1795.131074 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.876529 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 398664666 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 50648.516199 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 47648.516199 # average overall mshr miss latency @@ -205,10 +205,10 @@ system.cpu.l2cache.demand_mshr_misses 7180 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.103674 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.011338 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 3397.175455 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 371.536808 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.103674 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.011338 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 7825 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -250,6 +250,6 @@ system.cpu.num_int_register_writes 159335870 # nu system.cpu.num_load_insts 94754511 # Number of load instructions system.cpu.num_mem_refs 168275276 # number of memory refs system.cpu.num_store_insts 73520765 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 215 # Number of system calls +system.cpu.workload.num_syscalls 215 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini index a7fea3c2e..b2f50f12f 100644 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini @@ -498,7 +498,7 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/alisai01/dist/cpu2000/binaries/arm/linux/eon +executable=/dist/m5/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/30.eon/ref/arm/linux/o3-timing/simout index 556348771..09bb8bdda 100755 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 18:04:19 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 12:56:09 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt index 1de34b9ef..22fc80d01 100644 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 203026 # Simulator instruction rate (inst/s) -host_mem_usage 267492 # Number of bytes of host memory used -host_seconds 1719.32 # Real time elapsed on the host -host_tick_rate 88254289 # Simulator tick rate (ticks/s) +host_inst_rate 250845 # Simulator instruction rate (inst/s) +host_mem_usage 223896 # Number of bytes of host memory used +host_seconds 1391.56 # Real time elapsed on the host +host_tick_rate 109041329 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 349065985 # Number of instructions simulated sim_seconds 0.151737 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 3421912 # Nu system.cpu.BPredUnit.condPredicted 20033400 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 36581771 # Number of BP lookups system.cpu.BPredUnit.usedRAS 7288333 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 30521887 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 7594485 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 297396946 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.173740 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.829368 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 153798947 51.72% 51.72% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 68683080 23.09% 74.81% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 27481761 9.24% 84.05% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 16045950 5.40% 89.45% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 11196284 3.76% 93.21% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 6591467 2.22% 95.43% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 3251010 1.09% 96.52% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 2753962 0.93% 97.45% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 7594485 2.55% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 297396946 # Number of insts commited each cycle -system.cpu.commit.COM:count 349066597 # Number of instructions committed -system.cpu.commit.COM:fp_insts 114216705 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 6225112 # Number of function calls committed. -system.cpu.commit.COM:int_insts 287529375 # Number of committed integer instructions. -system.cpu.commit.COM:loads 94648997 # Number of loads committed -system.cpu.commit.COM:membars 11033 # Number of memory barriers committed -system.cpu.commit.COM:refs 177024839 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 3392850 # The number of times a branch was mispredicted +system.cpu.commit.branches 30521887 # Number of branches committed +system.cpu.commit.bw_lim_events 7594485 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 349066597 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 3555476 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 29812251 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 297396946 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.173740 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.829368 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 153798947 51.72% 51.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 68683080 23.09% 74.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 27481761 9.24% 84.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 16045950 5.40% 89.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 11196284 3.76% 93.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 6591467 2.22% 95.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3251010 1.09% 96.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2753962 0.93% 97.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7594485 2.55% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 297396946 # Number of insts commited each cycle +system.cpu.commit.count 349066597 # Number of instructions committed +system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. +system.cpu.commit.function_calls 6225112 # Number of function calls committed. +system.cpu.commit.int_insts 287529375 # Number of committed integer instructions. +system.cpu.commit.loads 94648997 # Number of loads committed +system.cpu.commit.membars 11033 # Number of memory barriers committed +system.cpu.commit.refs 177024839 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 349065985 # Number of Instructions Simulated system.cpu.committedInsts_total 349065985 # Number of Instructions Simulated system.cpu.cpi 0.869391 # CPI: Cycles Per Instruction @@ -105,8 +105,8 @@ system.cpu.dcache.demand_mshr_misses 4561 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.753211 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 3085.152893 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.753211 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 177564090 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 32354.475913 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 33694.694146 # average overall mshr miss latency @@ -128,15 +128,15 @@ system.cpu.dcache.tagsinuse 3085.152893 # Cy system.cpu.dcache.total_refs 177564704 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 1021 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 139649394 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 71446 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 7239931 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 408881420 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 85142692 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 69995506 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 5956648 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 202337 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 2609353 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 139649394 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 71446 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 7239931 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 408881420 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 85142692 # Number of cycles decode is idle +system.cpu.decode.RunCycles 69995506 # Number of cycles decode is running +system.cpu.decode.SquashCycles 5956648 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 202337 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 2609353 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -221,8 +221,8 @@ system.cpu.icache.demand_mshr_misses 15647 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.891809 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1826.425729 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.891809 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 38750811 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 11739.616414 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 8345.912955 # average overall mshr miss latency @@ -245,21 +245,13 @@ system.cpu.icache.total_refs 38734752 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 121166 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 31598497 # Number of branches executed -system.cpu.iew.EXEC:nop 47916 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.198862 # Inst execution rate -system.cpu.iew.EXEC:refs 183613240 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 84389722 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 302337892 # num instructions consuming a value -system.cpu.iew.WB:count 361679600 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.513512 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 155254133 # num instructions producing a value -system.cpu.iew.WB:rate 1.191795 # insts written-back per cycle -system.cpu.iew.WB:sent 362096434 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 3575174 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 31598497 # Number of branches executed +system.cpu.iew.exec_nop 47916 # number of nop insts executed +system.cpu.iew.exec_rate 1.198862 # Inst execution rate +system.cpu.iew.exec_refs 183613240 # number of memory reference insts executed +system.cpu.iew.exec_stores 84389722 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 6232 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 104118233 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 3634513 # Number of dispatched non-speculative instructions @@ -287,103 +279,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 6767279 # system.cpu.iew.memOrderViolationEvents 165832 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 360118 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 3215056 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 302337892 # num instructions consuming a value +system.cpu.iew.wb_count 361679600 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.513512 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 155254133 # num instructions producing a value +system.cpu.iew.wb_rate 1.191795 # insts written-back per cycle +system.cpu.iew.wb_sent 362096434 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 845155916 # number of integer regfile reads system.cpu.int_regfile_writes 184404886 # number of integer regfile writes system.cpu.ipc 1.150231 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.150231 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 125135876 34.07% 34.07% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 2147375 0.58% 34.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 34.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 3 0.00% 34.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 34.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 34.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 34.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 34.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 34.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 34.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 34.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 34.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 34.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 34.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 34.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 34.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 34.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 34.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 34.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 34.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 6684118 1.82% 36.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 36.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 8302383 2.26% 38.73% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 3402331 0.93% 39.66% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 1567187 0.43% 40.09% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 20210889 5.50% 45.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 7197544 1.96% 47.55% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 7077346 1.93% 49.48% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 175286 0.05% 49.52% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 100106815 27.25% 76.78% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 85290782 23.22% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 367297935 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 12277552 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.033427 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 1371 0.01% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 5040 0.04% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 66 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 1306 0.01% 0.06% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 3 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 233643 1.90% 1.97% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 626 0.01% 1.97% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 321940 2.62% 4.59% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 7517293 61.23% 65.82% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 4196264 34.18% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 303353593 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.210791 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.640692 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 151157606 49.83% 49.83% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 63646504 20.98% 70.81% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 27917034 9.20% 80.01% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 21656943 7.14% 87.15% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 21437631 7.07% 94.22% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 10744150 3.54% 97.76% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 4648214 1.53% 99.29% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 1678112 0.55% 99.85% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 467399 0.15% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 303353593 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.210308 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 125135876 34.07% 34.07% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2147375 0.58% 34.65% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 34.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 34.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6684118 1.82% 36.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8302383 2.26% 38.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3402331 0.93% 39.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1567187 0.43% 40.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20210889 5.50% 45.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7197544 1.96% 47.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7077346 1.93% 49.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 100106815 27.25% 76.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 85290782 23.22% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 367297935 # Type of FU issued system.cpu.iq.fp_alu_accesses 125160042 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 243629757 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 116471069 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 124289037 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 12277552 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.033427 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1371 0.01% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5040 0.04% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 66 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 1306 0.01% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 233643 1.90% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 626 0.01% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 321940 2.62% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7517293 61.23% 65.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4196264 34.18% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 254415445 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 807801978 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 245208531 # Number of integer instruction queue wakeup accesses @@ -395,6 +377,24 @@ system.cpu.iq.iqSquashedInstsExamined 27882412 # Nu system.cpu.iq.iqSquashedInstsIssued 1204720 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 90285 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 56560737 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 303353593 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.210791 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.640692 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 151157606 49.83% 49.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 63646504 20.98% 70.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 27917034 9.20% 80.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 21656943 7.14% 87.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21437631 7.07% 94.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 10744150 3.54% 97.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4648214 1.53% 99.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1678112 0.55% 99.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 467399 0.15% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 303353593 # Number of insts issued each cycle +system.cpu.iq.rate 1.210308 # Inst issue rate system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -468,10 +468,10 @@ system.cpu.l2cache.demand_mshr_misses 7094 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.103738 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.011318 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 3399.287353 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 370.862974 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.103738 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.011318 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 20201 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34371.098670 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31194.530589 # average overall mshr miss latency @@ -502,28 +502,28 @@ system.cpu.misc_regfile_writes 34422259 # nu system.cpu.numCycles 303474759 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 833030 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 340927172 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 47966 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 92085018 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 4772387 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 1 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 1568873073 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 396996902 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 382623172 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 66169446 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 5956648 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 17891726 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 41695997 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 798025803 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 770847270 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 120417725 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 12413036 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 58729283 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 3692499 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 833030 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 340927172 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 47966 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 92085018 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 4772387 # Number of times rename has blocked due to LSQ full +system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 1568873073 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 396996902 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 382623172 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 66169446 # Number of cycles rename is running +system.cpu.rename.SquashCycles 5956648 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 17891726 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 41695997 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 798025803 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 770847270 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 120417725 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 12413036 # count of serializing insts renamed +system.cpu.rename.skidInsts 58729283 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 3692499 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 668678786 # The number of ROB reads system.cpu.rob.rob_writes 763715026 # The number of ROB writes system.cpu.timesIdled 2617 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 191 # Number of system calls +system.cpu.workload.num_syscalls 191 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini index 50c83e5cc..a5b41f00b 100644 --- a/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini @@ -61,12 +61,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/eon +executable=/dist/m5/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/30.eon/ref/arm/linux/simple-atomic/simout index 6a6041ffa..e711f37f2 100755 --- a/tests/long/30.eon/ref/arm/linux/simple-atomic/simout +++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 18:05:11 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 12:58:30 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt index 9bfaf4046..20eb7fdea 100644 --- a/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 854402 # Simulator instruction rate (inst/s) -host_mem_usage 255368 # Number of bytes of host memory used -host_seconds 408.55 # Real time elapsed on the host -host_tick_rate 519751077 # Simulator tick rate (ticks/s) +host_inst_rate 3277679 # Simulator instruction rate (inst/s) +host_mem_usage 214524 # Number of bytes of host memory used +host_seconds 106.50 # Real time elapsed on the host +host_tick_rate 1993879698 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 349065408 # Number of instructions simulated sim_seconds 0.212344 # Number of seconds simulated @@ -71,6 +71,6 @@ system.cpu.num_int_register_writes 207564016 # nu system.cpu.num_load_insts 94648758 # Number of load instructions system.cpu.num_mem_refs 177024357 # number of memory refs system.cpu.num_store_insts 82375599 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 191 # Number of system calls +system.cpu.workload.num_syscalls 191 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini index 52b5d655c..aed18b872 100644 --- a/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini @@ -164,12 +164,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing +cwd=build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/eon +executable=/dist/m5/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/30.eon/ref/arm/linux/simple-timing/simout index b2eb72faf..daf6c8759 100755 --- a/tests/long/30.eon/ref/arm/linux/simple-timing/simout +++ b/tests/long/30.eon/ref/arm/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 18:11:41 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 13:00:20 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt index 91b489221..b979341f1 100644 --- a/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 469608 # Simulator instruction rate (inst/s) -host_mem_usage 263124 # Number of bytes of host memory used -host_seconds 742.51 # Real time elapsed on the host -host_tick_rate 708215535 # Simulator tick rate (ticks/s) +host_inst_rate 1789233 # Simulator instruction rate (inst/s) +host_mem_usage 222228 # Number of bytes of host memory used +host_seconds 194.88 # Real time elapsed on the host +host_tick_rate 2698337573 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 348687131 # Number of instructions simulated sim_seconds 0.525854 # Number of seconds simulated @@ -54,8 +54,8 @@ system.cpu.dcache.demand_mshr_misses 4478 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.751562 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 3078.396238 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.751562 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 176624288 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 53608.307280 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 50608.307280 # average overall mshr miss latency @@ -130,8 +130,8 @@ system.cpu.icache.demand_mshr_misses 15603 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.862297 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1765.984158 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.862297 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 348660359 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 21025.572005 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 18025.572005 # average overall mshr miss latency @@ -219,10 +219,10 @@ system.cpu.l2cache.demand_mshr_misses 6833 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.095644 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.010425 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 3134.059650 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 341.613272 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.095644 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.010425 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 20081 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -264,6 +264,6 @@ system.cpu.num_int_register_writes 207564015 # nu system.cpu.num_load_insts 94648758 # Number of load instructions system.cpu.num_mem_refs 177024357 # number of memory refs system.cpu.num_store_insts 82375599 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 191 # Number of system calls +system.cpu.workload.num_syscalls 191 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini index d7298148c..f5ffa5534 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini @@ -25,6 +25,8 @@ BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout index 4c38c001d..2316b9142 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 17 2011 21:44:37 -M5 started Mar 17 2011 21:45:13 -M5 executing on zizzer +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 11:58:35 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 870c3ba76..c6cbb8474 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 161084 # Simulator instruction rate (inst/s) -host_mem_usage 215416 # Number of bytes of host memory used -host_seconds 11317.35 # Real time elapsed on the host -host_tick_rate 60889223 # Simulator tick rate (ticks/s) +host_inst_rate 299190 # Simulator instruction rate (inst/s) +host_mem_usage 211252 # Number of bytes of host memory used +host_seconds 6093.26 # Real time elapsed on the host +host_tick_rate 113092899 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1823043370 # Number of instructions simulated sim_seconds 0.689105 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 28355376 # Nu system.cpu.BPredUnit.condPredicted 229155282 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 342127414 # Number of BP lookups system.cpu.BPredUnit.usedRAS 49327534 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 266706457 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 71745000 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1283484985 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.565260 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.221446 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 584328523 45.53% 45.53% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 266282466 20.75% 66.27% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 167965913 13.09% 79.36% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 72752284 5.67% 85.03% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 49726595 3.87% 88.90% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 31709768 2.47% 91.37% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 15719812 1.22% 92.60% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 23254624 1.81% 94.41% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 71745000 5.59% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1283484985 # Number of insts commited each cycle -system.cpu.commit.COM:count 2008987604 # Number of instructions committed -system.cpu.commit.COM:fp_insts 71824891 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 39955347 # Number of function calls committed. -system.cpu.commit.COM:int_insts 1778941351 # Number of committed integer instructions. -system.cpu.commit.COM:loads 511070026 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 721864922 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 28343556 # The number of times a branch was mispredicted +system.cpu.commit.branches 266706457 # Number of branches committed +system.cpu.commit.bw_lim_events 71745000 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 649535600 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 1283484985 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.565260 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.221446 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 584328523 45.53% 45.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 266282466 20.75% 66.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 167965913 13.09% 79.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 72752284 5.67% 85.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 49726595 3.87% 88.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 31709768 2.47% 91.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15719812 1.22% 92.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23254624 1.81% 94.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 71745000 5.59% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1283484985 # Number of insts commited each cycle +system.cpu.commit.count 2008987604 # Number of instructions committed +system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. +system.cpu.commit.function_calls 39955347 # Number of function calls committed. +system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. +system.cpu.commit.loads 511070026 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.refs 721864922 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated system.cpu.cpi 0.755994 # CPI: Cycles Per Instruction @@ -98,8 +98,8 @@ system.cpu.dcache.demand_mshr_misses 1530600 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999779 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4095.093805 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999779 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 672939834 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 37287.441089 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 34206.572586 # average overall mshr miss latency @@ -121,15 +121,15 @@ system.cpu.dcache.tagsinuse 4095.093805 # Cy system.cpu.dcache.total_refs 670466697 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 272263000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 107391 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 27367471 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 11874 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 29084935 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 2889732822 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 703418574 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 551446436 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 94589845 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 45736 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1252504 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 27367471 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 11874 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 29084935 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 2889732822 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 703418574 # Number of cycles decode is idle +system.cpu.decode.RunCycles 551446436 # Number of cycles decode is running +system.cpu.decode.SquashCycles 94589845 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 45736 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 1252504 # Number of cycles decode is unblocking system.cpu.dtb.data_accesses 766409541 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 765750752 # DTB hits @@ -209,8 +209,8 @@ system.cpu.icache.demand_mshr_misses 9774 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.787641 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1613.087790 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.787641 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 343698672 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 15692.605534 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 11569.674647 # average overall mshr miss latency @@ -233,21 +233,13 @@ system.cpu.icache.total_refs 343688083 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 134338 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 273848647 # Number of branches executed -system.cpu.iew.EXEC:nop 323098610 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.444031 # Inst execution rate -system.cpu.iew.EXEC:refs 766410290 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 251723816 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1598918223 # num instructions consuming a value -system.cpu.iew.WB:count 1989129822 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.699683 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1118735591 # num instructions producing a value -system.cpu.iew.WB:rate 1.443271 # insts written-back per cycle -system.cpu.iew.WB:sent 1990119861 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 30877415 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 273848647 # Number of branches executed +system.cpu.iew.exec_nop 323098610 # number of nop insts executed +system.cpu.iew.exec_rate 1.444031 # Inst execution rate +system.cpu.iew.exec_refs 766410290 # number of memory reference insts executed +system.cpu.iew.exec_stores 251723816 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 3355843 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 641174032 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 62 # Number of dispatched non-speculative instructions @@ -275,103 +267,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 84105156 # system.cpu.iew.memOrderViolationEvents 1647 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 787925 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 30089490 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1598918223 # num instructions consuming a value +system.cpu.iew.wb_count 1989129822 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.699683 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 1118735591 # num instructions producing a value +system.cpu.iew.wb_rate 1.443271 # insts written-back per cycle +system.cpu.iew.wb_sent 1990119861 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 2524191182 # number of integer regfile reads system.cpu.int_regfile_writes 1452780579 # number of integer regfile writes system.cpu.ipc 1.322762 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.322762 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1197059589 57.90% 57.90% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 18404 0.00% 57.90% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 57.90% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 27850873 1.35% 59.24% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 8254690 0.40% 59.64% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 7204648 0.35% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 550666151 26.63% 86.62% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 276547322 13.38% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 2067604433 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 36218004 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.017517 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 5127 0.01% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 27845547 76.88% 76.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 8367330 23.10% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 1378074830 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.500357 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.637561 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 509079016 36.94% 36.94% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 296362701 21.51% 58.45% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 259221008 18.81% 77.26% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 152505049 11.07% 88.32% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 67550622 4.90% 93.23% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 50043003 3.63% 96.86% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 31234899 2.27% 99.12% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 9170584 0.67% 99.79% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 2907948 0.21% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 1378074830 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.500211 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1197059589 57.90% 57.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 18404 0.00% 57.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 27850873 1.35% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 8254690 0.40% 59.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 7204648 0.35% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 550666151 26.63% 86.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 276547322 13.38% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 2067604433 # Type of FU issued system.cpu.iq.fp_alu_accesses 75415887 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 148066359 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 72617602 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 74982161 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 36218004 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.017517 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5127 0.01% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 27845547 76.88% 76.90% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 8367330 23.10% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 2028403798 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 5422106783 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 1916512220 # Number of integer instruction queue wakeup accesses @@ -383,6 +365,24 @@ system.cpu.iq.iqSquashedInstsExamined 522645709 # Nu system.cpu.iq.iqSquashedInstsIssued 20671442 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 23 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 487946872 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 1378074830 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.500357 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.637561 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 509079016 36.94% 36.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 296362701 21.51% 58.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 259221008 18.81% 77.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 152505049 11.07% 88.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 67550622 4.90% 93.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 50043003 3.63% 96.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 31234899 2.27% 99.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9170584 0.67% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2907948 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1378074830 # Number of insts issued each cycle +system.cpu.iq.rate 1.500211 # Inst issue rate system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits @@ -443,10 +443,10 @@ system.cpu.l2cache.demand_mshr_misses 1480593 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.881563 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.093197 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 28887.056134 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 3053.875830 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.881563 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.093197 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 1540374 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34301.836494 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31051.797489 # average overall mshr miss latency @@ -477,28 +477,28 @@ system.cpu.misc_regfile_writes 1 # nu system.cpu.numCycles 1378209168 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 17364773 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 667601 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 717318588 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 9756545 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 7 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 3251110860 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 2789102688 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 1858404761 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 538784806 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 94589845 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 9995832 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 473435691 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 109436331 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 3141674529 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 20986 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 2820 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 26060288 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 67 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 17364773 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 667601 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 717318588 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 9756545 # Number of times rename has blocked due to LSQ full +system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 3251110860 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 2789102688 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1858404761 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 538784806 # Number of cycles rename is running +system.cpu.rename.SquashCycles 94589845 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 9995832 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 473435691 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 109436331 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 3141674529 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 20986 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 2820 # count of serializing insts renamed +system.cpu.rename.skidInsts 26060288 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 67 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 3864626779 # The number of ROB reads system.cpu.rob.rob_writes 5411636382 # The number of ROB writes system.cpu.timesIdled 3611 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 39 # Number of system calls +system.cpu.workload.num_syscalls 39 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout index b7ecd550d..01eff331e 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:37 -M5 executing on burrito +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 12:05:07 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt index 855c5964e..f1d866c8d 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1477901 # Simulator instruction rate (inst/s) -host_mem_usage 224424 # Number of bytes of host memory used -host_seconds 1359.35 # Real time elapsed on the host -host_tick_rate 739109964 # Simulator tick rate (ticks/s) +host_inst_rate 5736498 # Simulator instruction rate (inst/s) +host_mem_usage 202144 # Number of bytes of host memory used +host_seconds 350.21 # Real time elapsed on the host +host_tick_rate 2868866718 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987605 # Number of instructions simulated sim_seconds 1.004711 # Number of seconds simulated @@ -61,6 +61,6 @@ system.cpu.num_int_register_writes 1332688300 # nu system.cpu.num_load_insts 511488910 # Number of load instructions system.cpu.num_mem_refs 722298387 # number of memory refs system.cpu.num_store_insts 210809477 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 39 # Number of system calls +system.cpu.workload.num_syscalls 39 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini index 9be1cb679..d0df4a5be 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini @@ -51,6 +51,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -86,6 +87,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +123,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout index 03731b56d..fd9623671 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:38 -M5 executing on burrito +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 12:00:30 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index c88cbd8f6..0966bdbb1 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 584935 # Simulator instruction rate (inst/s) -host_mem_usage 232204 # Number of bytes of host memory used -host_seconds 3434.55 # Real time elapsed on the host -host_tick_rate 819166202 # Simulator tick rate (ticks/s) +host_inst_rate 2647820 # Simulator instruction rate (inst/s) +host_mem_usage 209816 # Number of bytes of host memory used +host_seconds 758.73 # Real time elapsed on the host +host_tick_rate 3708113045 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987605 # Number of instructions simulated sim_seconds 2.813468 # Number of seconds simulated @@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses 1530144 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999806 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4095.204626 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999806 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 54553.304787 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 51553.304787 # average overall mshr miss latency @@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 10596 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.721886 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1478.423269 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.721886 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 2009421071 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 23421.857305 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 20421.857305 # average overall mshr miss latency @@ -205,10 +205,10 @@ system.cpu.l2cache.demand_mshr_misses 1479815 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.880371 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.094050 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 28848.012979 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 3081.828747 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.880371 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.094050 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 1540740 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -250,6 +250,6 @@ system.cpu.num_int_register_writes 1332688300 # nu system.cpu.num_load_insts 511488910 # Number of load instructions system.cpu.num_mem_refs 722298387 # number of memory refs system.cpu.num_store_insts 210809477 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 39 # Number of system calls +system.cpu.workload.num_syscalls 39 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini index 21ecdfc08..410b12d67 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -498,7 +498,7 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/alisai01/dist/cpu2000/binaries/arm/linux/perlbmk +executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout index 166a55741..ef09fb549 100755 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 18:12:10 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 13:00:27 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 6525e4aa7..d75eda4b1 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 140843 # Simulator instruction rate (inst/s) -host_mem_usage 264636 # Number of bytes of host memory used -host_seconds 13386.13 # Real time elapsed on the host -host_tick_rate 64927108 # Simulator tick rate (ticks/s) +host_inst_rate 198311 # Simulator instruction rate (inst/s) +host_mem_usage 221048 # Number of bytes of host memory used +host_seconds 9507.00 # Real time elapsed on the host +host_tick_rate 91419245 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1885343131 # Number of instructions simulated sim_seconds 0.869123 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 38509304 # Nu system.cpu.BPredUnit.condPredicted 414146262 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 547821195 # Number of BP lookups system.cpu.BPredUnit.usedRAS 52353944 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 291352101 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 58391194 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1569639960 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.201138 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.832019 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 741490044 47.24% 47.24% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 428382990 27.29% 74.53% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 179836279 11.46% 85.99% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 75300710 4.80% 90.79% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 51350508 3.27% 94.06% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 14363186 0.92% 94.97% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 16626388 1.06% 96.03% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 3898661 0.25% 96.28% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 58391194 3.72% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1569639960 # Number of insts commited each cycle -system.cpu.commit.COM:count 1885354147 # Number of instructions committed -system.cpu.commit.COM:fp_insts 52289415 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 41577833 # Number of function calls committed. -system.cpu.commit.COM:int_insts 1660589568 # Number of committed integer instructions. -system.cpu.commit.COM:loads 631390738 # Number of loads committed -system.cpu.commit.COM:membars 9986 # Number of memory barriers committed -system.cpu.commit.COM:refs 908389591 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 44034324 # The number of times a branch was mispredicted +system.cpu.commit.branches 291352101 # Number of branches committed +system.cpu.commit.bw_lim_events 58391194 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 1885354147 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 211788 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 1159545124 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 1569639960 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.201138 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.832019 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 741490044 47.24% 47.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 428382990 27.29% 74.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 179836279 11.46% 85.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 75300710 4.80% 90.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 51350508 3.27% 94.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14363186 0.92% 94.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 16626388 1.06% 96.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3898661 0.25% 96.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 58391194 3.72% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1569639960 # Number of insts commited each cycle +system.cpu.commit.count 1885354147 # Number of instructions committed +system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. +system.cpu.commit.function_calls 41577833 # Number of function calls committed. +system.cpu.commit.int_insts 1660589568 # Number of committed integer instructions. +system.cpu.commit.loads 631390738 # Number of loads committed +system.cpu.commit.membars 9986 # Number of memory barriers committed +system.cpu.commit.refs 908389591 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 1885343131 # Number of Instructions Simulated system.cpu.committedInsts_total 1885343131 # Number of Instructions Simulated system.cpu.cpi 0.921978 # CPI: Cycles Per Instruction @@ -105,8 +105,8 @@ system.cpu.dcache.demand_mshr_misses 1535477 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999735 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4094.913997 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999735 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 996679005 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 34625.216763 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 34030.134935 # average overall mshr miss latency @@ -128,15 +128,15 @@ system.cpu.dcache.tagsinuse 4094.913997 # Cy system.cpu.dcache.total_refs 993970537 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 333433000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 106994 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 146923379 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 10558 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 87779592 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 3387651447 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 772293047 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 647864668 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 162682073 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 19702 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 2558864 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 146923379 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 10558 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 87779592 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 3387651447 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 772293047 # Number of cycles decode is idle +system.cpu.decode.RunCycles 647864668 # Number of cycles decode is running +system.cpu.decode.SquashCycles 162682073 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 19702 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 2558864 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -221,8 +221,8 @@ system.cpu.icache.demand_mshr_misses 24392 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.752702 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1541.532802 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.752702 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 367105078 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 9381.938291 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 6050.959331 # average overall mshr miss latency @@ -245,21 +245,13 @@ system.cpu.icache.total_refs 367080251 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 5923199 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 358605233 # Number of branches executed -system.cpu.iew.EXEC:nop 1350849 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.388402 # Inst execution rate -system.cpu.iew.EXEC:refs 1176236253 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 407328146 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 2464876715 # num instructions consuming a value -system.cpu.iew.WB:count 2378604713 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.531444 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1309943730 # num instructions producing a value -system.cpu.iew.WB:rate 1.368394 # insts written-back per cycle -system.cpu.iew.WB:sent 2386121679 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 46494560 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 358605233 # Number of branches executed +system.cpu.iew.exec_nop 1350849 # number of nop insts executed +system.cpu.iew.exec_rate 1.388402 # Inst execution rate +system.cpu.iew.exec_refs 1176236253 # number of memory reference insts executed +system.cpu.iew.exec_stores 407328146 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 11036637 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 946299703 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 229756 # Number of dispatched non-speculative instructions @@ -287,103 +279,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 201953747 # system.cpu.iew.memOrderViolationEvents 2659902 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 7823566 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 38670994 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 2464876715 # num instructions consuming a value +system.cpu.iew.wb_count 2378604713 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.531444 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 1309943730 # num instructions producing a value +system.cpu.iew.wb_rate 1.368394 # insts written-back per cycle +system.cpu.iew.wb_sent 2386121679 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 5694776843 # number of integer regfile reads system.cpu.int_regfile_writes 1751148886 # number of integer regfile writes system.cpu.ipc 1.084624 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.084624 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1205851764 48.37% 48.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 11238449 0.45% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 8633 0.00% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 1375289 0.06% 48.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 48.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 6876474 0.28% 49.15% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 5501201 0.22% 49.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 49.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 23385525 0.94% 50.31% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 50.31% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 50.31% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 50.31% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 797167964 31.97% 82.28% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 441731367 17.72% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 2493136666 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 86890569 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.034852 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 482 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 24113 0.03% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 55140629 63.46% 63.49% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 31725345 36.51% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 1732322031 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.439188 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.577350 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 668978981 38.62% 38.62% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 360959007 20.84% 59.45% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 315091353 18.19% 77.64% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 182075740 10.51% 88.15% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 118045462 6.81% 94.97% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 56433729 3.26% 98.23% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 19322035 1.12% 99.34% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 5840762 0.34% 99.68% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 5574962 0.32% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 1732322031 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.434284 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1205851764 48.37% 48.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11238449 0.45% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 8633 0.00% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 48.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876474 0.28% 49.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5501201 0.22% 49.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23385525 0.94% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 797167964 31.97% 82.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 441731367 17.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 2493136666 # Type of FU issued system.cpu.iq.fp_alu_accesses 66051736 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 126602345 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 59166260 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 83365842 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 86890569 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.034852 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 482 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 24113 0.03% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 55140629 63.46% 63.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 31725345 36.51% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 2513975499 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 6687198013 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 2319438453 # Number of integer instruction queue wakeup accesses @@ -395,6 +377,24 @@ system.cpu.iq.iqSquashedInstsExamined 1158104053 # Nu system.cpu.iq.iqSquashedInstsIssued 8314426 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 30366 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 1709199023 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 1732322031 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.439188 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.577350 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 668978981 38.62% 38.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 360959007 20.84% 59.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 315091353 18.19% 77.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 182075740 10.51% 88.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 118045462 6.81% 94.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 56433729 3.26% 98.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 19322035 1.12% 99.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 5840762 0.34% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5574962 0.32% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1732322031 # Number of insts issued each cycle +system.cpu.iq.rate 1.434284 # Inst issue rate system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -469,10 +469,10 @@ system.cpu.l2cache.demand_mshr_misses 1480664 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.884291 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.091352 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 28976.452018 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 2993.413242 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.884291 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.091352 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 1559863 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34267.085819 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31000.382261 # average overall mshr miss latency @@ -503,28 +503,28 @@ system.cpu.misc_regfile_writes 13780014 # nu system.cpu.numCycles 1738245230 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 26815429 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 1523726473 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 13358705 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 804669593 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 12419294 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 8858159876 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 3258876297 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 2595747724 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 616670755 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 162682073 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 32941123 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1072021248 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 417025150 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 8441134726 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 88543058 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 8500262 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 93807403 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 250407 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 26815429 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1523726473 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 13358705 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 804669593 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 12419294 # Number of times rename has blocked due to LSQ full +system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 8858159876 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 3258876297 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 2595747724 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 616670755 # Number of cycles rename is running +system.cpu.rename.SquashCycles 162682073 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 32941123 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 1072021248 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 417025150 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 8441134726 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 88543058 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 8500262 # count of serializing insts renamed +system.cpu.rename.skidInsts 93807403 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 250407 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 4556129692 # The number of ROB reads system.cpu.rob.rob_writes 6252480772 # The number of ROB writes system.cpu.timesIdled 1346475 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 1411 # Number of system calls +system.cpu.workload.num_syscalls 1411 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini index 4c80bccfd..97cb6c6e4 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini @@ -61,12 +61,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk +executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout index 47a67193a..343cd2a25 100755 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 18:14:25 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 13:03:45 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index a5bf8162c..fa8e0bd4e 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1065231 # Simulator instruction rate (inst/s) -host_mem_usage 252312 # Number of bytes of host memory used -host_seconds 1769.89 # Real time elapsed on the host -host_tick_rate 534279231 # Simulator tick rate (ticks/s) +host_inst_rate 3903299 # Simulator instruction rate (inst/s) +host_mem_usage 211416 # Number of bytes of host memory used +host_seconds 483.01 # Real time elapsed on the host +host_tick_rate 1957745790 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1885336367 # Number of instructions simulated sim_seconds 0.945613 # Number of seconds simulated @@ -71,6 +71,6 @@ system.cpu.num_int_register_writes 1404936302 # nu system.cpu.num_load_insts 631387182 # Number of load instructions system.cpu.num_mem_refs 908382480 # number of memory refs system.cpu.num_store_insts 276995298 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 1411 # Number of system calls +system.cpu.workload.num_syscalls 1411 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini index 53d197f66..f566d5f40 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini @@ -164,12 +164,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing +cwd=build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk +executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout index 5f6cb9527..5a9581642 100755 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 18:18:27 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 13:11:59 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index 3345b6b66..064048304 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 561445 # Simulator instruction rate (inst/s) -host_mem_usage 260040 # Number of bytes of host memory used -host_seconds 3338.25 # Real time elapsed on the host -host_tick_rate 709922934 # Simulator tick rate (ticks/s) +host_inst_rate 2093812 # Simulator instruction rate (inst/s) +host_mem_usage 219156 # Number of bytes of host memory used +host_seconds 895.14 # Real time elapsed on the host +host_tick_rate 2647534553 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1874244950 # Number of instructions simulated sim_seconds 2.369902 # Number of seconds simulated @@ -54,8 +54,8 @@ system.cpu.dcache.demand_mshr_misses 1533653 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999746 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4094.960333 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999746 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 897271092 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 54458.738711 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 51458.738711 # average overall mshr miss latency @@ -130,8 +130,8 @@ system.cpu.icache.demand_mshr_misses 19803 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.679846 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1392.324437 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.679846 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 1390271511 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 18786.850477 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 15786.850477 # average overall mshr miss latency @@ -219,10 +219,10 @@ system.cpu.l2cache.demand_mshr_misses 1479630 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.881757 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.092817 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 28893.420796 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 3041.423322 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.881757 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.092817 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 1553456 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -264,6 +264,6 @@ system.cpu.num_int_register_writes 1404936302 # nu system.cpu.num_load_insts 631387182 # Number of load instructions system.cpu.num_mem_refs 908382480 # number of memory refs system.cpu.num_store_insts 276995298 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 1411 # Number of system calls +system.cpu.workload.num_syscalls 1411 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini index 46d47f481..2452e8b3b 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini @@ -86,6 +86,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +122,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -156,6 +158,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout index 55fcb321a..124e9408d 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 18 2011 15:40:30 -M5 revision Unknown -M5 started Feb 18 2011 18:53:22 -M5 executing on m55-001.pool +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 11:58:35 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 883ec05af..e986b9b66 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,37 +1,25 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 140237 # Simulator instruction rate (inst/s) -host_mem_usage 237028 # Number of bytes of host memory used -host_seconds 629.94 # Real time elapsed on the host -host_tick_rate 69352666 # Simulator tick rate (ticks/s) +host_inst_rate 198512 # Simulator instruction rate (inst/s) +host_mem_usage 241900 # Number of bytes of host memory used +host_seconds 445.02 # Real time elapsed on the host +host_tick_rate 98171525 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated sim_seconds 0.043688 # Number of seconds simulated sim_ticks 43687852500 # Number of ticks simulated -system.cpu.AGEN-Unit.agens 35033051 # Number of Address Generations -system.cpu.Branch-Predictor.BTBHitPct 40.125186 # BTB Hit Percentage -system.cpu.Branch-Predictor.BTBHits 4678520 # Number of BTB hits -system.cpu.Branch-Predictor.BTBLookups 11659809 # Number of BTB lookups -system.cpu.Branch-Predictor.RASInCorrect 1539 # Number of incorrect RAS predictions. -system.cpu.Branch-Predictor.condIncorrect 753993 # Number of conditional branches incorrect -system.cpu.Branch-Predictor.condPredicted 9173160 # Number of conditional branches predicted -system.cpu.Branch-Predictor.lookups 14237671 # Number of BP lookups -system.cpu.Branch-Predictor.predictedNotTaken 6139595 # Number of Branches Predicted As Not Taken (False). -system.cpu.Branch-Predictor.predictedTaken 8098076 # Number of Branches Predicted As Taken (True). -system.cpu.Branch-Predictor.usedRAS 1660495 # Number of times the RAS was used to get a target. -system.cpu.Execution-Unit.executions 44841137 # Number of Instructions Executed. -system.cpu.Execution-Unit.mispredictPct 5.481801 # Percentage of Incorrect Branches Predicts -system.cpu.Execution-Unit.mispredicted 753993 # Number of Branches Incorrectly Predicted -system.cpu.Execution-Unit.predicted 13000484 # Number of Branches Incorrectly Predicted -system.cpu.Execution-Unit.predictedNotTakenIncorrect 550902 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.Execution-Unit.predictedTakenIncorrect 203091 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed -system.cpu.Mult-Div-Unit.multiplies 41101 # Number of Multipy Operations Executed -system.cpu.RegFile-Manager.regFileAccesses 145605009 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.RegFile-Manager.regFileReads 93058128 # Number of Reads from Register File -system.cpu.RegFile-Manager.regFileWrites 52546881 # Number of Writes to Register File -system.cpu.RegFile-Manager.regForwards 13517276 # Number of Registers Read Through Forwarding Logic system.cpu.activity 70.715162 # Percentage of cycles cpu is active +system.cpu.agen_unit.agens 35033051 # Number of Address Generations +system.cpu.branch_predictor.BTBHitPct 40.125186 # BTB Hit Percentage +system.cpu.branch_predictor.BTBHits 4678520 # Number of BTB hits +system.cpu.branch_predictor.BTBLookups 11659809 # Number of BTB lookups +system.cpu.branch_predictor.RASInCorrect 1539 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.condIncorrect 753993 # Number of conditional branches incorrect +system.cpu.branch_predictor.condPredicted 9173160 # Number of conditional branches predicted +system.cpu.branch_predictor.lookups 14237671 # Number of BP lookups +system.cpu.branch_predictor.predictedNotTaken 6139595 # Number of Branches Predicted As Not Taken (False). +system.cpu.branch_predictor.predictedTaken 8098076 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.usedRAS 1660495 # Number of times the RAS was used to get a target. system.cpu.comBranches 13754477 # Number of Branches instructions committed system.cpu.comFloats 151453 # Number of Floating Point instructions committed system.cpu.comInts 30791227 # Number of Integer instructions committed @@ -88,8 +76,8 @@ system.cpu.dcache.demand_mshr_misses 204344 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.994103 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4071.844772 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.994103 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 48047.843576 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 45018.459069 # average overall mshr miss latency @@ -127,6 +115,12 @@ system.cpu.dtb.write_accesses 14620629 # DT system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_hits 14613377 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses +system.cpu.execution_unit.executions 44841137 # Number of Instructions Executed. +system.cpu.execution_unit.mispredictPct 5.481801 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.mispredicted 753993 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 13000484 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predictedNotTakenIncorrect 550902 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.predictedTakenIncorrect 203091 # Number of Branches Incorrectly Predicted As Taken. system.cpu.icache.ReadReq_accesses 11384439 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 18620.927639 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 15557.720286 # average ReadReq mshr miss latency @@ -160,8 +154,8 @@ system.cpu.icache.demand_mshr_misses 88669 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.918759 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1881.619179 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.918759 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 11384439 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 18620.927639 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 15557.720286 # average overall mshr miss latency @@ -246,10 +240,10 @@ system.cpu.l2cache.demand_mshr_misses 174462 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.093044 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.476016 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 3048.873160 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 15598.097053 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.093044 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.476016 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 293012 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52103.234515 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40007.007257 # average overall mshr miss latency @@ -271,31 +265,37 @@ system.cpu.l2cache.tagsinuse 18646.970214 # Cy system.cpu.l2cache.total_refs 134496 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 120516 # number of writebacks +system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed +system.cpu.mult_div_unit.multiplies 41101 # Number of Multipy Operations Executed system.cpu.numCycles 87375706 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.regfile_manager.regFileAccesses 145605009 # Number of Total Accesses (Read+Write) to the Register File +system.cpu.regfile_manager.regFileReads 93058128 # Number of Reads from Register File +system.cpu.regfile_manager.regFileWrites 52546881 # Number of Writes to Register File +system.cpu.regfile_manager.regForwards 13517276 # Number of Registers Read Through Forwarding Logic system.cpu.runCycles 61787872 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 42493951 # Number of cycles 0 instructions are processed. -system.cpu.stage-0.runCycles 44881755 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 51.366400 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 48181868 # Number of cycles 0 instructions are processed. -system.cpu.stage-1.runCycles 39193838 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 44.856677 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 46079607 # Number of cycles 0 instructions are processed. -system.cpu.stage-2.runCycles 41296099 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 47.262678 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 63477269 # Number of cycles 0 instructions are processed. -system.cpu.stage-3.runCycles 23898437 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 27.351352 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 39338499 # Number of cycles 0 instructions are processed. -system.cpu.stage-4.runCycles 48037207 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 54.977761 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage0.idleCycles 42493951 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 44881755 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 51.366400 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 48181868 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 39193838 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 44.856677 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 46079607 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 41296099 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 47.262678 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 63477269 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 23898437 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 27.351352 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 39338499 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 48037207 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 54.977761 # Percentage of cycles stage was utilized (processing insts). system.cpu.threadCycles 69007682 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.timesIdled 289197 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls +system.cpu.workload.num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini index 22a45b8cb..c10dc5f2b 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -25,6 +25,8 @@ BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout index 78849816e..0e04160b4 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 17 2011 21:44:37 -M5 started Mar 17 2011 21:45:41 -M5 executing on zizzer +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 11:58:35 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 2c566c667..2aed2a2e0 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 229170 # Simulator instruction rate (inst/s) -host_mem_usage 217968 # Number of bytes of host memory used -host_seconds 347.30 # Real time elapsed on the host -host_tick_rate 73616120 # Simulator tick rate (ticks/s) +host_inst_rate 329538 # Simulator instruction rate (inst/s) +host_mem_usage 213968 # Number of bytes of host memory used +host_seconds 241.53 # Real time elapsed on the host +host_tick_rate 105857368 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 79591756 # Number of instructions simulated sim_seconds 0.025567 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 450273 # Nu system.cpu.BPredUnit.condPredicted 10401089 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 16008370 # Number of BP lookups system.cpu.BPredUnit.usedRAS 1909965 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 13754477 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 3841167 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 49654357 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.779112 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.457508 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 22596462 45.51% 45.51% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 9701520 19.54% 65.05% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 4636863 9.34% 74.38% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 2945074 5.93% 80.32% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 2498358 5.03% 85.35% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 1627223 3.28% 88.62% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 982509 1.98% 90.60% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 825181 1.66% 92.26% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 3841167 7.74% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 49654357 # Number of insts commited each cycle -system.cpu.commit.COM:count 88340672 # Number of instructions committed -system.cpu.commit.COM:fp_insts 267754 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 1661057 # Number of function calls committed. -system.cpu.commit.COM:int_insts 77942044 # Number of committed integer instructions. -system.cpu.commit.COM:loads 20276638 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 34890015 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 354109 # The number of times a branch was mispredicted +system.cpu.commit.branches 13754477 # Number of branches committed +system.cpu.commit.bw_lim_events 3841167 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 6568373 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 49654357 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.779112 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.457508 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 22596462 45.51% 45.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9701520 19.54% 65.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4636863 9.34% 74.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2945074 5.93% 80.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2498358 5.03% 85.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1627223 3.28% 88.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 982509 1.98% 90.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 825181 1.66% 92.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3841167 7.74% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 49654357 # Number of insts commited each cycle +system.cpu.commit.count 88340672 # Number of instructions committed +system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. +system.cpu.commit.function_calls 1661057 # Number of function calls committed. +system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. +system.cpu.commit.loads 20276638 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.refs 34890015 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated system.cpu.cpi 0.642459 # CPI: Cycles Per Instruction @@ -98,8 +98,8 @@ system.cpu.dcache.demand_mshr_misses 205151 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.995275 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4076.644885 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.995275 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 35172985 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 31791.373703 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 29357.307544 # average overall mshr miss latency @@ -121,15 +121,15 @@ system.cpu.dcache.tagsinuse 4076.644885 # Cy system.cpu.dcache.total_refs 33980616 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 177876000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 161514 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 2460997 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 97681 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3594435 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 100084760 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 27762644 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 19396266 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1063649 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 276834 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 34450 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 2460997 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 97681 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 3594435 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 100084760 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 27762644 # Number of cycles decode is idle +system.cpu.decode.RunCycles 19396266 # Number of cycles decode is running +system.cpu.decode.SquashCycles 1063649 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 276834 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 34450 # Number of cycles decode is unblocking system.cpu.dtb.data_accesses 36973918 # DTB accesses system.cpu.dtb.data_acv 20 # DTB access violations system.cpu.dtb.data_hits 36772232 # DTB hits @@ -209,8 +209,8 @@ system.cpu.icache.demand_mshr_misses 85058 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.935566 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1916.040169 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.935566 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 13158718 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 9582.065520 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 6079.057819 # average overall mshr miss latency @@ -233,21 +233,13 @@ system.cpu.icache.total_refs 13070837 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 416464 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 14700654 # Number of branches executed -system.cpu.iew.EXEC:nop 9311504 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.660486 # Inst execution rate -system.cpu.iew.EXEC:refs 36975872 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 15225695 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 40429267 # num instructions consuming a value -system.cpu.iew.WB:count 84366668 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.767758 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 31039892 # num instructions producing a value -system.cpu.iew.WB:rate 1.649898 # insts written-back per cycle -system.cpu.iew.WB:sent 84634554 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 395795 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 14700654 # Number of branches executed +system.cpu.iew.exec_nop 9311504 # number of nop insts executed +system.cpu.iew.exec_rate 1.660486 # Inst execution rate +system.cpu.iew.exec_refs 36975872 # number of memory reference insts executed +system.cpu.iew.exec_stores 15225695 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 429488 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 22491432 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 4739 # Number of dispatched non-speculative instructions @@ -275,103 +267,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 1168217 # system.cpu.iew.memOrderViolationEvents 6217 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 133065 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 262730 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 40429267 # num instructions consuming a value +system.cpu.iew.wb_count 84366668 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.767758 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 31039892 # num instructions producing a value +system.cpu.iew.wb_rate 1.649898 # insts written-back per cycle +system.cpu.iew.wb_sent 84634554 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 112360564 # number of integer regfile reads system.cpu.int_regfile_writes 55786710 # number of integer regfile writes system.cpu.ipc 1.556519 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.556519 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 47939957 56.08% 56.08% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 43473 0.05% 56.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 56.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 122672 0.14% 56.28% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 87 0.00% 56.28% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 123541 0.14% 56.42% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 52 0.00% 56.42% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 38558 0.05% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 21877865 25.59% 82.06% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 15331781 17.94% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 85477986 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 1052413 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.012312 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 99607 9.46% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 509872 48.45% 57.91% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 442934 42.09% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 50718006 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.685358 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.886898 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 18797586 37.06% 37.06% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 10551252 20.80% 57.87% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 7740515 15.26% 73.13% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 3878311 7.65% 80.78% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 5219123 10.29% 91.07% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 1973435 3.89% 94.96% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 1302970 2.57% 97.53% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 789228 1.56% 99.08% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 465586 0.92% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 50718006 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.671631 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 47939957 56.08% 56.08% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43473 0.05% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 122672 0.14% 56.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 87 0.00% 56.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 123541 0.14% 56.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 52 0.00% 56.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38558 0.05% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 21877865 25.59% 82.06% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15331781 17.94% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 85477986 # Type of FU issued system.cpu.iq.fp_alu_accesses 297653 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 595198 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 282834 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 410179 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 1052413 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012312 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 99607 9.46% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 509872 48.45% 57.91% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 442934 42.09% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 86232746 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 222155982 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 84083834 # Number of integer instruction queue wakeup accesses @@ -383,6 +365,24 @@ system.cpu.iq.iqSquashedInstsExamined 8137764 # Nu system.cpu.iq.iqSquashedInstsIssued 24789 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 156 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 4541669 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 50718006 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.685358 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.886898 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 18797586 37.06% 37.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10551252 20.80% 57.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7740515 15.26% 73.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3878311 7.65% 80.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5219123 10.29% 91.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1973435 3.89% 94.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1302970 2.57% 97.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 789228 1.56% 99.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 465586 0.92% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 50718006 # Number of insts issued each cycle +system.cpu.iq.rate 1.671631 # Inst issue rate system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits @@ -443,10 +443,10 @@ system.cpu.l2cache.demand_mshr_misses 175063 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.091039 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.482420 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 2983.162459 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 15807.936259 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.091039 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.482420 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 290209 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34335.524925 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31214.302851 # average overall mshr miss latency @@ -477,28 +477,28 @@ system.cpu.misc_regfile_writes 1 # nu system.cpu.numCycles 51134470 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 1389160 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 11049 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 28153155 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 921609 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 39 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 119490611 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 99297358 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 59691366 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 19024050 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1063649 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 1018413 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 7144485 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 428893 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 119061718 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 69579 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 5023 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 2212492 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 5020 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 1389160 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 11049 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 28153155 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 921609 # Number of times rename has blocked due to LSQ full +system.cpu.rename.ROBFullEvents 39 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 119490611 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 99297358 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 59691366 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 19024050 # Number of cycles rename is running +system.cpu.rename.SquashCycles 1063649 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 1018413 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 7144485 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 428893 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 119061718 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 69579 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 5023 # count of serializing insts renamed +system.cpu.rename.skidInsts 2212492 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 5020 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 139404893 # The number of ROB reads system.cpu.rob.rob_writes 190882895 # The number of ROB writes system.cpu.timesIdled 12185 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls +system.cpu.workload.num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout index 47e63ab68..01b718e71 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:38 -M5 executing on burrito +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 11:58:24 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt index 1ad0b8bf6..cf38a10a9 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1614429 # Simulator instruction rate (inst/s) -host_mem_usage 226740 # Number of bytes of host memory used -host_seconds 54.72 # Real time elapsed on the host -host_tick_rate 808136192 # Simulator tick rate (ticks/s) +host_inst_rate 5661046 # Simulator instruction rate (inst/s) +host_mem_usage 204384 # Number of bytes of host memory used +host_seconds 15.61 # Real time elapsed on the host +host_tick_rate 2833734985 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated sim_seconds 0.044221 # Number of seconds simulated @@ -61,6 +61,6 @@ system.cpu.num_int_register_writes 52319251 # nu system.cpu.num_load_insts 20366786 # Number of load instructions system.cpu.num_mem_refs 34987415 # number of memory refs system.cpu.num_store_insts 14620629 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls +system.cpu.workload.num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini index 6f171a7fa..7e8e19e97 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini @@ -51,6 +51,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -86,6 +87,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +123,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout index 4f3f97870..c65ed7989 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:37 -M5 executing on burrito +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 12:02:47 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index 4a3fdb24c..d459892f5 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 599191 # Simulator instruction rate (inst/s) -host_mem_usage 234452 # Number of bytes of host memory used -host_seconds 147.43 # Real time elapsed on the host -host_tick_rate 910763031 # Simulator tick rate (ticks/s) +host_inst_rate 2375162 # Simulator instruction rate (inst/s) +host_mem_usage 212132 # Number of bytes of host memory used +host_seconds 37.19 # Real time elapsed on the host +host_tick_rate 3610204318 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated sim_seconds 0.134277 # Number of seconds simulated @@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses 204344 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.995815 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4078.858373 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.995815 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 47925.116470 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 44925.116470 # average overall mshr miss latency @@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 76436 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.913772 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1871.404551 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.913772 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 88438074 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 18793.107960 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 15793.107960 # average overall mshr miss latency @@ -205,10 +205,10 @@ system.cpu.l2cache.demand_mshr_misses 173780 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.085649 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.482430 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 2806.549776 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 15808.263557 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.085649 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.482430 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 280780 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -250,6 +250,6 @@ system.cpu.num_int_register_writes 52319251 # nu system.cpu.num_load_insts 20366786 # Number of load instructions system.cpu.num_mem_refs 34987415 # number of memory refs system.cpu.num_store_insts 14620629 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls +system.cpu.workload.num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini index 6767fc19c..2426ff257 100644 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -498,7 +498,7 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/alisai01/dist/cpu2000/binaries/arm/linux/vortex +executable=/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout index 3d6783bda..8381f7581 100755 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 18:24:14 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 13:18:26 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt index 2c7e07f74..50e06cc2a 100644 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 216149 # Simulator instruction rate (inst/s) -host_mem_usage 267340 # Number of bytes of host memory used -host_seconds 465.57 # Real time elapsed on the host -host_tick_rate 85683012 # Simulator tick rate (ticks/s) +host_inst_rate 252526 # Simulator instruction rate (inst/s) +host_mem_usage 223792 # Number of bytes of host memory used +host_seconds 398.51 # Real time elapsed on the host +host_tick_rate 100102950 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 100633305 # Number of instructions simulated sim_seconds 0.039892 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 830445 # Nu system.cpu.BPredUnit.condPredicted 11914381 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 18227498 # Number of BP lookups system.cpu.BPredUnit.usedRAS 1851553 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 13669912 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 2877364 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 76617428 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.313524 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.896154 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 34018334 44.40% 44.40% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 22269182 29.07% 73.47% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 6570057 8.58% 82.04% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 4759391 6.21% 88.25% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 3903161 5.09% 93.35% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 1377879 1.80% 95.15% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 463983 0.61% 95.75% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 378077 0.49% 96.24% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 2877364 3.76% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 76617428 # Number of insts commited each cycle -system.cpu.commit.COM:count 100638857 # Number of instructions committed -system.cpu.commit.COM:fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 1679850 # Number of function calls committed. -system.cpu.commit.COM:int_insts 91477923 # Number of committed integer instructions. -system.cpu.commit.COM:loads 27308393 # Number of loads committed -system.cpu.commit.COM:membars 15920 # Number of memory barriers committed -system.cpu.commit.COM:refs 47865415 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 800437 # The number of times a branch was mispredicted +system.cpu.commit.branches 13669912 # Number of branches committed +system.cpu.commit.bw_lim_events 2877364 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 100638857 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 700914 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 13588852 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 76617428 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.313524 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.896154 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 34018334 44.40% 44.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 22269182 29.07% 73.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 6570057 8.58% 82.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4759391 6.21% 88.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3903161 5.09% 93.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1377879 1.80% 95.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 463983 0.61% 95.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 378077 0.49% 96.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2877364 3.76% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 76617428 # Number of insts commited each cycle +system.cpu.commit.count 100638857 # Number of instructions committed +system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. +system.cpu.commit.function_calls 1679850 # Number of function calls committed. +system.cpu.commit.int_insts 91477923 # Number of committed integer instructions. +system.cpu.commit.loads 27308393 # Number of loads committed +system.cpu.commit.membars 15920 # Number of memory barriers committed +system.cpu.commit.refs 47865415 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 100633305 # Number of Instructions Simulated system.cpu.committedInsts_total 100633305 # Number of Instructions Simulated system.cpu.cpi 0.792814 # CPI: Cycles Per Instruction @@ -109,8 +109,8 @@ system.cpu.dcache.demand_mshr_misses 161560 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.994984 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4075.453819 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.994984 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 46799358 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 31971.352710 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 28987.939465 # average overall mshr miss latency @@ -132,15 +132,15 @@ system.cpu.dcache.tagsinuse 4075.453819 # Cy system.cpu.dcache.total_refs 45185537 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 327416000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 123381 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 28767889 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 93628 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3727749 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 120621461 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 25476849 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 21756774 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 2130394 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 323992 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 615915 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 28767889 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 93628 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 3727749 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 120621461 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 25476849 # Number of cycles decode is idle +system.cpu.decode.RunCycles 21756774 # Number of cycles decode is running +system.cpu.decode.SquashCycles 2130394 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 323992 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 615915 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -225,8 +225,8 @@ system.cpu.icache.demand_mshr_misses 24591 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.875696 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1793.424749 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.875696 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 11770565 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 12757.129371 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 9282.013745 # average overall mshr miss latency @@ -249,21 +249,13 @@ system.cpu.icache.total_refs 11745142 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 1035652 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 14732348 # Number of branches executed -system.cpu.iew.EXEC:nop 77233 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.323750 # Inst execution rate -system.cpu.iew.EXEC:refs 49299625 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 21011299 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 107738460 # num instructions consuming a value -system.cpu.iew.WB:count 105037825 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.490563 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 52852456 # num instructions producing a value -system.cpu.iew.WB:rate 1.316536 # insts written-back per cycle -system.cpu.iew.WB:sent 105209239 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 874742 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 14732348 # Number of branches executed +system.cpu.iew.exec_nop 77233 # number of nop insts executed +system.cpu.iew.exec_rate 1.323750 # Inst execution rate +system.cpu.iew.exec_refs 49299625 # number of memory reference insts executed +system.cpu.iew.exec_stores 21011299 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 976865 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 29744817 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 738677 # Number of dispatched non-speculative instructions @@ -291,103 +283,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 1650781 # system.cpu.iew.memOrderViolationEvents 8523 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 227397 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 647345 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 107738460 # num instructions consuming a value +system.cpu.iew.wb_count 105037825 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.490563 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 52852456 # num instructions producing a value +system.cpu.iew.wb_rate 1.316536 # insts written-back per cycle +system.cpu.iew.wb_sent 105209239 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 252839831 # number of integer regfile reads system.cpu.int_regfile_writes 78127703 # number of integer regfile writes system.cpu.ipc 1.261330 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.261330 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 56712642 53.23% 53.23% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 95301 0.09% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 11 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 1 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 8 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 28583241 26.83% 80.15% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 21153285 19.85% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 106544489 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 1792992 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.016829 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 49061 2.74% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 1439096 80.26% 83.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 304835 17.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 78747821 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.352983 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.550711 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 30449549 38.67% 38.67% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 20272773 25.74% 64.41% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 12837785 16.30% 80.71% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 6496976 8.25% 88.96% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 4874072 6.19% 95.15% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 2197331 2.79% 97.94% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 925872 1.18% 99.12% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 480661 0.61% 99.73% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 212802 0.27% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 78747821 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.335421 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56712642 53.23% 53.23% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95301 0.09% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 11 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 1 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 8 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28583241 26.83% 80.15% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21153285 19.85% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 106544489 # Type of FU issued system.cpu.iq.fp_alu_accesses 82 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 160 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 68 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 144 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 1792992 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016829 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 49061 2.74% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1439096 80.26% 83.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 304835 17.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 108337399 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 293735316 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 105037757 # Number of integer instruction queue wakeup accesses @@ -399,6 +381,24 @@ system.cpu.iq.iqSquashedInstsExamined 13400232 # Nu system.cpu.iq.iqSquashedInstsIssued 105692 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 54866 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 21923544 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 78747821 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.352983 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.550711 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 30449549 38.67% 38.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 20272773 25.74% 64.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 12837785 16.30% 80.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6496976 8.25% 88.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4874072 6.19% 95.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2197331 2.79% 97.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 925872 1.18% 99.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 480661 0.61% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 212802 0.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 78747821 # Number of insts issued each cycle +system.cpu.iq.rate 1.335421 # Inst issue rate system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -473,10 +473,10 @@ system.cpu.l2cache.demand_mshr_misses 134835 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.070082 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.488463 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 2296.436358 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 16005.968558 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.070082 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.488463 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 186127 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34374.638605 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31202.784885 # average overall mshr miss latency @@ -507,28 +507,28 @@ system.cpu.misc_regfile_writes 34408 # nu system.cpu.numCycles 79783473 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 2921057 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 75878617 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 205954 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 27124909 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2993782 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 315599119 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 118180992 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 90551096 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 20607135 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 2130394 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 4279204 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 14672443 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 83429 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 315515690 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 21685122 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 759000 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 12013897 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 759711 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 2921057 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 75878617 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 205954 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 27124909 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 2993782 # Number of times rename has blocked due to LSQ full +system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 315599119 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 118180992 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 90551096 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 20607135 # Number of cycles rename is running +system.cpu.rename.SquashCycles 2130394 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 4279204 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 14672443 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 83429 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 315515690 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 21685122 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 759000 # count of serializing insts renamed +system.cpu.rename.skidInsts 12013897 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 759711 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 187942474 # The number of ROB reads system.cpu.rob.rob_writes 230588533 # The number of ROB writes system.cpu.timesIdled 60808 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls +system.cpu.workload.num_syscalls 1946 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini index 262e03017..d284ed163 100644 --- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini @@ -61,12 +61,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/vortex +executable=/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout index 66dafc4ae..6efadf55b 100755 --- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout +++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 18:44:05 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 13:19:31 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt index c99f59463..a40e03286 100644 --- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1067183 # Simulator instruction rate (inst/s) -host_mem_usage 254708 # Number of bytes of host memory used -host_seconds 94.30 # Real time elapsed on the host -host_tick_rate 571936208 # Simulator tick rate (ticks/s) +host_inst_rate 3930429 # Simulator instruction rate (inst/s) +host_mem_usage 213832 # Number of bytes of host memory used +host_seconds 25.60 # Real time elapsed on the host +host_tick_rate 2106429498 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 100632437 # Number of instructions simulated sim_seconds 0.053932 # Number of seconds simulated @@ -71,6 +71,6 @@ system.cpu.num_int_register_writes 73126599 # nu system.cpu.num_load_insts 27307109 # Number of load instructions system.cpu.num_mem_refs 47862848 # number of memory refs system.cpu.num_store_insts 20555739 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls +system.cpu.workload.num_syscalls 1946 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini index c681e2402..8d849c15a 100644 --- a/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini @@ -164,12 +164,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing +cwd=build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/vortex +executable=/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/50.vortex/ref/arm/linux/simple-timing/simout index b08e3aaf1..7b793d7b7 100755 --- a/tests/long/50.vortex/ref/arm/linux/simple-timing/simout +++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 18:45:50 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 13:20:07 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt index 0bdccd82b..4142f5d9a 100644 --- a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 558313 # Simulator instruction rate (inst/s) -host_mem_usage 262448 # Number of bytes of host memory used -host_seconds 178.74 # Real time elapsed on the host -host_tick_rate 744762819 # Simulator tick rate (ticks/s) +host_inst_rate 2031292 # Simulator instruction rate (inst/s) +host_mem_usage 221580 # Number of bytes of host memory used +host_seconds 49.13 # Real time elapsed on the host +host_tick_rate 2709639216 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 99791663 # Number of instructions simulated sim_seconds 0.133117 # Number of seconds simulated @@ -54,8 +54,8 @@ system.cpu.dcache.demand_mshr_misses 159998 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.995345 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4076.934010 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.995345 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 46990235 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 47946.924337 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 44946.924337 # average overall mshr miss latency @@ -130,8 +130,8 @@ system.cpu.icache.demand_mshr_misses 18908 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.847746 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1736.182852 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.847746 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 78145078 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 24211.233340 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 21211.233340 # average overall mshr miss latency @@ -219,10 +219,10 @@ system.cpu.l2cache.demand_mshr_misses 133917 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.066099 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.489066 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 2165.921088 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 16025.699940 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.066099 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.489066 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 178906 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -264,6 +264,6 @@ system.cpu.num_int_register_writes 73126599 # nu system.cpu.num_load_insts 27307109 # Number of load instructions system.cpu.num_mem_refs 47862848 # number of memory refs system.cpu.num_store_insts 20555739 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls +system.cpu.workload.num_syscalls 1946 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout index 7f5789393..8359194cf 100755 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:13:30 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:14:11 -M5 executing on burrito +M5 compiled Apr 19 2011 12:19:46 +M5 started Apr 19 2011 12:19:52 +M5 executing on maize command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt index d6bfda298..25cfa073d 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1204089 # Simulator instruction rate (inst/s) -host_mem_usage 228576 # Number of bytes of host memory used -host_seconds 113.06 # Real time elapsed on the host -host_tick_rate 602742669 # Simulator tick rate (ticks/s) +host_inst_rate 4754404 # Simulator instruction rate (inst/s) +host_mem_usage 206464 # Number of bytes of host memory used +host_seconds 28.63 # Real time elapsed on the host +host_tick_rate 2379947985 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136139203 # Number of instructions simulated sim_seconds 0.068149 # Number of seconds simulated @@ -29,6 +29,6 @@ system.cpu.num_int_register_writes 113225733 # nu system.cpu.num_load_insts 37275868 # Number of load instructions system.cpu.num_mem_refs 58160249 # number of memory refs system.cpu.num_store_insts 20884381 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls +system.cpu.workload.num_syscalls 1946 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini index 8ec9f75ef..4d41b9cb9 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -51,6 +51,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -86,6 +87,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +123,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout index b27952d03..0a7053375 100755 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:13:30 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:13:39 -M5 executing on burrito +M5 compiled Apr 19 2011 12:19:46 +M5 started Apr 19 2011 12:21:09 +M5 executing on maize command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt index eb6eca0bd..f75c53329 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 463084 # Simulator instruction rate (inst/s) -host_mem_usage 236284 # Number of bytes of host memory used -host_seconds 293.98 # Real time elapsed on the host -host_tick_rate 690315679 # Simulator tick rate (ticks/s) +host_inst_rate 2437881 # Simulator instruction rate (inst/s) +host_mem_usage 214216 # Number of bytes of host memory used +host_seconds 55.84 # Real time elapsed on the host +host_tick_rate 3634125508 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136139203 # Number of instructions simulated sim_seconds 0.202942 # Number of seconds simulated @@ -60,8 +60,8 @@ system.cpu.dcache.demand_mshr_misses 150663 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.997953 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4087.617150 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.997953 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 49432.508313 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 46432.508313 # average overall mshr miss latency @@ -115,8 +115,8 @@ system.cpu.icache.demand_mshr_misses 187024 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.978868 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 2004.721102 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.978868 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 134553584 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 16930.864488 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 13930.864488 # average overall mshr miss latency @@ -183,10 +183,10 @@ system.cpu.l2cache.demand_mshr_misses 140161 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.121030 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.481204 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 3965.924560 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 15768.107062 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.121030 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.481204 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 337702 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -228,6 +228,6 @@ system.cpu.num_int_register_writes 113225732 # nu system.cpu.num_load_insts 37275868 # Number of load instructions system.cpu.num_mem_refs 58160249 # number of memory refs system.cpu.num_store_insts 20884381 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls +system.cpu.workload.num_syscalls 1946 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini index 95d2d20dc..6cb2c5232 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini @@ -86,6 +86,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +122,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -156,6 +158,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout index febae9611..6c62eaee3 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/inorder-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/inorder-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 27 2011 03:06:45 -M5 revision baf4b5f6782e 8094 default tip -M5 started Feb 27 2011 03:13:10 -M5 executing on zizzer +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 11:58:24 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index 68c508b83..3b06d5b45 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,37 +1,25 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 121455 # Simulator instruction rate (inst/s) -host_mem_usage 1130520 # Number of bytes of host memory used -host_seconds 14983.11 # Real time elapsed on the host -host_tick_rate 65403738 # Simulator tick rate (ticks/s) +host_inst_rate 191712 # Simulator instruction rate (inst/s) +host_mem_usage 1122860 # Number of bytes of host memory used +host_seconds 9492.28 # Real time elapsed on the host +host_tick_rate 103236678 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780127 # Number of instructions simulated sim_seconds 0.979951 # Number of seconds simulated sim_ticks 979951369500 # Number of ticks simulated -system.cpu.AGEN-Unit.agens 614316005 # Number of Address Generations -system.cpu.Branch-Predictor.BTBHitPct 69.872947 # BTB Hit Percentage -system.cpu.Branch-Predictor.BTBHits 82064192 # Number of BTB hits -system.cpu.Branch-Predictor.BTBLookups 117447733 # Number of BTB lookups -system.cpu.Branch-Predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.Branch-Predictor.condIncorrect 79224651 # Number of conditional branches incorrect -system.cpu.Branch-Predictor.condPredicted 175157411 # Number of conditional branches predicted -system.cpu.Branch-Predictor.lookups 253574750 # Number of BP lookups -system.cpu.Branch-Predictor.predictedNotTaken 124923988 # Number of Branches Predicted As Not Taken (False). -system.cpu.Branch-Predictor.predictedTaken 128650762 # Number of Branches Predicted As Taken (True). -system.cpu.Branch-Predictor.usedRAS 16767439 # Number of times the RAS was used to get a target. -system.cpu.Execution-Unit.executions 1162207758 # Number of Instructions Executed. -system.cpu.Execution-Unit.mispredictPct 36.911759 # Percentage of Incorrect Branches Predicts -system.cpu.Execution-Unit.mispredicted 79224651 # Number of Branches Incorrectly Predicted -system.cpu.Execution-Unit.predicted 135407901 # Number of Branches Incorrectly Predicted -system.cpu.Execution-Unit.predictedNotTakenIncorrect 71572967 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.Execution-Unit.predictedTakenIncorrect 7651684 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed -system.cpu.Mult-Div-Unit.multiplies 75 # Number of Multipy Operations Executed -system.cpu.RegFile-Manager.regFileAccesses 3178023708 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.RegFile-Manager.regFileReads 1801820745 # Number of Reads from Register File -system.cpu.RegFile-Manager.regFileWrites 1376202963 # Number of Writes to Register File -system.cpu.RegFile-Manager.regForwards 604786987 # Number of Registers Read Through Forwarding Logic system.cpu.activity 74.309805 # Percentage of cycles cpu is active +system.cpu.agen_unit.agens 614316005 # Number of Address Generations +system.cpu.branch_predictor.BTBHitPct 69.872947 # BTB Hit Percentage +system.cpu.branch_predictor.BTBHits 82064192 # Number of BTB hits +system.cpu.branch_predictor.BTBLookups 117447733 # Number of BTB lookups +system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.condIncorrect 79224651 # Number of conditional branches incorrect +system.cpu.branch_predictor.condPredicted 175157411 # Number of conditional branches predicted +system.cpu.branch_predictor.lookups 253574750 # Number of BP lookups +system.cpu.branch_predictor.predictedNotTaken 124923988 # Number of Branches Predicted As Not Taken (False). +system.cpu.branch_predictor.predictedTaken 128650762 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target. system.cpu.comBranches 214632552 # Number of Branches instructions committed system.cpu.comFloats 190 # Number of Floating Point instructions committed system.cpu.comInts 916086844 # Number of Integer instructions committed @@ -88,8 +76,8 @@ system.cpu.dcache.demand_mshr_misses 9111643 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.996505 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4081.685602 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.996505 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 27335.708502 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 23594.611641 # average overall mshr miss latency @@ -127,6 +115,12 @@ system.cpu.dtb.write_accesses 162429806 # DT system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_hits 160728502 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses +system.cpu.execution_unit.executions 1162207758 # Number of Instructions Executed. +system.cpu.execution_unit.mispredictPct 36.911759 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.mispredicted 79224651 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 135407901 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predictedNotTakenIncorrect 71572967 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.predictedTakenIncorrect 7651684 # Number of Branches Incorrectly Predicted As Taken. system.cpu.icache.ReadReq_accesses 207004701 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 54777.453839 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53438.372093 # average ReadReq mshr miss latency @@ -160,8 +154,8 @@ system.cpu.icache.demand_mshr_misses 860 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.324416 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 664.403935 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.324416 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 207004701 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 54777.453839 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53438.372093 # average overall mshr miss latency @@ -246,10 +240,10 @@ system.cpu.l2cache.demand_mshr_misses 2697152 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.458476 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.337280 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 15023.339345 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 11052.003329 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.458476 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.337280 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 9112503 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52212.225711 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40035.092201 # average overall mshr miss latency @@ -271,31 +265,37 @@ system.cpu.l2cache.tagsinuse 26075.342674 # Cy system.cpu.l2cache.total_refs 7565242 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 230207194000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 1170923 # number of writebacks +system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed +system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.numCycles 1959902740 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.regfile_manager.regFileAccesses 3178023708 # Number of Total Accesses (Read+Write) to the Register File +system.cpu.regfile_manager.regFileReads 1801820745 # Number of Reads from Register File +system.cpu.regfile_manager.regFileWrites 1376202963 # Number of Writes to Register File +system.cpu.regfile_manager.regForwards 604786987 # Number of Registers Read Through Forwarding Logic system.cpu.runCycles 1456399909 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 902142172 # Number of cycles 0 instructions are processed. -system.cpu.stage-0.runCycles 1057760568 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 53.970054 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 1064240534 # Number of cycles 0 instructions are processed. -system.cpu.stage-1.runCycles 895662206 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 45.699319 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 1036315285 # Number of cycles 0 instructions are processed. -system.cpu.stage-2.runCycles 923587455 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 47.124147 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 1537492347 # Number of cycles 0 instructions are processed. -system.cpu.stage-3.runCycles 422410393 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 21.552620 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 932643705 # Number of cycles 0 instructions are processed. -system.cpu.stage-4.runCycles 1027259035 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 52.413776 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage0.idleCycles 902142172 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1057760568 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 53.970054 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1064240534 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 895662206 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 45.699319 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 1036315285 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 923587455 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 47.124147 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1537492347 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 422410393 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.552620 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 932643705 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1027259035 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 52.413776 # Percentage of cycles stage was utilized (processing insts). system.cpu.threadCycles 1619523667 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.timesIdled 8517352 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 29 # Number of system calls +system.cpu.workload.num_syscalls 29 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index 2659460cd..73cbafb08 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -25,6 +25,8 @@ BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout index 141143bd2..489ef9061 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 17 2011 21:44:37 -M5 started Mar 17 2011 21:44:53 -M5 executing on zizzer +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 12:02:34 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 5851c27dd..bd83aa84a 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 172436 # Simulator instruction rate (inst/s) -host_mem_usage 208600 # Number of bytes of host memory used -host_seconds 10067.76 # Real time elapsed on the host -host_tick_rate 69724149 # Simulator tick rate (ticks/s) +host_inst_rate 279473 # Simulator instruction rate (inst/s) +host_mem_usage 204448 # Number of bytes of host memory used +host_seconds 6211.84 # Real time elapsed on the host +host_tick_rate 113004567 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1736043781 # Number of instructions simulated sim_seconds 0.701966 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 19849428 # Nu system.cpu.BPredUnit.condPredicted 261227143 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 338874509 # Number of BP lookups system.cpu.BPredUnit.usedRAS 23706003 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 214632552 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 64109829 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1311318680 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.387748 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.144873 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 679377178 51.81% 51.81% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 251802247 19.20% 71.01% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 122784402 9.36% 80.37% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 79744679 6.08% 86.46% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 49330681 3.76% 90.22% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 25797964 1.97% 92.18% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 24618038 1.88% 94.06% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 13753662 1.05% 95.11% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 64109829 4.89% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1311318680 # Number of insts commited each cycle -system.cpu.commit.COM:count 1819780126 # Number of instructions committed -system.cpu.commit.COM:fp_insts 805525 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 16767440 # Number of function calls committed. -system.cpu.commit.COM:int_insts 1718967519 # Number of committed integer instructions. -system.cpu.commit.COM:loads 444595663 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 605324165 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 19848912 # The number of times a branch was mispredicted +system.cpu.commit.branches 214632552 # Number of branches committed +system.cpu.commit.bw_lim_events 64109829 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 560481052 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 1311318680 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.387748 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.144873 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 679377178 51.81% 51.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 251802247 19.20% 71.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 122784402 9.36% 80.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 79744679 6.08% 86.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 49330681 3.76% 90.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 25797964 1.97% 92.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24618038 1.88% 94.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 13753662 1.05% 95.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 64109829 4.89% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1311318680 # Number of insts commited each cycle +system.cpu.commit.count 1819780126 # Number of instructions committed +system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. +system.cpu.commit.function_calls 16767440 # Number of function calls committed. +system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. +system.cpu.commit.loads 444595663 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.refs 605324165 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated system.cpu.cpi 0.808697 # CPI: Cycles Per Instruction @@ -106,8 +106,8 @@ system.cpu.dcache.demand_mshr_misses 9161274 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.997370 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4085.228479 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.997370 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 684893373 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 19952.876714 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 12930.225374 # average overall mshr miss latency @@ -129,15 +129,15 @@ system.cpu.dcache.tagsinuse 4085.228479 # Cy system.cpu.dcache.total_refs 670151457 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 7052593000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 3077964 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 69300100 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 734 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 53326576 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 2753583044 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 704925020 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 533426665 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 83930076 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 1732 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 3666895 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 69300100 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 734 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 53326576 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 2753583044 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 704925020 # Number of cycles decode is idle +system.cpu.decode.RunCycles 533426665 # Number of cycles decode is running +system.cpu.decode.SquashCycles 83930076 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 1732 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 3666895 # Number of cycles decode is unblocking system.cpu.dtb.data_accesses 776927298 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 761318004 # DTB hits @@ -217,8 +217,8 @@ system.cpu.icache.demand_mshr_misses 913 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.349808 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 716.407669 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.349808 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 346935606 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 35242.436306 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35438.663746 # average overall mshr miss latency @@ -241,21 +241,13 @@ system.cpu.icache.total_refs 346934350 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 8683896 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 278210520 # Number of branches executed -system.cpu.iew.EXEC:nop 128264130 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.613458 # Inst execution rate -system.cpu.iew.EXEC:refs 776927311 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 203625107 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1505740839 # num instructions consuming a value -system.cpu.iew.WB:count 2224607717 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.814091 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1225810379 # num instructions producing a value -system.cpu.iew.WB:rate 1.584554 # insts written-back per cycle -system.cpu.iew.WB:sent 2246216503 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 21671278 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 278210520 # Number of branches executed +system.cpu.iew.exec_nop 128264130 # number of nop insts executed +system.cpu.iew.exec_rate 1.613458 # Inst execution rate +system.cpu.iew.exec_refs 776927311 # number of memory reference insts executed +system.cpu.iew.exec_stores 203625107 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 12833645 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 610412990 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 45 # Number of dispatched non-speculative instructions @@ -283,103 +275,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 66687540 # system.cpu.iew.memOrderViolationEvents 198174 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 3374280 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 18296998 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1505740839 # num instructions consuming a value +system.cpu.iew.wb_count 2224607717 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.814091 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 1225810379 # num instructions producing a value +system.cpu.iew.wb_rate 1.584554 # insts written-back per cycle +system.cpu.iew.wb_sent 2246216503 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 3052265091 # number of integer regfile reads system.cpu.int_regfile_writes 1775418368 # number of integer regfile writes system.cpu.ipc 1.236558 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.236558 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1511867682 65.65% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 94 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 234 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 19 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 136 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 16 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 24 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 584171534 25.37% 91.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 206823272 8.98% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 2302863011 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 12654324 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.005495 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 2979112 23.54% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 7017383 55.45% 79.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 2657829 21.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 1395248756 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.650504 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.793673 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 526952247 37.77% 37.77% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 258740979 18.54% 56.31% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 229473715 16.45% 72.76% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 137779252 9.87% 82.63% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 109981774 7.88% 90.52% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 76286512 5.47% 95.98% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 43503715 3.12% 99.10% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 10789596 0.77% 99.88% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 1740966 0.12% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 1395248756 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.640295 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1511867682 65.65% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 94 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 234 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 19 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 136 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.65% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 584171534 25.37% 91.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 206823272 8.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 2302863011 # Type of FU issued system.cpu.iq.fp_alu_accesses 821696 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 1643378 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 816998 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 858249 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 12654324 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005495 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2979112 23.54% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 23.54% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7017383 55.45% 79.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2657829 21.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 2314695639 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 6012429707 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 2223790719 # Number of integer instruction queue wakeup accesses @@ -391,6 +373,24 @@ system.cpu.iq.iqSquashedInstsExamined 686898644 # Nu system.cpu.iq.iqSquashedInstsIssued 443983 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 276282436 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 1395248756 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.650504 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.793673 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 526952247 37.77% 37.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 258740979 18.54% 56.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 229473715 16.45% 72.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 137779252 9.87% 82.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 109981774 7.88% 90.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 76286512 5.47% 95.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 43503715 3.12% 99.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10789596 0.77% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1740966 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1395248756 # Number of insts issued each cycle +system.cpu.iq.rate 1.640295 # Inst issue rate system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits @@ -451,10 +451,10 @@ system.cpu.l2cache.demand_mshr_misses 2703837 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.482747 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.327799 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 15818.650272 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 10741.307183 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.482747 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.327799 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 9162188 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34369.172587 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31180.345746 # average overall mshr miss latency @@ -485,28 +485,28 @@ system.cpu.misc_regfile_writes 1 # nu system.cpu.numCycles 1403932652 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 45015493 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 2058465 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 721970868 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 19605286 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 493414 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 3482054752 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 2693944594 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 2019690549 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 519735088 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 83930076 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 24596395 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 643487586 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 875387 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 3481179365 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 836 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 50 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 51588618 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 48 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 45015493 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 2058465 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 721970868 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 19605286 # Number of times rename has blocked due to LSQ full +system.cpu.rename.ROBFullEvents 493414 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 3482054752 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 2693944594 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 2019690549 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 519735088 # Number of cycles rename is running +system.cpu.rename.SquashCycles 83930076 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 24596395 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 643487586 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 875387 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 3481179365 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 836 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 50 # count of serializing insts renamed +system.cpu.rename.skidInsts 51588618 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 48 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 3541690829 # The number of ROB reads system.cpu.rob.rob_writes 4844528665 # The number of ROB writes system.cpu.timesIdled 283673 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 29 # Number of system calls +system.cpu.workload.num_syscalls 29 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout index 56c0d3893..5e9a97c65 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:37 -M5 executing on burrito +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 11:59:33 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt index 7812c0d15..c03fa7e28 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1468260 # Simulator instruction rate (inst/s) -host_mem_usage 218108 # Number of bytes of host memory used -host_seconds 1239.41 # Real time elapsed on the host -host_tick_rate 736791940 # Simulator tick rate (ticks/s) +host_inst_rate 6003103 # Simulator instruction rate (inst/s) +host_mem_usage 195756 # Number of bytes of host memory used +host_seconds 303.14 # Real time elapsed on the host +host_tick_rate 3012433327 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780127 # Number of instructions simulated sim_seconds 0.913189 # Number of seconds simulated @@ -61,6 +61,6 @@ system.cpu.num_int_register_writes 1376202618 # nu system.cpu.num_load_insts 449492741 # Number of load instructions system.cpu.num_mem_refs 611922547 # number of memory refs system.cpu.num_store_insts 162429806 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 29 # Number of system calls +system.cpu.workload.num_syscalls 29 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini index 6d6374beb..6ccdf7868 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini @@ -51,6 +51,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -86,6 +87,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +123,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout index b361f245f..6c70cf5a2 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:37 -M5 executing on burrito +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 11:59:01 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index f893b334a..315c5ad86 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 590383 # Simulator instruction rate (inst/s) -host_mem_usage 225824 # Number of bytes of host memory used -host_seconds 3082.37 # Real time elapsed on the host -host_tick_rate 864089077 # Simulator tick rate (ticks/s) +host_inst_rate 2523486 # Simulator instruction rate (inst/s) +host_mem_usage 203508 # Number of bytes of host memory used +host_seconds 721.14 # Real time elapsed on the host +host_tick_rate 3693391340 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780127 # Number of instructions simulated sim_seconds 2.663444 # Number of seconds simulated @@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses 9111734 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.995973 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4079.504248 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.995973 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 26428.412638 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 23428.412638 # average overall mshr miss latency @@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 802 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.299002 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 612.356766 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.299002 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 1826378510 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -205,10 +205,10 @@ system.cpu.l2cache.demand_mshr_misses 2697097 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.467301 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.327380 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 15312.508302 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 10727.578894 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.467301 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.327380 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 9112536 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -250,6 +250,6 @@ system.cpu.num_int_register_writes 1376202618 # nu system.cpu.num_load_insts 449492741 # Number of load instructions system.cpu.num_mem_refs 611922547 # number of memory refs system.cpu.num_store_insts 162429806 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 29 # Number of system calls +system.cpu.workload.num_syscalls 29 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini index 5d9a2313d..2386e9fa4 100644 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -498,7 +498,7 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/alisai01/dist/cpu2000/binaries/arm/linux/bzip2 +executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout index cc554e99a..dc1adbfd8 100755 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 18:48:59 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 13:21:07 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt index a38ba9b9e..5a7da6a72 100644 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 189685 # Simulator instruction rate (inst/s) -host_mem_usage 258720 # Number of bytes of host memory used -host_seconds 9083.85 # Real time elapsed on the host -host_tick_rate 70772893 # Simulator tick rate (ticks/s) +host_inst_rate 253143 # Simulator instruction rate (inst/s) +host_mem_usage 215164 # Number of bytes of host memory used +host_seconds 6806.72 # Real time elapsed on the host +host_tick_rate 94449374 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1723073854 # Number of instructions simulated sim_seconds 0.642891 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 18005065 # Nu system.cpu.BPredUnit.condPredicted 242843937 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 296310364 # Number of BP lookups system.cpu.BPredUnit.usedRAS 17771313 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 213462366 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 57604302 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1166659925 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.476929 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.106061 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 510754561 43.78% 43.78% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 303447125 26.01% 69.79% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 123940356 10.62% 80.41% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 73811223 6.33% 86.74% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 36743344 3.15% 89.89% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 32005168 2.74% 92.63% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 15998188 1.37% 94.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 12355658 1.06% 95.06% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 57604302 4.94% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1166659925 # Number of insts commited each cycle -system.cpu.commit.COM:count 1723073872 # Number of instructions committed -system.cpu.commit.COM:fp_insts 36 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 13665177 # Number of function calls committed. -system.cpu.commit.COM:int_insts 1536941857 # Number of committed integer instructions. -system.cpu.commit.COM:loads 485926772 # Number of loads committed -system.cpu.commit.COM:membars 62 # Number of memory barriers committed -system.cpu.commit.COM:refs 660773819 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 18004568 # The number of times a branch was mispredicted +system.cpu.commit.branches 213462366 # Number of branches committed +system.cpu.commit.bw_lim_events 57604302 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 1723073872 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 458 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 488146148 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 1166659925 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.476929 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.106061 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 510754561 43.78% 43.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 303447125 26.01% 69.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 123940356 10.62% 80.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 73811223 6.33% 86.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 36743344 3.15% 89.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 32005168 2.74% 92.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15998188 1.37% 94.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 12355658 1.06% 95.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 57604302 4.94% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1166659925 # Number of insts commited each cycle +system.cpu.commit.count 1723073872 # Number of instructions committed +system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. +system.cpu.commit.function_calls 13665177 # Number of function calls committed. +system.cpu.commit.int_insts 1536941857 # Number of committed integer instructions. +system.cpu.commit.loads 485926772 # Number of loads committed +system.cpu.commit.membars 62 # Number of memory barriers committed +system.cpu.commit.refs 660773819 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 1723073854 # Number of Instructions Simulated system.cpu.committedInsts_total 1723073854 # Number of Instructions Simulated system.cpu.cpi 0.746214 # CPI: Cycles Per Instruction @@ -105,8 +105,8 @@ system.cpu.dcache.demand_mshr_misses 9541290 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.997826 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4087.096656 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.997826 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 674170659 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 18251.409094 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 13363.406222 # average overall mshr miss latency @@ -128,15 +128,15 @@ system.cpu.dcache.tagsinuse 4087.096656 # Cy system.cpu.dcache.total_refs 661474732 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 5035189000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 3122149 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 127119222 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 630 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 46145837 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 2344585205 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 578307676 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 449658106 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 70439042 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 2261 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 11574920 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 127119222 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 630 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 46145837 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 2344585205 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 578307676 # Number of cycles decode is idle +system.cpu.decode.RunCycles 449658106 # Number of cycles decode is running +system.cpu.decode.SquashCycles 70439042 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 2261 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 11574920 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -221,8 +221,8 @@ system.cpu.icache.demand_mshr_misses 713 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.281945 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 577.423416 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.281945 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 276394619 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 34658.288770 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 34406.030856 # average overall mshr miss latency @@ -245,21 +245,13 @@ system.cpu.icache.total_refs 276393684 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 48682141 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 233410057 # Number of branches executed -system.cpu.iew.EXEC:nop 371 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.517006 # Inst execution rate -system.cpu.iew.EXEC:refs 747857641 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 187754946 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 2256424150 # num instructions consuming a value -system.cpu.iew.WB:count 1928710637 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.551017 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1243327288 # num instructions producing a value -system.cpu.iew.WB:rate 1.500030 # insts written-back per cycle -system.cpu.iew.WB:sent 1934940770 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 19351943 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 233410057 # Number of branches executed +system.cpu.iew.exec_nop 371 # number of nop insts executed +system.cpu.iew.exec_rate 1.517006 # Inst execution rate +system.cpu.iew.exec_refs 747857641 # number of memory reference insts executed +system.cpu.iew.exec_stores 187754946 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 24201668 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 626078428 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 573 # Number of dispatched non-speculative instructions @@ -287,103 +279,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 50405377 # system.cpu.iew.memOrderViolationEvents 734835 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 3232685 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 16119258 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 2256424150 # num instructions consuming a value +system.cpu.iew.wb_count 1928710637 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.551017 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 1243327288 # num instructions producing a value +system.cpu.iew.wb_rate 1.500030 # insts written-back per cycle +system.cpu.iew.wb_sent 1934940770 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 5040549881 # number of integer regfile reads system.cpu.int_regfile_writes 1533135927 # number of integer regfile writes system.cpu.ipc 1.340099 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.340099 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1212590834 61.50% 61.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 1140241 0.06% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 6 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 1 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 7 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 568540639 28.84% 90.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 189395216 9.61% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 1971666946 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 20875026 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.010588 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 491210 2.35% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 2 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 19087912 91.44% 93.79% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 1295902 6.21% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 1237098966 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.593783 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.635374 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 418606363 33.84% 33.84% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 277983689 22.47% 56.31% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 220653980 17.84% 74.14% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 149807025 12.11% 86.25% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 89527255 7.24% 93.49% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 51723580 4.18% 97.67% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 17902939 1.45% 99.12% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 8343412 0.67% 99.79% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 2550723 0.21% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 1237098966 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.533439 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1212590834 61.50% 61.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1140241 0.06% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 6 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 568540639 28.84% 90.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 189395216 9.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1971666946 # Type of FU issued system.cpu.iq.fp_alu_accesses 63 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 120 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 51 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 94 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 20875026 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010588 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 491210 2.35% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 19087912 91.44% 93.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1295902 6.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 1992541909 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 5201971393 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 1928710586 # Number of integer instruction queue wakeup accesses @@ -395,6 +377,24 @@ system.cpu.iq.iqSquashedInstsExamined 484979968 # Nu system.cpu.iq.iqSquashedInstsIssued 663629 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 179 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 843902514 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 1237098966 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.593783 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.635374 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 418606363 33.84% 33.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 277983689 22.47% 56.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 220653980 17.84% 74.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 149807025 12.11% 86.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 89527255 7.24% 93.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 51723580 4.18% 97.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 17902939 1.45% 99.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 8343412 0.67% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2550723 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1237098966 # Number of insts issued each cycle +system.cpu.iq.rate 1.533439 # Inst issue rate system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -461,10 +461,10 @@ system.cpu.l2cache.demand_mshr_misses 2931748 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.487988 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.329914 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 15990.396178 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 10810.627507 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.487988 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.329914 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 9542003 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34375.299564 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31194.683001 # average overall mshr miss latency @@ -495,28 +495,28 @@ system.cpu.misc_regfile_writes 128 # nu system.cpu.numCycles 1285781107 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 67172415 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 1360917377 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 14851346 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 600335413 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 40774846 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 10242 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 6331353991 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 2292668273 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 1803116545 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 438383597 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 70439042 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 60752889 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 442199165 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 393 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 6331353598 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 15610 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 650 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 118137729 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 645 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 67172415 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1360917377 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 14851346 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 600335413 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 40774846 # Number of times rename has blocked due to LSQ full +system.cpu.rename.ROBFullEvents 10242 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 6331353991 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 2292668273 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1803116545 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 438383597 # Number of cycles rename is running +system.cpu.rename.SquashCycles 70439042 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 60752889 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 442199165 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 393 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 6331353598 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 15610 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 650 # count of serializing insts renamed +system.cpu.rename.skidInsts 118137729 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 645 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 3320275044 # The number of ROB reads system.cpu.rob.rob_writes 4492885352 # The number of ROB writes system.cpu.timesIdled 1544733 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 46 # Number of system calls +system.cpu.workload.num_syscalls 46 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini index b27b25e6d..8d90d74d0 100644 --- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini @@ -61,12 +61,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2 +executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout index d37b6d85d..4e09f0c47 100755 --- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout +++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 18:50:12 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 13:22:49 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index 0c882577d..bd13defc5 100644 --- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1075067 # Simulator instruction rate (inst/s) -host_mem_usage 247128 # Number of bytes of host memory used -host_seconds 1602.76 # Real time elapsed on the host -host_tick_rate 537533999 # Simulator tick rate (ticks/s) +host_inst_rate 4004296 # Simulator instruction rate (inst/s) +host_mem_usage 206252 # Number of bytes of host memory used +host_seconds 430.31 # Real time elapsed on the host +host_tick_rate 2002150173 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1723073862 # Number of instructions simulated sim_seconds 0.861538 # Number of seconds simulated @@ -71,6 +71,6 @@ system.cpu.num_int_register_writes 1329729952 # nu system.cpu.num_load_insts 485926770 # Number of load instructions system.cpu.num_mem_refs 660773816 # number of memory refs system.cpu.num_store_insts 174847046 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 46 # Number of system calls +system.cpu.workload.num_syscalls 46 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini index b26c9b5f5..00bc540f8 100644 --- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini @@ -164,12 +164,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing +cwd=build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2 +executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout index 50181b6ce..88386aeb5 100755 --- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout +++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 19:14:16 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 13:25:15 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt index b09cdeb30..1dcb25e1c 100644 --- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 536583 # Simulator instruction rate (inst/s) -host_mem_usage 254860 # Number of bytes of host memory used -host_seconds 3200.38 # Real time elapsed on the host -host_tick_rate 759728459 # Simulator tick rate (ticks/s) +host_inst_rate 2103726 # Simulator instruction rate (inst/s) +host_mem_usage 213996 # Number of bytes of host memory used +host_seconds 816.30 # Real time elapsed on the host +host_tick_rate 2978588238 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1717270343 # Number of instructions simulated sim_seconds 2.431420 # Number of seconds simulated @@ -54,8 +54,8 @@ system.cpu.dcache.demand_mshr_misses 9115236 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.997002 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4083.719979 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.997002 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 654970174 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 26435.424162 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 23435.424162 # average overall mshr miss latency @@ -130,8 +130,8 @@ system.cpu.icache.demand_mshr_misses 638 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.251403 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 514.872896 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.251403 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 1544565599 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 54551.724138 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 51551.724138 # average overall mshr miss latency @@ -219,10 +219,10 @@ system.cpu.l2cache.demand_mshr_misses 2699469 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.458607 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.338956 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 15027.621217 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 11106.896016 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.458607 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.338956 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 9115874 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -264,6 +264,6 @@ system.cpu.num_int_register_writes 1329729952 # nu system.cpu.num_load_insts 485926770 # Number of load instructions system.cpu.num_mem_refs 660773816 # number of memory refs system.cpu.num_store_insts 174847046 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 46 # Number of system calls +system.cpu.workload.num_syscalls 46 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout index 403cb4d0b..fd345ce8f 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 8 2011 00:58:32 -M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip -M5 started Feb 8 2011 00:58:34 -M5 executing on burrito +M5 compiled Apr 19 2011 12:22:33 +M5 started Apr 19 2011 12:22:46 +M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index 9e70ccdd1..3863ba265 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2540540 # Simulator instruction rate (inst/s) -host_mem_usage 223860 # Number of bytes of host memory used -host_seconds 1844.83 # Real time elapsed on the host -host_tick_rate 1542694185 # Simulator tick rate (ticks/s) +host_inst_rate 2952357 # Simulator instruction rate (inst/s) +host_mem_usage 202444 # Number of bytes of host memory used +host_seconds 1587.50 # Real time elapsed on the host +host_tick_rate 1792761763 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4686862651 # Number of instructions simulated sim_seconds 2.846007 # Number of seconds simulated @@ -29,6 +29,6 @@ system.cpu.num_int_register_writes 4679057393 # nu system.cpu.num_load_insts 1239184749 # Number of load instructions system.cpu.num_mem_refs 1677713086 # number of memory refs system.cpu.num_store_insts 438528337 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 46 # Number of system calls +system.cpu.workload.num_syscalls 46 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini index a92ea4a1d..c75881c3f 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini @@ -51,6 +51,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -86,6 +87,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +123,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout index 65c0a8840..60300fa55 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 8 2011 00:58:32 -M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip -M5 started Feb 8 2011 00:58:34 -M5 executing on burrito +M5 compiled Apr 19 2011 12:22:33 +M5 started Apr 19 2011 12:36:40 +M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 59534c87e..e9ae83f48 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1546064 # Simulator instruction rate (inst/s) -host_mem_usage 231584 # Number of bytes of host memory used -host_seconds 3031.48 # Real time elapsed on the host -host_tick_rate 1954011316 # Simulator tick rate (ticks/s) +host_inst_rate 1878760 # Simulator instruction rate (inst/s) +host_mem_usage 210192 # Number of bytes of host memory used +host_seconds 2494.66 # Real time elapsed on the host +host_tick_rate 2374493636 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4686862651 # Number of instructions simulated sim_seconds 5.923548 # Number of seconds simulated @@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses 9112677 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.997232 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4084.662246 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.997232 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 1677713086 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 26521.034159 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 23521.034159 # average overall mshr miss latency @@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses 675 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.271344 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 555.713137 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.271344 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 4013232927 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -173,10 +173,10 @@ system.cpu.l2cache.demand_mshr_misses 2717345 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.472376 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.336564 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 15478.805498 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 11028.544571 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.472376 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.336564 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 9113352 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -218,6 +218,6 @@ system.cpu.num_int_register_writes 4679057393 # nu system.cpu.num_load_insts 1239184749 # Number of load instructions system.cpu.num_mem_refs 1677713086 # number of memory refs system.cpu.num_store_insts 438528337 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 46 # Number of system calls +system.cpu.workload.num_syscalls 46 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini index 8ab14c5fa..84850f694 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini @@ -86,6 +86,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +122,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -156,6 +158,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout index d80de6314..21f9ae246 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 18 2011 15:40:30 -M5 revision Unknown -M5 started Feb 18 2011 19:04:15 -M5 executing on m55-001.pool +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 12:01:01 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sav Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2 diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index b78683303..53d449590 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,37 +1,25 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 137731 # Simulator instruction rate (inst/s) -host_mem_usage 254052 # Number of bytes of host memory used -host_seconds 667.27 # Real time elapsed on the host -host_tick_rate 60742348 # Simulator tick rate (ticks/s) +host_inst_rate 197293 # Simulator instruction rate (inst/s) +host_mem_usage 267004 # Number of bytes of host memory used +host_seconds 465.82 # Real time elapsed on the host +host_tick_rate 87010339 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated sim_seconds 0.040531 # Number of seconds simulated sim_ticks 40531279000 # Number of ticks simulated -system.cpu.AGEN-Unit.agens 27308571 # Number of Address Generations -system.cpu.Branch-Predictor.BTBHitPct 59.146483 # BTB Hit Percentage -system.cpu.Branch-Predictor.BTBHits 4489525 # Number of BTB hits -system.cpu.Branch-Predictor.BTBLookups 7590519 # Number of BTB lookups -system.cpu.Branch-Predictor.RASInCorrect 138 # Number of incorrect RAS predictions. -system.cpu.Branch-Predictor.condIncorrect 2806970 # Number of conditional branches incorrect -system.cpu.Branch-Predictor.condPredicted 7883251 # Number of conditional branches predicted -system.cpu.Branch-Predictor.lookups 11539980 # Number of BP lookups -system.cpu.Branch-Predictor.predictedNotTaken 4913265 # Number of Branches Predicted As Not Taken (False). -system.cpu.Branch-Predictor.predictedTaken 6626715 # Number of Branches Predicted As Taken (True). -system.cpu.Branch-Predictor.usedRAS 1029619 # Number of times the RAS was used to get a target. -system.cpu.Execution-Unit.executions 57928840 # Number of Instructions Executed. -system.cpu.Execution-Unit.mispredictPct 27.409983 # Percentage of Incorrect Branches Predicts -system.cpu.Execution-Unit.mispredicted 2806970 # Number of Branches Incorrectly Predicted -system.cpu.Execution-Unit.predicted 7433715 # Number of Branches Incorrectly Predicted -system.cpu.Execution-Unit.predictedNotTakenIncorrect 1384945 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.Execution-Unit.predictedTakenIncorrect 1422025 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed -system.cpu.Mult-Div-Unit.multiplies 458252 # Number of Multipy Operations Executed -system.cpu.RegFile-Manager.regFileAccesses 152685930 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.RegFile-Manager.regFileReads 84258569 # Number of Reads from Register File -system.cpu.RegFile-Manager.regFileWrites 68427361 # Number of Writes to Register File -system.cpu.RegFile-Manager.regForwards 38185928 # Number of Registers Read Through Forwarding Logic system.cpu.activity 91.670040 # Percentage of cycles cpu is active +system.cpu.agen_unit.agens 27308571 # Number of Address Generations +system.cpu.branch_predictor.BTBHitPct 59.146483 # BTB Hit Percentage +system.cpu.branch_predictor.BTBHits 4489525 # Number of BTB hits +system.cpu.branch_predictor.BTBLookups 7590519 # Number of BTB lookups +system.cpu.branch_predictor.RASInCorrect 138 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.condIncorrect 2806970 # Number of conditional branches incorrect +system.cpu.branch_predictor.condPredicted 7883251 # Number of conditional branches predicted +system.cpu.branch_predictor.lookups 11539980 # Number of BP lookups +system.cpu.branch_predictor.predictedNotTaken 4913265 # Number of Branches Predicted As Not Taken (False). +system.cpu.branch_predictor.predictedTaken 6626715 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target. system.cpu.comBranches 10240685 # Number of Branches instructions committed system.cpu.comFloats 3775974 # Number of Floating Point instructions committed system.cpu.comInts 43665352 # Number of Integer instructions committed @@ -88,8 +76,8 @@ system.cpu.dcache.demand_mshr_misses 2223 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.351931 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 1441.508051 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.351931 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 55469.292673 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 51941.745389 # average overall mshr miss latency @@ -127,6 +115,12 @@ system.cpu.dtb.write_accesses 6501126 # DT system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_hits 6501103 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses +system.cpu.execution_unit.executions 57928840 # Number of Instructions Executed. +system.cpu.execution_unit.mispredictPct 27.409983 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.mispredicted 2806970 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 7433715 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predictedNotTakenIncorrect 1384945 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.predictedTakenIncorrect 1422025 # Number of Branches Incorrectly Predicted As Taken. system.cpu.icache.ReadReq_accesses 9759564 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 26779.967317 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 23139.993880 # average ReadReq mshr miss latency @@ -160,8 +154,8 @@ system.cpu.icache.demand_mshr_misses 9804 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.729171 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1493.341252 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.729171 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 9759564 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 26779.967317 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 23139.993880 # average overall mshr miss latency @@ -246,10 +240,10 @@ system.cpu.l2cache.demand_mshr_misses 4938 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.066327 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.000542 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 2173.408531 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 17.762817 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.066327 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000542 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 12027 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52334.244633 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40121.709194 # average overall mshr miss latency @@ -271,31 +265,37 @@ system.cpu.l2cache.tagsinuse 2191.171348 # Cy system.cpu.l2cache.total_refs 7072 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed +system.cpu.mult_div_unit.multiplies 458252 # Number of Multipy Operations Executed system.cpu.numCycles 81062559 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.regfile_manager.regFileAccesses 152685930 # Number of Total Accesses (Read+Write) to the Register File +system.cpu.regfile_manager.regFileReads 84258569 # Number of Reads from Register File +system.cpu.regfile_manager.regFileWrites 68427361 # Number of Writes to Register File +system.cpu.regfile_manager.regForwards 38185928 # Number of Registers Read Through Forwarding Logic system.cpu.runCycles 74310080 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 27951091 # Number of cycles 0 instructions are processed. -system.cpu.stage-0.runCycles 53111468 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 65.519111 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 33262621 # Number of cycles 0 instructions are processed. -system.cpu.stage-1.runCycles 47799938 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 58.966727 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 32674404 # Number of cycles 0 instructions are processed. -system.cpu.stage-2.runCycles 48388155 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 59.692361 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 63236282 # Number of cycles 0 instructions are processed. -system.cpu.stage-3.runCycles 17826277 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 21.990765 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 26883065 # Number of cycles 0 instructions are processed. -system.cpu.stage-4.runCycles 54179494 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 66.836644 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage0.idleCycles 27951091 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 53111468 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 65.519111 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 33262621 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 47799938 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 58.966727 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 32674404 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 48388155 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 59.692361 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 63236282 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 17826277 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.990765 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 26883065 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 54179494 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 66.836644 # Percentage of cycles stage was utilized (processing insts). system.cpu.threadCycles 80607865 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.timesIdled 10786 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 389 # Number of system calls +system.cpu.workload.num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 0fa57e7b8..9d0ac975a 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -25,6 +25,8 @@ BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout index c1340f659..ec6c3f639 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -5,10 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 17 2011 21:44:37 -M5 started Mar 17 2011 21:44:40 -M5 executing on zizzer +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 11:58:35 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index c969dd1c3..8dc1a35af 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 141441 # Simulator instruction rate (inst/s) -host_mem_usage 212592 # Number of bytes of host memory used -host_seconds 595.16 # Real time elapsed on the host -host_tick_rate 57448767 # Simulator tick rate (ticks/s) +host_inst_rate 274016 # Simulator instruction rate (inst/s) +host_mem_usage 208580 # Number of bytes of host memory used +host_seconds 307.21 # Real time elapsed on the host +host_tick_rate 111296260 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 84179709 # Number of instructions simulated sim_seconds 0.034191 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 1952481 # Nu system.cpu.BPredUnit.condPredicted 13040695 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 17634633 # Number of BP lookups system.cpu.BPredUnit.usedRAS 1674129 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 10240685 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 3636559 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 62672395 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.466404 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.205429 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 30204906 48.19% 48.19% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 13903993 22.19% 70.38% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 6182558 9.86% 80.24% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 3801476 6.07% 86.31% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 2048830 3.27% 89.58% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 1270161 2.03% 91.61% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 776463 1.24% 92.85% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 847449 1.35% 94.20% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 3636559 5.80% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 62672395 # Number of insts commited each cycle -system.cpu.commit.COM:count 91903055 # Number of instructions committed -system.cpu.commit.COM:fp_insts 6862061 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 1029620 # Number of function calls committed. -system.cpu.commit.COM:int_insts 79581076 # Number of committed integer instructions. -system.cpu.commit.COM:loads 19996198 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 26497301 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 1939282 # The number of times a branch was mispredicted +system.cpu.commit.branches 10240685 # Number of branches committed +system.cpu.commit.bw_lim_events 3636559 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 35667755 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 62672395 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.466404 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.205429 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 30204906 48.19% 48.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13903993 22.19% 70.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 6182558 9.86% 80.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3801476 6.07% 86.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2048830 3.27% 89.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1270161 2.03% 91.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 776463 1.24% 92.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 847449 1.35% 94.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3636559 5.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 62672395 # Number of insts commited each cycle +system.cpu.commit.count 91903055 # Number of instructions committed +system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. +system.cpu.commit.function_calls 1029620 # Number of function calls committed. +system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. +system.cpu.commit.loads 19996198 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.refs 26497301 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated system.cpu.cpi 0.812335 # CPI: Cycles Per Instruction @@ -98,8 +98,8 @@ system.cpu.dcache.demand_mshr_misses 2243 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.356334 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 1459.544584 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.356334 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 30021191 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 34866.834452 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 34674.765938 # average overall mshr miss latency @@ -121,15 +121,15 @@ system.cpu.dcache.tagsinuse 1459.544584 # Cy system.cpu.dcache.total_refs 30012261 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 109 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 838288 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 13474 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 2813146 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 143267385 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 35496040 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 26313036 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 5601227 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 49112 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 25031 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 838288 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 13474 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 2813146 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 143267385 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 35496040 # Number of cycles decode is idle +system.cpu.decode.RunCycles 26313036 # Number of cycles decode is running +system.cpu.decode.SquashCycles 5601227 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 49112 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 25031 # Number of cycles decode is unblocking system.cpu.dtb.data_accesses 32239873 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 31883201 # DTB hits @@ -209,8 +209,8 @@ system.cpu.icache.demand_mshr_misses 10134 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.755537 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1547.340406 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.755537 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 17397269 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 15677.629201 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 11875.370041 # average overall mshr miss latency @@ -233,21 +233,13 @@ system.cpu.icache.total_refs 17386201 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 108531 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 12448390 # Number of branches executed -system.cpu.iew.EXEC:nop 11194543 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.455255 # Inst execution rate -system.cpu.iew.EXEC:refs 32240280 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 7278167 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 87558338 # num instructions consuming a value -system.cpu.iew.WB:count 97422402 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.737743 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 64595544 # num instructions producing a value -system.cpu.iew.WB:rate 1.424676 # insts written-back per cycle -system.cpu.iew.WB:sent 98290476 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 2083154 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 12448390 # Number of branches executed +system.cpu.iew.exec_nop 11194543 # number of nop insts executed +system.cpu.iew.exec_rate 1.455255 # Inst execution rate +system.cpu.iew.exec_refs 32240280 # number of memory reference insts executed +system.cpu.iew.exec_stores 7278167 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 54226 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 28836221 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 434 # Number of dispatched non-speculative instructions @@ -275,103 +267,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 2710213 # system.cpu.iew.memOrderViolationEvents 361752 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 455682 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 1627472 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 87558338 # num instructions consuming a value +system.cpu.iew.wb_count 97422402 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.737743 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 64595544 # num instructions producing a value +system.cpu.iew.wb_rate 1.424676 # insts written-back per cycle +system.cpu.iew.wb_sent 98290476 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 134796814 # number of integer regfile reads system.cpu.int_regfile_writes 73485618 # number of integer regfile writes system.cpu.ipc 1.231019 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.231019 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 61903709 60.72% 60.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 478641 0.47% 61.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 61.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2776827 2.72% 63.91% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 114478 0.11% 64.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2390013 2.34% 66.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 305170 0.30% 66.66% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 758780 0.74% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 320 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 25831010 25.34% 92.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 7397506 7.26% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 101956461 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 1618550 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.015875 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 211558 13.07% 13.07% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 13.07% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 13.07% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 411 0.03% 13.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 13.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 13.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 1262 0.08% 13.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 831302 51.36% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 469173 28.99% 93.52% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 104844 6.48% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 68273622 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.493351 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.698376 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 26699327 39.11% 39.11% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 15011311 21.99% 61.09% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 10325819 15.12% 76.22% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 6572668 9.63% 85.84% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 4677869 6.85% 92.70% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 2930251 4.29% 96.99% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 1292691 1.89% 98.88% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 652857 0.96% 99.84% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 110829 0.16% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 68273622 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.490981 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 61903709 60.72% 60.72% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 478641 0.47% 61.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2776827 2.72% 63.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 114478 0.11% 64.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2390013 2.34% 66.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 305170 0.30% 66.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 758780 0.74% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 320 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25831010 25.34% 92.74% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7397506 7.26% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 101956461 # Type of FU issued system.cpu.iq.fp_alu_accesses 7926911 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 15016184 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 7008699 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 8486129 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 1618550 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.015875 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 211558 13.07% 13.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 13.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 13.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 411 0.03% 13.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 1262 0.08% 13.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 831302 51.36% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.54% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 469173 28.99% 93.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 104844 6.48% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 95648093 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 258930448 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 90413703 # Number of integer instruction queue wakeup accesses @@ -383,6 +365,24 @@ system.cpu.iq.iqSquashedInstsExamined 30709271 # Nu system.cpu.iq.iqSquashedInstsIssued 141538 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 24277340 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 68273622 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.493351 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.698376 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 26699327 39.11% 39.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15011311 21.99% 61.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10325819 15.12% 76.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6572668 9.63% 85.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4677869 6.85% 92.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2930251 4.29% 96.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1292691 1.89% 98.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 652857 0.96% 99.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 110829 0.16% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 68273622 # Number of insts issued each cycle +system.cpu.iq.rate 1.490981 # Inst issue rate system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits @@ -443,10 +443,10 @@ system.cpu.l2cache.demand_mshr_misses 5098 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.070076 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.000540 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 2296.266103 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 17.691689 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.070076 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000540 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 12377 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34375.147117 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31211.357395 # average overall mshr miss latency @@ -477,27 +477,27 @@ system.cpu.misc_regfile_writes 1 # nu system.cpu.numCycles 68382153 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 332303 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 66062 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 36404617 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 424450 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 178909439 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 138778599 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 101591818 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 25415273 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 5601227 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 515125 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 33164457 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 9732280 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 169177159 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 5077 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 469 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 1208043 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 457 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 332303 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 66062 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 36404617 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 424450 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenameLookups 178909439 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 138778599 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 101591818 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 25415273 # Number of cycles rename is running +system.cpu.rename.SquashCycles 5601227 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 515125 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 33164457 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 9732280 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 169177159 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 5077 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 469 # count of serializing insts renamed +system.cpu.rename.skidInsts 1208043 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 457 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 186605606 # The number of ROB reads system.cpu.rob.rob_writes 260771760 # The number of ROB writes system.cpu.timesIdled 2331 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 389 # Number of system calls +system.cpu.workload.num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout index 06628f244..8a2d657fe 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:38 -M5 executing on burrito +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 12:02:07 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sav Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sv2 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt index 3667c8fef..17088cdf6 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1609489 # Simulator instruction rate (inst/s) -host_mem_usage 222008 # Number of bytes of host memory used -host_seconds 57.10 # Real time elapsed on the host -host_tick_rate 804741446 # Simulator tick rate (ticks/s) +host_inst_rate 5556970 # Simulator instruction rate (inst/s) +host_mem_usage 199664 # Number of bytes of host memory used +host_seconds 16.54 # Real time elapsed on the host +host_tick_rate 2778455792 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated sim_seconds 0.045952 # Number of seconds simulated @@ -61,6 +61,6 @@ system.cpu.num_int_register_writes 62575473 # nu system.cpu.num_load_insts 19996208 # Number of load instructions system.cpu.num_mem_refs 26497334 # number of memory refs system.cpu.num_store_insts 6501126 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 389 # Number of system calls +system.cpu.workload.num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini index cab9a523d..f2a594baf 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -51,6 +51,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -86,6 +87,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +123,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout index 5503045c3..c82977f3d 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:48 -M5 executing on burrito +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 12:05:08 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sav Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sv2 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index 2aaa18b18..ea7e649f7 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 559604 # Simulator instruction rate (inst/s) -host_mem_usage 229724 # Number of bytes of host memory used -host_seconds 164.23 # Real time elapsed on the host -host_tick_rate 723015392 # Simulator tick rate (ticks/s) +host_inst_rate 2623121 # Simulator instruction rate (inst/s) +host_mem_usage 207408 # Number of bytes of host memory used +host_seconds 35.04 # Real time elapsed on the host +host_tick_rate 3389091421 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated sim_seconds 0.118740 # Number of seconds simulated @@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses 2223 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.352058 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 1442.028823 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.352058 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 54507.422402 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 51507.422402 # average overall mshr miss latency @@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 8510 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.692401 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1418.037996 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.692401 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 91903090 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 26935.605170 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency @@ -205,10 +205,10 @@ system.cpu.l2cache.demand_mshr_misses 4765 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.062752 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.000543 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 2056.253411 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 17.795183 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.062752 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000543 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 10733 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -250,6 +250,6 @@ system.cpu.num_int_register_writes 62575473 # nu system.cpu.num_load_insts 19996208 # Number of load instructions system.cpu.num_mem_refs 26497334 # number of memory refs system.cpu.num_store_insts 6501126 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 389 # Number of system calls +system.cpu.workload.num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini index 0db8749b7..6ac40b8d3 100644 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -498,7 +498,7 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/alisai01/dist/cpu2000/binaries/arm/linux/twolf +executable=/dist/m5/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout index 0ed791575..573beb25f 100755 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout @@ -5,10 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 19:17:05 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 13:27:04 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing +Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing/smred.sav +Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt index cc80406fa..cc9da8f96 100644 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 145657 # Simulator instruction rate (inst/s) -host_mem_usage 262540 # Number of bytes of host memory used -host_seconds 1295.30 # Real time elapsed on the host -host_tick_rate 97115047 # Simulator tick rate (ticks/s) +host_inst_rate 180598 # Simulator instruction rate (inst/s) +host_mem_usage 218960 # Number of bytes of host memory used +host_seconds 1044.69 # Real time elapsed on the host +host_tick_rate 120412102 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 188669132 # Number of instructions simulated sim_seconds 0.125793 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 9866046 # Nu system.cpu.BPredUnit.condPredicted 86389460 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 110931092 # Number of BP lookups system.cpu.BPredUnit.usedRAS 4559844 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 40284207 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 1785335 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 224388172 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.840880 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.269231 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 118836869 52.96% 52.96% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 58355167 26.01% 78.97% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 31951737 14.24% 93.21% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 7144506 3.18% 96.39% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 2914461 1.30% 97.69% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 1962763 0.87% 98.56% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 824316 0.37% 98.93% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 613018 0.27% 99.20% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 1785335 0.80% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 224388172 # Number of insts commited each cycle -system.cpu.commit.COM:count 188683520 # Number of instructions committed -system.cpu.commit.COM:fp_insts 1752310 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 1848934 # Number of function calls committed. -system.cpu.commit.COM:int_insts 150271150 # Number of committed integer instructions. -system.cpu.commit.COM:loads 29852009 # Number of loads committed -system.cpu.commit.COM:membars 22408 # Number of memory barriers committed -system.cpu.commit.COM:refs 42499167 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 9726959 # The number of times a branch was mispredicted +system.cpu.commit.branches 40284207 # Number of branches committed +system.cpu.commit.bw_lim_events 1785335 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 188683520 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 1635919 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 179794570 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 224388172 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.840880 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.269231 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 118836869 52.96% 52.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 58355167 26.01% 78.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 31951737 14.24% 93.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7144506 3.18% 96.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2914461 1.30% 97.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1962763 0.87% 98.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 824316 0.37% 98.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 613018 0.27% 99.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1785335 0.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 224388172 # Number of insts commited each cycle +system.cpu.commit.count 188683520 # Number of instructions committed +system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. +system.cpu.commit.function_calls 1848934 # Number of function calls committed. +system.cpu.commit.int_insts 150271150 # Number of committed integer instructions. +system.cpu.commit.loads 29852009 # Number of loads committed +system.cpu.commit.membars 22408 # Number of memory barriers committed +system.cpu.commit.refs 42499167 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 188669132 # Number of Instructions Simulated system.cpu.committedInsts_total 188669132 # Number of Instructions Simulated system.cpu.cpi 1.333479 # CPI: Cycles Per Instruction @@ -105,8 +105,8 @@ system.cpu.dcache.demand_mshr_misses 1827 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.338856 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 1387.955871 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.338856 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 50846441 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 31573.330399 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 33963.054187 # average overall mshr miss latency @@ -128,15 +128,15 @@ system.cpu.dcache.tagsinuse 1387.955871 # Cy system.cpu.dcache.total_refs 50888924 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 16 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 36464777 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 170249 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 17878904 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 446600367 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 82272510 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 104826667 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 27129630 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 707147 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 824217 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 36464777 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 170249 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 17878904 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 446600367 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 82272510 # Number of cycles decode is idle +system.cpu.decode.RunCycles 104826667 # Number of cycles decode is running +system.cpu.decode.SquashCycles 27129630 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 707147 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 824217 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -221,8 +221,8 @@ system.cpu.icache.demand_mshr_misses 3509 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.620491 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1270.764699 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.620491 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 38679890 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 23669.425633 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 20344.827586 # average overall mshr miss latency @@ -245,21 +245,13 @@ system.cpu.icache.total_refs 38675903 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 68606 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 53273558 # Number of branches executed -system.cpu.iew.EXEC:nop 53064 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.964190 # Inst execution rate -system.cpu.iew.EXEC:refs 53783248 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 13613267 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 284801843 # num instructions consuming a value -system.cpu.iew.WB:count 238885590 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.499623 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 142293577 # num instructions producing a value -system.cpu.iew.WB:rate 0.949517 # insts written-back per cycle -system.cpu.iew.WB:sent 240138833 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 11160275 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 53273558 # Number of branches executed +system.cpu.iew.exec_nop 53064 # number of nop insts executed +system.cpu.iew.exec_rate 0.964190 # Inst execution rate +system.cpu.iew.exec_refs 53783248 # number of memory reference insts executed +system.cpu.iew.exec_stores 13613267 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 19997 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 50338304 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 2241625 # Number of dispatched non-speculative instructions @@ -287,103 +279,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 5462392 # system.cpu.iew.memOrderViolationEvents 222499 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 2295597 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 8864678 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 284801843 # num instructions consuming a value +system.cpu.iew.wb_count 238885590 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.499623 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 142293577 # num instructions producing a value +system.cpu.iew.wb_rate 0.949517 # insts written-back per cycle +system.cpu.iew.wb_sent 240138833 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 542109498 # number of integer regfile reads system.cpu.int_regfile_writes 231159216 # number of integer regfile writes system.cpu.ipc 0.749918 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.749918 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 192549438 76.89% 76.89% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 913605 0.36% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 7231 0.00% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 32771 0.01% 77.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 77.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 160968 0.06% 77.34% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 255770 0.10% 77.44% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 76475 0.03% 77.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 457524 0.18% 77.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 202683 0.08% 77.73% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 71630 0.03% 77.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 325 0.00% 77.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 41871023 16.72% 94.48% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 13821469 5.52% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 250420912 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 1580075 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.006310 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 55 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 5520 0.35% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 1266721 80.17% 80.52% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 307779 19.48% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 251517801 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.995639 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.196239 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 114687732 45.60% 45.60% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 66176551 26.31% 71.91% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 44052792 17.51% 89.42% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 15274317 6.07% 95.50% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 7530457 2.99% 98.49% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 2838961 1.13% 99.62% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 766561 0.30% 99.92% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 123613 0.05% 99.97% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 66817 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 251517801 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.995367 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 192549438 76.89% 76.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 913605 0.36% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 7231 0.00% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 77.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 32771 0.01% 77.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 77.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 160968 0.06% 77.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 255770 0.10% 77.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76475 0.03% 77.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 457524 0.18% 77.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 202683 0.08% 77.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71630 0.03% 77.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 325 0.00% 77.76% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 41871023 16.72% 94.48% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13821469 5.52% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 250420912 # Type of FU issued system.cpu.iq.fp_alu_accesses 1881090 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 3742288 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 1821838 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 2251906 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 1580075 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006310 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 55 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5520 0.35% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1266721 80.17% 80.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 307779 19.48% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 250119897 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 750424252 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 237063752 # Number of integer instruction queue wakeup accesses @@ -395,6 +377,24 @@ system.cpu.iq.iqSquashedInstsExamined 177594377 # Nu system.cpu.iq.iqSquashedInstsIssued 226843 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 629835 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 280770553 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 251517801 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.995639 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.196239 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 114687732 45.60% 45.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 66176551 26.31% 71.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 44052792 17.51% 89.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 15274317 6.07% 95.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 7530457 2.99% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2838961 1.13% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 766561 0.30% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 123613 0.05% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 66817 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 251517801 # Number of insts issued each cycle +system.cpu.iq.rate 0.995367 # Inst issue rate system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -461,10 +461,10 @@ system.cpu.l2cache.demand_mshr_misses 3652 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.055915 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.000092 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 1832.230344 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 3.029186 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.055915 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000092 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 5336 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34289.940022 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31059.967141 # average overall mshr miss latency @@ -495,27 +495,27 @@ system.cpu.misc_regfile_writes 825084 # nu system.cpu.numCycles 251586407 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 895052 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 180981200 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 614225 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 90974405 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2116730 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 956098353 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 414819410 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 416850208 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 96863032 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 27129630 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 5258013 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 235869004 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 13790121 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 942308232 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 30397669 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 2658319 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 23659926 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 2454002 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 895052 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 180981200 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 614225 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 90974405 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 2116730 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenameLookups 956098353 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 414819410 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 416850208 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 96863032 # Number of cycles rename is running +system.cpu.rename.SquashCycles 27129630 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 5258013 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 235869004 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 13790121 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 942308232 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 30397669 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 2658319 # count of serializing insts renamed +system.cpu.rename.skidInsts 23659926 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 2454002 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 591075726 # The number of ROB reads system.cpu.rob.rob_writes 764090765 # The number of ROB writes system.cpu.timesIdled 1409 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 400 # Number of system calls +system.cpu.workload.num_syscalls 400 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini index d713880d3..283406dc2 100644 --- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini @@ -61,12 +61,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/twolf +executable=/dist/m5/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout index 8b4af0675..03f12e59d 100755 --- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout +++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout @@ -5,10 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 19:22:24 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 13:30:09 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic +Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic/smred.sav +Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt index bbc7121bd..bdd5452bf 100644 --- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1042149 # Simulator instruction rate (inst/s) -host_mem_usage 250372 # Number of bytes of host memory used -host_seconds 181.04 # Real time elapsed on the host -host_tick_rate 569523249 # Simulator tick rate (ticks/s) +host_inst_rate 3821612 # Simulator instruction rate (inst/s) +host_mem_usage 209488 # Number of bytes of host memory used +host_seconds 49.37 # Real time elapsed on the host +host_tick_rate 2088466357 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 188670900 # Number of instructions simulated sim_seconds 0.103107 # Number of seconds simulated @@ -71,6 +71,6 @@ system.cpu.num_int_register_writes 177007633 # nu system.cpu.num_load_insts 29849485 # Number of load instructions system.cpu.num_mem_refs 42494120 # number of memory refs system.cpu.num_store_insts 12644635 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 400 # Number of system calls +system.cpu.workload.num_syscalls 400 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini index 0ecbfede5..c22086808 100644 --- a/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini @@ -164,12 +164,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing +cwd=build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/twolf +executable=/dist/m5/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/70.twolf/ref/arm/linux/simple-timing/simout index 9ae12354c..a62fdd8f9 100755 --- a/tests/long/70.twolf/ref/arm/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/simout @@ -5,10 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 19:25:36 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 13:31:09 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing +Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing/smred.sav +Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt index 1ea8a3c3d..6b9d8abcc 100644 --- a/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 569972 # Simulator instruction rate (inst/s) -host_mem_usage 258100 # Number of bytes of host memory used -host_seconds 330.17 # Real time elapsed on the host -host_tick_rate 702907358 # Simulator tick rate (ticks/s) +host_inst_rate 2299830 # Simulator instruction rate (inst/s) +host_mem_usage 217236 # Number of bytes of host memory used +host_seconds 81.83 # Real time elapsed on the host +host_tick_rate 2836221203 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 188185929 # Number of instructions simulated sim_seconds 0.232077 # Number of seconds simulated @@ -54,8 +54,8 @@ system.cpu.dcache.demand_mshr_misses 1789 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.332911 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 1363.604315 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.332911 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 41964334 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 54474.007826 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 51474.007826 # average overall mshr miss latency @@ -130,8 +130,8 @@ system.cpu.icache.demand_mshr_misses 3051 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.560538 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1147.981155 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.560538 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 189860061 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 37801.376598 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 34801.376598 # average overall mshr miss latency @@ -219,10 +219,10 @@ system.cpu.l2cache.demand_mshr_misses 3453 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.051044 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.000093 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 1672.609981 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 3.038048 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.051044 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000093 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 4840 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -264,6 +264,6 @@ system.cpu.num_int_register_writes 177007633 # nu system.cpu.num_load_insts 29849485 # Number of load instructions system.cpu.num_mem_refs 42494120 # number of memory refs system.cpu.num_store_insts 12644635 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 400 # Number of system calls +system.cpu.workload.num_syscalls 400 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout index f4dfd8899..9f7fb86bc 100755 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:13:30 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:13:39 -M5 executing on burrito +M5 compiled Apr 19 2011 12:19:46 +M5 started Apr 19 2011 12:20:03 +M5 executing on maize command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sv2 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt index 5f3549812..df028f09a 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1142521 # Simulator instruction rate (inst/s) -host_mem_usage 224208 # Number of bytes of host memory used -host_seconds 169.31 # Real time elapsed on the host -host_tick_rate 571263026 # Simulator tick rate (ticks/s) +host_inst_rate 4299467 # Simulator instruction rate (inst/s) +host_mem_usage 202100 # Number of bytes of host memory used +host_seconds 44.99 # Real time elapsed on the host +host_tick_rate 2149737482 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 193444769 # Number of instructions simulated sim_seconds 0.096723 # Number of seconds simulated @@ -29,6 +29,6 @@ system.cpu.num_int_register_writes 163703467 # nu system.cpu.num_load_insts 57735092 # Number of load instructions system.cpu.num_mem_refs 76733959 # number of memory refs system.cpu.num_store_insts 18998867 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 401 # Number of system calls +system.cpu.workload.num_syscalls 401 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini index c8439f7fb..1787724e4 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -51,6 +51,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -86,6 +87,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +123,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout index a4abb12dd..748c08434 100755 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:13:30 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:14:19 -M5 executing on burrito +M5 compiled Apr 19 2011 12:19:46 +M5 started Apr 19 2011 12:21:39 +M5 executing on maize command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt index f02c69451..9ba399fb8 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 498703 # Simulator instruction rate (inst/s) -host_mem_usage 231920 # Number of bytes of host memory used -host_seconds 387.90 # Real time elapsed on the host -host_tick_rate 697549821 # Simulator tick rate (ticks/s) +host_inst_rate 2425845 # Simulator instruction rate (inst/s) +host_mem_usage 209848 # Number of bytes of host memory used +host_seconds 79.74 # Real time elapsed on the host +host_tick_rate 3393094719 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 193444769 # Number of instructions simulated sim_seconds 0.270577 # Number of seconds simulated @@ -60,8 +60,8 @@ system.cpu.dcache.demand_mshr_misses 1575 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.302050 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 1237.197455 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.302050 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 76711508 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -115,8 +115,8 @@ system.cpu.icache.demand_mshr_misses 12288 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.777135 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1591.571713 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.777135 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 193445549 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 26294.433594 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency @@ -182,10 +182,10 @@ system.cpu.l2cache.demand_mshr_misses 5173 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.081736 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 2678.326682 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 0.000454 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.081736 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 13864 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -227,6 +227,6 @@ system.cpu.num_int_register_writes 163703466 # nu system.cpu.num_load_insts 57735092 # Number of load instructions system.cpu.num_mem_refs 76733959 # number of memory refs system.cpu.num_store_insts 18998867 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 401 # Number of system calls +system.cpu.workload.num_syscalls 401 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini index 61dc4a8fe..15faea73a 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -25,6 +25,8 @@ BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout index d11a4f41f..09f414a42 100755 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout @@ -5,10 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 18 2011 20:12:06 -M5 started Mar 18 2011 20:12:16 -M5 executing on zizzer +M5 compiled Apr 19 2011 12:22:33 +M5 started Apr 19 2011 12:39:55 +M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sav +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt index 4edd15028..84b97ca66 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 118324 # Simulator instruction rate (inst/s) -host_mem_usage 224536 # Number of bytes of host memory used -host_seconds 1870.83 # Real time elapsed on the host -host_tick_rate 57079180 # Simulator tick rate (ticks/s) +host_inst_rate 200454 # Simulator instruction rate (inst/s) +host_mem_usage 220376 # Number of bytes of host memory used +host_seconds 1104.31 # Real time elapsed on the host +host_tick_rate 96698720 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 221363017 # Number of instructions simulated sim_seconds 0.106785 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 3071588 # Nu system.cpu.BPredUnit.condPredicted 25075434 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 25075434 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 12326943 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 2318001 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 190318905 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.163116 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.516800 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 74095187 38.93% 38.93% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 71171116 37.40% 76.33% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 18278998 9.60% 85.93% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 12739096 6.69% 92.63% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 5868968 3.08% 95.71% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 2789277 1.47% 97.18% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 1957482 1.03% 98.20% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 1100780 0.58% 98.78% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 2318001 1.22% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 190318905 # Number of insts commited each cycle -system.cpu.commit.COM:count 221363017 # Number of instructions committed -system.cpu.commit.COM:fp_insts 2162459 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 0 # Number of function calls committed. -system.cpu.commit.COM:int_insts 220339606 # Number of committed integer instructions. -system.cpu.commit.COM:loads 56649590 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 77165306 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 3071621 # The number of times a branch was mispredicted +system.cpu.commit.branches 12326943 # Number of branches committed +system.cpu.commit.bw_lim_events 2318001 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 174370767 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 190318905 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.163116 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.516800 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 74095187 38.93% 38.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 71171116 37.40% 76.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 18278998 9.60% 85.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12739096 6.69% 92.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5868968 3.08% 95.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2789277 1.47% 97.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1957482 1.03% 98.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1100780 0.58% 98.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2318001 1.22% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 190318905 # Number of insts commited each cycle +system.cpu.commit.count 221363017 # Number of instructions committed +system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. +system.cpu.commit.function_calls 0 # Number of function calls committed. +system.cpu.commit.int_insts 220339606 # Number of committed integer instructions. +system.cpu.commit.loads 56649590 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.refs 77165306 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 221363017 # Number of Instructions Simulated system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated system.cpu.cpi 0.964799 # CPI: Cycles Per Instruction @@ -96,8 +96,8 @@ system.cpu.dcache.demand_mshr_misses 1955 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.341442 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 1398.546932 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.341442 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 71006066 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 27063.622370 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 35228.132992 # average overall mshr miss latency @@ -119,12 +119,12 @@ system.cpu.dcache.tagsinuse 1398.546932 # Cy system.cpu.dcache.total_refs 70998272 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 10 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 57112679 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 420105654 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 67048451 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 60385094 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 23161998 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 5772681 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 57112679 # Number of cycles decode is blocked +system.cpu.decode.DecodedInsts 420105654 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 67048451 # Number of cycles decode is idle +system.cpu.decode.RunCycles 60385094 # Number of cycles decode is running +system.cpu.decode.SquashCycles 23161998 # Number of cycles decode is squashing +system.cpu.decode.UnblockCycles 5772681 # Number of cycles decode is unblocking system.cpu.fetch.Branches 25075434 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 27531173 # Number of cache lines fetched system.cpu.fetch.Cycles 69569563 # Number of cycles fetch has run and was not squashing or blocked @@ -188,8 +188,8 @@ system.cpu.icache.demand_mshr_misses 5384 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.784044 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1605.721886 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.784044 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 27531173 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 25557.221784 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 22462.481426 # average overall mshr miss latency @@ -212,21 +212,13 @@ system.cpu.icache.total_refs 27524838 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 89860 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 15858881 # Number of branches executed -system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.303230 # Inst execution rate -system.cpu.iew.EXEC:refs 90240962 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 23196856 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 371845968 # num instructions consuming a value -system.cpu.iew.WB:count 275965139 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.599241 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 222825226 # num instructions producing a value -system.cpu.iew.WB:rate 1.292148 # insts written-back per cycle -system.cpu.iew.WB:sent 277010234 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 3274274 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 15858881 # Number of branches executed +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_rate 1.303230 # Inst execution rate +system.cpu.iew.exec_refs 90240962 # number of memory reference insts executed +system.cpu.iew.exec_stores 23196856 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 536838 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 104995800 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 1427 # Number of dispatched non-speculative instructions @@ -254,103 +246,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 16601009 # system.cpu.iew.memOrderViolationEvents 35659 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 741660 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 2532614 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 371845968 # num instructions consuming a value +system.cpu.iew.wb_count 275965139 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.599241 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 222825226 # num instructions producing a value +system.cpu.iew.wb_rate 1.292148 # insts written-back per cycle +system.cpu.iew.wb_sent 277010234 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 516469209 # number of integer regfile reads system.cpu.int_regfile_writes 283974364 # number of integer regfile writes system.cpu.ipc 1.036486 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.036486 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 1200408 0.43% 0.43% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 187079024 66.38% 66.80% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 66.80% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 66.80% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 1589764 0.56% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 68461114 24.29% 91.66% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 23516361 8.34% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 281846671 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 2813875 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.009984 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 68222 2.42% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 2379596 84.57% 86.99% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 366057 13.01% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 213480903 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.320243 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.372505 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 72600816 34.01% 34.01% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 65586069 30.72% 64.73% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 36613512 17.15% 81.88% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 20576315 9.64% 91.52% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 12054901 5.65% 97.17% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 3944773 1.85% 99.01% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 1483005 0.69% 99.71% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 508962 0.24% 99.95% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 112550 0.05% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 213480903 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.319688 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 1200408 0.43% 0.43% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 187079024 66.38% 66.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1589764 0.56% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.37% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 68461114 24.29% 91.66% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 23516361 8.34% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 281846671 # Type of FU issued system.cpu.iq.fp_alu_accesses 2636909 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 5233833 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 2531388 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 5663526 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 2813875 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009984 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 68222 2.42% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2379596 84.57% 86.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 366057 13.01% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 280823229 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 774810101 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 273433751 # Number of integer instruction queue wakeup accesses @@ -362,6 +344,24 @@ system.cpu.iq.iqSquashedInstsExamined 174039946 # Nu system.cpu.iq.iqSquashedInstsIssued 55814 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 181 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 358439815 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 213480903 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.320243 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.372505 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 72600816 34.01% 34.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 65586069 30.72% 64.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 36613512 17.15% 81.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20576315 9.64% 91.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12054901 5.65% 97.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3944773 1.85% 99.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1483005 0.69% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 508962 0.24% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 112550 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 213480903 # Number of insts issued each cycle +system.cpu.iq.rate 1.319688 # Inst issue rate system.cpu.l2cache.ReadExReq_accesses 1567 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 34548.046124 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31351.697630 # average ReadExReq mshr miss latency @@ -413,10 +413,10 @@ system.cpu.l2cache.demand_mshr_misses 5223 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.074157 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.000031 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 2429.985932 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 1.014854 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.074157 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000031 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 7335 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34369.136512 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31135.171357 # average overall mshr miss latency @@ -447,27 +447,27 @@ system.cpu.misc_regfile_writes 844 # nu system.cpu.numCycles 213570763 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 18060003 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 234363409 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 21564374 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 74887260 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 16382604 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 1054491347 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 409882715 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 430914543 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 57380379 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 23161998 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 39968831 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 196551134 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 11087102 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 1043404245 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 22432 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 1444 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 83221554 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 1312 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 18060003 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 234363409 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 21564374 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 74887260 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 16382604 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenameLookups 1054491347 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 409882715 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 430914543 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 57380379 # Number of cycles rename is running +system.cpu.rename.SquashCycles 23161998 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 39968831 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 196551134 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 11087102 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 1043404245 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 22432 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 1444 # count of serializing insts renamed +system.cpu.rename.skidInsts 83221554 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 1312 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 583734688 # The number of ROB reads system.cpu.rob.rob_writes 814640460 # The number of ROB writes system.cpu.timesIdled 1934 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 400 # Number of system calls +system.cpu.workload.num_syscalls 400 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout index 9f05df433..6d11a44d3 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout @@ -5,11 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 8 2011 00:58:32 -M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip -M5 started Feb 8 2011 00:58:34 -M5 executing on burrito +M5 compiled Apr 19 2011 12:22:33 +M5 started Apr 19 2011 12:38:23 +M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt index 0c54c7d41..80e0c67c1 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1396551 # Simulator instruction rate (inst/s) -host_mem_usage 231332 # Number of bytes of host memory used -host_seconds 158.51 # Real time elapsed on the host -host_tick_rate 828940820 # Simulator tick rate (ticks/s) +host_inst_rate 3098099 # Simulator instruction rate (inst/s) +host_mem_usage 209904 # Number of bytes of host memory used +host_seconds 71.45 # Real time elapsed on the host +host_tick_rate 1838915708 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 221363018 # Number of instructions simulated sim_seconds 0.131393 # Number of seconds simulated @@ -29,6 +29,6 @@ system.cpu.num_int_register_writes 232532006 # nu system.cpu.num_load_insts 56649590 # Number of load instructions system.cpu.num_mem_refs 77165306 # number of memory refs system.cpu.num_store_insts 20515716 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 400 # Number of system calls +system.cpu.workload.num_syscalls 400 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini index 2709fd0f4..040454ea4 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini @@ -51,6 +51,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -86,6 +87,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +123,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout index 72c0f8f4d..ac8ab44c7 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout @@ -5,11 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 8 2011 00:58:32 -M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip -M5 started Feb 8 2011 00:58:34 -M5 executing on burrito +M5 compiled Apr 19 2011 12:22:33 +M5 started Apr 19 2011 12:30:33 +M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sav +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt index bbd74268b..b2588e568 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 920852 # Simulator instruction rate (inst/s) -host_mem_usage 239052 # Number of bytes of host memory used -host_seconds 240.39 # Real time elapsed on the host -host_tick_rate 1043974445 # Simulator tick rate (ticks/s) +host_inst_rate 1944621 # Simulator instruction rate (inst/s) +host_mem_usage 217656 # Number of bytes of host memory used +host_seconds 113.83 # Real time elapsed on the host +host_tick_rate 2204625935 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 221363018 # Number of instructions simulated sim_seconds 0.250961 # Number of seconds simulated @@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses 1905 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.332874 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 1363.451495 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.332874 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 77197738 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 55780.577428 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 52780.314961 # average overall mshr miss latency @@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses 4694 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.710590 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1455.289108 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.710590 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 173494412 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 39420.856412 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency @@ -173,10 +173,10 @@ system.cpu.l2cache.demand_mshr_misses 4735 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.062810 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.000001 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 2058.146434 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 0.021756 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.062810 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000001 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 6599 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52003.273495 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -218,6 +218,6 @@ system.cpu.num_int_register_writes 232532006 # nu system.cpu.num_load_insts 56649590 # Number of load instructions system.cpu.num_mem_refs 77165306 # number of memory refs system.cpu.num_store_insts 20515716 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 400 # Number of system calls +system.cpu.workload.num_syscalls 400 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout index fe4ad698b..62a971a25 100755 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:10:38 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:10:45 -M5 executing on burrito +M5 compiled Apr 19 2011 12:22:08 +M5 started Apr 19 2011 12:22:10 +M5 executing on maize command line: build/SPARC_FS/m5.fast -d build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic Global frequency set at 2000000000 ticks per second info: No kernel set for full system simulation. Assuming you know what you're doing... diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt index d05ca1e9f..3bd8ad178 100644 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1272725 # Simulator instruction rate (inst/s) -host_mem_usage 524564 # Number of bytes of host memory used -host_seconds 1751.49 # Real time elapsed on the host -host_tick_rate 1275361 # Simulator tick rate (ticks/s) +host_inst_rate 4668188 # Simulator instruction rate (inst/s) +host_mem_usage 504368 # Number of bytes of host memory used +host_seconds 477.52 # Real time elapsed on the host +host_tick_rate 4677854 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks sim_insts 2229160714 # Number of instructions simulated sim_seconds 1.116889 # Number of seconds simulated |