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-rw-r--r--tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini10
-rwxr-xr-xtests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout6
-rw-r--r--tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt19
-rw-r--r--tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini8
-rwxr-xr-xtests/long/00.gzip/ref/alpha/tru64/o3-timing/simout6
-rw-r--r--tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt19
-rw-r--r--tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini13
-rwxr-xr-xtests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout8
-rw-r--r--tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt19
-rw-r--r--tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini11
-rwxr-xr-xtests/long/00.gzip/ref/alpha/tru64/simple-timing/simout8
-rw-r--r--tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt19
-rw-r--r--tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini10
-rwxr-xr-xtests/long/00.gzip/ref/arm/linux/o3-timing/simout6
-rw-r--r--tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt19
-rw-r--r--tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini13
-rwxr-xr-xtests/long/00.gzip/ref/arm/linux/simple-atomic/simerr1
-rwxr-xr-xtests/long/00.gzip/ref/arm/linux/simple-atomic/simout16
-rw-r--r--tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt109
-rw-r--r--tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini11
-rwxr-xr-xtests/long/00.gzip/ref/arm/linux/simple-timing/simerr1
-rwxr-xr-xtests/long/00.gzip/ref/arm/linux/simple-timing/simout16
-rw-r--r--tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt475
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini10
-rwxr-xr-xtests/long/00.gzip/ref/sparc/linux/o3-timing/simout6
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt19
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini12
-rwxr-xr-xtests/long/00.gzip/ref/sparc/linux/simple-atomic/simout6
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt19
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini10
-rwxr-xr-xtests/long/00.gzip/ref/sparc/linux/simple-timing/simout6
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt19
-rw-r--r--tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini10
-rwxr-xr-xtests/long/00.gzip/ref/x86/linux/o3-timing/simout8
-rw-r--r--tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt19
-rw-r--r--tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini12
-rwxr-xr-xtests/long/00.gzip/ref/x86/linux/simple-atomic/simout8
-rw-r--r--tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt19
-rw-r--r--tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini10
-rwxr-xr-xtests/long/00.gzip/ref/x86/linux/simple-timing/simout8
-rw-r--r--tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt19
-rw-r--r--tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini47
-rwxr-xr-xtests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout8
-rw-r--r--tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt19
-rw-r--r--tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini47
-rwxr-xr-xtests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout8
-rw-r--r--tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt19
-rw-r--r--tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini68
-rwxr-xr-xtests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout6
-rw-r--r--tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt28
-rw-r--r--tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini68
-rwxr-xr-xtests/long/10.linux-boot/ref/arm/linux/realview-o3/simout6
-rw-r--r--tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt28
-rw-r--r--tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini85
-rwxr-xr-xtests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout11
-rw-r--r--tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt19
-rw-r--r--tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini12
-rwxr-xr-xtests/long/10.mcf/ref/arm/linux/o3-timing/simout6
-rw-r--r--tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt19
-rw-r--r--tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini13
-rwxr-xr-xtests/long/10.mcf/ref/arm/linux/simple-atomic/simerr1
-rwxr-xr-xtests/long/10.mcf/ref/arm/linux/simple-atomic/simout16
-rw-r--r--tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt109
-rw-r--r--tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini11
-rwxr-xr-xtests/long/10.mcf/ref/arm/linux/simple-timing/simerr1
-rwxr-xr-xtests/long/10.mcf/ref/arm/linux/simple-timing/simout16
-rw-r--r--tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt475
-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini12
-rwxr-xr-xtests/long/10.mcf/ref/sparc/linux/simple-atomic/simout6
-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt19
-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini10
-rwxr-xr-xtests/long/10.mcf/ref/sparc/linux/simple-timing/simout6
-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt19
-rw-r--r--tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini12
-rwxr-xr-xtests/long/10.mcf/ref/x86/linux/o3-timing/simout8
-rw-r--r--tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt19
-rw-r--r--tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini14
-rwxr-xr-xtests/long/10.mcf/ref/x86/linux/simple-atomic/simout8
-rw-r--r--tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt19
-rw-r--r--tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini12
-rwxr-xr-xtests/long/10.mcf/ref/x86/linux/simple-timing/simout8
-rw-r--r--tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt19
-rw-r--r--tests/long/20.parser/ref/arm/linux/o3-timing/config.ini7
-rwxr-xr-xtests/long/20.parser/ref/arm/linux/o3-timing/simout6
-rw-r--r--tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt19
-rw-r--r--tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini13
-rwxr-xr-xtests/long/20.parser/ref/arm/linux/simple-atomic/simerr1
-rwxr-xr-xtests/long/20.parser/ref/arm/linux/simple-atomic/simout16
-rw-r--r--tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt109
-rw-r--r--tests/long/20.parser/ref/arm/linux/simple-timing/config.ini11
-rwxr-xr-xtests/long/20.parser/ref/arm/linux/simple-timing/simerr1
-rwxr-xr-xtests/long/20.parser/ref/arm/linux/simple-timing/simout16
-rw-r--r--tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt475
-rw-r--r--tests/long/20.parser/ref/x86/linux/o3-timing/config.ini12
-rwxr-xr-xtests/long/20.parser/ref/x86/linux/o3-timing/simout8
-rw-r--r--tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt19
-rw-r--r--tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini14
-rwxr-xr-xtests/long/20.parser/ref/x86/linux/simple-atomic/simout8
-rw-r--r--tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt19
-rw-r--r--tests/long/20.parser/ref/x86/linux/simple-timing/config.ini12
-rwxr-xr-xtests/long/20.parser/ref/x86/linux/simple-timing/simout8
-rw-r--r--tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt19
-rw-r--r--tests/long/30.eon/ref/alpha/tru64/inorder-timing/config.ini10
-rwxr-xr-xtests/long/30.eon/ref/alpha/tru64/inorder-timing/simout6
-rw-r--r--tests/long/30.eon/ref/alpha/tru64/inorder-timing/stats.txt18
-rw-r--r--tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini8
-rwxr-xr-xtests/long/30.eon/ref/alpha/tru64/o3-timing/simout6
-rw-r--r--tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt18
-rw-r--r--tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini13
-rwxr-xr-xtests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr11
-rwxr-xr-xtests/long/30.eon/ref/alpha/tru64/simple-atomic/simout16
-rw-r--r--tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt89
-rw-r--r--tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini11
-rwxr-xr-xtests/long/30.eon/ref/alpha/tru64/simple-timing/simerr11
-rwxr-xr-xtests/long/30.eon/ref/alpha/tru64/simple-timing/simout16
-rw-r--r--tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt446
-rw-r--r--tests/long/30.eon/ref/arm/linux/o3-timing/config.ini10
-rwxr-xr-xtests/long/30.eon/ref/arm/linux/o3-timing/simout6
-rw-r--r--tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt18
-rw-r--r--tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini13
-rwxr-xr-xtests/long/30.eon/ref/arm/linux/simple-atomic/simerr1
-rwxr-xr-xtests/long/30.eon/ref/arm/linux/simple-atomic/simout16
-rw-r--r--tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt109
-rw-r--r--tests/long/30.eon/ref/arm/linux/simple-timing/config.ini11
-rwxr-xr-xtests/long/30.eon/ref/arm/linux/simple-timing/simerr1
-rwxr-xr-xtests/long/30.eon/ref/arm/linux/simple-timing/simout16
-rw-r--r--tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt474
-rw-r--r--tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini8
-rwxr-xr-xtests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout6
-rw-r--r--tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt19
-rw-r--r--tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini13
-rwxr-xr-xtests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout8
-rw-r--r--tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt19
-rw-r--r--tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini11
-rwxr-xr-xtests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout8
-rw-r--r--tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt19
-rw-r--r--tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini10
-rwxr-xr-xtests/long/40.perlbmk/ref/arm/linux/o3-timing/simout6
-rw-r--r--tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt19
-rw-r--r--tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini13
-rwxr-xr-xtests/long/40.perlbmk/ref/arm/linux/simple-atomic/simerr2
-rwxr-xr-xtests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout16
-rw-r--r--tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt109
-rw-r--r--tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini11
-rwxr-xr-xtests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr2
-rwxr-xr-xtests/long/40.perlbmk/ref/arm/linux/simple-timing/simout16
-rw-r--r--tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt475
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini10
-rwxr-xr-xtests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout6
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt19
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini8
-rwxr-xr-xtests/long/50.vortex/ref/alpha/tru64/o3-timing/simout6
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt19
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini13
-rwxr-xr-xtests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout8
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt19
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini11
-rwxr-xr-xtests/long/50.vortex/ref/alpha/tru64/simple-timing/simout8
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt19
-rw-r--r--tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini10
-rwxr-xr-xtests/long/50.vortex/ref/arm/linux/o3-timing/simout6
-rw-r--r--tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt19
-rw-r--r--tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini13
-rwxr-xr-xtests/long/50.vortex/ref/arm/linux/simple-atomic/simerr1
-rwxr-xr-xtests/long/50.vortex/ref/arm/linux/simple-atomic/simout16
-rw-r--r--tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt109
-rw-r--r--tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini11
-rwxr-xr-xtests/long/50.vortex/ref/arm/linux/simple-timing/simerr1
-rwxr-xr-xtests/long/50.vortex/ref/arm/linux/simple-timing/simout16
-rw-r--r--tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt475
-rw-r--r--tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini12
-rwxr-xr-xtests/long/50.vortex/ref/sparc/linux/simple-atomic/simout6
-rw-r--r--tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt19
-rw-r--r--tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini10
-rwxr-xr-xtests/long/50.vortex/ref/sparc/linux/simple-timing/simout6
-rw-r--r--tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt19
-rw-r--r--tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini10
-rwxr-xr-xtests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout6
-rw-r--r--tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt19
-rw-r--r--tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini8
-rwxr-xr-xtests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout6
-rw-r--r--tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt19
-rw-r--r--tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini13
-rwxr-xr-xtests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout8
-rw-r--r--tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt19
-rw-r--r--tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini11
-rwxr-xr-xtests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout8
-rw-r--r--tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt19
-rw-r--r--tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini10
-rwxr-xr-xtests/long/60.bzip2/ref/arm/linux/o3-timing/simout6
-rw-r--r--tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt19
-rw-r--r--tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini13
-rwxr-xr-xtests/long/60.bzip2/ref/arm/linux/simple-atomic/simerr1
-rwxr-xr-xtests/long/60.bzip2/ref/arm/linux/simple-atomic/simout16
-rw-r--r--tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt109
-rw-r--r--tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini11
-rwxr-xr-xtests/long/60.bzip2/ref/arm/linux/simple-timing/simerr1
-rwxr-xr-xtests/long/60.bzip2/ref/arm/linux/simple-timing/simout16
-rw-r--r--tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt475
-rw-r--r--tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini12
-rwxr-xr-xtests/long/60.bzip2/ref/x86/linux/simple-atomic/simout8
-rw-r--r--tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt19
-rw-r--r--tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini10
-rwxr-xr-xtests/long/60.bzip2/ref/x86/linux/simple-timing/simout8
-rw-r--r--tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt19
-rw-r--r--tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini10
-rwxr-xr-xtests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout6
-rw-r--r--tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt18
-rw-r--r--tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini8
-rwxr-xr-xtests/long/70.twolf/ref/alpha/tru64/o3-timing/simout6
-rw-r--r--tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt18
-rw-r--r--tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini13
-rwxr-xr-xtests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout12
-rw-r--r--tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt19
-rw-r--r--tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini11
-rwxr-xr-xtests/long/70.twolf/ref/alpha/tru64/simple-timing/simout12
-rw-r--r--tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt18
-rw-r--r--tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini10
-rwxr-xr-xtests/long/70.twolf/ref/arm/linux/o3-timing/simout6
-rw-r--r--tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt18
-rw-r--r--tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini13
-rwxr-xr-xtests/long/70.twolf/ref/arm/linux/simple-atomic/simerr1
-rwxr-xr-xtests/long/70.twolf/ref/arm/linux/simple-atomic/simout20
-rw-r--r--tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt109
-rw-r--r--tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini11
-rwxr-xr-xtests/long/70.twolf/ref/arm/linux/simple-timing/simerr1
-rwxr-xr-xtests/long/70.twolf/ref/arm/linux/simple-timing/simout20
-rw-r--r--tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt474
-rw-r--r--tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini12
-rwxr-xr-xtests/long/70.twolf/ref/sparc/linux/simple-atomic/simout10
-rw-r--r--tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt19
-rw-r--r--tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini10
-rwxr-xr-xtests/long/70.twolf/ref/sparc/linux/simple-timing/simout10
-rw-r--r--tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt18
-rw-r--r--tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini10
-rwxr-xr-xtests/long/70.twolf/ref/x86/linux/o3-timing/simout8
-rw-r--r--tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt18
-rw-r--r--tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini12
-rwxr-xr-xtests/long/70.twolf/ref/x86/linux/simple-atomic/simout8
-rw-r--r--tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt19
-rw-r--r--tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini10
-rwxr-xr-xtests/long/70.twolf/ref/x86/linux/simple-timing/simout8
-rw-r--r--tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt18
-rw-r--r--tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini25
-rwxr-xr-xtests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout8
-rw-r--r--tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt63
246 files changed, 4572 insertions, 3659 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
index b6c1d1a1d..6c1c0e974 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=InOrderCPU
@@ -182,7 +184,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -205,7 +207,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
gid=100
input=cin
max_stack_size=67108864
@@ -224,7 +226,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -234,5 +236,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout
index 9da502021..30b31a527 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 8 2011 15:00:53
-gem5 started Jul 8 2011 16:09:24
-gem5 executing on u200439-lin.austin.arm.com
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:24:12
+gem5 executing on zizzer
command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
index ec1428295..b5662ac02 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.274500 # Number of seconds simulated
sim_ticks 274500333500 # Number of ticks simulated
+final_tick 274500333500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 56944 # Simulator instruction rate (inst/s)
-host_tick_rate 25971361 # Simulator tick rate (ticks/s)
-host_mem_usage 245756 # Number of bytes of host memory used
-host_seconds 10569.35 # Real time elapsed on the host
+host_inst_rate 113367 # Simulator instruction rate (inst/s)
+host_tick_rate 51705325 # Simulator tick rate (ticks/s)
+host_mem_usage 207980 # Number of bytes of host memory used
+host_seconds 5308.94 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated
+system.physmem.bytes_read 5894016 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 54720 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 3798080 # Number of bytes written to this memory
+system.physmem.num_reads 92094 # Number of read requests responded to by this memory
+system.physmem.num_writes 59345 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 21471799 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 199344 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 13836340 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 35308139 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
index b11fadb7f..cc9b0c683 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -519,7 +521,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
index 9acd0ed7e..ad1c408b1 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
@@ -1,10 +1,8 @@
-Redirecting stdout to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 20 2011 16:10:02
-gem5 started Aug 20 2011 16:10:09
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:24:12
gem5 executing on zizzer
command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
index bcb696265..8681db468 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.144450 # Number of seconds simulated
sim_ticks 144450185500 # Number of ticks simulated
+final_tick 144450185500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 180758 # Simulator instruction rate (inst/s)
-host_tick_rate 46168195 # Simulator tick rate (ticks/s)
-host_mem_usage 205240 # Number of bytes of host memory used
-host_seconds 3128.78 # Real time elapsed on the host
+host_inst_rate 205040 # Simulator instruction rate (inst/s)
+host_tick_rate 52370107 # Simulator tick rate (ticks/s)
+host_mem_usage 208620 # Number of bytes of host memory used
+host_seconds 2758.26 # Real time elapsed on the host
sim_insts 565552443 # Number of instructions simulated
+system.physmem.bytes_read 5936768 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 60416 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 3797120 # Number of bytes written to this memory
+system.physmem.num_reads 92762 # Number of read requests responded to by this memory
+system.physmem.num_writes 59330 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 41099068 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 418248 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 26286709 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 67385777 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
index 355960d42..282141772 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=AlphaTLB
@@ -61,7 +64,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic
+cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-atomic
egid=100
env=
errout=cerr
@@ -85,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
index 7ce6e1e9f..1dc402141 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 19 2011 06:59:13
-gem5 started Jun 20 2011 12:20:39
-gem5 executing on m60-009.pool
-command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:24:12
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
index b2d2b0068..ad4f39b85 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.300931 # Number of seconds simulated
sim_ticks 300930958000 # Number of ticks simulated
+final_tick 300930958000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3663682 # Simulator instruction rate (inst/s)
-host_tick_rate 1831855621 # Simulator tick rate (ticks/s)
-host_mem_usage 184012 # Number of bytes of host memory used
-host_seconds 164.28 # Real time elapsed on the host
+host_inst_rate 4527143 # Simulator instruction rate (inst/s)
+host_tick_rate 2263589972 # Simulator tick rate (ticks/s)
+host_mem_usage 198960 # Number of bytes of host memory used
+host_seconds 132.94 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated
+system.physmem.bytes_read 2782990928 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 2407447588 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 152669504 # Number of bytes written to this memory
+system.physmem.num_reads 716375939 # Number of read requests responded to by this memory
+system.physmem.num_writes 39451321 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 9247938286 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 7999999747 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 507324022 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 9755262308 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
index 50ef6266f..0bc5277c7 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -164,7 +167,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing
+cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
@@ -188,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
index 26ae974dd..36bd68fb7 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 19 2011 06:59:13
-gem5 started Jun 20 2011 12:47:45
-gem5 executing on m60-009.pool
-command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:24:12
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
index 9bcf790a8..4d7850adf 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.765623 # Number of seconds simulated
sim_ticks 765623032000 # Number of ticks simulated
+final_tick 765623032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1640067 # Simulator instruction rate (inst/s)
-host_tick_rate 2086331180 # Simulator tick rate (ticks/s)
-host_mem_usage 192652 # Number of bytes of host memory used
-host_seconds 366.97 # Real time elapsed on the host
+host_inst_rate 2199350 # Simulator instruction rate (inst/s)
+host_tick_rate 2797795440 # Simulator tick rate (ticks/s)
+host_mem_usage 207676 # Number of bytes of host memory used
+host_seconds 273.65 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated
+system.physmem.bytes_read 5889984 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 50880 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 3797824 # Number of bytes written to this memory
+system.physmem.num_reads 92031 # Number of read requests responded to by this memory
+system.physmem.num_writes 59341 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 7693060 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 66456 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 4960436 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 12653496 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini
index 158bcba97..9f24d0367 100644
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -500,7 +502,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
+executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
gid=100
input=cin
max_stack_size=67108864
@@ -519,7 +521,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout
index c90a30371..d3786fda6 100755
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 21 2011 16:28:02
-gem5 started Nov 22 2011 16:59:04
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:31:06
+gem5 executing on zizzer
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
index 7a98c6c82..5022d17a1 100644
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.177099 # Number of seconds simulated
sim_ticks 177098873000 # Number of ticks simulated
+final_tick 177098873000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 166594 # Simulator instruction rate (inst/s)
-host_tick_rate 48979898 # Simulator tick rate (ticks/s)
-host_mem_usage 214636 # Number of bytes of host memory used
-host_seconds 3615.75 # Real time elapsed on the host
+host_inst_rate 154897 # Simulator instruction rate (inst/s)
+host_tick_rate 45541130 # Simulator tick rate (ticks/s)
+host_mem_usage 220436 # Number of bytes of host memory used
+host_seconds 3888.77 # Real time elapsed on the host
sim_insts 602359805 # Number of instructions simulated
+system.physmem.bytes_read 5833856 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 46976 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 3720192 # Number of bytes written to this memory
+system.physmem.num_reads 91154 # Number of read requests responded to by this memory
+system.physmem.num_writes 58128 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 32941237 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 265253 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 21006300 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 53947537 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini
index 17d38a039..8c7671d34 100644
--- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=ArmTLB
@@ -61,7 +64,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic
egid=100
env=
errout=cerr
@@ -85,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr
index eabe42249..e45cd058f 100755
--- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr
@@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout
index ceb1053f2..95da0efca 100755
--- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 12:47:58
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:36:54
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt
index 2dd995d75..f48dc3640 100644
--- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt
@@ -1,76 +1,87 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 2791643 # Simulator instruction rate (inst/s)
-host_mem_usage 253504 # Number of bytes of host memory used
-host_seconds 215.77 # Real time elapsed on the host
-host_tick_rate 1395873441 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 602359851 # Number of instructions simulated
sim_seconds 0.301191 # Number of seconds simulated
sim_ticks 301191370000 # Number of ticks simulated
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+final_tick 301191370000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 2998309 # Simulator instruction rate (inst/s)
+host_tick_rate 1499211130 # Simulator tick rate (ticks/s)
+host_mem_usage 210136 # Number of bytes of host memory used
+host_seconds 200.90 # Real time elapsed on the host
+sim_insts 602359851 # Number of instructions simulated
+system.physmem.bytes_read 2680160157 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 2280298136 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 236359611 # Number of bytes written to this memory
+system.physmem.num_reads 717867713 # Number of read requests responded to by this memory
+system.physmem.num_writes 69418858 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 8898529055 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 7570927866 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 784748949 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 9683278004 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 602382741 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 602382741 # Number of busy cycles
-system.cpu.num_conditional_control_insts 67017827 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
-system.cpu.num_fp_insts 16 # number of float instructions
-system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_func_calls 1993546 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 602359851 # Number of instructions executed
system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
+system.cpu.num_func_calls 1993546 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 67017827 # number of instructions that are conditional controls
system.cpu.num_int_insts 533522639 # number of integer instructions
+system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_int_register_reads 2770243005 # number of times the integer registers were read
system.cpu.num_int_register_writes 614470985 # number of times the integer registers were written
-system.cpu.num_load_insts 148952594 # Number of load instructions
+system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 219173607 # number of memory refs
+system.cpu.num_load_insts 148952594 # Number of load instructions
system.cpu.num_store_insts 70221013 # Number of store instructions
-system.cpu.workload.num_syscalls 48 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 602382741 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini
index f2a118cfd..6a1e2b970 100644
--- a/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -164,7 +167,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing
egid=100
env=
errout=cerr
@@ -188,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/simerr b/tests/long/00.gzip/ref/arm/linux/simple-timing/simerr
index eabe42249..e45cd058f 100755
--- a/tests/long/00.gzip/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/simerr
@@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/simout b/tests/long/00.gzip/ref/arm/linux/simple-timing/simout
index 99cb1ccc7..589b03862 100755
--- a/tests/long/00.gzip/ref/arm/linux/simple-timing/simout
+++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 12:48:29
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:40:26
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt
index ba03a3195..3846f97fb 100644
--- a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt
@@ -1,269 +1,280 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1298278 # Simulator instruction rate (inst/s)
-host_mem_usage 260992 # Number of bytes of host memory used
-host_seconds 462.46 # Real time elapsed on the host
-host_tick_rate 1722888732 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 600398281 # Number of instructions simulated
sim_seconds 0.796763 # Number of seconds simulated
sim_ticks 796762926000 # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses 1327 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits 1327 # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses 147791852 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 20842.679226 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17842.679226 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 147602036 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 3956274000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.001284 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 189816 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 3386826000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.001284 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 189816 # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses 1327 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits 1327 # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 23909.028529 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20909.028529 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 69169783 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 5923414000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.003569 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 247748 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 5180170000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.003569 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 247748 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 495.412038 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 217209383 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 22578.841038 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 19578.841038 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 216771819 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 9879688000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.002014 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 437564 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 8566996000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.002014 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 437564 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0 4094.222434 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.999566 # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses 217209383 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 22578.841038 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 19578.841038 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 216771819 # number of overall hits
-system.cpu.dcache.overall_miss_latency 9879688000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.002014 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 437564 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 8566996000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.002014 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 437564 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 433468 # number of replacements
-system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4094.222434 # Cycle average of tags in use
-system.cpu.dcache.total_refs 216774473 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 537031000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 392392 # number of writebacks
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+final_tick 796762926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1450316 # Simulator instruction rate (inst/s)
+host_tick_rate 1924652930 # Simulator tick rate (ticks/s)
+host_mem_usage 219100 # Number of bytes of host memory used
+host_seconds 413.98 # Real time elapsed on the host
+sim_insts 600398281 # Number of instructions simulated
+system.physmem.bytes_read 5759488 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 39424 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 3704704 # Number of bytes written to this memory
+system.physmem.num_reads 89992 # Number of read requests responded to by this memory
+system.physmem.num_writes 57886 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 7228609 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 49480 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 4649694 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 11878304 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.icache.ReadReq_accesses 570074535 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 54236.391913 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 51236.391913 # average ReadReq mshr miss latency
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
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+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
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+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 48 # Number of system calls
+system.cpu.numCycles 1593525852 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 600398281 # Number of instructions executed
+system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
+system.cpu.num_func_calls 1993546 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 67017827 # number of instructions that are conditional controls
+system.cpu.num_int_insts 533522639 # number of integer instructions
+system.cpu.num_fp_insts 16 # number of float instructions
+system.cpu.num_int_register_reads 3212467108 # number of times the integer registers were read
+system.cpu.num_int_register_writes 614470985 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
+system.cpu.num_mem_refs 219173607 # number of memory refs
+system.cpu.num_load_insts 148952594 # Number of load instructions
+system.cpu.num_store_insts 70221013 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 1593525852 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.icache.replacements 12 # number of replacements
+system.cpu.icache.tagsinuse 577.728532 # Cycle average of tags in use
+system.cpu.icache.total_refs 570073892 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 886584.590980 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 577.728532 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.282094 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 570073892 # number of ReadReq hits
+system.cpu.icache.demand_hits 570073892 # number of demand (read+write) hits
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+system.cpu.icache.ReadReq_misses 643 # number of ReadReq misses
+system.cpu.icache.demand_misses 643 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 643 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 34874000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 34874000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 34874000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 570074535 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 570074535 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 570074535 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 643 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 32945000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 643 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 886584.590980 # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 54236.391913 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 54236.391913 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 54236.391913 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 570074535 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 54236.391913 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 51236.391913 # average overall mshr miss latency
-system.cpu.icache.demand_hits 570073892 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 34874000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
-system.cpu.icache.demand_misses 643 # number of demand (read+write) misses
+system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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+system.cpu.icache.ReadReq_mshr_misses 643 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses 643 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 643 # number of overall MSHR misses
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+system.cpu.icache.ReadReq_mshr_miss_latency 32945000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 32945000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 32945000 # number of overall MSHR miss cycles
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+system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 643 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0 577.728532 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.282094 # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses 570074535 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 54236.391913 # average overall miss latency
+system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 51236.391913 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 51236.391913 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 51236.391913 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 570073892 # number of overall hits
-system.cpu.icache.overall_miss_latency 34874000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
-system.cpu.icache.overall_misses 643 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 32945000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 643 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 12 # number of replacements
-system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks.
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 577.728532 # Cycle average of tags in use
-system.cpu.icache.total_refs 570073892 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses 247748 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 433468 # number of replacements
+system.cpu.dcache.tagsinuse 4094.222434 # Cycle average of tags in use
+system.cpu.dcache.total_refs 216774473 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 495.412038 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 537031000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 4094.222434 # Average occupied blocks per context
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+system.cpu.dcache.WriteReq_misses 247748 # number of WriteReq misses
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+system.cpu.dcache.ReadReq_miss_latency 3956274000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 5923414000 # number of WriteReq miss cycles
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+system.cpu.dcache.ReadReq_accesses 147791852 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses 1327 # number of LoadLockedReq accesses(hits+misses)
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+system.cpu.dcache.demand_accesses 217209383 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses 217209383 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate 0.001284 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate 0.003569 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate 0.002014 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate 0.002014 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 20842.679226 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 23909.028529 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 22578.841038 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 22578.841038 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
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+system.cpu.dcache.writebacks 392392 # number of writebacks
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+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 189816 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 247748 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 437564 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 437564 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 3386826000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 5180170000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 8566996000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 8566996000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.001284 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.003569 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate 0.002014 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate 0.002014 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17842.679226 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20909.028529 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 19578.841038 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 19578.841038 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 71804 # number of replacements
+system.cpu.l2cache.tagsinuse 17904.014680 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 411836 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 87286 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 4.718237 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 1762.179345 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 16141.835335 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.053777 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.492610 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits 158918 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits 392392 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 189297 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency 3039452000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 0.235929 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_hits 348215 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 348215 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 31541 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 58451 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2338040000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235929 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 58451 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 190459 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 158918 # number of ReadReq hits
+system.cpu.l2cache.demand_misses 89992 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 89992 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 1640132000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.165605 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 31541 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1261640000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165605 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 31541 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_miss_latency 3039452000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 4679584000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 4679584000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 190459 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 392392 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 392392 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 4.718237 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_accesses 247748 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 438207 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 438207 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate 0.165605 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate 0.235929 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.205364 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.205364 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 438207 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 348215 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 4679584000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.205364 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 89992 # number of demand (read+write) misses
+system.cpu.l2cache.writebacks 57886 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 31541 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 58451 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 89992 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 89992 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1261640000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 2338040000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 3599680000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 3599680000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165605 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235929 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.205364 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 89992 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0 1762.179345 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 16141.835335 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.053777 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1 0.492610 # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses 438207 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_mshr_miss_rate 0.205364 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 348215 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 4679584000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.205364 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 89992 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 3599680000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.205364 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 89992 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 71804 # number of replacements
-system.cpu.l2cache.sampled_refs 87286 # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 17904.014680 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 411836 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 57886 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 1593525852 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 1593525852 # Number of busy cycles
-system.cpu.num_conditional_control_insts 67017827 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
-system.cpu.num_fp_insts 16 # number of float instructions
-system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_func_calls 1993546 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_insts 600398281 # Number of instructions executed
-system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses
-system.cpu.num_int_insts 533522639 # number of integer instructions
-system.cpu.num_int_register_reads 3212467108 # number of times the integer registers were read
-system.cpu.num_int_register_writes 614470985 # number of times the integer registers were written
-system.cpu.num_load_insts 148952594 # Number of load instructions
-system.cpu.num_mem_refs 219173607 # number of memory refs
-system.cpu.num_store_insts 70221013 # Number of store instructions
-system.cpu.workload.num_syscalls 48 # Number of system calls
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
index f1874f64f..dcba73ec2 100644
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -495,7 +497,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
+cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing
egid=100
env=
errout=cerr
@@ -519,7 +521,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
index df0fa130a..a835cbd79 100755
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 30 2011 17:14:16
-gem5 started Nov 30 2011 17:16:48
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 06:17:40
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
index 8c5bfcb3c..e4d9fca07 100644
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.408816 # Number of seconds simulated
sim_ticks 408816360000 # Number of ticks simulated
+final_tick 408816360000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 252046 # Simulator instruction rate (inst/s)
-host_tick_rate 73306837 # Simulator tick rate (ticks/s)
-host_mem_usage 206388 # Number of bytes of host memory used
-host_seconds 5576.78 # Real time elapsed on the host
+host_inst_rate 175830 # Simulator instruction rate (inst/s)
+host_tick_rate 51139829 # Simulator tick rate (ticks/s)
+host_mem_usage 215728 # Number of bytes of host memory used
+host_seconds 7994.10 # Real time elapsed on the host
sim_insts 1405604152 # Number of instructions simulated
+system.physmem.bytes_read 6021376 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 81792 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 3792448 # Number of bytes written to this memory
+system.physmem.num_reads 94084 # Number of read requests responded to by this memory
+system.physmem.num_writes 59257 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 14728804 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 200070 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 9276654 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 24005458 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 49 # Number of system calls
system.cpu.numCycles 817632721 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
index 864c2771b..b52495d06 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -45,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=SparcTLB
@@ -62,7 +64,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic
+cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic
egid=100
env=
errout=cerr
@@ -86,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -96,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
index 3eb09159b..d2df5cc09 100755
--- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 30 2011 17:14:16
-gem5 started Nov 30 2011 17:16:48
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 06:18:03
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
index ae12e23e4..afe2bae4f 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.744764 # Number of seconds simulated
sim_ticks 744764119000 # Number of ticks simulated
+final_tick 744764119000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 4241689 # Simulator instruction rate (inst/s)
-host_tick_rate 2120851440 # Simulator tick rate (ticks/s)
-host_mem_usage 196528 # Number of bytes of host memory used
-host_seconds 351.16 # Real time elapsed on the host
+host_inst_rate 3773289 # Simulator instruction rate (inst/s)
+host_tick_rate 1886650577 # Simulator tick rate (ticks/s)
+host_mem_usage 205844 # Number of bytes of host memory used
+host_seconds 394.75 # Real time elapsed on the host
sim_insts 1489523295 # Number of instructions simulated
+system.physmem.bytes_read 7326269637 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 5940452044 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 614672063 # Number of bytes written to this memory
+system.physmem.num_reads 1887625855 # Number of read requests responded to by this memory
+system.physmem.num_writes 166846816 # Number of write requests responded to by this memory
+system.physmem.num_other 1326 # Number of other requests responded to by this memory
+system.physmem.bw_read 9837033566 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 7976286575 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 825324485 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 10662358051 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 49 # Number of system calls
system.cpu.numCycles 1489528239 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
index 6dbddf888..ea98a23a1 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -147,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -165,7 +167,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing
+cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing
egid=100
env=
errout=cerr
@@ -189,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -199,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
index 4a77ef60d..b26fb3f41 100755
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 30 2011 17:14:16
-gem5 started Nov 30 2011 17:16:48
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 06:19:05
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
index d75fccee8..059312926 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.064259 # Number of seconds simulated
sim_ticks 2064258667000 # Number of ticks simulated
+final_tick 2064258667000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2284016 # Simulator instruction rate (inst/s)
-host_tick_rate 3165307188 # Simulator tick rate (ticks/s)
-host_mem_usage 205232 # Number of bytes of host memory used
-host_seconds 652.15 # Real time elapsed on the host
+host_inst_rate 1766930 # Simulator instruction rate (inst/s)
+host_tick_rate 2448703239 # Simulator tick rate (ticks/s)
+host_mem_usage 214556 # Number of bytes of host memory used
+host_seconds 843.00 # Real time elapsed on the host
sim_insts 1489523295 # Number of instructions simulated
+system.physmem.bytes_read 5909952 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 70592 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 3778240 # Number of bytes written to this memory
+system.physmem.num_reads 92343 # Number of read requests responded to by this memory
+system.physmem.num_writes 59035 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 2862990 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 34197 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 1830313 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 4693303 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 49 # Number of system calls
system.cpu.numCycles 4128517334 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini
index c626036a3..42f7aa66f 100644
--- a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -500,7 +502,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
+executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
gid=100
input=cin
max_stack_size=67108864
@@ -519,7 +521,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout
index d3f649818..48ae315a0 100755
--- a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout
+++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 9 2012 14:18:02
-gem5 started Jan 9 2012 14:29:08
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 06:28:24
+gem5 executing on zizzer
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt
index 9655899ee..802bd6f5d 100644
--- a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.586294 # Number of seconds simulated
sim_ticks 586294224000 # Number of ticks simulated
+final_tick 586294224000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 115446 # Simulator instruction rate (inst/s)
-host_tick_rate 41742717 # Simulator tick rate (ticks/s)
-host_mem_usage 244900 # Number of bytes of host memory used
-host_seconds 14045.43 # Real time elapsed on the host
+host_inst_rate 145094 # Simulator instruction rate (inst/s)
+host_tick_rate 52462700 # Simulator tick rate (ticks/s)
+host_mem_usage 215548 # Number of bytes of host memory used
+host_seconds 11175.48 # Real time elapsed on the host
sim_insts 1621493982 # Number of instructions simulated
+system.physmem.bytes_read 5880640 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 56960 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 3744192 # Number of bytes written to this memory
+system.physmem.num_reads 91885 # Number of read requests responded to by this memory
+system.physmem.num_writes 58503 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 10030186 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 97153 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 6386200 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 16416386 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 1172588449 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
index dd4d7f0aa..393d71365 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -45,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=X86TLB
@@ -67,7 +69,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
+executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
gid=100
input=cin
max_stack_size=67108864
@@ -86,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -96,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
index 510b69206..3da3c7641 100755
--- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 9 2012 14:18:02
-gem5 started Jan 9 2012 14:29:08
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 06:33:19
+gem5 executing on zizzer
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
index a5e9437b0..3a54bb2c8 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.963993 # Number of seconds simulated
sim_ticks 963992704000 # Number of ticks simulated
+final_tick 963992704000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1220339 # Simulator instruction rate (inst/s)
-host_tick_rate 725502264 # Simulator tick rate (ticks/s)
-host_mem_usage 234168 # Number of bytes of host memory used
-host_seconds 1328.72 # Real time elapsed on the host
+host_inst_rate 2202720 # Simulator instruction rate (inst/s)
+host_tick_rate 1309536712 # Simulator tick rate (ticks/s)
+host_mem_usage 204800 # Number of bytes of host memory used
+host_seconds 736.13 # Real time elapsed on the host
sim_insts 1621493983 # Number of instructions simulated
+system.physmem.bytes_read 11334586825 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 9492133912 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 864451000 # Number of bytes written to this memory
+system.physmem.num_reads 1605558864 # Number of read requests responded to by this memory
+system.physmem.num_writes 188186057 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 11757959140 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 9846686466 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 896740189 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 12654699330 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 1927985409 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
index 129642a98..f841786ec 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -147,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -170,7 +172,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
+executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
gid=100
input=cin
max_stack_size=67108864
@@ -189,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -199,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout
index 613f79639..c3d33da65 100755
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 9 2012 14:18:02
-gem5 started Jan 9 2012 14:29:08
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 06:37:10
+gem5 executing on zizzer
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
index 5aedfb687..8e512b7b9 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.803259 # Number of seconds simulated
sim_ticks 1803258587000 # Number of ticks simulated
+final_tick 1803258587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 760773 # Simulator instruction rate (inst/s)
-host_tick_rate 846053445 # Simulator tick rate (ticks/s)
-host_mem_usage 242892 # Number of bytes of host memory used
-host_seconds 2131.38 # Real time elapsed on the host
+host_inst_rate 1279975 # Simulator instruction rate (inst/s)
+host_tick_rate 1423455894 # Simulator tick rate (ticks/s)
+host_mem_usage 213784 # Number of bytes of host memory used
+host_seconds 1266.82 # Real time elapsed on the host
sim_insts 1621493983 # Number of instructions simulated
+system.physmem.bytes_read 5725952 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 46208 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 3712448 # Number of bytes written to this memory
+system.physmem.num_reads 89468 # Number of read requests responded to by this memory
+system.physmem.num_writes 58007 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 3175336 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 25625 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 2058744 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 5234080 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 3606517174 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
index 78fc12019..94bfc8925 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
@@ -10,13 +10,14 @@ type=LinuxAlphaSystem
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
-console=/projects/pd/randd/dist/binaries/console
+console=/dist/m5/system/binaries/console
init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux
+kernel=/dist/m5/system/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
-pal=/projects/pd/randd/dist/binaries/ts_osfpal
+num_work_ids=16
+pal=/dist/m5/system/binaries/ts_osfpal
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
@@ -29,20 +30,18 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[2]
[system.bridge]
type=Bridge
delay=50000
-filter_ranges_a=0:18446744073709551615
-filter_ranges_b=0:8589934591
nack_delay=4000
-req_size_a=16
-req_size_b=16
-resp_size_a=16
-resp_size_b=16
+ranges=8796093022208:18446744073709551615
+req_size=16
+resp_size=16
write_ack=false
-side_a=system.iobus.port[0]
-side_b=system.membus.port[0]
+master=system.iobus.port[0]
+slave=system.membus.port[0]
[system.cpu0]
type=DerivO3CPU
@@ -933,7 +932,7 @@ table_size=65536
[system.disk0.image.child]
type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[system.disk2]
@@ -953,7 +952,7 @@ table_size=65536
[system.disk2.image.child]
type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
@@ -969,7 +968,7 @@ header_cycles=1
use_default_range=true
width=64
default=system.tsunami.pciconfig.pio
-port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
+port=system.bridge.master system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ide.dma system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.iocache.cpu_side
[system.iocache]
type=BaseCache
@@ -1000,8 +999,8 @@ tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
-cpu_side=system.iobus.port[28]
-mem_side=system.membus.port[2]
+cpu_side=system.iobus.port[32]
+mem_side=system.membus.port[3]
[system.l2c]
type=BaseCache
@@ -1033,7 +1032,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[3]
+mem_side=system.membus.port[4]
[system.membus]
type=Bus
@@ -1045,7 +1044,7 @@ header_cycles=1
use_default_range=false
width=64
default=system.membus.badaddr_responder.pio
-port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side
+port=system.bridge.slave system.physmem.port[0] system.system_port system.iocache.mem_side system.l2c.mem_side
[system.membus.badaddr_responder]
type=IsaFake
@@ -1082,7 +1081,7 @@ system=system
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[system.terminal]
@@ -1195,9 +1194,9 @@ system=system
tx_delay=1000000
tx_fifo_size=524288
tx_thread=false
-config=system.iobus.port[29]
-dma=system.iobus.port[30]
-pio=system.iobus.port[27]
+config=system.iobus.port[30]
+dma=system.iobus.port[31]
+pio=system.iobus.port[29]
[system.tsunami.fake_OROM]
type=IsaFake
@@ -1583,8 +1582,8 @@ pci_func=0
pio_latency=1000
platform=system.tsunami
system=system
-config=system.iobus.port[31]
-dma=system.iobus.port[32]
+config=system.iobus.port[27]
+dma=system.iobus.port[28]
pio=system.iobus.port[26]
[system.tsunami.io]
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
index cb23e1c15..35f0311de 100755
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
@@ -1,13 +1,13 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 21 2011 16:05:33
-gem5 started Nov 21 2011 19:03:16
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2012 03:53:29
+gem5 started Jan 23 2012 06:11:48
+gem5 executing on zizzer
command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
+info: kernel located at: /dist/m5/system/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
info: Launching CPU 1 @ 106949500
Exiting @ tick 1897465263500 because m5_exit instruction encountered
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
index 65d49a60e..d2e784a3f 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.897465 # Number of seconds simulated
sim_ticks 1897465263500 # Number of ticks simulated
+final_tick 1897465263500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 138767 # Simulator instruction rate (inst/s)
-host_tick_rate 4690907118 # Simulator tick rate (ticks/s)
-host_mem_usage 293696 # Number of bytes of host memory used
-host_seconds 404.50 # Real time elapsed on the host
+host_inst_rate 131690 # Simulator instruction rate (inst/s)
+host_tick_rate 4451680142 # Simulator tick rate (ticks/s)
+host_mem_usage 298548 # Number of bytes of host memory used
+host_seconds 426.24 # Real time elapsed on the host
sim_insts 56130966 # Number of instructions simulated
+system.physmem.bytes_read 30408320 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 1097728 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 10468544 # Number of bytes written to this memory
+system.physmem.num_reads 475130 # Number of read requests responded to by this memory
+system.physmem.num_writes 163571 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 16025758 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 578523 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 5517120 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 21542879 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 397795 # number of replacements
system.l2c.tagsinuse 35116.884908 # Cycle average of tags in use
system.l2c.total_refs 2482671 # Total number of references to valid blocks.
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
index c437d8a70..b0a37466e 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
@@ -10,13 +10,14 @@ type=LinuxAlphaSystem
children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
-console=/projects/pd/randd/dist/binaries/console
+console=/dist/m5/system/binaries/console
init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux
+kernel=/dist/m5/system/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
-pal=/projects/pd/randd/dist/binaries/ts_osfpal
+num_work_ids=16
+pal=/dist/m5/system/binaries/ts_osfpal
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
@@ -29,20 +30,18 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[2]
[system.bridge]
type=Bridge
delay=50000
-filter_ranges_a=0:18446744073709551615
-filter_ranges_b=0:8589934591
nack_delay=4000
-req_size_a=16
-req_size_b=16
-resp_size_a=16
-resp_size_b=16
+ranges=8796093022208:18446744073709551615
+req_size=16
+resp_size=16
write_ack=false
-side_a=system.iobus.port[0]
-side_b=system.membus.port[0]
+master=system.iobus.port[0]
+slave=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
@@ -497,7 +496,7 @@ table_size=65536
[system.disk0.image.child]
type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[system.disk2]
@@ -517,7 +516,7 @@ table_size=65536
[system.disk2.image.child]
type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
@@ -533,7 +532,7 @@ header_cycles=1
use_default_range=true
width=64
default=system.tsunami.pciconfig.pio
-port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
+port=system.bridge.master system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ide.dma system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.iocache.cpu_side
[system.iocache]
type=BaseCache
@@ -564,8 +563,8 @@ tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
-cpu_side=system.iobus.port[28]
-mem_side=system.membus.port[2]
+cpu_side=system.iobus.port[32]
+mem_side=system.membus.port[3]
[system.l2c]
type=BaseCache
@@ -597,7 +596,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[3]
+mem_side=system.membus.port[4]
[system.membus]
type=Bus
@@ -609,7 +608,7 @@ header_cycles=1
use_default_range=false
width=64
default=system.membus.badaddr_responder.pio
-port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side
+port=system.bridge.slave system.physmem.port[0] system.system_port system.iocache.mem_side system.l2c.mem_side
[system.membus.badaddr_responder]
type=IsaFake
@@ -646,7 +645,7 @@ system=system
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[system.terminal]
@@ -759,9 +758,9 @@ system=system
tx_delay=1000000
tx_fifo_size=524288
tx_thread=false
-config=system.iobus.port[29]
-dma=system.iobus.port[30]
-pio=system.iobus.port[27]
+config=system.iobus.port[30]
+dma=system.iobus.port[31]
+pio=system.iobus.port[29]
[system.tsunami.fake_OROM]
type=IsaFake
@@ -1147,8 +1146,8 @@ pci_func=0
pio_latency=1000
platform=system.tsunami
system=system
-config=system.iobus.port[31]
-dma=system.iobus.port[32]
+config=system.iobus.port[27]
+dma=system.iobus.port[28]
pio=system.iobus.port[26]
[system.tsunami.io]
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
index b8893b11f..2911b29fc 100755
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
@@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 21 2011 16:05:33
-gem5 started Nov 21 2011 18:56:50
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2012 03:53:29
+gem5 started Jan 23 2012 06:11:15
+gem5 executing on zizzer
command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
+info: kernel located at: /dist/m5/system/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1858873594500 because m5_exit instruction encountered
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
index 16f374a0c..de8941321 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.858874 # Number of seconds simulated
sim_ticks 1858873594500 # Number of ticks simulated
+final_tick 1858873594500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 141632 # Simulator instruction rate (inst/s)
-host_tick_rate 4958330764 # Simulator tick rate (ticks/s)
-host_mem_usage 290572 # Number of bytes of host memory used
-host_seconds 374.90 # Real time elapsed on the host
+host_inst_rate 134152 # Simulator instruction rate (inst/s)
+host_tick_rate 4696460042 # Simulator tick rate (ticks/s)
+host_mem_usage 295432 # Number of bytes of host memory used
+host_seconds 395.80 # Real time elapsed on the host
sim_insts 53097697 # Number of instructions simulated
+system.physmem.bytes_read 29819840 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 1062784 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 10193408 # Number of bytes written to this memory
+system.physmem.num_reads 465935 # Number of read requests responded to by this memory
+system.physmem.num_writes 159272 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 16041887 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 571735 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 5483648 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 21525535 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 391354 # number of replacements
system.l2c.tagsinuse 34898.086140 # Cycle average of tags in use
system.l2c.total_refs 2410581 # Total number of references to valid blocks.
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
index e6a0de845..6f9417ef5 100644
--- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
+++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
@@ -32,20 +32,18 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[7]
[system.bridge]
type=Bridge
delay=50000
-filter_ranges_a=0:18446744073709551615
-filter_ranges_b=0:268435455
nack_delay=4000
-req_size_a=16
-req_size_b=16
-resp_size_a=16
-resp_size_b=16
+ranges=268435456:520093695 1073741824:18446744073709551615
+req_size=16
+resp_size=16
write_ack=false
-side_a=system.iobus.port[0]
-side_b=system.membus.port[0]
+master=system.iobus.port[0]
+slave=system.membus.port[0]
[system.cf0]
type=IdeDisk
@@ -987,7 +985,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.clcd.dma
+port=system.bridge.master system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.clcd.dma system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side
[system.iocache]
type=BaseCache
@@ -1018,8 +1016,8 @@ tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
-cpu_side=system.iobus.port[25]
-mem_side=system.membus.port[7]
+cpu_side=system.iobus.port[28]
+mem_side=system.membus.port[8]
[system.l2c]
type=BaseCache
@@ -1051,7 +1049,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[8]
+mem_side=system.membus.port[9]
[system.membus]
type=Bus
@@ -1063,7 +1061,7 @@ header_cycles=1
use_default_range=false
width=64
default=system.membus.badaddr_responder.pio
-port=system.bridge.side_b system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.iocache.mem_side system.l2c.mem_side
+port=system.bridge.slave system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.system_port system.iocache.mem_side system.l2c.mem_side
[system.membus.badaddr_responder]
type=IsaFake
@@ -1125,7 +1123,7 @@ pio_addr=268451840
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[21]
+pio=system.iobus.port[24]
[system.realview.cf_ctrl]
type=IdeController
@@ -1179,9 +1177,9 @@ pci_func=0
pio_latency=1000
platform=system.realview
system=system
-config=system.iobus.port[26]
-dma=system.iobus.port[27]
-pio=system.iobus.port[8]
+config=system.iobus.port[10]
+dma=system.iobus.port[11]
+pio=system.iobus.port[9]
[system.realview.clcd]
type=Pl111
@@ -1196,7 +1194,7 @@ pio_latency=10000
platform=system.realview
system=system
vnc=system.vncserver
-dma=system.iobus.port[28]
+dma=system.iobus.port[6]
pio=system.iobus.port[5]
[system.realview.dmac_fake]
@@ -1207,7 +1205,7 @@ pio_addr=268632064
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[9]
+pio=system.iobus.port[12]
[system.realview.flash_fake]
type=IsaFake
@@ -1224,7 +1222,7 @@ ret_data8=255
system=system
update_data=false
warn_access=
-pio=system.iobus.port[24]
+pio=system.iobus.port[27]
[system.realview.gic]
type=Gic
@@ -1246,7 +1244,7 @@ pio_addr=268513280
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[16]
+pio=system.iobus.port[19]
[system.realview.gpio1_fake]
type=AmbaFake
@@ -1256,7 +1254,7 @@ pio_addr=268517376
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[17]
+pio=system.iobus.port[20]
[system.realview.gpio2_fake]
type=AmbaFake
@@ -1266,7 +1264,7 @@ pio_addr=268521472
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[18]
+pio=system.iobus.port[21]
[system.realview.kmi0]
type=Pl050
@@ -1280,7 +1278,7 @@ pio_latency=1000
platform=system.realview
system=system
vnc=system.vncserver
-pio=system.iobus.port[6]
+pio=system.iobus.port[7]
[system.realview.kmi1]
type=Pl050
@@ -1294,7 +1292,7 @@ pio_latency=1000
platform=system.realview
system=system
vnc=system.vncserver
-pio=system.iobus.port[7]
+pio=system.iobus.port[8]
[system.realview.l2x0_fake]
type=IsaFake
@@ -1333,7 +1331,7 @@ pio_addr=268455936
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[22]
+pio=system.iobus.port[25]
[system.realview.realview_io]
type=RealViewCtrl
@@ -1354,7 +1352,7 @@ pio_addr=268529664
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[23]
+pio=system.iobus.port[26]
[system.realview.sci_fake]
type=AmbaFake
@@ -1364,7 +1362,7 @@ pio_addr=268492800
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[20]
+pio=system.iobus.port[23]
[system.realview.smc_fake]
type=AmbaFake
@@ -1374,7 +1372,7 @@ pio_addr=269357056
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[13]
+pio=system.iobus.port[16]
[system.realview.sp810_fake]
type=AmbaFake
@@ -1384,7 +1382,7 @@ pio_addr=268439552
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[14]
+pio=system.iobus.port[17]
[system.realview.ssp_fake]
type=AmbaFake
@@ -1394,7 +1392,7 @@ pio_addr=268488704
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[19]
+pio=system.iobus.port[22]
[system.realview.timer0]
type=Sp804
@@ -1445,7 +1443,7 @@ pio_addr=268476416
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[10]
+pio=system.iobus.port[13]
[system.realview.uart2_fake]
type=AmbaFake
@@ -1455,7 +1453,7 @@ pio_addr=268480512
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[11]
+pio=system.iobus.port[14]
[system.realview.uart3_fake]
type=AmbaFake
@@ -1465,7 +1463,7 @@ pio_addr=268484608
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[12]
+pio=system.iobus.port[15]
[system.realview.watchdog_fake]
type=AmbaFake
@@ -1475,7 +1473,7 @@ pio_addr=268500992
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[15]
+pio=system.iobus.port[18]
[system.terminal]
type=Terminal
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
index 13d4b63f2..28da0bb31 100755
--- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
+++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
@@ -1,10 +1,8 @@
-Redirecting stdout to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual/simout
-Redirecting stderr to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 8 2012 22:12:58
-gem5 started Jan 9 2012 03:33:38
+gem5 compiled Jan 23 2012 04:21:22
+gem5 started Jan 23 2012 09:54:17
gem5 executing on zizzer
command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
index 3163bcf32..11b3b4098 100644
--- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
+++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
@@ -2,12 +2,32 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.582494 # Number of seconds simulated
sim_ticks 2582494395500 # Number of ticks simulated
+final_tick 2582494395500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 65512 # Simulator instruction rate (inst/s)
-host_tick_rate 2118472138 # Simulator tick rate (ticks/s)
-host_mem_usage 384260 # Number of bytes of host memory used
-host_seconds 1219.04 # Real time elapsed on the host
+host_inst_rate 77486 # Simulator instruction rate (inst/s)
+host_tick_rate 2505663009 # Simulator tick rate (ticks/s)
+host_mem_usage 386072 # Number of bytes of host memory used
+host_seconds 1030.66 # Real time elapsed on the host
sim_insts 79862069 # Number of instructions simulated
+system.nvmem.bytes_read 384 # Number of bytes read from this memory
+system.nvmem.bytes_inst_read 384 # Number of instructions bytes read from this memory
+system.nvmem.bytes_written 0 # Number of bytes written to this memory
+system.nvmem.num_reads 6 # Number of read requests responded to by this memory
+system.nvmem.num_writes 0 # Number of write requests responded to by this memory
+system.nvmem.num_other 0 # Number of other requests responded to by this memory
+system.nvmem.bw_read 149 # Total read bandwidth from this memory (bytes/s)
+system.nvmem.bw_inst_read 149 # Instruction read bandwidth from this memory (bytes/s)
+system.nvmem.bw_total 149 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read 131490980 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 1177856 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 10251344 # Number of bytes written to this memory
+system.physmem.num_reads 15129077 # Number of read requests responded to by this memory
+system.physmem.num_writes 870131 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 50916269 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 456092 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 3969551 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 54885821 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 132200 # number of replacements
system.l2c.tagsinuse 27582.989225 # Cycle average of tags in use
system.l2c.total_refs 1817822 # Total number of references to valid blocks.
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini
index 0e78591b5..c84a9ea85 100644
--- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini
+++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini
@@ -32,20 +32,18 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[7]
[system.bridge]
type=Bridge
delay=50000
-filter_ranges_a=0:18446744073709551615
-filter_ranges_b=0:268435455
nack_delay=4000
-req_size_a=16
-req_size_b=16
-resp_size_a=16
-resp_size_b=16
+ranges=268435456:520093695 1073741824:18446744073709551615
+req_size=16
+resp_size=16
write_ack=false
-side_a=system.iobus.port[0]
-side_b=system.membus.port[0]
+master=system.iobus.port[0]
+slave=system.membus.port[0]
[system.cf0]
type=IdeDisk
@@ -533,7 +531,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.clcd.dma
+port=system.bridge.master system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.clcd.dma system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side
[system.iocache]
type=BaseCache
@@ -564,8 +562,8 @@ tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
-cpu_side=system.iobus.port[25]
-mem_side=system.membus.port[7]
+cpu_side=system.iobus.port[28]
+mem_side=system.membus.port[8]
[system.l2c]
type=BaseCache
@@ -597,7 +595,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[8]
+mem_side=system.membus.port[9]
[system.membus]
type=Bus
@@ -609,7 +607,7 @@ header_cycles=1
use_default_range=false
width=64
default=system.membus.badaddr_responder.pio
-port=system.bridge.side_b system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.iocache.mem_side system.l2c.mem_side
+port=system.bridge.slave system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.system_port system.iocache.mem_side system.l2c.mem_side
[system.membus.badaddr_responder]
type=IsaFake
@@ -671,7 +669,7 @@ pio_addr=268451840
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[21]
+pio=system.iobus.port[24]
[system.realview.cf_ctrl]
type=IdeController
@@ -725,9 +723,9 @@ pci_func=0
pio_latency=1000
platform=system.realview
system=system
-config=system.iobus.port[26]
-dma=system.iobus.port[27]
-pio=system.iobus.port[8]
+config=system.iobus.port[10]
+dma=system.iobus.port[11]
+pio=system.iobus.port[9]
[system.realview.clcd]
type=Pl111
@@ -742,7 +740,7 @@ pio_latency=10000
platform=system.realview
system=system
vnc=system.vncserver
-dma=system.iobus.port[28]
+dma=system.iobus.port[6]
pio=system.iobus.port[5]
[system.realview.dmac_fake]
@@ -753,7 +751,7 @@ pio_addr=268632064
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[9]
+pio=system.iobus.port[12]
[system.realview.flash_fake]
type=IsaFake
@@ -770,7 +768,7 @@ ret_data8=255
system=system
update_data=false
warn_access=
-pio=system.iobus.port[24]
+pio=system.iobus.port[27]
[system.realview.gic]
type=Gic
@@ -792,7 +790,7 @@ pio_addr=268513280
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[16]
+pio=system.iobus.port[19]
[system.realview.gpio1_fake]
type=AmbaFake
@@ -802,7 +800,7 @@ pio_addr=268517376
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[17]
+pio=system.iobus.port[20]
[system.realview.gpio2_fake]
type=AmbaFake
@@ -812,7 +810,7 @@ pio_addr=268521472
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[18]
+pio=system.iobus.port[21]
[system.realview.kmi0]
type=Pl050
@@ -826,7 +824,7 @@ pio_latency=1000
platform=system.realview
system=system
vnc=system.vncserver
-pio=system.iobus.port[6]
+pio=system.iobus.port[7]
[system.realview.kmi1]
type=Pl050
@@ -840,7 +838,7 @@ pio_latency=1000
platform=system.realview
system=system
vnc=system.vncserver
-pio=system.iobus.port[7]
+pio=system.iobus.port[8]
[system.realview.l2x0_fake]
type=IsaFake
@@ -879,7 +877,7 @@ pio_addr=268455936
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[22]
+pio=system.iobus.port[25]
[system.realview.realview_io]
type=RealViewCtrl
@@ -900,7 +898,7 @@ pio_addr=268529664
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[23]
+pio=system.iobus.port[26]
[system.realview.sci_fake]
type=AmbaFake
@@ -910,7 +908,7 @@ pio_addr=268492800
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[20]
+pio=system.iobus.port[23]
[system.realview.smc_fake]
type=AmbaFake
@@ -920,7 +918,7 @@ pio_addr=269357056
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[13]
+pio=system.iobus.port[16]
[system.realview.sp810_fake]
type=AmbaFake
@@ -930,7 +928,7 @@ pio_addr=268439552
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[14]
+pio=system.iobus.port[17]
[system.realview.ssp_fake]
type=AmbaFake
@@ -940,7 +938,7 @@ pio_addr=268488704
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[19]
+pio=system.iobus.port[22]
[system.realview.timer0]
type=Sp804
@@ -991,7 +989,7 @@ pio_addr=268476416
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[10]
+pio=system.iobus.port[13]
[system.realview.uart2_fake]
type=AmbaFake
@@ -1001,7 +999,7 @@ pio_addr=268480512
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[11]
+pio=system.iobus.port[14]
[system.realview.uart3_fake]
type=AmbaFake
@@ -1011,7 +1009,7 @@ pio_addr=268484608
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[12]
+pio=system.iobus.port[15]
[system.realview.watchdog_fake]
type=AmbaFake
@@ -1021,7 +1019,7 @@ pio_addr=268500992
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[15]
+pio=system.iobus.port[18]
[system.terminal]
type=Terminal
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout
index 9d4c8ae86..231dec8b1 100755
--- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout
+++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout
@@ -1,10 +1,8 @@
-Redirecting stdout to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3/simout
-Redirecting stderr to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 8 2012 22:12:58
-gem5 started Jan 9 2012 03:32:35
+gem5 compiled Jan 23 2012 04:21:22
+gem5 started Jan 23 2012 09:54:06
gem5 executing on zizzer
command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
index 768983a75..ad6b1630f 100644
--- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
+++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
@@ -2,12 +2,32 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.503566 # Number of seconds simulated
sim_ticks 2503566110500 # Number of ticks simulated
+final_tick 2503566110500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 72389 # Simulator instruction rate (inst/s)
-host_tick_rate 2360079964 # Simulator tick rate (ticks/s)
-host_mem_usage 384076 # Number of bytes of host memory used
-host_seconds 1060.80 # Real time elapsed on the host
+host_inst_rate 76624 # Simulator instruction rate (inst/s)
+host_tick_rate 2498140220 # Simulator tick rate (ticks/s)
+host_mem_usage 386188 # Number of bytes of host memory used
+host_seconds 1002.17 # Real time elapsed on the host
sim_insts 76790007 # Number of instructions simulated
+system.nvmem.bytes_read 64 # Number of bytes read from this memory
+system.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory
+system.nvmem.bytes_written 0 # Number of bytes written to this memory
+system.nvmem.num_reads 1 # Number of read requests responded to by this memory
+system.nvmem.num_writes 0 # Number of write requests responded to by this memory
+system.nvmem.num_other 0 # Number of other requests responded to by this memory
+system.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s)
+system.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s)
+system.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read 130731152 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 1101568 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 9585992 # Number of bytes written to this memory
+system.physmem.num_reads 15117140 # Number of read requests responded to by this memory
+system.physmem.num_writes 856673 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 52217975 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 440000 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 3828935 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 56046910 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 119509 # number of replacements
system.l2c.tagsinuse 25929.897253 # Cycle average of tags in use
system.l2c.total_refs 1795434 # Total number of references to valid blocks.
diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
index 9ef75afe6..f406247a4 100644
--- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
+++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
@@ -7,7 +7,7 @@ time_sync_spin_threshold=100000000
[system]
type=LinuxX86System
-children=acpi_description_table_pointer bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus
+children=acpi_description_table_pointer bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobridge iobus iocache l2c membus pc physmem smbios_table toL2Bus
acpi_description_table_pointer=system.acpi_description_table_pointer
boot_cpu_frequency=500
boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
@@ -15,7 +15,7 @@ e820_table=system.e820_table
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
-kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
load_addr_mask=18446744073709551615
mem_mode=timing
memories=system.physmem
@@ -31,6 +31,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[3]
[system.acpi_description_table_pointer]
type=X86ACPIRSDP
@@ -52,16 +53,13 @@ oem_table_id=
[system.bridge]
type=Bridge
delay=50000
-filter_ranges_a=0:1152921504606846975
-filter_ranges_b=0:134217727
nack_delay=4000
-req_size_a=16
-req_size_b=16
-resp_size_a=16
-resp_size_b=16
+ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
+req_size=16
+resp_size=16
write_ack=false
-side_a=system.iobus.port[0]
-side_b=system.membus.port[1]
+master=system.iobus.port[0]
+slave=system.membus.port[1]
[system.cpu]
type=DerivO3CPU
@@ -535,8 +533,8 @@ pio_addr=2305843009213693952
pio_latency=1000
platform=system.pc
system=system
-int_port=system.membus.port[5]
-pio=system.membus.port[4]
+int_port=system.membus.port[7]
+pio=system.membus.port[6]
[system.cpu.itb]
type=X86TLB
@@ -947,6 +945,17 @@ subtractive_decode=true
type=IntrControl
sys=system
+[system.iobridge]
+type=Bridge
+delay=50000
+nack_delay=4000
+ranges=11529215046068469760:11529215046068473855
+req_size=16
+resp_size=16
+write_ack=false
+master=system.membus.port[2]
+slave=system.iobus.port[1]
+
[system.iobus]
type=Bus
block_size=64
@@ -956,7 +965,7 @@ header_cycles=1
use_default_range=true
width=64
default=system.pc.pciconfig.pio
-port=system.bridge.side_a system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma
+port=system.bridge.master system.iobridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
[system.iocache]
type=BaseCache
@@ -987,8 +996,8 @@ tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
-cpu_side=system.iobus.port[18]
-mem_side=system.membus.port[2]
+cpu_side=system.iobus.port[21]
+mem_side=system.membus.port[4]
[system.l2c]
type=BaseCache
@@ -1020,7 +1029,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[3]
+mem_side=system.membus.port[5]
[system.membus]
type=Bus
@@ -1032,7 +1041,7 @@ header_cycles=1
use_default_range=false
width=64
default=system.membus.badaddr_responder.pio
-port=system.physmem.port[0] system.bridge.side_b system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
+port=system.physmem.port[0] system.bridge.slave system.iobridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
[system.membus.badaddr_responder]
type=IsaFake
@@ -1072,7 +1081,7 @@ ret_data8=255
system=system
update_data=false
warn_access=
-pio=system.iobus.port[12]
+pio=system.iobus.port[15]
[system.pc.com_1]
type=Uart8250
@@ -1082,7 +1091,7 @@ pio_latency=1000
platform=system.pc
system=system
terminal=system.pc.com_1.terminal
-pio=system.iobus.port[13]
+pio=system.iobus.port[16]
[system.pc.com_1.terminal]
type=Terminal
@@ -1113,7 +1122,7 @@ ret_data8=255
system=system
update_data=false
warn_access=
-pio=system.iobus.port[14]
+pio=system.iobus.port[17]
[system.pc.fake_com_3]
type=IsaFake
@@ -1130,7 +1139,7 @@ ret_data8=255
system=system
update_data=false
warn_access=
-pio=system.iobus.port[15]
+pio=system.iobus.port[18]
[system.pc.fake_com_4]
type=IsaFake
@@ -1147,7 +1156,7 @@ ret_data8=255
system=system
update_data=false
warn_access=
-pio=system.iobus.port[16]
+pio=system.iobus.port[19]
[system.pc.fake_floppy]
type=IsaFake
@@ -1164,7 +1173,7 @@ ret_data8=255
system=system
update_data=false
warn_access=
-pio=system.iobus.port[17]
+pio=system.iobus.port[20]
[system.pc.i_dont_exist]
type=IsaFake
@@ -1181,7 +1190,7 @@ ret_data8=255
system=system
update_data=false
warn_access=
-pio=system.iobus.port[11]
+pio=system.iobus.port[14]
[system.pc.pciconfig]
type=PciConfigAll
@@ -1215,7 +1224,7 @@ pio_latency=1000
platform=system.pc
system=system
time=Sun Jan 1 00:00:00 2012
-pio=system.iobus.port[1]
+pio=system.iobus.port[2]
[system.pc.south_bridge.cmos.int_pin]
type=X86IntSourcePin
@@ -1226,7 +1235,7 @@ pio_addr=9223372036854775808
pio_latency=1000
platform=system.pc
system=system
-pio=system.iobus.port[2]
+pio=system.iobus.port[3]
[system.pc.south_bridge.ide]
type=IdeController
@@ -1281,9 +1290,9 @@ pci_func=0
pio_latency=1000
platform=system.pc
system=system
-config=system.iobus.port[19]
-dma=system.iobus.port[20]
-pio=system.iobus.port[3]
+config=system.iobus.port[5]
+dma=system.iobus.port[6]
+pio=system.iobus.port[4]
[system.pc.south_bridge.ide.disks0]
type=IdeDisk
@@ -1302,7 +1311,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
+image_file=/dist/m5/system/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
@@ -1322,7 +1331,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]
@@ -1411,8 +1420,8 @@ pio_addr=4273995776
pio_latency=1000
platform=system.pc
system=system
-int_port=system.iobus.port[10]
-pio=system.iobus.port[9]
+int_port=system.iobus.port[13]
+pio=system.iobus.port[12]
[system.pc.south_bridge.keyboard]
type=I8042
@@ -1425,7 +1434,7 @@ pio_addr=0
pio_latency=1000
platform=system.pc
system=system
-pio=system.iobus.port[4]
+pio=system.iobus.port[7]
[system.pc.south_bridge.keyboard.keyboard_int_pin]
type=X86IntSourcePin
@@ -1443,7 +1452,7 @@ pio_latency=1000
platform=system.pc
slave=system.pc.south_bridge.pic2
system=system
-pio=system.iobus.port[5]
+pio=system.iobus.port[8]
[system.pc.south_bridge.pic1.output]
type=X86IntSourcePin
@@ -1458,7 +1467,7 @@ pio_latency=1000
platform=system.pc
slave=Null
system=system
-pio=system.iobus.port[6]
+pio=system.iobus.port[9]
[system.pc.south_bridge.pic2.output]
type=X86IntSourcePin
@@ -1471,7 +1480,7 @@ pio_addr=9223372036854775872
pio_latency=1000
platform=system.pc
system=system
-pio=system.iobus.port[7]
+pio=system.iobus.port[10]
[system.pc.south_bridge.pit.int_pin]
type=X86IntSourcePin
@@ -1483,7 +1492,7 @@ pio_addr=9223372036854775905
pio_latency=1000
platform=system.pc
system=system
-pio=system.iobus.port[8]
+pio=system.iobus.port[11]
[system.physmem]
type=PhysicalMemory
diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
index 18f42b689..873e1bea2 100755
--- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
+++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
@@ -1,12 +1,13 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 9 2012 20:47:38
-gem5 started Jan 9 2012 21:13:16
-gem5 executing on ribera.cs.wisc.edu
-command line: build/X86_FS/gem5.fast -d build/X86_FS/tests/fast/long/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86_FS/tests/fast/long/10.linux-boot/x86/linux/pc-o3-timing
+gem5 compiled Jan 23 2012 04:12:17
+gem5 started Jan 23 2012 08:29:15
+gem5 executing on zizzer
+command line: build/X86_FS/gem5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing
warning: add_child('terminal'): child 'terminal' already has parent
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+ 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
+info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 5161177988500 because m5_exit instruction encountered
diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
index e687ea7eb..c62526985 100644
--- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
+++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 5.161178 # Number of seconds simulated
sim_ticks 5161177988500 # Number of ticks simulated
+final_tick 5161177988500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 384526 # Simulator instruction rate (inst/s)
-host_tick_rate 2360358751 # Simulator tick rate (ticks/s)
-host_mem_usage 386468 # Number of bytes of host memory used
-host_seconds 2186.61 # Real time elapsed on the host
+host_inst_rate 290092 # Simulator instruction rate (inst/s)
+host_tick_rate 1780684720 # Simulator tick rate (ticks/s)
+host_mem_usage 364016 # Number of bytes of host memory used
+host_seconds 2898.42 # Real time elapsed on the host
sim_insts 840808469 # Number of instructions simulated
+system.physmem.bytes_read 16106624 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 1233856 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 12115136 # Number of bytes written to this memory
+system.physmem.num_reads 251666 # Number of read requests responded to by this memory
+system.physmem.num_writes 189299 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 3120726 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 239065 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 2347359 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 5468085 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 169467 # number of replacements
system.l2c.tagsinuse 38339.786444 # Cycle average of tags in use
system.l2c.total_refs 3812924 # Total number of references to valid blocks.
diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini
index 665888efd..bec9490f3 100644
--- a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -500,9 +502,9 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
+executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100
-input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
@@ -519,7 +521,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
null=false
range=0:268435455
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout
index af9fa8a65..db74d3d24 100755
--- a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 21 2011 16:28:02
-gem5 started Nov 22 2011 17:34:42
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:43:41
+gem5 executing on zizzer
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt
index b76763b67..190781128 100644
--- a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.033081 # Number of seconds simulated
sim_ticks 33080569000 # Number of ticks simulated
+final_tick 33080569000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 152633 # Simulator instruction rate (inst/s)
-host_tick_rate 55333677 # Simulator tick rate (ticks/s)
-host_mem_usage 347340 # Number of bytes of host memory used
-host_seconds 597.84 # Real time elapsed on the host
+host_inst_rate 140676 # Simulator instruction rate (inst/s)
+host_tick_rate 50998874 # Simulator tick rate (ticks/s)
+host_mem_usage 353196 # Number of bytes of host memory used
+host_seconds 648.65 # Real time elapsed on the host
sim_insts 91249885 # Number of instructions simulated
+system.physmem.bytes_read 997440 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 44864 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 2048 # Number of bytes written to this memory
+system.physmem.num_reads 15585 # Number of read requests responded to by this memory
+system.physmem.num_writes 32 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 30151839 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 1356204 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 61909 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 30213749 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini
index a584d29ed..67a5d19a5 100644
--- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=ArmTLB
@@ -61,7 +64,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
-cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic
egid=100
env=
errout=cerr
@@ -85,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
null=false
range=0:268435455
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/simerr b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simerr
index eabe42249..e45cd058f 100755
--- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simerr
@@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout
index 778a5635d..902784594 100755
--- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 12:50:38
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:47:31
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt
index 6dfbf09ec..66ab48bd5 100644
--- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt
@@ -1,76 +1,87 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1991743 # Simulator instruction rate (inst/s)
-host_mem_usage 385676 # Number of bytes of host memory used
-host_seconds 45.82 # Real time elapsed on the host
-host_tick_rate 1183885034 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 91252969 # Number of instructions simulated
sim_seconds 0.054241 # Number of seconds simulated
sim_ticks 54240666000 # Number of ticks simulated
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+final_tick 54240666000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 2777644 # Simulator instruction rate (inst/s)
+host_tick_rate 1651027932 # Simulator tick rate (ticks/s)
+host_mem_usage 342980 # Number of bytes of host memory used
+host_seconds 32.85 # Real time elapsed on the host
+sim_insts 91252969 # Number of instructions simulated
+system.physmem.bytes_read 521339715 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 431323116 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 18908138 # Number of bytes written to this memory
+system.physmem.num_reads 130384074 # Number of read requests responded to by this memory
+system.physmem.num_writes 4738868 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 9611602391 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 7952024704 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 348597084 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 9960199475 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 442 # Number of system calls
system.cpu.numCycles 108481333 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 108481333 # Number of busy cycles
-system.cpu.num_conditional_control_insts 15127614 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
-system.cpu.num_fp_insts 48 # number of float instructions
-system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
-system.cpu.num_func_calls 96832 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 91252969 # Number of instructions executed
system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
+system.cpu.num_func_calls 96832 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 15127614 # number of instructions that are conditional controls
system.cpu.num_int_insts 72525682 # number of integer instructions
+system.cpu.num_fp_insts 48 # number of float instructions
system.cpu.num_int_register_reads 396912516 # number of times the integer registers were read
system.cpu.num_int_register_writes 106840370 # number of times the integer registers were written
-system.cpu.num_load_insts 22573967 # Number of load instructions
+system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
system.cpu.num_mem_refs 27318811 # number of memory refs
+system.cpu.num_load_insts 22573967 # Number of load instructions
system.cpu.num_store_insts 4744844 # Number of store instructions
-system.cpu.workload.num_syscalls 442 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 108481333 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini
index b43580bea..2f73411a5 100644
--- a/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -164,7 +167,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
-cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing
egid=100
env=
errout=cerr
@@ -188,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
null=false
range=0:268435455
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/simerr b/tests/long/10.mcf/ref/arm/linux/simple-timing/simerr
index eabe42249..e45cd058f 100755
--- a/tests/long/10.mcf/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/simerr
@@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/10.mcf/ref/arm/linux/simple-timing/simout
index ce41a8bab..959967602 100755
--- a/tests/long/10.mcf/ref/arm/linux/simple-timing/simout
+++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 12:51:14
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:48:15
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
index 9c2d92308..d6f3be234 100644
--- a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
@@ -1,269 +1,280 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1371366 # Simulator instruction rate (inst/s)
-host_mem_usage 393424 # Number of bytes of host memory used
-host_seconds 66.52 # Real time elapsed on the host
-host_tick_rate 2226109550 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 91226321 # Number of instructions simulated
sim_seconds 0.148086 # Number of seconds simulated
sim_ticks 148086239000 # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses 3887 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits 3887 # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses 22549408 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 14013.157237 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11013.157237 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 21649219 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 12614490000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.039921 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 900189 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 9913923000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.039921 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 900189 # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses 3887 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits 3887 # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses 4734981 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 27109.399472 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24109.399472 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 4688372 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 1263542000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.009844 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 46609 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 1123715000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.009844 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 46609 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 27.825751 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 27284389 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 14657.859438 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 11657.859438 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 26337591 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 13878032000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.034701 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 946798 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 11037638000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.034701 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 946798 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0 3568.549501 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.871228 # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses 27284389 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 14657.859438 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 11657.859438 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 26337591 # number of overall hits
-system.cpu.dcache.overall_miss_latency 13878032000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.034701 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 946798 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 11037638000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.034701 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 946798 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 942702 # number of replacements
-system.cpu.dcache.sampled_refs 946798 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 3568.549501 # Cycle average of tags in use
-system.cpu.dcache.total_refs 26345365 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 54479156000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 942309 # number of writebacks
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+final_tick 148086239000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1300672 # Simulator instruction rate (inst/s)
+host_tick_rate 2111359212 # Simulator tick rate (ticks/s)
+host_mem_usage 351948 # Number of bytes of host memory used
+host_seconds 70.14 # Real time elapsed on the host
+sim_insts 91226321 # Number of instructions simulated
+system.physmem.bytes_read 986112 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 36992 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 2048 # Number of bytes written to this memory
+system.physmem.num_reads 15408 # Number of read requests responded to by this memory
+system.physmem.num_writes 32 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 6659039 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 249800 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 13830 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 6672869 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.icache.ReadReq_accesses 107830780 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 54527.545910 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 51527.545910 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 107830181 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 32662000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.demand_mshr_miss_latency 30865000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_avg_mshr_miss_latency 51527.545910 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.l2cache.Writeback_accesses 942309 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 942309 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 103.595504 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_accesses 46609 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 947397 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 947397 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate 0.000955 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate 0.312129 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.016264 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.016264 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 947397 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 931989 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 801216000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.016264 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 15408 # number of demand (read+write) misses
+system.cpu.l2cache.writebacks 32 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 860 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 14548 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 15408 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 15408 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 34400000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 581920000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 616320000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 616320000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.000955 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.312129 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.016264 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 15408 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0 325.097811 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 8910.209882 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.009921 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1 0.271918 # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses 947397 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_mshr_miss_rate 0.016264 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 931989 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 801216000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.016264 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 15408 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 616320000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.016264 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 15408 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 634 # number of replacements
-system.cpu.l2cache.sampled_refs 15392 # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 9235.307693 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1594542 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 32 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 296172478 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 296172478 # Number of busy cycles
-system.cpu.num_conditional_control_insts 15127614 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
-system.cpu.num_fp_insts 48 # number of float instructions
-system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
-system.cpu.num_func_calls 96832 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_insts 91226321 # Number of instructions executed
-system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses
-system.cpu.num_int_insts 72525682 # number of integer instructions
-system.cpu.num_int_register_reads 464563396 # number of times the integer registers were read
-system.cpu.num_int_register_writes 106840370 # number of times the integer registers were written
-system.cpu.num_load_insts 22573967 # Number of load instructions
-system.cpu.num_mem_refs 27318811 # number of memory refs
-system.cpu.num_store_insts 4744844 # Number of store instructions
-system.cpu.workload.num_syscalls 442 # Number of system calls
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
index 7b0140e7c..77055bd16 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -45,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=SparcTLB
@@ -62,7 +64,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
-cwd=build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic
+cwd=build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic
egid=100
env=
errout=cerr
@@ -86,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -96,5 +98,5 @@ latency_var=0
null=false
range=0:268435455
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout
index ef22c481f..18a19b6d7 100755
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 30 2011 17:14:16
-gem5 started Nov 30 2011 17:16:48
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 06:20:13
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
index a31e20e25..e3ffceab4 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.122216 # Number of seconds simulated
sim_ticks 122215830000 # Number of ticks simulated
+final_tick 122215830000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3705610 # Simulator instruction rate (inst/s)
-host_tick_rate 1857336235 # Simulator tick rate (ticks/s)
-host_mem_usage 328592 # Number of bytes of host memory used
-host_seconds 65.80 # Real time elapsed on the host
+host_inst_rate 3409932 # Simulator instruction rate (inst/s)
+host_tick_rate 1709135687 # Simulator tick rate (ticks/s)
+host_mem_usage 338176 # Number of bytes of host memory used
+host_seconds 71.51 # Real time elapsed on the host
sim_insts 243835278 # Number of instructions simulated
+system.physmem.bytes_read 1306360053 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 977686044 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 91606089 # Number of bytes written to this memory
+system.physmem.num_reads 326641945 # Number of read requests responded to by this memory
+system.physmem.num_writes 22901951 # Number of write requests responded to by this memory
+system.physmem.num_other 3886 # Number of other requests responded to by this memory
+system.physmem.bw_read 10688959466 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 7999667834 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 749543566 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 11438503032 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 443 # Number of system calls
system.cpu.numCycles 244431661 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
index f14a1754a..acd41b2d5 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -147,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -165,7 +167,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
-cwd=build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing
+cwd=build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing
egid=100
env=
errout=cerr
@@ -189,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -199,5 +201,5 @@ latency_var=0
null=false
range=0:268435455
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
index 5a81ca9dc..ca44a686d 100755
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 30 2011 17:14:16
-gem5 started Nov 30 2011 17:16:48
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 06:21:35
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
index cec6d8979..7dc591cfe 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.362431 # Number of seconds simulated
sim_ticks 362430887000 # Number of ticks simulated
+final_tick 362430887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1940887 # Simulator instruction rate (inst/s)
-host_tick_rate 2884887520 # Simulator tick rate (ticks/s)
-host_mem_usage 337564 # Number of bytes of host memory used
-host_seconds 125.63 # Real time elapsed on the host
+host_inst_rate 1587659 # Simulator instruction rate (inst/s)
+host_tick_rate 2359857170 # Simulator tick rate (ticks/s)
+host_mem_usage 346888 # Number of bytes of host memory used
+host_seconds 153.58 # Real time elapsed on the host
sim_insts 243835278 # Number of instructions simulated
+system.physmem.bytes_read 1001472 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 56256 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 2560 # Number of bytes written to this memory
+system.physmem.num_reads 15648 # Number of read requests responded to by this memory
+system.physmem.num_writes 40 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 2763208 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 155219 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 7063 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 2770272 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 443 # Number of system calls
system.cpu.numCycles 724861774 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini
index 103b3f085..cfda7ba22 100644
--- a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -500,9 +502,9 @@ egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
+executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
@@ -519,7 +521,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
null=false
range=0:268435455
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout
index 5b6f3a1bd..426afea0c 100755
--- a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 9 2012 14:18:02
-gem5 started Jan 9 2012 14:29:08
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 06:45:46
+gem5 executing on zizzer
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt
index 6fc7a3666..f9c970889 100644
--- a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.070313 # Number of seconds simulated
sim_ticks 70312944500 # Number of ticks simulated
+final_tick 70312944500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 109444 # Simulator instruction rate (inst/s)
-host_tick_rate 27661822 # Simulator tick rate (ticks/s)
-host_mem_usage 378996 # Number of bytes of host memory used
-host_seconds 2541.88 # Real time elapsed on the host
+host_inst_rate 168126 # Simulator instruction rate (inst/s)
+host_tick_rate 42493747 # Simulator tick rate (ticks/s)
+host_mem_usage 349904 # Number of bytes of host memory used
+host_seconds 1654.67 # Real time elapsed on the host
sim_insts 278192519 # Number of instructions simulated
+system.physmem.bytes_read 4896576 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 65344 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 1867840 # Number of bytes written to this memory
+system.physmem.num_reads 76509 # Number of read requests responded to by this memory
+system.physmem.num_writes 29185 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 69639752 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 929331 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 26564668 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 96204419 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 444 # Number of system calls
system.cpu.numCycles 140625890 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini
index aaa5a7780..96706c5cc 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -45,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=X86TLB
@@ -67,9 +69,9 @@ egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
+executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
@@ -86,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -96,5 +98,5 @@ latency_var=0
null=false
range=0:268435455
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
index c929e4789..eb189c10a 100755
--- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 9 2012 14:18:02
-gem5 started Jan 9 2012 14:29:08
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 06:52:52
+gem5 executing on zizzer
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
index 0cce68f38..e99e16cd0 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.168950 # Number of seconds simulated
sim_ticks 168950072000 # Number of ticks simulated
+final_tick 168950072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1147935 # Simulator instruction rate (inst/s)
-host_tick_rate 697156581 # Simulator tick rate (ticks/s)
-host_mem_usage 368676 # Number of bytes of host memory used
-host_seconds 242.34 # Real time elapsed on the host
+host_inst_rate 2042288 # Simulator instruction rate (inst/s)
+host_tick_rate 1240309006 # Simulator tick rate (ticks/s)
+host_mem_usage 339312 # Number of bytes of host memory used
+host_seconds 136.22 # Real time elapsed on the host
sim_insts 278192520 # Number of instructions simulated
+system.physmem.bytes_read 2458815679 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 1741569664 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 243173115 # Number of bytes written to this memory
+system.physmem.num_reads 308475658 # Number of read requests responded to by this memory
+system.physmem.num_writes 31439751 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 14553504772 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 10308191310 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 1439319393 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 15992824164 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 444 # Number of system calls
system.cpu.numCycles 337900145 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
index 2ff958baf..008adeebb 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -147,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -170,9 +172,9 @@ egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
+executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
@@ -189,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -199,5 +201,5 @@ latency_var=0
null=false
range=0:268435455
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout
index 07f15598f..e89b51a20 100755
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 9 2012 14:18:02
-gem5 started Jan 9 2012 14:29:08
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 06:55:19
+gem5 executing on zizzer
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
index 35887f197..59ae818d2 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.370011 # Number of seconds simulated
sim_ticks 370010840000 # Number of ticks simulated
+final_tick 370010840000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 588786 # Simulator instruction rate (inst/s)
-host_tick_rate 783116445 # Simulator tick rate (ticks/s)
-host_mem_usage 377276 # Number of bytes of host memory used
-host_seconds 472.49 # Real time elapsed on the host
+host_inst_rate 1163147 # Simulator instruction rate (inst/s)
+host_tick_rate 1547047043 # Simulator tick rate (ticks/s)
+host_mem_usage 348152 # Number of bytes of host memory used
+host_seconds 239.17 # Real time elapsed on the host
sim_insts 278192520 # Number of instructions simulated
+system.physmem.bytes_read 4900800 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 51712 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 1885440 # Number of bytes written to this memory
+system.physmem.num_reads 76575 # Number of read requests responded to by this memory
+system.physmem.num_writes 29460 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 13245017 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 139758 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 5095634 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 18340652 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 444 # Number of system calls
system.cpu.numCycles 740021680 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini
index bdd61e6fb..e2c071016 100644
--- a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini
@@ -19,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
@@ -478,7 +479,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -520,7 +521,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -530,5 +531,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/20.parser/ref/arm/linux/o3-timing/simout
index a9de996c2..c61c0591a 100755
--- a/tests/long/20.parser/ref/arm/linux/o3-timing/simout
+++ b/tests/long/20.parser/ref/arm/linux/o3-timing/simout
@@ -1,10 +1,8 @@
-Redirecting stdout to build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing/simout
-Redirecting stderr to build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 8 2012 22:11:51
-gem5 started Jan 9 2012 02:13:40
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:49:36
gem5 executing on zizzer
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
index 6e5455372..0cc2b2b8d 100644
--- a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.274199 # Number of seconds simulated
sim_ticks 274198757500 # Number of ticks simulated
+final_tick 274198757500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 113676 # Simulator instruction rate (inst/s)
-host_tick_rate 54365362 # Simulator tick rate (ticks/s)
-host_mem_usage 225168 # Number of bytes of host memory used
-host_seconds 5043.63 # Real time elapsed on the host
+host_inst_rate 114096 # Simulator instruction rate (inst/s)
+host_tick_rate 54566255 # Simulator tick rate (ticks/s)
+host_mem_usage 225172 # Number of bytes of host memory used
+host_seconds 5025.06 # Real time elapsed on the host
sim_insts 573341162 # Number of instructions simulated
+system.physmem.bytes_read 15248640 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 230400 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 10960192 # Number of bytes written to this memory
+system.physmem.num_reads 238260 # Number of read requests responded to by this memory
+system.physmem.num_writes 171253 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 55611631 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 840266 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 39971706 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 95583336 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini
index 8b55eca4f..cbe7d05b4 100644
--- a/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=ArmTLB
@@ -61,7 +64,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=parser 2.1.dict -batch
-cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic
egid=100
env=
errout=cerr
@@ -85,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/simerr b/tests/long/20.parser/ref/arm/linux/simple-atomic/simerr
index eabe42249..e45cd058f 100755
--- a/tests/long/20.parser/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/simerr
@@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/simout b/tests/long/20.parser/ref/arm/linux/simple-atomic/simout
index 7da122073..e26a927e8 100755
--- a/tests/long/20.parser/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 12:53:21
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:54:41
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt
index 6d10538b7..12a51d6fd 100644
--- a/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt
@@ -1,76 +1,87 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 3887693 # Simulator instruction rate (inst/s)
-host_mem_usage 256484 # Number of bytes of host memory used
-host_seconds 146.87 # Real time elapsed on the host
-host_tick_rate 1977989899 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 570968176 # Number of instructions simulated
sim_seconds 0.290499 # Number of seconds simulated
sim_ticks 290498972000 # Number of ticks simulated
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+final_tick 290498972000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 3123764 # Simulator instruction rate (inst/s)
+host_tick_rate 1589318228 # Simulator tick rate (ticks/s)
+host_mem_usage 213568 # Number of bytes of host memory used
+host_seconds 182.78 # Real time elapsed on the host
+sim_insts 570968176 # Number of instructions simulated
+system.physmem.bytes_read 2489298238 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 2066445536 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 216067624 # Number of bytes written to this memory
+system.physmem.num_reads 641840242 # Number of read requests responded to by this memory
+system.physmem.num_writes 55727847 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 8569043191 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 7113434935 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 743781028 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 9312824219 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 548 # Number of system calls
system.cpu.numCycles 580997945 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 580997945 # Number of busy cycles
-system.cpu.num_conditional_control_insts 95872736 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
-system.cpu.num_fp_insts 16 # number of float instructions
-system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_func_calls 15725605 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 570968176 # Number of instructions executed
system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
+system.cpu.num_func_calls 15725605 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 95872736 # number of instructions that are conditional controls
system.cpu.num_int_insts 470727703 # number of integer instructions
+system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_int_register_reads 2465023721 # number of times the integer registers were read
system.cpu.num_int_register_writes 646169365 # number of times the integer registers were written
-system.cpu.num_load_insts 126029556 # Number of load instructions
+system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 182890035 # number of memory refs
+system.cpu.num_load_insts 126029556 # Number of load instructions
system.cpu.num_store_insts 56860479 # Number of store instructions
-system.cpu.workload.num_syscalls 548 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 580997945 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini
index 1771ad8e9..5a2d86232 100644
--- a/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -164,7 +167,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=parser 2.1.dict -batch
-cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing
egid=100
env=
errout=cerr
@@ -188,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/simerr b/tests/long/20.parser/ref/arm/linux/simple-timing/simerr
index eabe42249..e45cd058f 100755
--- a/tests/long/20.parser/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/20.parser/ref/arm/linux/simple-timing/simerr
@@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/20.parser/ref/arm/linux/simple-timing/simout
index 3ee3b4f05..8c1353073 100755
--- a/tests/long/20.parser/ref/arm/linux/simple-timing/simout
+++ b/tests/long/20.parser/ref/arm/linux/simple-timing/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 12:55:52
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:54:55
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt
index 9f67dc057..f9d747bd5 100644
--- a/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt
@@ -1,269 +1,280 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1138464 # Simulator instruction rate (inst/s)
-host_mem_usage 264236 # Number of bytes of host memory used
-host_seconds 499.83 # Real time elapsed on the host
-host_tick_rate 1444968716 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 569034848 # Number of instructions simulated
sim_seconds 0.722234 # Number of seconds simulated
sim_ticks 722234364000 # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses 1488541 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits 1488541 # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses 123740317 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 19807.762778 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 16807.762778 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 122957659 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 15502704000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.006325 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 782658 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 13154730000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.006325 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 782658 # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses 1488541 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits 1488541 # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 28150.625947 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 25150.625947 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 53883046 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 10028942000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.006568 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 356260 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 8960162000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.006568 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 356260 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 157.884753 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 177979623 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 22417.457622 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 19417.457622 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 176840705 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 25531646000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.006399 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 1138918 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 22114892000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.006399 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 1138918 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0 4065.490059 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.992551 # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses 177979623 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 22417.457622 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 19417.457622 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 176840705 # number of overall hits
-system.cpu.dcache.overall_miss_latency 25531646000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.006399 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 1138918 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 22114892000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.006399 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 1138918 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 1134822 # number of replacements
-system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4065.490059 # Cycle average of tags in use
-system.cpu.dcache.total_refs 179817787 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 11889987000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 1025440 # number of writebacks
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+final_tick 722234364000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1518630 # Simulator instruction rate (inst/s)
+host_tick_rate 1927485562 # Simulator tick rate (ticks/s)
+host_mem_usage 222536 # Number of bytes of host memory used
+host_seconds 374.70 # Real time elapsed on the host
+sim_insts 569034848 # Number of instructions simulated
+system.physmem.bytes_read 14797056 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 188608 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 11027328 # Number of bytes written to this memory
+system.physmem.num_reads 231204 # Number of read requests responded to by this memory
+system.physmem.num_writes 172302 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 20487887 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 261145 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 15268351 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 35756238 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.icache.ReadReq_accesses 516611385 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 24743.338252 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 21743.338252 # average ReadReq mshr miss latency
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 548 # Number of system calls
+system.cpu.numCycles 1444468728 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 569034848 # Number of instructions executed
+system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
+system.cpu.num_func_calls 15725605 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 95872736 # number of instructions that are conditional controls
+system.cpu.num_int_insts 470727703 # number of integer instructions
+system.cpu.num_fp_insts 16 # number of float instructions
+system.cpu.num_int_register_reads 2844375220 # number of times the integer registers were read
+system.cpu.num_int_register_writes 646169365 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
+system.cpu.num_mem_refs 182890035 # number of memory refs
+system.cpu.num_load_insts 126029556 # Number of load instructions
+system.cpu.num_store_insts 56860479 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 1444468728 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.icache.replacements 9788 # number of replacements
+system.cpu.icache.tagsinuse 984.426148 # Cycle average of tags in use
+system.cpu.icache.total_refs 516599864 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 44839.845847 # Average number of references to valid blocks.
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+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 919235 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 12022608000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.200970 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 231204 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 9248160000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.200970 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 231204 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 212089 # number of replacements
-system.cpu.l2cache.sampled_refs 232128 # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 20443.163614 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1426644 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 513135223000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 172302 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 1444468728 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 1444468728 # Number of busy cycles
-system.cpu.num_conditional_control_insts 95872736 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
-system.cpu.num_fp_insts 16 # number of float instructions
-system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_func_calls 15725605 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_insts 569034848 # Number of instructions executed
-system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses
-system.cpu.num_int_insts 470727703 # number of integer instructions
-system.cpu.num_int_register_reads 2844375220 # number of times the integer registers were read
-system.cpu.num_int_register_writes 646169365 # number of times the integer registers were written
-system.cpu.num_load_insts 126029556 # Number of load instructions
-system.cpu.num_mem_refs 182890035 # number of memory refs
-system.cpu.num_store_insts 56860479 # Number of store instructions
-system.cpu.workload.num_syscalls 548 # Number of system calls
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini
index b2ef015f3..9cc27361f 100644
--- a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -500,9 +502,9 @@ egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
+executable=/dist/m5/cpu2000/binaries/x86/linux/parser
gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100
@@ -519,7 +521,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/20.parser/ref/x86/linux/o3-timing/simout
index f37768727..de72d963a 100755
--- a/tests/long/20.parser/ref/x86/linux/o3-timing/simout
+++ b/tests/long/20.parser/ref/x86/linux/o3-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 9 2012 14:18:02
-gem5 started Jan 9 2012 14:29:08
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 06:58:28
+gem5 executing on zizzer
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt
index 556f62c4f..92ece0bed 100644
--- a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.493912 # Number of seconds simulated
sim_ticks 493912286000 # Number of ticks simulated
+final_tick 493912286000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 108889 # Simulator instruction rate (inst/s)
-host_tick_rate 35174673 # Simulator tick rate (ticks/s)
-host_mem_usage 280548 # Number of bytes of host memory used
-host_seconds 14041.70 # Real time elapsed on the host
+host_inst_rate 145271 # Simulator instruction rate (inst/s)
+host_tick_rate 46927205 # Simulator tick rate (ticks/s)
+host_mem_usage 251468 # Number of bytes of host memory used
+host_seconds 10525.07 # Real time elapsed on the host
sim_insts 1528988756 # Number of instructions simulated
+system.physmem.bytes_read 37487424 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 347584 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 26320960 # Number of bytes written to this memory
+system.physmem.num_reads 585741 # Number of read requests responded to by this memory
+system.physmem.num_writes 411265 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 75898950 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 703736 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 53290758 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 129189708 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 551 # Number of system calls
system.cpu.numCycles 987824573 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini
index da3b012b0..b1057156b 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -45,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=X86TLB
@@ -67,9 +69,9 @@ egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
+executable=/dist/m5/cpu2000/binaries/x86/linux/parser
gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100
@@ -86,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -96,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout
index d3e847fa3..b86175ab2 100755
--- a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 9 2012 14:18:02
-gem5 started Jan 9 2012 14:29:08
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 06:59:28
+gem5 executing on zizzer
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
index c9073b3b2..4e0a10e13 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.885229 # Number of seconds simulated
sim_ticks 885229360000 # Number of ticks simulated
+final_tick 885229360000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1063398 # Simulator instruction rate (inst/s)
-host_tick_rate 615669149 # Simulator tick rate (ticks/s)
-host_mem_usage 237896 # Number of bytes of host memory used
-host_seconds 1437.83 # Real time elapsed on the host
+host_inst_rate 2258239 # Simulator instruction rate (inst/s)
+host_tick_rate 1307438877 # Simulator tick rate (ticks/s)
+host_mem_usage 208528 # Number of bytes of host memory used
+host_seconds 677.07 # Real time elapsed on the host
sim_insts 1528988757 # Number of instructions simulated
+system.physmem.bytes_read 10832432532 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 8546776872 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 991849460 # Number of bytes written to this memory
+system.physmem.num_reads 1452449298 # Number of read requests responded to by this memory
+system.physmem.num_writes 149160201 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 12236865406 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 9654872803 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 1120443475 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 13357308881 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 551 # Number of system calls
system.cpu.numCycles 1770458721 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
index e63456bf2..c570a48d2 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -147,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -170,9 +172,9 @@ egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
+executable=/dist/m5/cpu2000/binaries/x86/linux/parser
gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100
@@ -189,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -199,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/20.parser/ref/x86/linux/simple-timing/simout
index 268de88f4..a297c4bc8 100755
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/simout
+++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 9 2012 14:18:02
-gem5 started Jan 9 2012 14:29:08
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 07:10:56
+gem5 executing on zizzer
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
index a96327ae0..28d09902a 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.658730 # Number of seconds simulated
sim_ticks 1658729604000 # Number of ticks simulated
+final_tick 1658729604000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 746220 # Simulator instruction rate (inst/s)
-host_tick_rate 809539282 # Simulator tick rate (ticks/s)
-host_mem_usage 246668 # Number of bytes of host memory used
-host_seconds 2048.98 # Real time elapsed on the host
+host_inst_rate 1326745 # Simulator instruction rate (inst/s)
+host_tick_rate 1439324936 # Simulator tick rate (ticks/s)
+host_mem_usage 217512 # Number of bytes of host memory used
+host_seconds 1152.44 # Real time elapsed on the host
sim_insts 1528988757 # Number of instructions simulated
+system.physmem.bytes_read 37094976 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 148544 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 26349376 # Number of bytes written to this memory
+system.physmem.num_reads 579609 # Number of read requests responded to by this memory
+system.physmem.num_writes 411709 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 22363486 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 89553 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 15885275 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 38248761 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 551 # Number of system calls
system.cpu.numCycles 3317459208 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/inorder-timing/config.ini
index c7fe40f76..16e4d1756 100644
--- a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/inorder-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=InOrderCPU
@@ -182,7 +184,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -205,7 +207,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/eon
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
max_stack_size=67108864
@@ -224,7 +226,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -234,5 +236,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/simout b/tests/long/30.eon/ref/alpha/tru64/inorder-timing/simout
index 9794df862..1c2a18294 100755
--- a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/30.eon/ref/alpha/tru64/inorder-timing/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 8 2011 15:00:53
-gem5 started Jul 8 2011 16:09:26
-gem5 executing on u200439-lin.austin.arm.com
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:24:12
+gem5 executing on zizzer
command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
index 8f2720cda..a04efd18a 100644
--- a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
@@ -2,12 +2,22 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.139995 # Number of seconds simulated
sim_ticks 139995113500 # Number of ticks simulated
+final_tick 139995113500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 56567 # Simulator instruction rate (inst/s)
-host_tick_rate 19864025 # Simulator tick rate (ticks/s)
-host_mem_usage 252292 # Number of bytes of host memory used
-host_seconds 7047.67 # Real time elapsed on the host
+host_inst_rate 118986 # Simulator instruction rate (inst/s)
+host_tick_rate 41783300 # Simulator tick rate (ticks/s)
+host_mem_usage 214012 # Number of bytes of host memory used
+host_seconds 3350.50 # Real time elapsed on the host
sim_insts 398664595 # Number of instructions simulated
+system.physmem.bytes_read 469184 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 214784 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 7331 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 3351431 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 1534225 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 3351431 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
index 01d03e5c5..0fce2844b 100644
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -519,7 +521,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
index 46133d214..137fd0ee8 100755
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
@@ -1,10 +1,8 @@
-Redirecting stdout to build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 20 2011 16:10:02
-gem5 started Aug 20 2011 16:10:09
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:24:12
gem5 executing on zizzer
command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
index f27e3deec..28785f469 100644
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
@@ -2,12 +2,22 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.089480 # Number of seconds simulated
sim_ticks 89480174500 # Number of ticks simulated
+final_tick 89480174500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 168732 # Simulator instruction rate (inst/s)
-host_tick_rate 40200085 # Simulator tick rate (ticks/s)
-host_mem_usage 211620 # Number of bytes of host memory used
-host_seconds 2225.87 # Real time elapsed on the host
+host_inst_rate 190161 # Simulator instruction rate (inst/s)
+host_tick_rate 45305657 # Simulator tick rate (ticks/s)
+host_mem_usage 214676 # Number of bytes of host memory used
+host_seconds 1975.03 # Real time elapsed on the host
sim_insts 375574794 # Number of instructions simulated
+system.physmem.bytes_read 475840 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 219968 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 7435 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 5317826 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 2458288 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 5317826 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
index 5f40a4aa8..8310ba9e4 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=AlphaTLB
@@ -61,7 +64,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic
+cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-atomic
egid=100
env=
errout=cerr
@@ -85,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr
index ea7dd73a3..860580eeb 100755
--- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr
@@ -1,11 +1,7 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
getting pixel output filename pixels_out.cook
opening control file chair.control.cook
opening camera file chair.camera
@@ -53,5 +49,4 @@ Writing to chair.cook.ppm
13 8 14
14 8 14
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-For more information see: http://www.m5sim.org/warn/5c5b547f
hack: be nice to actually delete the event here
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout
index 0fd1f360f..3a628f576 100755
--- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 11:52:53
-M5 started Apr 19 2011 12:03:34
-M5 executing on maize
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:24:12
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
index 6655c3650..3ed2b47f1 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,66 +1,77 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 5567399 # Simulator instruction rate (inst/s)
-host_mem_usage 202284 # Number of bytes of host memory used
-host_seconds 71.61 # Real time elapsed on the host
-host_tick_rate 2783694716 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 398664595 # Number of instructions simulated
sim_seconds 0.199332 # Number of seconds simulated
sim_ticks 199332411500 # Number of ticks simulated
-system.cpu.dtb.data_accesses 168275274 # DTB accesses
-system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_hits 168275218 # DTB hits
-system.cpu.dtb.data_misses 56 # DTB misses
-system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.fetch_acv 0 # ITB acv
+final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 3927016 # Simulator instruction rate (inst/s)
+host_tick_rate 1963508553 # Simulator tick rate (ticks/s)
+host_mem_usage 204908 # Number of bytes of host memory used
+host_seconds 101.52 # Real time elapsed on the host
+sim_insts 398664595 # Number of instructions simulated
+system.physmem.bytes_read 2257107875 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 1594658604 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 492356798 # Number of bytes written to this memory
+system.physmem.num_reads 493419140 # Number of read requests responded to by this memory
+system.physmem.num_writes 73520729 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 11323336020 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 7999996548 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 2470028804 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 13793364824 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.read_accesses 94754510 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 94754489 # DTB read hits
system.cpu.dtb.read_misses 21 # DTB read misses
-system.cpu.dtb.write_accesses 73520764 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_accesses 94754510 # DTB read accesses
system.cpu.dtb.write_hits 73520729 # DTB write hits
system.cpu.dtb.write_misses 35 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.itb.data_acv 0 # DTB access violations
-system.cpu.itb.data_hits 0 # DTB hits
-system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.fetch_accesses 398664824 # ITB accesses
-system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_accesses 73520764 # DTB write accesses
+system.cpu.dtb.data_hits 168275218 # DTB hits
+system.cpu.dtb.data_misses 56 # DTB misses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_accesses 168275274 # DTB accesses
system.cpu.itb.fetch_hits 398664651 # ITB hits
system.cpu.itb.fetch_misses 173 # ITB misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_accesses 398664824 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 215 # Number of system calls
system.cpu.numCycles 398664824 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 398664824 # Number of busy cycles
-system.cpu.num_conditional_control_insts 25997787 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses
-system.cpu.num_fp_insts 155295119 # number of float instructions
-system.cpu.num_fp_register_reads 151776196 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 100196481 # number of times the floating registers were written
-system.cpu.num_func_calls 16015498 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 398664595 # Number of instructions executed
system.cpu.num_int_alu_accesses 316365907 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses
+system.cpu.num_func_calls 16015498 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 25997787 # number of instructions that are conditional controls
system.cpu.num_int_insts 316365907 # number of integer instructions
+system.cpu.num_fp_insts 155295119 # number of float instructions
system.cpu.num_int_register_reads 372938760 # number of times the integer registers were read
system.cpu.num_int_register_writes 159335860 # number of times the integer registers were written
-system.cpu.num_load_insts 94754510 # Number of load instructions
+system.cpu.num_fp_register_reads 151776196 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 100196481 # number of times the floating registers were written
system.cpu.num_mem_refs 168275274 # number of memory refs
+system.cpu.num_load_insts 94754510 # Number of load instructions
system.cpu.num_store_insts 73520764 # Number of store instructions
-system.cpu.workload.num_syscalls 215 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 398664824 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
index c222d6133..63aac5a1a 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -164,7 +167,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing
+cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
@@ -188,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr
index ea7dd73a3..860580eeb 100755
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr
@@ -1,11 +1,7 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
getting pixel output filename pixels_out.cook
opening control file chair.control.cook
opening camera file chair.camera
@@ -53,5 +49,4 @@ Writing to chair.cook.ppm
13 8 14
14 8 14
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-For more information see: http://www.m5sim.org/warn/5c5b547f
hack: be nice to actually delete the event here
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
index 2be6be9ef..06075d86e 100755
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 11:52:53
-M5 started Apr 19 2011 12:04:03
-M5 executing on maize
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:24:12
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
index 94a73b71f..af7a7f90d 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,255 +1,265 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 2583171 # Simulator instruction rate (inst/s)
-host_mem_usage 210032 # Number of bytes of host memory used
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-host_tick_rate 3676130341 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 398664609 # Number of instructions simulated
sim_seconds 0.567343 # Number of seconds simulated
sim_ticks 567343170000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 94754490 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 50827.368421 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 47827.368421 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 94753540 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 48286000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 950 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 45436000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 73520730 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55212.991880 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52212.991880 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 73517528 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 176792000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.000044 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 3202 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 167186000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 3202 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dtb.write_misses 35 # DTB write misses
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+system.cpu.dcache.demand_mshr_misses 4152 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 4152 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 45436000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 167186000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 212622000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 212622000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 47827.368421 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52212.991880 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 51209.537572 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 51209.537572 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 13 # number of replacements
+system.cpu.l2cache.tagsinuse 3768.712262 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 656 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 4572 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.143482 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 3397.175455 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 371.536808 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.103674 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.011338 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits 585 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits 649 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 60 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency 163384000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 0.981262 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_hits 645 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 645 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 4038 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 3142 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 125680000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.981262 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 3142 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 4623 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 585 # number of ReadReq hits
+system.cpu.l2cache.demand_misses 7180 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 7180 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 209976000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.873459 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 4038 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 161520000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.873459 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 4038 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_miss_latency 163384000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 373360000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 373360000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 4623 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 649 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 649 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.143482 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_accesses 3202 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 7825 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 7825 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate 0.873459 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate 0.981262 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.917572 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.917572 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 7825 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 645 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 373360000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.917572 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 7180 # number of demand (read+write) misses
+system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 4038 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 3142 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 7180 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 7180 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 161520000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 125680000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 287200000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 287200000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.873459 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.981262 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.917572 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 7180 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0 3397.175455 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 371.536808 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.103674 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1 0.011338 # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses 7825 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_mshr_miss_rate 0.917572 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 645 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 373360000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.917572 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 7180 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 287200000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.917572 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 7180 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 13 # number of replacements
-system.cpu.l2cache.sampled_refs 4572 # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 3768.712262 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 656 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 1134686340 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 1134686340 # Number of busy cycles
-system.cpu.num_conditional_control_insts 25997790 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses
-system.cpu.num_fp_insts 155295119 # number of float instructions
-system.cpu.num_fp_register_reads 151776196 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 100196481 # number of times the floating registers were written
-system.cpu.num_func_calls 16015498 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_insts 398664609 # Number of instructions executed
-system.cpu.num_int_alu_accesses 316365921 # Number of integer alu accesses
-system.cpu.num_int_insts 316365921 # number of integer instructions
-system.cpu.num_int_register_reads 372938779 # number of times the integer registers were read
-system.cpu.num_int_register_writes 159335870 # number of times the integer registers were written
-system.cpu.num_load_insts 94754511 # Number of load instructions
-system.cpu.num_mem_refs 168275276 # number of memory refs
-system.cpu.num_store_insts 73520765 # Number of store instructions
-system.cpu.workload.num_syscalls 215 # Number of system calls
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini
index 8c023b5bc..297538e80 100644
--- a/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -500,7 +502,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/eon
+executable=/dist/m5/cpu2000/binaries/arm/linux/eon
gid=100
input=cin
max_stack_size=67108864
@@ -519,7 +521,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/30.eon/ref/arm/linux/o3-timing/simout
index 5bda3e9bb..2948fc7c4 100755
--- a/tests/long/30.eon/ref/arm/linux/o3-timing/simout
+++ b/tests/long/30.eon/ref/arm/linux/o3-timing/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 21 2011 16:28:02
-gem5 started Nov 22 2011 17:59:30
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:57:55
+gem5 executing on zizzer
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt
index 3a7bc5069..995432cc7 100644
--- a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt
@@ -2,12 +2,22 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.104498 # Number of seconds simulated
sim_ticks 104497559500 # Number of ticks simulated
+final_tick 104497559500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 166687 # Simulator instruction rate (inst/s)
-host_tick_rate 49899949 # Simulator tick rate (ticks/s)
-host_mem_usage 223124 # Number of bytes of host memory used
-host_seconds 2094.14 # Real time elapsed on the host
+host_inst_rate 155883 # Simulator instruction rate (inst/s)
+host_tick_rate 46665641 # Simulator tick rate (ticks/s)
+host_mem_usage 228988 # Number of bytes of host memory used
+host_seconds 2239.28 # Real time elapsed on the host
sim_insts 349066034 # Number of instructions simulated
+system.physmem.bytes_read 464512 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 192704 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 7258 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 4445195 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 1844100 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 4445195 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini
index a5b41f00b..5628f29f0 100644
--- a/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=ArmTLB
@@ -61,7 +64,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic
egid=100
env=
errout=cerr
@@ -85,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/simerr b/tests/long/30.eon/ref/arm/linux/simple-atomic/simerr
index 0de362399..bf930ad43 100755
--- a/tests/long/30.eon/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/simerr
@@ -1,5 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
getting pixel output filename pixels_out.cook
opening control file chair.control.cook
opening camera file chair.camera
diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/30.eon/ref/arm/linux/simple-atomic/simout
index e711f37f2..2369bef1b 100755
--- a/tests/long/30.eon/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 12:58:30
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:01:21
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt
index 01b0f0b3b..7857a9031 100644
--- a/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt
@@ -1,76 +1,87 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1939083 # Simulator instruction rate (inst/s)
-host_mem_usage 261408 # Number of bytes of host memory used
-host_seconds 180.02 # Real time elapsed on the host
-host_tick_rate 1179584644 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 349065408 # Number of instructions simulated
sim_seconds 0.212344 # Number of seconds simulated
sim_ticks 212344048000 # Number of ticks simulated
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+final_tick 212344048000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 2434260 # Simulator instruction rate (inst/s)
+host_tick_rate 1480812932 # Simulator tick rate (ticks/s)
+host_mem_usage 218160 # Number of bytes of host memory used
+host_seconds 143.40 # Real time elapsed on the host
+sim_insts 349065408 # Number of instructions simulated
+system.physmem.bytes_read 1875350709 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 1394641440 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 400047783 # Number of bytes written to this memory
+system.physmem.num_reads 443242866 # Number of read requests responded to by this memory
+system.physmem.num_writes 82063572 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 8831661291 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 6567838624 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 1883960425 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 10715621716 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 191 # Number of system calls
system.cpu.numCycles 424688097 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 424688097 # Number of busy cycles
-system.cpu.num_conditional_control_insts 16271154 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
-system.cpu.num_fp_insts 114216705 # number of float instructions
-system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
-system.cpu.num_func_calls 12433363 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 349065408 # Number of instructions executed
system.cpu.num_int_alu_accesses 279584926 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
+system.cpu.num_func_calls 12433363 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 16271154 # number of instructions that are conditional controls
system.cpu.num_int_insts 279584926 # number of integer instructions
+system.cpu.num_fp_insts 114216705 # number of float instructions
system.cpu.num_int_register_reads 1887652191 # number of times the integer registers were read
system.cpu.num_int_register_writes 251197918 # number of times the integer registers were written
-system.cpu.num_load_insts 94648758 # Number of load instructions
+system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
system.cpu.num_mem_refs 177024357 # number of memory refs
+system.cpu.num_load_insts 94648758 # Number of load instructions
system.cpu.num_store_insts 82375599 # Number of store instructions
-system.cpu.workload.num_syscalls 191 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 424688097 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini
index aed18b872..28a0917d8 100644
--- a/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -164,7 +167,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing
egid=100
env=
errout=cerr
@@ -188,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/simerr b/tests/long/30.eon/ref/arm/linux/simple-timing/simerr
index 0de362399..bf930ad43 100755
--- a/tests/long/30.eon/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/30.eon/ref/arm/linux/simple-timing/simerr
@@ -1,5 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
getting pixel output filename pixels_out.cook
opening control file chair.control.cook
opening camera file chair.camera
diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/30.eon/ref/arm/linux/simple-timing/simout
index daf6c8759..3428f8224 100755
--- a/tests/long/30.eon/ref/arm/linux/simple-timing/simout
+++ b/tests/long/30.eon/ref/arm/linux/simple-timing/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 13:00:20
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:03:55
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt
index 1ba27a33f..3b365c759 100644
--- a/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt
@@ -1,269 +1,279 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1262416 # Simulator instruction rate (inst/s)
-host_mem_usage 269124 # Number of bytes of host memory used
-host_seconds 276.21 # Real time elapsed on the host
-host_tick_rate 1903846429 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 348687131 # Number of instructions simulated
sim_seconds 0.525854 # Number of seconds simulated
sim_ticks 525854475000 # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses 10895 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits 10895 # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses 94571611 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 49749.688667 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 46749.688667 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 94570005 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 79898000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.000017 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 1606 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 75080000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.000017 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 1606 # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses 10895 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits 10895 # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses 82052677 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55766.016713 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52766.016713 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 82049805 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 160160000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.000035 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 2872 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 151544000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000035 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 2872 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 39446.538633 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 176624288 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 53608.307280 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 50608.307280 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 176619810 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 240058000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 4478 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 226624000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 4478 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0 3078.396238 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.751562 # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses 176624288 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 53608.307280 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 50608.307280 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 176619810 # number of overall hits
-system.cpu.dcache.overall_miss_latency 240058000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 4478 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 226624000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 4478 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 1332 # number of replacements
-system.cpu.dcache.sampled_refs 4478 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 3078.396238 # Cycle average of tags in use
-system.cpu.dcache.total_refs 176641600 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 998 # number of writebacks
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+final_tick 525854475000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1206167 # Simulator instruction rate (inst/s)
+host_tick_rate 1819018700 # Simulator tick rate (ticks/s)
+host_mem_usage 227092 # Number of bytes of host memory used
+host_seconds 289.09 # Real time elapsed on the host
+sim_insts 348687131 # Number of instructions simulated
+system.physmem.bytes_read 437312 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 167040 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 6833 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 831622 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 317654 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 831622 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.icache.ReadReq_accesses 348660359 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 21025.572005 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 18025.572005 # average ReadReq mshr miss latency
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.icache.ReadReq_hits 348644756 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 328062000 # number of ReadReq miss cycles
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system.cpu.icache.demand_mshr_miss_latency 281253000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_avg_mshr_miss_latency 18025.572005 # average overall mshr miss latency
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-system.cpu.itb.misses 0 # DTB misses
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+system.cpu.l2cache.overall_mshr_miss_latency 273320000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.231100 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.994429 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.340272 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 6833 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0 3134.059650 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 341.613272 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.095644 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1 0.010425 # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses 20081 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_mshr_miss_rate 0.340272 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 13248 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 355316000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.340272 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 6833 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 273320000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.340272 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 6833 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 48 # number of replacements
-system.cpu.l2cache.sampled_refs 4883 # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 3475.672922 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 13308 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 1051708950 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 1051708950 # Number of busy cycles
-system.cpu.num_conditional_control_insts 16271153 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
-system.cpu.num_fp_insts 114216705 # number of float instructions
-system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
-system.cpu.num_func_calls 12433363 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_insts 348687131 # Number of instructions executed
-system.cpu.num_int_alu_accesses 279584925 # Number of integer alu accesses
-system.cpu.num_int_insts 279584925 # number of integer instructions
-system.cpu.num_int_register_reads 2212913209 # number of times the integer registers were read
-system.cpu.num_int_register_writes 251197915 # number of times the integer registers were written
-system.cpu.num_load_insts 94648758 # Number of load instructions
-system.cpu.num_mem_refs 177024357 # number of memory refs
-system.cpu.num_store_insts 82375599 # Number of store instructions
-system.cpu.workload.num_syscalls 191 # Number of system calls
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
index 7c1b2f7e5..c87170fbe 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -519,7 +521,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
index ec96cb05b..2a099e16b 100755
--- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 20 2011 16:10:02
-gem5 started Aug 20 2011 21:33:28
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:26:04
gem5 executing on zizzer
-command line: ./build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
index c68641234..90210da82 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.643030 # Number of seconds simulated
sim_ticks 643030478500 # Number of ticks simulated
+final_tick 643030478500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 153773 # Simulator instruction rate (inst/s)
-host_tick_rate 54239400 # Simulator tick rate (ticks/s)
-host_mem_usage 218648 # Number of bytes of host memory used
-host_seconds 11855.41 # Real time elapsed on the host
+host_inst_rate 153915 # Simulator instruction rate (inst/s)
+host_tick_rate 54289503 # Simulator tick rate (ticks/s)
+host_mem_usage 215008 # Number of bytes of host memory used
+host_seconds 11844.47 # Real time elapsed on the host
sim_insts 1823043370 # Number of instructions simulated
+system.physmem.bytes_read 94779264 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 185664 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 4281472 # Number of bytes written to this memory
+system.physmem.num_reads 1480926 # Number of read requests responded to by this memory
+system.physmem.num_writes 66898 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 147394668 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 288733 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 6658272 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 154052940 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
index f80631f28..a895468a4 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=AlphaTLB
@@ -61,7 +64,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic
+cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-atomic
egid=100
env=
errout=cerr
@@ -85,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
index c5f9e3fdc..67c7a90bd 100755
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 19 2011 06:59:13
-gem5 started Jun 20 2011 12:33:29
-gem5 executing on m60-009.pool
-command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:26:36
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
index b6ea3474a..5a9e50b92 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.004711 # Number of seconds simulated
sim_ticks 1004710587000 # Number of ticks simulated
+final_tick 1004710587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3394241 # Simulator instruction rate (inst/s)
-host_tick_rate 1697486503 # Simulator tick rate (ticks/s)
-host_mem_usage 190248 # Number of bytes of host memory used
-host_seconds 591.88 # Real time elapsed on the host
+host_inst_rate 4051601 # Simulator instruction rate (inst/s)
+host_tick_rate 2026237516 # Simulator tick rate (ticks/s)
+host_mem_usage 204820 # Number of bytes of host memory used
+host_seconds 495.85 # Real time elapsed on the host
sim_insts 2008987605 # Number of instructions simulated
+system.physmem.bytes_read 11607100996 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 8037684280 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 1586125963 # Number of bytes written to this memory
+system.physmem.num_reads 2520491096 # Number of read requests responded to by this memory
+system.physmem.num_writes 210794896 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 11552681087 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 7999999586 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 1578689409 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 13131370496 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
index d0df4a5be..f60b78837 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -164,7 +167,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing
+cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
@@ -188,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout
index 8bb74946d..e767ec1c4 100755
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 19 2011 06:59:13
-gem5 started Jun 20 2011 13:15:24
-gem5 executing on m60-009.pool
-command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:28:03
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
index eed39f9d4..668a6f1dd 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.813468 # Number of seconds simulated
sim_ticks 2813467842000 # Number of ticks simulated
+final_tick 2813467842000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1436300 # Simulator instruction rate (inst/s)
-host_tick_rate 2011453251 # Simulator tick rate (ticks/s)
-host_mem_usage 198964 # Number of bytes of host memory used
-host_seconds 1398.72 # Real time elapsed on the host
+host_inst_rate 1954286 # Simulator instruction rate (inst/s)
+host_tick_rate 2736861040 # Simulator tick rate (ticks/s)
+host_mem_usage 213480 # Number of bytes of host memory used
+host_seconds 1027.99 # Real time elapsed on the host
sim_insts 2008987605 # Number of instructions simulated
+system.physmem.bytes_read 94708160 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 152128 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 4281472 # Number of bytes written to this memory
+system.physmem.num_reads 1479815 # Number of read requests responded to by this memory
+system.physmem.num_writes 66898 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 33662428 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 54071 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 1521777 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 35184206 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini
index eaf32daa6..7e5e4838d 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -500,7 +502,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk
+executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
gid=100
input=cin
max_stack_size=67108864
@@ -519,7 +521,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout
index fc03e6958..af8b043ac 100755
--- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout
+++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 21 2011 16:28:02
-gem5 started Nov 22 2011 18:31:45
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:08:55
+gem5 executing on zizzer
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
index e47b3cac2..7b72f7ce4 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.708403 # Number of seconds simulated
sim_ticks 708403313500 # Number of ticks simulated
+final_tick 708403313500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 129621 # Simulator instruction rate (inst/s)
-host_tick_rate 48704258 # Simulator tick rate (ticks/s)
-host_mem_usage 220728 # Number of bytes of host memory used
-host_seconds 14545.00 # Real time elapsed on the host
+host_inst_rate 118434 # Simulator instruction rate (inst/s)
+host_tick_rate 44501063 # Simulator tick rate (ticks/s)
+host_mem_usage 226576 # Number of bytes of host memory used
+host_seconds 15918.80 # Real time elapsed on the host
sim_insts 1885333786 # Number of instructions simulated
+system.physmem.bytes_read 94812032 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 200960 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 4230336 # Number of bytes written to this memory
+system.physmem.num_reads 1481438 # Number of read requests responded to by this memory
+system.physmem.num_writes 66099 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 133839058 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 283680 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 5971649 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 139810707 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
index 97cb6c6e4..6a275dc9a 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=ArmTLB
@@ -61,7 +64,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic
egid=100
env=
errout=cerr
@@ -85,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simerr b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simerr
index 805a6606f..cba73e085 100755
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simerr
@@ -1,5 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
warn: fcntl64(3, 2) passed through to host
-For more information see: http://www.m5sim.org/warn/a55e2c46
hack: be nice to actually delete the event here
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout
index 343cd2a25..dd29e750e 100755
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 13:03:45
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:17:45
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
index 9d864db40..49ae2817e 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
@@ -1,76 +1,87 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1799997 # Simulator instruction rate (inst/s)
-host_mem_usage 258316 # Number of bytes of host memory used
-host_seconds 1047.41 # Real time elapsed on the host
-host_tick_rate 902810159 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1885336367 # Number of instructions simulated
sim_seconds 0.945613 # Number of seconds simulated
sim_ticks 945613131000 # Number of ticks simulated
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+final_tick 945613131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 2997522 # Simulator instruction rate (inst/s)
+host_tick_rate 1503443037 # Simulator tick rate (ticks/s)
+host_mem_usage 215364 # Number of bytes of host memory used
+host_seconds 628.97 # Real time elapsed on the host
+sim_insts 1885336367 # Number of instructions simulated
+system.physmem.bytes_read 8025491315 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 5561086040 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 1123958396 # Number of bytes written to this memory
+system.physmem.num_reads 2010616909 # Number of read requests responded to by this memory
+system.physmem.num_writes 276945663 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 8487076852 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 5880931491 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 1188602780 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 9675679632 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 1411 # Number of system calls
system.cpu.numCycles 1891226263 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 1891226263 # Number of busy cycles
-system.cpu.num_conditional_control_insts 223625914 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses
-system.cpu.num_fp_insts 52289415 # number of float instructions
-system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written
-system.cpu.num_func_calls 80344203 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 1885336367 # Number of instructions executed
system.cpu.num_int_alu_accesses 1653698876 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses
+system.cpu.num_func_calls 80344203 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 223625914 # number of instructions that are conditional controls
system.cpu.num_int_insts 1653698876 # number of integer instructions
+system.cpu.num_fp_insts 52289415 # number of float instructions
system.cpu.num_int_register_reads 8601515950 # number of times the integer registers were read
system.cpu.num_int_register_writes 1874331406 # number of times the integer registers were written
-system.cpu.num_load_insts 631387182 # Number of load instructions
+system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written
system.cpu.num_mem_refs 908382480 # number of memory refs
+system.cpu.num_load_insts 631387182 # Number of load instructions
system.cpu.num_store_insts 276995298 # Number of store instructions
-system.cpu.workload.num_syscalls 1411 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 1891226263 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini
index f566d5f40..01aaafc03 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -164,7 +167,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing
egid=100
env=
errout=cerr
@@ -188,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr
index 805a6606f..cba73e085 100755
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr
@@ -1,5 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
warn: fcntl64(3, 2) passed through to host
-For more information see: http://www.m5sim.org/warn/a55e2c46
hack: be nice to actually delete the event here
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout
index 5a9581642..df0dd80b9 100755
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 13:11:59
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:28:26
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
index fd9599dfa..117215dc5 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
@@ -1,269 +1,280 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 933614 # Simulator instruction rate (inst/s)
-host_mem_usage 266072 # Number of bytes of host memory used
-host_seconds 2007.52 # Real time elapsed on the host
-host_tick_rate 1180515097 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1874244950 # Number of instructions simulated
sim_seconds 2.369902 # Number of seconds simulated
sim_ticks 2369901960000 # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses 9985 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits 9985 # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses 620335414 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 54574.204602 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 51574.204602 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 618874541 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 79725982000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.002355 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 1460873 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 75343363000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.002355 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 1460873 # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses 9985 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits 9985 # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses 276935678 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 52141.055235 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49141.055235 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 276862898 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 3794826000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.000263 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 72780 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 3576486000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000263 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 72780 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 584.067849 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 897271092 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 54458.738711 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 51458.738711 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 895737439 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 83520808000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.001709 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 1533653 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 78919849000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.001709 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 1533653 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0 4094.960333 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.999746 # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses 897271092 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 54458.738711 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 51458.738711 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 895737439 # number of overall hits
-system.cpu.dcache.overall_miss_latency 83520808000 # number of overall miss cycles
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-system.cpu.dcache.overall_misses 1533653 # number of overall misses
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-system.cpu.dcache.overall_mshr_miss_rate 0.001709 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 1533653 # number of overall MSHR misses
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-system.cpu.dcache.replacements 1529557 # number of replacements
-system.cpu.dcache.sampled_refs 1533653 # Sample count of references to valid blocks.
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-system.cpu.dcache.tagsinuse 4094.960333 # Cycle average of tags in use
-system.cpu.dcache.total_refs 895757409 # Total number of references to valid blocks.
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-system.cpu.dcache.writebacks 107259 # number of writebacks
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-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+final_tick 2369901960000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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+host_inst_rate 1407810 # Simulator instruction rate (inst/s)
+host_tick_rate 1780114775 # Simulator tick rate (ticks/s)
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+host_seconds 1331.32 # Real time elapsed on the host
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+system.physmem.bytes_inst_read 144448 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 4230336 # Number of bytes written to this memory
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+system.physmem.bw_read 39957906 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 60951 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 1785026 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 41742932 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.icache.ReadReq_accesses 1390271511 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 18786.850477 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 15786.850477 # average ReadReq mshr miss latency
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+system.cpu.itb.accesses 0 # DTB accesses
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+system.cpu.numCycles 4739803920 # number of cpu cycles simulated
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+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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+system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses
+system.cpu.num_func_calls 80344203 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 223625914 # number of instructions that are conditional controls
+system.cpu.num_int_insts 1653698876 # number of integer instructions
+system.cpu.num_fp_insts 52289415 # number of float instructions
+system.cpu.num_int_register_reads 10466679954 # number of times the integer registers were read
+system.cpu.num_int_register_writes 1874331406 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written
+system.cpu.num_mem_refs 908382480 # number of memory refs
+system.cpu.num_load_insts 631387182 # Number of load instructions
+system.cpu.num_store_insts 276995298 # Number of store instructions
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+system.cpu.num_busy_cycles 4739803920 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
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+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 1392.324437 # Average occupied blocks per context
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system.cpu.icache.ReadReq_hits 1390251708 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 372036000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 19803 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 312627000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 19803 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 70204.095743 # Average number of references to valid blocks.
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-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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+system.cpu.icache.ReadReq_avg_miss_latency 18786.850477 # average ReadReq miss latency
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+system.cpu.icache.overall_avg_miss_latency 18786.850477 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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-system.cpu.icache.demand_avg_miss_latency 18786.850477 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 15786.850477 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1390251708 # number of demand (read+write) hits
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 312627000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses
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-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0 1392.324437 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.679846 # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses 1390271511 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 18786.850477 # average overall miss latency
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency 15786.850477 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 15786.850477 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 15786.850477 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1390251708 # number of overall hits
-system.cpu.icache.overall_miss_latency 372036000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000014 # miss rate for overall accesses
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-system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses
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-system.cpu.icache.replacements 18364 # number of replacements
-system.cpu.icache.sampled_refs 19803 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1392.324437 # Cycle average of tags in use
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-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.inst_hits 0 # ITB inst hits
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-system.cpu.itb.misses 0 # DTB misses
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-system.cpu.itb.read_accesses 0 # DTB read accesses
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-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses 72780 # number of ReadExReq accesses(hits+misses)
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-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu.dcache.tagsinuse 4094.960333 # Cycle average of tags in use
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+system.cpu.dcache.ReadReq_avg_miss_latency 54574.204602 # average ReadReq miss latency
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+system.cpu.dcache.overall_avg_miss_latency 54458.738711 # average overall miss latency
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+system.cpu.dcache.ReadReq_mshr_miss_latency 75343363000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 3576486000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 78919849000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 78919849000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.002355 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000263 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate 0.001709 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate 0.001709 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 51574.204602 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49141.055235 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 51458.738711 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 51458.738711 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 1478755 # number of replacements
+system.cpu.l2cache.tagsinuse 31934.844118 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 75453 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 1511475 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.049920 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 28893.420796 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 3041.423322 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.881757 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.092817 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits 67139 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits 107259 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 6687 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency 3436836000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 0.908120 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_hits 73826 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 73826 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 1413537 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 66093 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2643720000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908120 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 66093 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 1480676 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 67139 # number of ReadReq hits
+system.cpu.l2cache.demand_misses 1479630 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 1479630 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 73503924000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.954657 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 1413537 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 56541480000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.954657 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 1413537 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_miss_latency 3436836000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 76940760000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 76940760000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 1480676 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 107259 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 107259 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.049920 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_accesses 72780 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 1553456 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 1553456 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate 0.954657 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate 0.908120 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.952476 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.952476 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 1553456 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 73826 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 76940760000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.952476 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 1479630 # number of demand (read+write) misses
+system.cpu.l2cache.writebacks 66099 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 1413537 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 66093 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 1479630 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 1479630 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 56541480000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 2643720000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 59185200000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 59185200000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.954657 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908120 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.952476 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 1479630 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0 28893.420796 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 3041.423322 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.881757 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1 0.092817 # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses 1553456 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_mshr_miss_rate 0.952476 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 73826 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 76940760000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.952476 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 1479630 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 59185200000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.952476 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 1479630 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 1478755 # number of replacements
-system.cpu.l2cache.sampled_refs 1511475 # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 31934.844118 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 75453 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 66099 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 4739803920 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 4739803920 # Number of busy cycles
-system.cpu.num_conditional_control_insts 223625914 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses
-system.cpu.num_fp_insts 52289415 # number of float instructions
-system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written
-system.cpu.num_func_calls 80344203 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_insts 1874244950 # Number of instructions executed
-system.cpu.num_int_alu_accesses 1653698876 # Number of integer alu accesses
-system.cpu.num_int_insts 1653698876 # number of integer instructions
-system.cpu.num_int_register_reads 10466679954 # number of times the integer registers were read
-system.cpu.num_int_register_writes 1874331406 # number of times the integer registers were written
-system.cpu.num_load_insts 631387182 # Number of load instructions
-system.cpu.num_mem_refs 908382480 # number of memory refs
-system.cpu.num_store_insts 276995298 # Number of store instructions
-system.cpu.workload.num_syscalls 1411 # Number of system calls
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
index e20a60e8c..1b963b10c 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=InOrderCPU
@@ -182,7 +184,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -205,7 +207,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
max_stack_size=67108864
@@ -224,7 +226,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -234,5 +236,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
index a3cf9c876..0aab67a06 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 8 2011 15:00:53
-gem5 started Jul 8 2011 16:45:59
-gem5 executing on u200439-lin.austin.arm.com
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:28:56
+gem5 executing on zizzer
command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
index a84fb4906..32a07ce20 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.046914 # Number of seconds simulated
sim_ticks 46914279500 # Number of ticks simulated
+final_tick 46914279500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 53929 # Simulator instruction rate (inst/s)
-host_tick_rate 28639497 # Simulator tick rate (ticks/s)
-host_mem_usage 254456 # Number of bytes of host memory used
-host_seconds 1638.10 # Real time elapsed on the host
+host_inst_rate 107347 # Simulator instruction rate (inst/s)
+host_tick_rate 57007816 # Simulator tick rate (ticks/s)
+host_mem_usage 216192 # Number of bytes of host memory used
+host_seconds 822.94 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
+system.physmem.bytes_read 11164096 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 599296 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 7712960 # Number of bytes written to this memory
+system.physmem.num_reads 174439 # Number of read requests responded to by this memory
+system.physmem.num_writes 120515 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 237967973 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 12774277 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 164405381 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 402373354 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
index 2f92d3206..ea038d4da 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -519,7 +521,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
index 6c1f5182e..9e435cc97 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
@@ -1,10 +1,8 @@
-Redirecting stdout to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 20 2011 16:10:02
-gem5 started Aug 20 2011 16:10:08
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:35:02
gem5 executing on zizzer
command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
index a5baa0129..9c4b77b7d 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.021260 # Number of seconds simulated
sim_ticks 21259532000 # Number of ticks simulated
+final_tick 21259532000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 184165 # Simulator instruction rate (inst/s)
-host_tick_rate 49191900 # Simulator tick rate (ticks/s)
-host_mem_usage 214460 # Number of bytes of host memory used
-host_seconds 432.18 # Real time elapsed on the host
+host_inst_rate 187781 # Simulator instruction rate (inst/s)
+host_tick_rate 50157547 # Simulator tick rate (ticks/s)
+host_mem_usage 217440 # Number of bytes of host memory used
+host_seconds 423.86 # Real time elapsed on the host
sim_insts 79591756 # Number of instructions simulated
+system.physmem.bytes_read 11229312 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 642688 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 7713344 # Number of bytes written to this memory
+system.physmem.num_reads 175458 # Number of read requests responded to by this memory
+system.physmem.num_writes 120521 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 528201279 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 30230581 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 362818147 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 891019426 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
index d98970549..d8535707b 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=AlphaTLB
@@ -61,7 +64,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
-cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic
+cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-atomic
egid=100
env=
errout=cerr
@@ -85,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
index c4b225cf1..160c80ddb 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 19 2011 06:59:13
-gem5 started Jun 20 2011 12:18:39
-gem5 executing on m60-009.pool
-command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:42:17
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
index 1ca39fde6..4fc91e266 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.044221 # Number of seconds simulated
sim_ticks 44221003000 # Number of ticks simulated
+final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3266324 # Simulator instruction rate (inst/s)
-host_tick_rate 1635033806 # Simulator tick rate (ticks/s)
-host_mem_usage 192576 # Number of bytes of host memory used
-host_seconds 27.05 # Real time elapsed on the host
+host_inst_rate 3998504 # Simulator instruction rate (inst/s)
+host_tick_rate 2001543652 # Simulator tick rate (ticks/s)
+host_mem_usage 206876 # Number of bytes of host memory used
+host_seconds 22.09 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
+system.physmem.bytes_read 480454939 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 353752292 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 91652896 # Number of bytes written to this memory
+system.physmem.num_reads 108714711 # Number of read requests responded to by this memory
+system.physmem.num_writes 14613377 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 10864858470 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 7999644241 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 2072610067 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 12937468537 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
index 7e8e19e97..f99b5fb55 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -164,7 +167,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
-cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing
+cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
@@ -188,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
index eff2b3a97..e74b48d2a 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 19 2011 06:59:13
-gem5 started Jun 20 2011 12:44:27
-gem5 executing on m60-009.pool
-command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:42:49
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
index 02c53f6a1..59b869a9f 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.134277 # Number of seconds simulated
sim_ticks 134276988000 # Number of ticks simulated
+final_tick 134276988000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1277823 # Simulator instruction rate (inst/s)
-host_tick_rate 1942278600 # Simulator tick rate (ticks/s)
-host_mem_usage 201212 # Number of bytes of host memory used
-host_seconds 69.13 # Real time elapsed on the host
+host_inst_rate 1801981 # Simulator instruction rate (inst/s)
+host_tick_rate 2738992827 # Simulator tick rate (ticks/s)
+host_mem_usage 215584 # Number of bytes of host memory used
+host_seconds 49.02 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
+system.physmem.bytes_read 11121920 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 558272 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 7712384 # Number of bytes written to this memory
+system.physmem.num_reads 173780 # Number of read requests responded to by this memory
+system.physmem.num_writes 120506 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 82828191 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 4157615 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 57436379 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 140264570 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini
index 64e40f331..1feff9641 100644
--- a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -500,7 +502,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/vortex
+executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
gid=100
input=cin
max_stack_size=67108864
@@ -519,7 +521,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout
index 46db9d24e..41153b9d0 100755
--- a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout
+++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 21 2011 16:28:02
-gem5 started Nov 22 2011 18:34:35
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:34:51
+gem5 executing on zizzer
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt
index ceab52925..858b9d08f 100644
--- a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.031183 # Number of seconds simulated
sim_ticks 31183407000 # Number of ticks simulated
+final_tick 31183407000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 167832 # Simulator instruction rate (inst/s)
-host_tick_rate 52006067 # Simulator tick rate (ticks/s)
-host_mem_usage 223216 # Number of bytes of host memory used
-host_seconds 599.61 # Real time elapsed on the host
+host_inst_rate 157932 # Simulator instruction rate (inst/s)
+host_tick_rate 48938242 # Simulator tick rate (ticks/s)
+host_mem_usage 229072 # Number of bytes of host memory used
+host_seconds 637.20 # Real time elapsed on the host
sim_insts 100634165 # Number of instructions simulated
+system.physmem.bytes_read 8651648 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 350016 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 5661184 # Number of bytes written to this memory
+system.physmem.num_reads 135182 # Number of read requests responded to by this memory
+system.physmem.num_writes 88456 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 277443962 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 11224431 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 181544756 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 458988718 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini
index d284ed163..321a621c1 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=ArmTLB
@@ -61,7 +64,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
-cwd=build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic
egid=100
env=
errout=cerr
@@ -85,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simerr b/tests/long/50.vortex/ref/arm/linux/simple-atomic/simerr
index eabe42249..e45cd058f 100755
--- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/simerr
@@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout
index 6efadf55b..cba7edc9e 100755
--- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 13:19:31
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:35:25
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt
index 7bc0f9c46..550377594 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt
@@ -1,76 +1,87 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 3680206 # Simulator instruction rate (inst/s)
-host_mem_usage 260724 # Number of bytes of host memory used
-host_seconds 27.34 # Real time elapsed on the host
-host_tick_rate 1972325214 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 100632437 # Number of instructions simulated
sim_seconds 0.053932 # Number of seconds simulated
sim_ticks 53932162000 # Number of ticks simulated
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+final_tick 53932162000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 3016681 # Simulator instruction rate (inst/s)
+host_tick_rate 1616735818 # Simulator tick rate (ticks/s)
+host_mem_usage 217624 # Number of bytes of host memory used
+host_seconds 33.36 # Real time elapsed on the host
+sim_insts 100632437 # Number of instructions simulated
+system.physmem.bytes_read 419153654 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 312580308 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 78660211 # Number of bytes written to this memory
+system.physmem.num_reads 105301330 # Number of read requests responded to by this memory
+system.physmem.num_writes 19865820 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 7771868185 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 5795805256 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 1458502832 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 9230371017 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 107864325 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 107864325 # Number of busy cycles
-system.cpu.num_conditional_control_insts 8920660 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses
-system.cpu.num_fp_insts 56 # number of float instructions
-system.cpu.num_fp_register_reads 36 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 20 # number of times the floating registers were written
-system.cpu.num_func_calls 3287514 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 100632437 # Number of instructions executed
system.cpu.num_int_alu_accesses 91472788 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses
+system.cpu.num_func_calls 3287514 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 8920660 # number of instructions that are conditional controls
system.cpu.num_int_insts 91472788 # number of integer instructions
+system.cpu.num_fp_insts 56 # number of float instructions
system.cpu.num_int_register_reads 452177233 # number of times the integer registers were read
system.cpu.num_int_register_writes 96252298 # number of times the integer registers were written
-system.cpu.num_load_insts 27307109 # Number of load instructions
+system.cpu.num_fp_register_reads 36 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 20 # number of times the floating registers were written
system.cpu.num_mem_refs 47862848 # number of memory refs
+system.cpu.num_load_insts 27307109 # Number of load instructions
system.cpu.num_store_insts 20555739 # Number of store instructions
-system.cpu.workload.num_syscalls 1946 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 107864325 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
index 8d849c15a..62eb4cdbf 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -164,7 +167,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
-cwd=build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing
egid=100
env=
errout=cerr
@@ -188,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/simerr b/tests/long/50.vortex/ref/arm/linux/simple-timing/simerr
index eabe42249..e45cd058f 100755
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/simerr
@@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/50.vortex/ref/arm/linux/simple-timing/simout
index 7b793d7b7..4fb750502 100755
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/simout
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 13:20:07
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:36:06
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
index 4595bb26f..2fff6cef5 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
@@ -1,269 +1,280 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 978868 # Simulator instruction rate (inst/s)
-host_mem_usage 268480 # Number of bytes of host memory used
-host_seconds 101.95 # Real time elapsed on the host
-host_tick_rate 1305762006 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 99791663 # Number of instructions simulated
sim_seconds 0.133117 # Number of seconds simulated
sim_ticks 133117442000 # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses 15919 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits 15919 # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses 27140334 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 35166.521920 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32166.521920 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 27087368 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 1862630000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.001952 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 52966 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 1703732000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.001952 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 52966 # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses 15919 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits 15919 # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses 19849901 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 54271.451529 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51271.451529 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 19742869 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 5808782000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.005392 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 107032 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 5487686000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.005392 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 107032 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 292.891630 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 46990235 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 47946.924337 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 44946.924337 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 46830237 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 7671412000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.003405 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 159998 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 7191418000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.003405 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 159998 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0 4076.934010 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.995345 # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses 46990235 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 47946.924337 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 44946.924337 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 46830237 # number of overall hits
-system.cpu.dcache.overall_miss_latency 7671412000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.003405 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 159998 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 7191418000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.003405 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 159998 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 155902 # number of replacements
-system.cpu.dcache.sampled_refs 159998 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4076.934010 # Cycle average of tags in use
-system.cpu.dcache.total_refs 46862075 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 1079641000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 122808 # number of writebacks
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+final_tick 133117442000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1410680 # Simulator instruction rate (inst/s)
+host_tick_rate 1881780580 # Simulator tick rate (ticks/s)
+host_mem_usage 226592 # Number of bytes of host memory used
+host_seconds 70.74 # Real time elapsed on the host
+sim_insts 99791663 # Number of instructions simulated
+system.physmem.bytes_read 8570688 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 294208 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 5660736 # Number of bytes written to this memory
+system.physmem.num_reads 133917 # Number of read requests responded to by this memory
+system.physmem.num_writes 88449 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 64384410 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 2210139 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 42524375 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 106908785 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.icache.ReadReq_accesses 78145078 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 24211.233340 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 21211.233340 # average ReadReq mshr miss latency
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 1946 # Number of system calls
+system.cpu.numCycles 266234884 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 99791663 # Number of instructions executed
+system.cpu.num_int_alu_accesses 91472788 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses
+system.cpu.num_func_calls 3287514 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 8920660 # number of instructions that are conditional controls
+system.cpu.num_int_insts 91472788 # number of integer instructions
+system.cpu.num_fp_insts 56 # number of float instructions
+system.cpu.num_int_register_reads 533542913 # number of times the integer registers were read
+system.cpu.num_int_register_writes 96252298 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 36 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 20 # number of times the floating registers were written
+system.cpu.num_mem_refs 47862848 # number of memory refs
+system.cpu.num_load_insts 27307109 # Number of load instructions
+system.cpu.num_store_insts 20555739 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 266234884 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.icache.replacements 16890 # number of replacements
+system.cpu.icache.tagsinuse 1736.182852 # Cycle average of tags in use
+system.cpu.icache.total_refs 78126170 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 18908 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 4131.910831 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 1736.182852 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.847746 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 78126170 # number of ReadReq hits
+system.cpu.icache.demand_hits 78126170 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 78126170 # number of overall hits
+system.cpu.icache.ReadReq_misses 18908 # number of ReadReq misses
+system.cpu.icache.demand_misses 18908 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 18908 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 457786000 # number of ReadReq miss cycles
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system.cpu.icache.demand_mshr_miss_latency 401062000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_avg_mshr_miss_latency 21211.233340 # average overall mshr miss latency
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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-system.cpu.l2cache.overall_mshr_miss_rate 0.748533 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 133917 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 113660 # number of replacements
-system.cpu.l2cache.sampled_refs 132489 # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 18191.621028 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 61800 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 88449 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 266234884 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 266234884 # Number of busy cycles
-system.cpu.num_conditional_control_insts 8920660 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses
-system.cpu.num_fp_insts 56 # number of float instructions
-system.cpu.num_fp_register_reads 36 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 20 # number of times the floating registers were written
-system.cpu.num_func_calls 3287514 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_insts 99791663 # Number of instructions executed
-system.cpu.num_int_alu_accesses 91472788 # Number of integer alu accesses
-system.cpu.num_int_insts 91472788 # number of integer instructions
-system.cpu.num_int_register_reads 533542913 # number of times the integer registers were read
-system.cpu.num_int_register_writes 96252298 # number of times the integer registers were written
-system.cpu.num_load_insts 27307109 # Number of load instructions
-system.cpu.num_mem_refs 47862848 # number of memory refs
-system.cpu.num_store_insts 20555739 # Number of store instructions
-system.cpu.workload.num_syscalls 1946 # Number of system calls
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
index dcd4bf473..2df6b792d 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -45,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=SparcTLB
@@ -62,7 +64,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=vortex bendian.raw
-cwd=build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic
+cwd=build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-atomic
egid=100
env=
errout=cerr
@@ -86,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -96,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
index 746f2d87f..542479326 100755
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 30 2011 17:14:16
-gem5 started Nov 30 2011 17:17:49
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 06:24:20
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
index 2fa280f51..dc6c31998 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.068149 # Number of seconds simulated
sim_ticks 68148678500 # Number of ticks simulated
+final_tick 68148678500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3860753 # Simulator instruction rate (inst/s)
-host_tick_rate 1932617843 # Simulator tick rate (ticks/s)
-host_mem_usage 204428 # Number of bytes of host memory used
-host_seconds 35.26 # Real time elapsed on the host
+host_inst_rate 3420916 # Simulator instruction rate (inst/s)
+host_tick_rate 1712444497 # Simulator tick rate (ticks/s)
+host_mem_usage 214012 # Number of bytes of host memory used
+host_seconds 39.80 # Real time elapsed on the host
sim_insts 136139203 # Number of instructions simulated
+system.physmem.bytes_read 685773693 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 538214332 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 89882950 # Number of bytes written to this memory
+system.physmem.num_reads 171784884 # Number of read requests responded to by this memory
+system.physmem.num_writes 20864304 # Number of write requests responded to by this memory
+system.physmem.num_other 15916 # Number of other requests responded to by this memory
+system.physmem.bw_read 10062905226 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 7897648844 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 1318924328 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 11381829554 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 136297358 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
index 51f71312a..5e34ae7a1 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -147,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -165,7 +167,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=vortex bendian.raw
-cwd=build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing
+cwd=build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing
egid=100
env=
errout=cerr
@@ -189,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -199,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
index 7c4300466..787eaa97a 100755
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 30 2011 17:14:16
-gem5 started Nov 30 2011 17:16:48
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 06:24:48
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
index 15f83a274..168a8eefa 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.202942 # Number of seconds simulated
sim_ticks 202941992000 # Number of ticks simulated
+final_tick 202941992000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2092270 # Simulator instruction rate (inst/s)
-host_tick_rate 3118935472 # Simulator tick rate (ticks/s)
-host_mem_usage 213400 # Number of bytes of host memory used
-host_seconds 65.07 # Real time elapsed on the host
+host_inst_rate 1608666 # Simulator instruction rate (inst/s)
+host_tick_rate 2398029397 # Simulator tick rate (ticks/s)
+host_mem_usage 222724 # Number of bytes of host memory used
+host_seconds 84.63 # Real time elapsed on the host
sim_insts 136139203 # Number of instructions simulated
+system.physmem.bytes_read 8970304 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 835264 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 5584960 # Number of bytes written to this memory
+system.physmem.num_reads 140161 # Number of read requests responded to by this memory
+system.physmem.num_writes 87265 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 44201320 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 4115777 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 27519982 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 71721303 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 405883984 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
index e32660b85..0d09e2e14 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=InOrderCPU
@@ -182,7 +184,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -205,7 +207,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/bzip2
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
max_stack_size=67108864
@@ -224,7 +226,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -234,5 +236,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout
index 1fce660ea..8bc14bb8a 100755
--- a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 8 2011 15:00:53
-gem5 started Jul 8 2011 17:14:45
-gem5 executing on u200439-lin.austin.arm.com
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:42:50
+gem5 executing on zizzer
command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
index 48a5816be..bf815a6e1 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.009857 # Number of seconds simulated
sim_ticks 1009857089500 # Number of ticks simulated
+final_tick 1009857089500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 45175 # Simulator instruction rate (inst/s)
-host_tick_rate 25069239 # Simulator tick rate (ticks/s)
-host_mem_usage 245844 # Number of bytes of host memory used
-host_seconds 40282.72 # Real time elapsed on the host
+host_inst_rate 102085 # Simulator instruction rate (inst/s)
+host_tick_rate 56650413 # Simulator tick rate (ticks/s)
+host_mem_usage 208040 # Number of bytes of host memory used
+host_seconds 17826.12 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
+system.physmem.bytes_read 172617984 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 54912 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 74938304 # Number of bytes written to this memory
+system.physmem.num_reads 2697156 # Number of read requests responded to by this memory
+system.physmem.num_writes 1170911 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 170933081 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 54376 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 74206841 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 245139922 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
index a21027897..4951679e2 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -519,7 +521,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout
index a891031f9..35ea78ab1 100755
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 20 2011 16:10:02
-gem5 started Aug 20 2011 21:33:03
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:43:49
gem5 executing on zizzer
-command line: ./build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
index 73dcce945..3e098da07 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.615292 # Number of seconds simulated
sim_ticks 615292058500 # Number of ticks simulated
+final_tick 615292058500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 150883 # Simulator instruction rate (inst/s)
-host_tick_rate 53476218 # Simulator tick rate (ticks/s)
-host_mem_usage 211804 # Number of bytes of host memory used
-host_seconds 11505.90 # Real time elapsed on the host
+host_inst_rate 151558 # Simulator instruction rate (inst/s)
+host_tick_rate 53715526 # Simulator tick rate (ticks/s)
+host_mem_usage 208624 # Number of bytes of host memory used
+host_seconds 11454.64 # Real time elapsed on the host
sim_insts 1736043781 # Number of instructions simulated
+system.physmem.bytes_read 173080384 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 60288 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 74996480 # Number of bytes written to this memory
+system.physmem.num_reads 2704381 # Number of read requests responded to by this memory
+system.physmem.num_writes 1171820 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 281297933 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 97983 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 121887612 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 403185545 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
index e886c5917..52ac7c920 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=AlphaTLB
@@ -61,7 +64,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
-cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic
+cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-atomic
egid=100
env=
errout=cerr
@@ -85,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout
index eccdc3c2f..3465b9fda 100755
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 19 2011 06:59:13
-gem5 started Jun 20 2011 12:23:57
-gem5 executing on m60-009.pool
-command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:45:21
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
index 0df85f934..1f32f6942 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.913189 # Number of seconds simulated
sim_ticks 913189263000 # Number of ticks simulated
+final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3384825 # Simulator instruction rate (inst/s)
-host_tick_rate 1698548817 # Simulator tick rate (ticks/s)
-host_mem_usage 183944 # Number of bytes of host memory used
-host_seconds 537.63 # Real time elapsed on the host
+host_inst_rate 4221832 # Simulator instruction rate (inst/s)
+host_tick_rate 2118570165 # Simulator tick rate (ticks/s)
+host_mem_usage 198896 # Number of bytes of host memory used
+host_seconds 431.04 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
+system.physmem.bytes_read 9280309971 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 7305514036 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 827777307 # Number of bytes written to this memory
+system.physmem.num_reads 2270974172 # Number of read requests responded to by this memory
+system.physmem.num_writes 160728502 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 10162526375 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 7999999926 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 906468506 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 11068994882 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
index 6ccdf7868..b74c06509 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -164,7 +167,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
-cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing
+cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
@@ -188,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout
index 1b40535c5..5e40861f7 100755
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 19 2011 06:59:13
-gem5 started Jun 20 2011 12:54:26
-gem5 executing on m60-009.pool
-command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:52:43
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
index 03eecacc7..99a911858 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.663444 # Number of seconds simulated
sim_ticks 2663443716000 # Number of ticks simulated
+final_tick 2663443716000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1486818 # Simulator instruction rate (inst/s)
-host_tick_rate 2176118189 # Simulator tick rate (ticks/s)
-host_mem_usage 192584 # Number of bytes of host memory used
-host_seconds 1223.94 # Real time elapsed on the host
+host_inst_rate 1948044 # Simulator instruction rate (inst/s)
+host_tick_rate 2851171142 # Simulator tick rate (ticks/s)
+host_mem_usage 207608 # Number of bytes of host memory used
+host_seconds 934.16 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
+system.physmem.bytes_read 172614208 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 51328 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 74939072 # Number of bytes written to this memory
+system.physmem.num_reads 2697097 # Number of read requests responded to by this memory
+system.physmem.num_writes 1170923 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 64808656 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 19271 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 28136158 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 92944814 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini
index 0e065d7b6..669a8b83b 100644
--- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -500,7 +502,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2
+executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
gid=100
input=cin
max_stack_size=67108864
@@ -519,7 +521,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout
index 0aaab6517..1474108e5 100755
--- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout
+++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 21 2011 16:28:02
-gem5 started Nov 22 2011 18:44:48
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:36:09
+gem5 executing on zizzer
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt
index 42652cb1d..bd2b3efef 100644
--- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.483463 # Number of seconds simulated
sim_ticks 483463019500 # Number of ticks simulated
+final_tick 483463019500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 167165 # Simulator instruction rate (inst/s)
-host_tick_rate 46903472 # Simulator tick rate (ticks/s)
-host_mem_usage 214756 # Number of bytes of host memory used
-host_seconds 10307.62 # Real time elapsed on the host
+host_inst_rate 152421 # Simulator instruction rate (inst/s)
+host_tick_rate 42766664 # Simulator tick rate (ticks/s)
+host_mem_usage 220608 # Number of bytes of host memory used
+host_seconds 11304.67 # Real time elapsed on the host
sim_insts 1723073849 # Number of instructions simulated
+system.physmem.bytes_read 188174592 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 45888 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 77926272 # Number of bytes written to this memory
+system.physmem.num_reads 2940228 # Number of read requests responded to by this memory
+system.physmem.num_writes 1217598 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 389222307 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 94915 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 161183522 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 550405829 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini
index 8d90d74d0..bbede2479 100644
--- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=ArmTLB
@@ -61,7 +64,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
-cwd=build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic
egid=100
env=
errout=cerr
@@ -85,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simerr b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simerr
index eabe42249..e45cd058f 100755
--- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simerr
@@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout
index 4e09f0c47..e599bde0b 100755
--- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 13:22:49
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:37:28
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
index 42e09915d..e23300649 100644
--- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
@@ -1,76 +1,87 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 3743034 # Simulator instruction rate (inst/s)
-host_mem_usage 253144 # Number of bytes of host memory used
-host_seconds 460.34 # Real time elapsed on the host
-host_tick_rate 1871519168 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1723073862 # Number of instructions simulated
sim_seconds 0.861538 # Number of seconds simulated
sim_ticks 861538205000 # Number of ticks simulated
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+final_tick 861538205000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 3027828 # Simulator instruction rate (inst/s)
+host_tick_rate 1513916118 # Simulator tick rate (ticks/s)
+host_mem_usage 210380 # Number of bytes of host memory used
+host_seconds 569.08 # Real time elapsed on the host
+sim_insts 1723073862 # Number of instructions simulated
+system.physmem.bytes_read 7759650064 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 6178262392 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 624158392 # Number of bytes written to this memory
+system.physmem.num_reads 2026949786 # Number of read requests responded to by this memory
+system.physmem.num_writes 172586108 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 9006739363 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 7171199555 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 724469778 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 9731209141 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 1723076411 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 1723076411 # Number of busy cycles
-system.cpu.num_conditional_control_insts 177498066 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
-system.cpu.num_fp_insts 36 # number of float instructions
-system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
-system.cpu.num_func_calls 27330134 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 1723073862 # Number of instructions executed
system.cpu.num_int_alu_accesses 1536941850 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
+system.cpu.num_func_calls 27330134 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 177498066 # number of instructions that are conditional controls
system.cpu.num_int_insts 1536941850 # number of integer instructions
+system.cpu.num_fp_insts 36 # number of float instructions
system.cpu.num_int_register_reads 7861284536 # number of times the integer registers were read
system.cpu.num_int_register_writes 1675132418 # number of times the integer registers were written
-system.cpu.num_load_insts 485926770 # Number of load instructions
+system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
system.cpu.num_mem_refs 660773816 # number of memory refs
+system.cpu.num_load_insts 485926770 # Number of load instructions
system.cpu.num_store_insts 174847046 # Number of store instructions
-system.cpu.workload.num_syscalls 46 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 1723076411 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini
index 00bc540f8..71abd898d 100644
--- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -164,7 +167,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
-cwd=build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing
egid=100
env=
errout=cerr
@@ -188,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr
index eabe42249..e45cd058f 100755
--- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr
@@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout
index 88386aeb5..8198567b7 100755
--- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 13:25:15
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:45:39
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt
index c692715dc..04e3122e6 100644
--- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt
@@ -1,269 +1,280 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1772581 # Simulator instruction rate (inst/s)
-host_mem_usage 260892 # Number of bytes of host memory used
-host_seconds 968.80 # Real time elapsed on the host
-host_tick_rate 2509731503 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1717270343 # Number of instructions simulated
sim_seconds 2.431420 # Number of seconds simulated
sim_ticks 2431419954000 # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses 61 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits 61 # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses 482384127 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 24514.084594 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21514.084594 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 475158040 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 177140908000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.014980 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 7226087 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 155462647000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.014980 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 7226087 # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses 61 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits 61 # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses 172586047 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 33784.641656 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30784.641656 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 170696898 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 63824222000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.010946 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 1889149 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 58156775000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.010946 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 1889149 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 70.854453 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 654970174 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 26435.424162 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 23435.424162 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 645854938 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 240965130000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.013917 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 9115236 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 213619422000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.013917 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 9115236 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0 4083.719979 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.997002 # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses 654970174 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 26435.424162 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 23435.424162 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 645854938 # number of overall hits
-system.cpu.dcache.overall_miss_latency 240965130000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.013917 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 9115236 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 213619422000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.013917 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 9115236 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 9111140 # number of replacements
-system.cpu.dcache.sampled_refs 9115236 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4083.719979 # Cycle average of tags in use
-system.cpu.dcache.total_refs 645855060 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 25923025000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 3061985 # number of writebacks
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+final_tick 2431419954000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1410228 # Simulator instruction rate (inst/s)
+host_tick_rate 1996689457 # Simulator tick rate (ticks/s)
+host_mem_usage 219344 # Number of bytes of host memory used
+host_seconds 1217.73 # Real time elapsed on the host
+sim_insts 1717270343 # Number of instructions simulated
+system.physmem.bytes_read 172766016 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 39424 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 75006720 # Number of bytes written to this memory
+system.physmem.num_reads 2699469 # Number of read requests responded to by this memory
+system.physmem.num_writes 1171980 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 71055605 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 16214 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 30848937 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 101904542 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.icache.ReadReq_accesses 1544565599 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 54551.724138 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 51551.724138 # average ReadReq mshr miss latency
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 46 # Number of system calls
+system.cpu.numCycles 4862839908 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 1717270343 # Number of instructions executed
+system.cpu.num_int_alu_accesses 1536941850 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
+system.cpu.num_func_calls 27330134 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 177498066 # number of instructions that are conditional controls
+system.cpu.num_int_insts 1536941850 # number of integer instructions
+system.cpu.num_fp_insts 36 # number of float instructions
+system.cpu.num_int_register_reads 9304894713 # number of times the integer registers were read
+system.cpu.num_int_register_writes 1675132418 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
+system.cpu.num_mem_refs 660773816 # number of memory refs
+system.cpu.num_load_insts 485926770 # Number of load instructions
+system.cpu.num_store_insts 174847046 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 4862839908 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.icache.replacements 7 # number of replacements
+system.cpu.icache.tagsinuse 514.872896 # Cycle average of tags in use
+system.cpu.icache.total_refs 1544564961 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 638 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 2420948.214734 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 514.872896 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.251403 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 1544564961 # number of ReadReq hits
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-system.cpu.l2cache.overall_hits 6416405 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 140372388000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.296128 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 2699469 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 107978760000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.296128 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 2699469 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 2687066 # number of replacements
-system.cpu.l2cache.sampled_refs 2714383 # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 26134.517233 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 7569171 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 538044123000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 1171980 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 4862839908 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 4862839908 # Number of busy cycles
-system.cpu.num_conditional_control_insts 177498066 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
-system.cpu.num_fp_insts 36 # number of float instructions
-system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
-system.cpu.num_func_calls 27330134 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_insts 1717270343 # Number of instructions executed
-system.cpu.num_int_alu_accesses 1536941850 # Number of integer alu accesses
-system.cpu.num_int_insts 1536941850 # number of integer instructions
-system.cpu.num_int_register_reads 9304894713 # number of times the integer registers were read
-system.cpu.num_int_register_writes 1675132418 # number of times the integer registers were written
-system.cpu.num_load_insts 485926770 # Number of load instructions
-system.cpu.num_mem_refs 660773816 # number of memory refs
-system.cpu.num_store_insts 174847046 # Number of store instructions
-system.cpu.workload.num_syscalls 46 # Number of system calls
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini
index 862679185..fe30d10a3 100644
--- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -45,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=X86TLB
@@ -67,7 +69,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/bzip2
+executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2
gid=100
input=cin
max_stack_size=67108864
@@ -86,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -96,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout
index bad0385b9..a5a0064e6 100755
--- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 9 2012 14:18:02
-gem5 started Jan 9 2012 14:29:08
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 07:13:31
+gem5 executing on zizzer
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
index 9b17b524e..6725100b8 100644
--- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.846007 # Number of seconds simulated
sim_ticks 2846007259500 # Number of ticks simulated
+final_tick 2846007259500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1508697 # Simulator instruction rate (inst/s)
-host_tick_rate 916127309 # Simulator tick rate (ticks/s)
-host_mem_usage 234076 # Number of bytes of host memory used
-host_seconds 3106.56 # Real time elapsed on the host
+host_inst_rate 2006575 # Simulator instruction rate (inst/s)
+host_tick_rate 1218454030 # Simulator tick rate (ticks/s)
+host_mem_usage 204704 # Number of bytes of host memory used
+host_seconds 2335.75 # Real time elapsed on the host
sim_insts 4686862651 # Number of instructions simulated
+system.physmem.bytes_read 37129731755 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 32105863408 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 1544656790 # Number of bytes written to this memory
+system.physmem.num_reads 5252417675 # Number of read requests responded to by this memory
+system.physmem.num_writes 438528337 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 13046253354 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 11281019506 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 542745204 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 13588998558 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 5692014520 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini
index 90d473af2..e57f67518 100644
--- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -147,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -170,7 +172,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/bzip2
+executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2
gid=100
input=cin
max_stack_size=67108864
@@ -189,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -199,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout
index bfa3c0689..5d5232885 100755
--- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 9 2012 14:18:02
-gem5 started Jan 9 2012 14:29:08
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 07:30:19
+gem5 executing on zizzer
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt
index 75fcf4f7a..94c5d24c6 100644
--- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 5.923548 # Number of seconds simulated
sim_ticks 5923548078000 # Number of ticks simulated
+final_tick 5923548078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 871353 # Simulator instruction rate (inst/s)
-host_tick_rate 1101269643 # Simulator tick rate (ticks/s)
-host_mem_usage 242804 # Number of bytes of host memory used
-host_seconds 5378.84 # Real time elapsed on the host
+host_inst_rate 1176749 # Simulator instruction rate (inst/s)
+host_tick_rate 1487248019 # Simulator tick rate (ticks/s)
+host_mem_usage 213688 # Number of bytes of host memory used
+host_seconds 3982.89 # Real time elapsed on the host
sim_insts 4686862651 # Number of instructions simulated
+system.physmem.bytes_read 173910080 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 43200 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 75176384 # Number of bytes written to this memory
+system.physmem.num_reads 2717345 # Number of read requests responded to by this memory
+system.physmem.num_writes 1174631 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 29359107 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 7293 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 12691107 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 42050214 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 11847096156 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
index e1977cd05..64fd65cd8 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=InOrderCPU
@@ -182,7 +184,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -205,7 +207,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/twolf
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
max_stack_size=67108864
@@ -224,7 +226,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -234,5 +236,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout
index 90052853e..ab1cbef0e 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 8 2011 15:00:53
-gem5 started Jul 8 2011 17:47:44
-gem5 executing on u200439-lin.austin.arm.com
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:57:18
+gem5 executing on zizzer
command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing
Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sav
Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
index e905042e7..db43e1bd8 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
@@ -2,12 +2,22 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.041834 # Number of seconds simulated
sim_ticks 41833966000 # Number of ticks simulated
+final_tick 41833966000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 47398 # Simulator instruction rate (inst/s)
-host_tick_rate 21575287 # Simulator tick rate (ticks/s)
-host_mem_usage 249684 # Number of bytes of host memory used
-host_seconds 1938.98 # Real time elapsed on the host
+host_inst_rate 111295 # Simulator instruction rate (inst/s)
+host_tick_rate 50660994 # Simulator tick rate (ticks/s)
+host_mem_usage 211656 # Number of bytes of host memory used
+host_seconds 825.76 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
+system.physmem.bytes_read 316032 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 178816 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 4938 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 7554436 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 4274421 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 7554436 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
index 249041a4d..a6f9e5430 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -519,7 +521,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
index 2583cc940..9901dc40b 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
@@ -1,10 +1,8 @@
-Redirecting stdout to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 20 2011 16:10:02
-gem5 started Aug 20 2011 16:10:09
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 06:08:28
gem5 executing on zizzer
command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing
Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sav
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
index f77f26233..55d9dc21f 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
@@ -2,12 +2,22 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.029167 # Number of seconds simulated
sim_ticks 29167093500 # Number of ticks simulated
+final_tick 29167093500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 127298 # Simulator instruction rate (inst/s)
-host_tick_rate 44106983 # Simulator tick rate (ticks/s)
-host_mem_usage 209296 # Number of bytes of host memory used
-host_seconds 661.28 # Real time elapsed on the host
+host_inst_rate 155660 # Simulator instruction rate (inst/s)
+host_tick_rate 53933893 # Simulator tick rate (ticks/s)
+host_mem_usage 212576 # Number of bytes of host memory used
+host_seconds 540.79 # Real time elapsed on the host
sim_insts 84179709 # Number of instructions simulated
+system.physmem.bytes_read 332416 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 193856 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 5194 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 11396953 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 6646394 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 11396953 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
index 1801d3968..c3b5c0104 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=AlphaTLB
@@ -61,7 +64,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic
+cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic
egid=100
env=
errout=cerr
@@ -85,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout
index 6101328db..887ca3f4e 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout
@@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 19 2011 06:59:13
-gem5 started Jun 20 2011 12:19:40
-gem5 executing on m60-009.pool
-command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic
-Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sav
-Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sv2
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 06:10:21
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic
+Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic/smred.sav
+Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
index f61998e0c..af93195e1 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.045952 # Number of seconds simulated
sim_ticks 45951567500 # Number of ticks simulated
+final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3424834 # Simulator instruction rate (inst/s)
-host_tick_rate 1712417014 # Simulator tick rate (ticks/s)
-host_mem_usage 187848 # Number of bytes of host memory used
-host_seconds 26.83 # Real time elapsed on the host
+host_inst_rate 4191883 # Simulator instruction rate (inst/s)
+host_tick_rate 2095941744 # Simulator tick rate (ticks/s)
+host_mem_usage 202544 # Number of bytes of host memory used
+host_seconds 21.92 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
+system.physmem.bytes_read 475949877 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 367612356 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 30920974 # Number of bytes written to this memory
+system.physmem.num_reads 111899287 # Number of read requests responded to by this memory
+system.physmem.num_writes 6501103 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 10357641815 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 7999995996 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 672903574 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 11030545389 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
index f2a594baf..2fe44f969 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -164,7 +167,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing
+cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
@@ -188,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout
index e569eee9e..84097b1db 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout
@@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 19 2011 06:59:13
-gem5 started Jun 20 2011 12:46:11
-gem5 executing on m60-009.pool
-command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing
-Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sav
-Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sv2
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 06:10:54
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing
+Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/smred.sav
+Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
index c41863436..ba87aad33 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
@@ -2,12 +2,22 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.118740 # Number of seconds simulated
sim_ticks 118740049000 # Number of ticks simulated
+final_tick 118740049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1530436 # Simulator instruction rate (inst/s)
-host_tick_rate 1977344021 # Simulator tick rate (ticks/s)
-host_mem_usage 196484 # Number of bytes of host memory used
-host_seconds 60.05 # Real time elapsed on the host
+host_inst_rate 2095418 # Simulator instruction rate (inst/s)
+host_tick_rate 2707308980 # Simulator tick rate (ticks/s)
+host_mem_usage 211256 # Number of bytes of host memory used
+host_seconds 43.86 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
+system.physmem.bytes_read 304960 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 167744 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 4765 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 2568299 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 1412699 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 2568299 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini
index e5f29e92c..8db3f9119 100644
--- a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -500,7 +502,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/twolf
+executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
gid=100
input=cin
max_stack_size=67108864
@@ -519,7 +521,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout
index e68aac2cc..bee9aa417 100755
--- a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 21 2011 16:28:02
-gem5 started Nov 22 2011 18:53:02
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:47:07
+gem5 executing on zizzer
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing
Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/smred.sav
Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/smred.sv2
diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt
index 37554b8e7..4282a0231 100644
--- a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt
@@ -2,12 +2,22 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.105875 # Number of seconds simulated
sim_ticks 105874925000 # Number of ticks simulated
+final_tick 105874925000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 114442 # Simulator instruction rate (inst/s)
-host_tick_rate 64221605 # Simulator tick rate (ticks/s)
-host_mem_usage 218340 # Number of bytes of host memory used
-host_seconds 1648.59 # Real time elapsed on the host
+host_inst_rate 103612 # Simulator instruction rate (inst/s)
+host_tick_rate 58144234 # Simulator tick rate (ticks/s)
+host_mem_usage 224188 # Number of bytes of host memory used
+host_seconds 1820.90 # Real time elapsed on the host
sim_insts 188667572 # Number of instructions simulated
+system.physmem.bytes_read 240192 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 128512 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 3753 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 2268639 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 1213810 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 2268639 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini
index 283406dc2..01def30a3 100644
--- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=ArmTLB
@@ -61,7 +64,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic
egid=100
env=
errout=cerr
@@ -85,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/simerr b/tests/long/70.twolf/ref/arm/linux/simple-atomic/simerr
index eabe42249..e45cd058f 100755
--- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/simerr
@@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout
index 03f12e59d..f2a9f0661 100755
--- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout
@@ -1,16 +1,12 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 13:30:09
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic
-Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic/smred.sav
-Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic/smred.sv2
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:50:48
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic
+Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic/smred.sav
+Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt
index a4b991833..079a70f11 100644
--- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt
@@ -1,76 +1,87 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1596483 # Simulator instruction rate (inst/s)
-host_mem_usage 256912 # Number of bytes of host memory used
-host_seconds 118.18 # Real time elapsed on the host
-host_tick_rate 872460307 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 188670900 # Number of instructions simulated
sim_seconds 0.103107 # Number of seconds simulated
sim_ticks 103106771000 # Number of ticks simulated
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+final_tick 103106771000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 3006793 # Simulator instruction rate (inst/s)
+host_tick_rate 1643182108 # Simulator tick rate (ticks/s)
+host_mem_usage 213456 # Number of bytes of host memory used
+host_seconds 62.75 # Real time elapsed on the host
+sim_insts 188670900 # Number of instructions simulated
+system.physmem.bytes_read 869973902 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 759440240 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 45252940 # Number of bytes written to this memory
+system.physmem.num_reads 219482514 # Number of read requests responded to by this memory
+system.physmem.num_writes 12386694 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 8437602047 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 7365570977 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 438893969 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 8876496016 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 206213543 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 206213543 # Number of busy cycles
-system.cpu.num_conditional_control_insts 31949383 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses
-system.cpu.num_fp_insts 1752310 # number of float instructions
-system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written
-system.cpu.num_func_calls 3504894 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 188670900 # Number of instructions executed
system.cpu.num_int_alu_accesses 150106226 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses
+system.cpu.num_func_calls 3504894 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 31949383 # number of instructions that are conditional controls
system.cpu.num_int_insts 150106226 # number of integer instructions
+system.cpu.num_fp_insts 1752310 # number of float instructions
system.cpu.num_int_register_reads 809396650 # number of times the integer registers were read
system.cpu.num_int_register_writes 294073530 # number of times the integer registers were written
-system.cpu.num_load_insts 29849485 # Number of load instructions
+system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written
system.cpu.num_mem_refs 42494120 # number of memory refs
+system.cpu.num_load_insts 29849485 # Number of load instructions
system.cpu.num_store_insts 12644635 # Number of store instructions
-system.cpu.workload.num_syscalls 400 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 206213543 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini
index c22086808..3f54c6512 100644
--- a/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -164,7 +167,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing
egid=100
env=
errout=cerr
@@ -188,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/simerr b/tests/long/70.twolf/ref/arm/linux/simple-timing/simerr
index eabe42249..e45cd058f 100755
--- a/tests/long/70.twolf/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/simerr
@@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/70.twolf/ref/arm/linux/simple-timing/simout
index a62fdd8f9..b21763742 100755
--- a/tests/long/70.twolf/ref/arm/linux/simple-timing/simout
+++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/simout
@@ -1,16 +1,12 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 13:31:09
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing
-Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing/smred.sav
-Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing/smred.sv2
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:52:01
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing
+Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sav
+Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt
index 022cf6be1..d861ddab1 100644
--- a/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt
@@ -1,269 +1,279 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1108469 # Simulator instruction rate (inst/s)
-host_mem_usage 264128 # Number of bytes of host memory used
-host_seconds 169.77 # Real time elapsed on the host
-host_tick_rate 1366998833 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 188185929 # Number of instructions simulated
sim_seconds 0.232077 # Number of seconds simulated
sim_ticks 232077154000 # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses 22407 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits 22407 # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses 29600047 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 52525.399129 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 49525.399129 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 29599358 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 36190000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.000023 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 689 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 34123000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.000023 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 689 # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses 22407 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits 22407 # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses 12364287 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55694.545455 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52694.545455 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 12363187 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 61264000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.000089 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 1100 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 57964000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000089 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 1100 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 23480.916154 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 41964334 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 54474.007826 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 51474.007826 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 41962545 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 97454000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000043 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 1789 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 92087000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.000043 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 1789 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0 1363.604315 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.332911 # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses 41964334 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 54474.007826 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 51474.007826 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 41962545 # number of overall hits
-system.cpu.dcache.overall_miss_latency 97454000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000043 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 1789 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 92087000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000043 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 1789 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 40 # number of replacements
-system.cpu.dcache.sampled_refs 1789 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 1363.604315 # Cycle average of tags in use
-system.cpu.dcache.total_refs 42007359 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 16 # number of writebacks
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+final_tick 232077154000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1497030 # Simulator instruction rate (inst/s)
+host_tick_rate 1846187485 # Simulator tick rate (ticks/s)
+host_mem_usage 222460 # Number of bytes of host memory used
+host_seconds 125.71 # Real time elapsed on the host
+sim_insts 188185929 # Number of instructions simulated
+system.physmem.bytes_read 220992 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 110656 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 3453 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 952235 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 476807 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 952235 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.icache.ReadReq_accesses 189860061 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 37801.376598 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34801.376598 # average ReadReq mshr miss latency
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 400 # Number of system calls
+system.cpu.numCycles 464154308 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 188185929 # Number of instructions executed
+system.cpu.num_int_alu_accesses 150106226 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses
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system.cpu.icache.ReadReq_hits 189857010 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 115332000 # number of ReadReq miss cycles
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system.cpu.icache.overall_avg_mshr_miss_latency 34801.376598 # average overall mshr miss latency
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system.cpu.l2cache.demand_mshr_miss_rate 0.713430 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 3453 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0 1672.609981 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 3.038048 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.051044 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1 0.000093 # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses 4840 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_mshr_miss_rate 0.713430 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 1387 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 179556000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.713430 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 3453 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 138120000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.713430 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 3453 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 2369 # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 1675.648030 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1379 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 464154308 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 464154308 # Number of busy cycles
-system.cpu.num_conditional_control_insts 31949383 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses
-system.cpu.num_fp_insts 1752310 # number of float instructions
-system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written
-system.cpu.num_func_calls 3504894 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_insts 188185929 # Number of instructions executed
-system.cpu.num_int_alu_accesses 150106226 # Number of integer alu accesses
-system.cpu.num_int_insts 150106226 # number of integer instructions
-system.cpu.num_int_register_reads 898652287 # number of times the integer registers were read
-system.cpu.num_int_register_writes 294073530 # number of times the integer registers were written
-system.cpu.num_load_insts 29849485 # Number of load instructions
-system.cpu.num_mem_refs 42494120 # number of memory refs
-system.cpu.num_store_insts 12644635 # Number of store instructions
-system.cpu.workload.num_syscalls 400 # Number of system calls
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
index b59640844..5551fc718 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -45,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=SparcTLB
@@ -62,7 +64,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic
+cwd=build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic
egid=100
env=
errout=cerr
@@ -86,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -96,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout
index a36de6b20..5a1dc45d3 100755
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout
@@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 30 2011 17:14:16
-gem5 started Nov 30 2011 17:16:48
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 06:25:10
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic
-Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav
-Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sv2
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic
+Couldn't unlink build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic/smred.sav
+Couldn't unlink build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
index 9a564c8ae..fabf573dd 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.096723 # Number of seconds simulated
sim_ticks 96722951500 # Number of ticks simulated
+final_tick 96722951500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3820563 # Simulator instruction rate (inst/s)
-host_tick_rate 1910292029 # Simulator tick rate (ticks/s)
-host_mem_usage 200496 # Number of bytes of host memory used
-host_seconds 50.63 # Real time elapsed on the host
+host_inst_rate 3381365 # Simulator instruction rate (inst/s)
+host_tick_rate 1690691780 # Simulator tick rate (ticks/s)
+host_mem_usage 210080 # Number of bytes of host memory used
+host_seconds 57.21 # Real time elapsed on the host
sim_insts 193444769 # Number of instructions simulated
+system.physmem.bytes_read 997245606 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 773782192 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 72065412 # Number of bytes written to this memory
+system.physmem.num_reads 251180617 # Number of read requests responded to by this memory
+system.physmem.num_writes 18976439 # Number of write requests responded to by this memory
+system.physmem.num_other 22406 # Number of other requests responded to by this memory
+system.physmem.bw_read 10310330594 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 7999985319 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 745070440 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 11055401034 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 401 # Number of system calls
system.cpu.numCycles 193445904 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
index 6069e1413..2d0b36d34 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -147,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -165,7 +167,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing
+cwd=build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing
egid=100
env=
errout=cerr
@@ -189,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -199,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout
index 1a7df931f..e7f89f9a0 100755
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout
@@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 30 2011 17:14:16
-gem5 started Nov 30 2011 17:16:48
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 06:26:18
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing
-Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav
-Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing
+Couldn't unlink build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/smred.sav
+Couldn't unlink build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt
index 106cfd4f6..16bfeed42 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt
@@ -2,12 +2,22 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.270577 # Number of seconds simulated
sim_ticks 270576960000 # Number of ticks simulated
+final_tick 270576960000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2077025 # Simulator instruction rate (inst/s)
-host_tick_rate 2905196336 # Simulator tick rate (ticks/s)
-host_mem_usage 209472 # Number of bytes of host memory used
-host_seconds 93.14 # Real time elapsed on the host
+host_inst_rate 1675606 # Simulator instruction rate (inst/s)
+host_tick_rate 2343719954 # Simulator tick rate (ticks/s)
+host_mem_usage 218792 # Number of bytes of host memory used
+host_seconds 115.45 # Real time elapsed on the host
sim_insts 193444769 # Number of instructions simulated
+system.physmem.bytes_read 331072 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 230208 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 5173 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 1223578 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 850804 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 1223578 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 401 # Number of system calls
system.cpu.numCycles 541153920 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini
index d20296793..0cd9938ef 100644
--- a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -500,7 +502,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
+executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
gid=100
input=cin
max_stack_size=67108864
@@ -519,7 +521,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout
index a8f7791d3..1f9424384 100755
--- a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 9 2012 14:18:02
-gem5 started Jan 9 2012 14:29:08
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 07:52:38
+gem5 executing on zizzer
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing
Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sav
Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sv2
diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt
index f73117896..71e8505e4 100644
--- a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt
@@ -2,12 +2,22 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.096690 # Number of seconds simulated
sim_ticks 96689893000 # Number of ticks simulated
+final_tick 96689893000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 71082 # Simulator instruction rate (inst/s)
-host_tick_rate 31048201 # Simulator tick rate (ticks/s)
-host_mem_usage 253148 # Number of bytes of host memory used
-host_seconds 3114.19 # Real time elapsed on the host
+host_inst_rate 118200 # Simulator instruction rate (inst/s)
+host_tick_rate 51629155 # Simulator tick rate (ticks/s)
+host_mem_usage 224032 # Number of bytes of host memory used
+host_seconds 1872.78 # Real time elapsed on the host
sim_insts 221363017 # Number of instructions simulated
+system.physmem.bytes_read 340224 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 215424 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 5316 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 3518713 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 2227989 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 3518713 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 193379787 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini
index 22a2b62b1..4d9868de9 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -45,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=X86TLB
@@ -67,7 +69,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
+executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
gid=100
input=cin
max_stack_size=67108864
@@ -86,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -96,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
index d0fe2b96b..3217ab200 100755
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 9 2012 14:18:02
-gem5 started Jan 9 2012 14:29:08
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 08:24:02
+gem5 executing on zizzer
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic
Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sav
Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sv2
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
index 727d7b7f0..39967f660 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.131393 # Number of seconds simulated
sim_ticks 131393100000 # Number of ticks simulated
+final_tick 131393100000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 733183 # Simulator instruction rate (inst/s)
-host_tick_rate 435191133 # Simulator tick rate (ticks/s)
-host_mem_usage 241232 # Number of bytes of host memory used
-host_seconds 301.92 # Real time elapsed on the host
+host_inst_rate 1953897 # Simulator instruction rate (inst/s)
+host_tick_rate 1159762651 # Simulator tick rate (ticks/s)
+host_mem_usage 211876 # Number of bytes of host memory used
+host_seconds 113.29 # Real time elapsed on the host
sim_insts 221363018 # Number of instructions simulated
+system.physmem.bytes_read 1698379042 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 1387955288 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 99822189 # Number of bytes written to this memory
+system.physmem.num_reads 230176419 # Number of read requests responded to by this memory
+system.physmem.num_writes 20515730 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 12925937831 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 10563380330 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 759721698 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 13685659529 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 262786201 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
index 2acc29c81..d7a510398 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -147,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -170,7 +172,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
+executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
gid=100
input=cin
max_stack_size=67108864
@@ -189,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -199,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout
index a9cb69d9f..a3170a407 100755
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 9 2012 14:18:02
-gem5 started Jan 9 2012 14:29:08
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 08:26:06
+gem5 executing on zizzer
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing
Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sav
Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sv2
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
index d8ed7223d..1c9d2c1e6 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
@@ -2,12 +2,22 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.250961 # Number of seconds simulated
sim_ticks 250960631000 # Number of ticks simulated
+final_tick 250960631000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 461238 # Simulator instruction rate (inst/s)
-host_tick_rate 522908265 # Simulator tick rate (ticks/s)
-host_mem_usage 250008 # Number of bytes of host memory used
-host_seconds 479.93 # Real time elapsed on the host
+host_inst_rate 1263573 # Simulator instruction rate (inst/s)
+host_tick_rate 1432520595 # Simulator tick rate (ticks/s)
+host_mem_usage 220856 # Number of bytes of host memory used
+host_seconds 175.19 # Real time elapsed on the host
sim_insts 221363018 # Number of instructions simulated
+system.physmem.bytes_read 303040 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 181760 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 4735 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 1207520 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 724257 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 1207520 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 501921262 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
index 395184da9..409b736b6 100644
--- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
+++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
@@ -19,7 +19,8 @@ init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
-memories=system.nvram system.physmem2 system.partition_desc system.physmem system.hypervisor_desc system.rom
+memories=system.physmem2 system.nvram system.partition_desc system.rom system.physmem system.hypervisor_desc
+num_work_ids=16
nvram=system.nvram
nvram_addr=133429198848
nvram_bin=/dist/m5/system/binaries/nvram1
@@ -41,20 +42,18 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[9]
[system.bridge]
type=Bridge
delay=100
-filter_ranges_a=
-filter_ranges_b=
nack_delay=8
-req_size_a=16
-req_size_b=16
-resp_size_a=16
-resp_size_b=16
+ranges=133412421632:133412421639 134217728000:554050781183 644245094400:652835028991 725849473024:1095485095935 1099255955456:1099255955463
+req_size=16
+resp_size=16
write_ack=false
-side_a=system.iobus.port[14]
-side_b=system.membus.port[2]
+master=system.iobus.port[14]
+slave=system.membus.port[2]
[system.cpu]
type=AtomicSimpleCPU
@@ -84,8 +83,8 @@ simulate_inst_stalls=false
system=system
tracer=system.cpu.tracer
width=1
-dcache_port=system.membus.port[10]
-icache_port=system.membus.port[9]
+dcache_port=system.membus.port[11]
+icache_port=system.membus.port[10]
[system.cpu.dtb]
type=SparcTLB
@@ -146,7 +145,7 @@ clock=2
header_cycles=1
use_default_range=false
width=64
-port=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.bridge.side_a system.disk0.pio
+port=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.bridge.master system.disk0.pio
[system.membus]
type=Bus
@@ -158,7 +157,7 @@ header_cycles=1
use_default_range=false
width=64
default=system.membus.badaddr_responder.pio
-port=system.t1000.iob.pio system.t1000.htod.pio system.bridge.side_b system.physmem.port[0] system.physmem2.port[0] system.rom.port[0] system.nvram.port[0] system.hypervisor_desc.port[0] system.partition_desc.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.t1000.iob.pio system.t1000.htod.pio system.bridge.slave system.physmem.port[0] system.physmem2.port[0] system.rom.port[0] system.nvram.port[0] system.hypervisor_desc.port[0] system.partition_desc.port[0] system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.membus.badaddr_responder]
type=IsaFake
diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
index 6ef01a659..d81b5c20f 100755
--- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
+++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
@@ -1,15 +1,15 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 27 2011 04:34:45
-gem5 started Nov 27 2011 04:35:04
-gem5 executing on chips
+gem5 compiled Jan 23 2012 04:05:05
+gem5 started Jan 23 2012 06:26:23
+gem5 executing on zizzer
command line: build/SPARC_FS/gem5.opt -d build/SPARC_FS/tests/opt/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC_FS/tests/opt/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic
Global frequency set at 2000000000 ticks per second
-info: No kernel set for full system simulation. Assuming you know what you're doing...
0: system.t1000.htod: Real-time clock set to Thu Jan 1 00:00:00 2009
0: system.t1000.htod: Real-time clock set to 1230768000
+info: No kernel set for full system simulation. Assuming you know what you're doing...
info: Entering event queue @ 0. Starting simulation...
info: Ignoring write to SPARC ERROR regsiter
info: Ignoring write to SPARC ERROR regsiter
diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
index a8935aa0a..21a50a501 100644
--- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
+++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
@@ -2,12 +2,67 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.116889 # Number of seconds simulated
sim_ticks 2233777512 # Number of ticks simulated
+final_tick 2233777512 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 2000000000 # Frequency of simulated ticks
-host_inst_rate 941153 # Simulator instruction rate (inst/s)
-host_tick_rate 943102 # Simulator tick rate (ticks/s)
-host_mem_usage 535596 # Number of bytes of host memory used
-host_seconds 2368.54 # Real time elapsed on the host
+host_inst_rate 3505728 # Simulator instruction rate (inst/s)
+host_tick_rate 3512989 # Simulator tick rate (ticks/s)
+host_mem_usage 500940 # Number of bytes of host memory used
+host_seconds 635.86 # Real time elapsed on the host
sim_insts 2229160714 # Number of instructions simulated
+system.hypervisor_desc.bytes_read 16792 # Number of bytes read from this memory
+system.hypervisor_desc.bytes_inst_read 0 # Number of instructions bytes read from this memory
+system.hypervisor_desc.bytes_written 0 # Number of bytes written to this memory
+system.hypervisor_desc.num_reads 9024 # Number of read requests responded to by this memory
+system.hypervisor_desc.num_writes 0 # Number of write requests responded to by this memory
+system.hypervisor_desc.num_other 0 # Number of other requests responded to by this memory
+system.hypervisor_desc.bw_read 15035 # Total read bandwidth from this memory (bytes/s)
+system.hypervisor_desc.bw_total 15035 # Total bandwidth to/from this memory (bytes/s)
+system.physmem2.bytes_read 9813991967 # Number of bytes read from this memory
+system.physmem2.bytes_inst_read 8318106840 # Number of instructions bytes read from this memory
+system.physmem2.bytes_written 897268422 # Number of bytes written to this memory
+system.physmem2.num_reads 2403489130 # Number of read requests responded to by this memory
+system.physmem2.num_writes 187387796 # Number of write requests responded to by this memory
+system.physmem2.num_other 5403067 # Number of other requests responded to by this memory
+system.physmem2.bw_read 8786901931 # Total read bandwidth from this memory (bytes/s)
+system.physmem2.bw_inst_read 7447569684 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem2.bw_write 803364182 # Write bandwidth from this memory (bytes/s)
+system.physmem2.bw_total 9590266113 # Total bandwidth to/from this memory (bytes/s)
+system.nvram.bytes_read 284 # Number of bytes read from this memory
+system.nvram.bytes_inst_read 0 # Number of instructions bytes read from this memory
+system.nvram.bytes_written 92 # Number of bytes written to this memory
+system.nvram.num_reads 284 # Number of read requests responded to by this memory
+system.nvram.num_writes 92 # Number of write requests responded to by this memory
+system.nvram.num_other 0 # Number of other requests responded to by this memory
+system.nvram.bw_read 254 # Total read bandwidth from this memory (bytes/s)
+system.nvram.bw_write 82 # Write bandwidth from this memory (bytes/s)
+system.nvram.bw_total 337 # Total bandwidth to/from this memory (bytes/s)
+system.partition_desc.bytes_read 4846 # Number of bytes read from this memory
+system.partition_desc.bytes_inst_read 0 # Number of instructions bytes read from this memory
+system.partition_desc.bytes_written 0 # Number of bytes written to this memory
+system.partition_desc.num_reads 608 # Number of read requests responded to by this memory
+system.partition_desc.num_writes 0 # Number of write requests responded to by this memory
+system.partition_desc.num_other 0 # Number of other requests responded to by this memory
+system.partition_desc.bw_read 4339 # Total read bandwidth from this memory (bytes/s)
+system.partition_desc.bw_total 4339 # Total bandwidth to/from this memory (bytes/s)
+system.rom.bytes_read 1128688 # Number of bytes read from this memory
+system.rom.bytes_inst_read 432296 # Number of instructions bytes read from this memory
+system.rom.bytes_written 0 # Number of bytes written to this memory
+system.rom.num_reads 195123 # Number of read requests responded to by this memory
+system.rom.num_writes 0 # Number of write requests responded to by this memory
+system.rom.num_other 0 # Number of other requests responded to by this memory
+system.rom.bw_read 1010564 # Total read bandwidth from this memory (bytes/s)
+system.rom.bw_inst_read 387054 # Instruction read bandwidth from this memory (bytes/s)
+system.rom.bw_total 1010564 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read 709825348 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 612291324 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 15400223 # Number of bytes written to this memory
+system.physmem.num_reads 165224885 # Number of read requests responded to by this memory
+system.physmem.num_writes 1927067 # Number of write requests responded to by this memory
+system.physmem.num_other 14 # Number of other requests responded to by this memory
+system.physmem.bw_read 635538091 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 548211557 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 13788502 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 649326593 # Total bandwidth to/from this memory (bytes/s)
system.cpu.numCycles 2233777513 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed