diff options
Diffstat (limited to 'tests/long')
56 files changed, 2159 insertions, 2200 deletions
diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini index a12b8078f..c626036a3 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/gzip +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout index ffb5e6ddd..d3f649818 100755 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout @@ -3,11 +3,10 @@ Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing/si gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 16 2011 11:08:03 -gem5 started Nov 17 2011 13:09:16 +gem5 compiled Jan 9 2012 14:18:02 +gem5 started Jan 9 2012 14:29:08 gem5 executing on ribera.cs.wisc.edu command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -tests Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt index db687aea5..9655899ee 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -3,26 +3,26 @@ sim_seconds 0.586294 # Number of seconds simulated sim_ticks 586294224000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 112274 # Simulator instruction rate (inst/s) -host_tick_rate 40595683 # Simulator tick rate (ticks/s) -host_mem_usage 244844 # Number of bytes of host memory used -host_seconds 14442.28 # Real time elapsed on the host +host_inst_rate 115446 # Simulator instruction rate (inst/s) +host_tick_rate 41742717 # Simulator tick rate (ticks/s) +host_mem_usage 244900 # Number of bytes of host memory used +host_seconds 14045.43 # Real time elapsed on the host sim_insts 1621493982 # Number of instructions simulated system.cpu.workload.num_syscalls 48 # Number of system calls system.cpu.numCycles 1172588449 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 142448983 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 142448983 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 142448982 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 142448982 # Number of conditional branches predicted system.cpu.BPredUnit.condIncorrect 7804844 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 134509889 # Number of BTB lookups +system.cpu.BPredUnit.BTBLookups 134509888 # Number of BTB lookups system.cpu.BPredUnit.BTBHits 133615988 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.fetch.icacheStallCycles 143149229 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1143761055 # Number of instructions fetch has processed -system.cpu.fetch.Branches 142448983 # Number of branches that fetch encountered +system.cpu.fetch.Insts 1143761054 # Number of instructions fetch has processed +system.cpu.fetch.Branches 142448982 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 133615988 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 330199440 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 57554993 # Number of cycles fetch has spent squashing @@ -66,32 +66,32 @@ system.cpu.rename.RenamedInsts 2043122328 # Nu system.cpu.rename.ROBFullEvents 2634 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 278313629 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 129499394 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2031527324 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4954653616 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4954649396 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 2031527322 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4954653611 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4954649391 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4220 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1617994650 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 413532674 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 413532672 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 91 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 91 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 793190427 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 519090632 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 226808407 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 354951645 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 148937435 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1986583518 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 216 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1781630005 # Number of instructions issued +system.cpu.memDep0.conflictingStores 148937436 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1986583516 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 218 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1781630004 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 180825 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 364939190 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 670712331 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 166 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 670712329 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 168 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 1172439660 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 1.519592 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.333662 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 271921708 23.19% 23.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 416937500 35.56% 58.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 271921709 23.19% 23.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 416937499 35.56% 58.75% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 234725234 20.02% 78.77% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 156776493 13.37% 92.15% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 54385701 4.64% 96.79% # Number of insts issued each cycle @@ -138,7 +138,7 @@ system.cpu.iq.fu_full::MemWrite 148998 5.73% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 26894248 1.51% 1.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1102052870 61.86% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1102052869 61.86% 63.37% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 63.37% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 63.37% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 63.37% # Type of FU issued @@ -171,17 +171,17 @@ system.cpu.iq.FU_type_0::MemRead 457985397 25.71% 89.07% # Ty system.cpu.iq.FU_type_0::MemWrite 194697490 10.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1781630005 # Type of FU issued +system.cpu.iq.FU_type_0::total 1781630004 # Type of FU issued system.cpu.iq.rate 1.519399 # Inst issue rate system.cpu.iq.fu_busy_cnt 2598665 # FU busy when requested system.cpu.iq.fu_busy_rate 0.001459 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4738479065 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 4738479063 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 2351732069 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1760053766 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 1760053765 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 95 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 542 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1757334382 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 1757334381 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 40 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 205665909 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -208,7 +208,7 @@ system.cpu.iew.memOrderViolationEvents 216417 # Nu system.cpu.iew.predictedTakenIncorrect 4603219 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 3388875 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 7992094 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1768232809 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 1768232808 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 452047218 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 13397196 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed @@ -217,8 +217,8 @@ system.cpu.iew.exec_refs 645919458 # nu system.cpu.iew.exec_branches 112169596 # Number of branches executed system.cpu.iew.exec_stores 193872240 # Number of stores executed system.cpu.iew.exec_rate 1.507974 # Inst execution rate -system.cpu.iew.wb_sent 1766226830 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1760053778 # cumulative count of insts written-back +system.cpu.iew.wb_sent 1766226829 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1760053777 # cumulative count of insts written-back system.cpu.iew.wb_producers 1336567337 # num instructions producing a value system.cpu.iew.wb_consumers 2003494286 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ @@ -268,9 +268,9 @@ system.cpu.cpi_total 0.723153 # CP system.cpu.ipc 1.382833 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.382833 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 3273039620 # number of integer regfile reads -system.cpu.int_regfile_writes 1756091293 # number of integer regfile writes +system.cpu.int_regfile_writes 1756091292 # number of integer regfile writes system.cpu.fp_regfile_reads 12 # number of floating regfile reads -system.cpu.misc_regfile_reads 908871446 # number of misc regfile reads +system.cpu.misc_regfile_reads 908871445 # number of misc regfile reads system.cpu.icache.replacements 12 # number of replacements system.cpu.icache.tagsinuse 810.394392 # Cycle average of tags in use system.cpu.icache.total_refs 137025977 # Total number of references to valid blocks. diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini index 6c9d60230..dd4d7f0aa 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -61,12 +62,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic +cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/gzip +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr index 94d399eab..ac4ad20a5 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr @@ -1,7 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout index b229bc589..510b69206 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout @@ -1,14 +1,12 @@ -M5 Simulator System +Redirecting stdout to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic/simout +Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 12:22:33 -M5 started Apr 19 2011 12:22:36 -M5 executing on maize -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic +gem5 compiled Jan 9 2012 14:18:02 +gem5 started Jan 9 2012 14:29:08 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt index f6fa9ef1e..a5e9437b0 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3280168 # Simulator instruction rate (inst/s) -host_mem_usage 202508 # Number of bytes of host memory used -host_seconds 494.33 # Real time elapsed on the host -host_tick_rate 1950088412 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1621493983 # Number of instructions simulated sim_seconds 0.963993 # Number of seconds simulated sim_ticks 963992704000 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1220339 # Simulator instruction rate (inst/s) +host_tick_rate 725502264 # Simulator tick rate (ticks/s) +host_mem_usage 234168 # Number of bytes of host memory used +host_seconds 1328.72 # Real time elapsed on the host +sim_insts 1621493983 # Number of instructions simulated +system.cpu.workload.num_syscalls 48 # Number of system calls system.cpu.numCycles 1927985409 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 1927985409 # Number of busy cycles -system.cpu.num_conditional_control_insts 99478861 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.num_insts 1621493983 # Number of instructions executed system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 99478861 # number of instructions that are conditional controls system.cpu.num_int_insts 1621354493 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions system.cpu.num_int_register_reads 3953866002 # number of times the integer registers were read system.cpu.num_int_register_writes 1617994650 # number of times the integer registers were written -system.cpu.num_load_insts 419042125 # Number of load instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 607228182 # number of memory refs +system.cpu.num_load_insts 419042125 # Number of load instructions system.cpu.num_store_insts 188186057 # Number of store instructions -system.cpu.workload.num_syscalls 48 # Number of system calls +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 1927985409 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini index fa700a969..129642a98 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -164,12 +165,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing +cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/gzip +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simerr b/tests/long/00.gzip/ref/x86/linux/simple-timing/simerr index 94d399eab..ac4ad20a5 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simerr +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simerr @@ -1,7 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout index eb8442791..613f79639 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout @@ -1,14 +1,12 @@ -M5 Simulator System +Redirecting stdout to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing/simout +Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 12:22:33 -M5 started Apr 19 2011 12:23:09 -M5 executing on maize -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing +gem5 compiled Jan 9 2012 14:18:02 +gem5 started Jan 9 2012 14:29:08 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt index 1cc5290ea..5aedfb687 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,223 +1,223 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2023797 # Simulator instruction rate (inst/s) -host_mem_usage 210248 # Number of bytes of host memory used -host_seconds 801.21 # Real time elapsed on the host -host_tick_rate 2250658484 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1621493983 # Number of instructions simulated sim_seconds 1.803259 # Number of seconds simulated sim_ticks 1803258587000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 419042125 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 20490.305383 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17490.305383 # average ReadReq mshr miss latency +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 760773 # Simulator instruction rate (inst/s) +host_tick_rate 846053445 # Simulator tick rate (ticks/s) +host_mem_usage 242892 # Number of bytes of host memory used +host_seconds 2131.38 # Real time elapsed on the host +sim_insts 1621493983 # Number of instructions simulated +system.cpu.workload.num_syscalls 48 # Number of system calls +system.cpu.numCycles 3606517174 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.num_insts 1621493983 # Number of instructions executed +system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 99478861 # number of instructions that are conditional controls +system.cpu.num_int_insts 1621354493 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 3953866002 # number of times the integer registers were read +system.cpu.num_int_register_writes 1617994650 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 607228182 # number of memory refs +system.cpu.num_load_insts 419042125 # Number of load instructions +system.cpu.num_store_insts 188186057 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 3606517174 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.icache.replacements 4 # number of replacements +system.cpu.icache.tagsinuse 660.186297 # Cycle average of tags in use +system.cpu.icache.total_refs 1186516018 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1643373.986150 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 660.186297 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.322357 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 1186516018 # number of ReadReq hits +system.cpu.icache.demand_hits 1186516018 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1186516018 # number of overall hits +system.cpu.icache.ReadReq_misses 722 # number of ReadReq misses +system.cpu.icache.demand_misses 722 # number of demand (read+write) misses +system.cpu.icache.overall_misses 722 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 40432000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 40432000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 40432000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 1186516740 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 1186516740 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 1186516740 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 722 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 722 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 722 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 38266000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 38266000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 38266000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 437952 # number of replacements +system.cpu.dcache.tagsinuse 4094.896939 # Cycle average of tags in use +system.cpu.dcache.total_refs 606786134 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 1372.670239 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 778540000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4094.896939 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999731 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits 418844799 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4043270000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000471 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 197326 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3451292000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000471 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 197326 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 23997.572756 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20997.572756 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 187941335 # number of WriteReq hits +system.cpu.dcache.demand_hits 606786134 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 606786134 # number of overall hits +system.cpu.dcache.ReadReq_misses 197326 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 244722 # number of WriteReq misses +system.cpu.dcache.demand_misses 442048 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 442048 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 4043270000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency 5872734000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 9916004000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 9916004000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 419042125 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 607228182 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 607228182 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.000471 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.001300 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 244722 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 5138568000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001300 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 244722 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1372.670239 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate 0.000728 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000728 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 20490.305383 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 23997.572756 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 22431.962140 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 22431.962140 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 607228182 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 22431.962140 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 19431.962140 # average overall mshr miss latency -system.cpu.dcache.demand_hits 606786134 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 9916004000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000728 # miss rate for demand accesses -system.cpu.dcache.demand_misses 442048 # number of demand (read+write) misses +system.cpu.dcache.writebacks 396372 # number of writebacks system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 197326 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 244722 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 442048 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 442048 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 3451292000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 5138568000 # number of WriteReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency 8589860000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 8589860000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000471 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001300 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.000728 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 442048 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 4094.896939 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999731 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 607228182 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 22431.962140 # average overall miss latency +system.cpu.dcache.overall_mshr_miss_rate 0.000728 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17490.305383 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20997.572756 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 19431.962140 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 19431.962140 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 606786134 # number of overall hits -system.cpu.dcache.overall_miss_latency 9916004000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000728 # miss rate for overall accesses -system.cpu.dcache.overall_misses 442048 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 8589860000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000728 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 442048 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 437952 # number of replacements -system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks. +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.896939 # Cycle average of tags in use -system.cpu.dcache.total_refs 606786134 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 778540000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 396372 # number of writebacks -system.cpu.icache.ReadReq_accesses 1186516740 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1186516018 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 40432000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 722 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 38266000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 722 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1643373.986150 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1186516740 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 1186516018 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 40432000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses -system.cpu.icache.demand_misses 722 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 38266000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 722 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 660.186297 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.322357 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 1186516740 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1186516018 # number of overall hits -system.cpu.icache.overall_miss_latency 40432000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses -system.cpu.icache.overall_misses 722 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 38266000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 722 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 660.186297 # Cycle average of tags in use -system.cpu.icache.total_refs 1186516018 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 244722 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 71208 # number of replacements +system.cpu.l2cache.tagsinuse 18056.923092 # Cycle average of tags in use +system.cpu.l2cache.total_refs 423014 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 86793 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.873826 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 1869.199731 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 16187.723361 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.057043 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.494010 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 166833 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 396372 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 186469 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 3029156000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.238037 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_hits 353302 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 353302 # number of overall hits +system.cpu.l2cache.ReadReq_misses 31215 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 58253 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2330120000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.238037 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 58253 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 198048 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 166833 # number of ReadReq hits +system.cpu.l2cache.demand_misses 89468 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 89468 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency 1623180000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.157613 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 31215 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1248600000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.157613 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 31215 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_miss_latency 3029156000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 4652336000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 4652336000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 198048 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 396372 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 396372 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.873826 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_accesses 244722 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 442770 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 442770 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.157613 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.238037 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.202064 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.202064 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 442770 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 353302 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 4652336000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.202064 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 89468 # number of demand (read+write) misses +system.cpu.l2cache.writebacks 58007 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 31215 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 58253 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 89468 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 89468 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1248600000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2330120000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency 3578720000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 3578720000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.157613 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.238037 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.202064 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 89468 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 1869.199731 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16187.723361 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.057043 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.494010 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 442770 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_mshr_miss_rate 0.202064 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 353302 # number of overall hits -system.cpu.l2cache.overall_miss_latency 4652336000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.202064 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 89468 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 3578720000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.202064 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 89468 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 71208 # number of replacements -system.cpu.l2cache.sampled_refs 86793 # Sample count of references to valid blocks. +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18056.923092 # Cycle average of tags in use -system.cpu.l2cache.total_refs 423014 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 58007 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 3606517174 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 3606517174 # Number of busy cycles -system.cpu.num_conditional_control_insts 99478861 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 1621493983 # Number of instructions executed -system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses -system.cpu.num_int_insts 1621354493 # number of integer instructions -system.cpu.num_int_register_reads 3953866002 # number of times the integer registers were read -system.cpu.num_int_register_writes 1617994650 # number of times the integer registers were written -system.cpu.num_load_insts 419042125 # Number of load instructions -system.cpu.num_mem_refs 607228182 # number of memory refs -system.cpu.num_store_insts 188186057 # Number of store instructions -system.cpu.workload.num_syscalls 48 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index 5371c92be..9ef75afe6 100644 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -15,10 +15,11 @@ e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/projects/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing memories=system.physmem +num_work_ids=16 physmem=system.physmem readfile=tests/halt.sh smbios_table=system.smbios_table @@ -1301,7 +1302,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-x86.img +image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1321,7 +1322,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index 795bcf9d9..18f42b689 100755 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,13 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 21 2011 16:24:08 -gem5 started Nov 21 2011 23:30:30 -gem5 executing on u200540-lin -command line: build/X86_FS/gem5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing +gem5 compiled Jan 9 2012 20:47:38 +gem5 started Jan 9 2012 21:13:16 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86_FS/gem5.fast -d build/X86_FS/tests/fast/long/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86_FS/tests/fast/long/10.linux-boot/x86/linux/pc-o3-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9 - 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 +info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5145286546500 because m5_exit instruction encountered +Exiting @ tick 5161177988500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index f0652d752..e687ea7eb 100644 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,97 +1,97 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.145287 # Number of seconds simulated -sim_ticks 5145286546500 # Number of ticks simulated +sim_seconds 5.161178 # Number of seconds simulated +sim_ticks 5161177988500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 333179 # Simulator instruction rate (inst/s) -host_tick_rate 2041066369 # Simulator tick rate (ticks/s) -host_mem_usage 358476 # Number of bytes of host memory used -host_seconds 2520.88 # Real time elapsed on the host -sim_insts 839904894 # Number of instructions simulated -system.l2c.replacements 171120 # number of replacements -system.l2c.tagsinuse 38411.926866 # Cycle average of tags in use -system.l2c.total_refs 3818646 # Total number of references to valid blocks. -system.l2c.sampled_refs 206013 # Sample count of references to valid blocks. -system.l2c.avg_refs 18.535947 # Average number of references to valid blocks. +host_inst_rate 384526 # Simulator instruction rate (inst/s) +host_tick_rate 2360358751 # Simulator tick rate (ticks/s) +host_mem_usage 386468 # Number of bytes of host memory used +host_seconds 2186.61 # Real time elapsed on the host +sim_insts 840808469 # Number of instructions simulated +system.l2c.replacements 169467 # number of replacements +system.l2c.tagsinuse 38339.786444 # Cycle average of tags in use +system.l2c.total_refs 3812924 # Total number of references to valid blocks. +system.l2c.sampled_refs 204660 # Sample count of references to valid blocks. +system.l2c.avg_refs 18.630529 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 11983.527500 # Average occupied blocks per context -system.l2c.occ_blocks::1 26428.399366 # Average occupied blocks per context -system.l2c.occ_percent::0 0.182854 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.403265 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 2330328 # number of ReadReq hits -system.l2c.ReadReq_hits::1 145914 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2476242 # number of ReadReq hits -system.l2c.Writeback_hits::0 1599020 # number of Writeback hits -system.l2c.Writeback_hits::total 1599020 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 343 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 343 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::0 150210 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 150210 # number of ReadExReq hits -system.l2c.demand_hits::0 2480538 # number of demand (read+write) hits -system.l2c.demand_hits::1 145914 # number of demand (read+write) hits -system.l2c.demand_hits::total 2626452 # number of demand (read+write) hits -system.l2c.overall_hits::0 2480538 # number of overall hits -system.l2c.overall_hits::1 145914 # number of overall hits -system.l2c.overall_hits::total 2626452 # number of overall hits -system.l2c.ReadReq_misses::0 68080 # number of ReadReq misses -system.l2c.ReadReq_misses::1 84 # number of ReadReq misses -system.l2c.ReadReq_misses::total 68164 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 3905 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3905 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 142426 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 142426 # number of ReadExReq misses -system.l2c.demand_misses::0 210506 # number of demand (read+write) misses -system.l2c.demand_misses::1 84 # number of demand (read+write) misses -system.l2c.demand_misses::total 210590 # number of demand (read+write) misses -system.l2c.overall_misses::0 210506 # number of overall misses -system.l2c.overall_misses::1 84 # number of overall misses -system.l2c.overall_misses::total 210590 # number of overall misses -system.l2c.ReadReq_miss_latency 3574844000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 37228000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 7453066500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 11027910500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 11027910500 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2398408 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 145998 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2544406 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 1599020 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1599020 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 4248 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4248 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 292636 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 292636 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2691044 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 145998 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2837042 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2691044 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 145998 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2837042 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.028385 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.000575 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.028961 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.919256 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.486700 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.078225 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.000575 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.078800 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.078225 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.000575 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.078800 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52509.459459 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 42557666.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 42610176.126126 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 9533.418694 # average UpgradeReq miss latency +system.l2c.occ_blocks::0 11950.408174 # Average occupied blocks per context +system.l2c.occ_blocks::1 26389.378270 # Average occupied blocks per context +system.l2c.occ_percent::0 0.182349 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.402670 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 2335607 # number of ReadReq hits +system.l2c.ReadReq_hits::1 145488 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2481095 # number of ReadReq hits +system.l2c.Writeback_hits::0 1594493 # number of Writeback hits +system.l2c.Writeback_hits::total 1594493 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 327 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 327 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::0 150672 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 150672 # number of ReadExReq hits +system.l2c.demand_hits::0 2486279 # number of demand (read+write) hits +system.l2c.demand_hits::1 145488 # number of demand (read+write) hits +system.l2c.demand_hits::total 2631767 # number of demand (read+write) hits +system.l2c.overall_hits::0 2486279 # number of overall hits +system.l2c.overall_hits::1 145488 # number of overall hits +system.l2c.overall_hits::total 2631767 # number of overall hits +system.l2c.ReadReq_misses::0 66850 # number of ReadReq misses +system.l2c.ReadReq_misses::1 109 # number of ReadReq misses +system.l2c.ReadReq_misses::total 66959 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 3932 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3932 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::0 142221 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 142221 # number of ReadExReq misses +system.l2c.demand_misses::0 209071 # number of demand (read+write) misses +system.l2c.demand_misses::1 109 # number of demand (read+write) misses +system.l2c.demand_misses::total 209180 # number of demand (read+write) misses +system.l2c.overall_misses::0 209071 # number of overall misses +system.l2c.overall_misses::1 109 # number of overall misses +system.l2c.overall_misses::total 209180 # number of overall misses +system.l2c.ReadReq_miss_latency 3511861000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 38996000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 7442399000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 10954260000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 10954260000 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 2402457 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 145597 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2548054 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 1594493 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1594493 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 4259 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 4259 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 292893 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 292893 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 2695350 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 145597 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2840947 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 2695350 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 145597 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2840947 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.027826 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.000749 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.028574 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.923221 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.485573 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.077567 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.000749 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.078316 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.077567 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.000749 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.078316 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 52533.448018 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 32218908.256881 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 32271441.704899 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 9917.599186 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52329.395616 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 52329.817678 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52387.630281 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 131284648.809524 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 131337036.439805 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52387.630281 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 131284648.809524 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 131337036.439805 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 52394.928039 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 100497798.165138 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 100550193.093176 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 52394.928039 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 100497798.165138 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 100550193.093176 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -100,58 +100,58 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 142550 # number of writebacks +system.l2c.writebacks 142631 # number of writebacks system.l2c.ReadReq_mshr_hits 2 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits 2 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits 2 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 68162 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 3905 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 142426 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 210588 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 210588 # number of overall MSHR misses +system.l2c.ReadReq_mshr_misses 66957 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 3932 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 142221 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 209178 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 209178 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 2743592500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 156565000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5717024500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 8460617000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 8460617000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 61532546500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1222452000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 62754998500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.028420 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.466869 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.495289 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.919256 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_latency 2695362500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 157637000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 5708607000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 8403969500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 8403969500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 59978490000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 1230737500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 61209227500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.027870 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.459879 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.487749 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 0.923221 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.486700 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.485573 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.078255 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.442403 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 1.520658 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.078255 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.442403 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 1.520658 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40251.056307 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40093.469910 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40140.314971 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40176.159135 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40176.159135 # average overall mshr miss latency +system.l2c.demand_mshr_miss_rate::0 0.077607 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.436692 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 1.514299 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.077607 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.436692 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 1.514299 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency 40255.126424 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40090.793489 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40138.987913 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40176.163363 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40176.163363 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47572 # number of replacements -system.iocache.tagsinuse 0.146650 # Cycle average of tags in use +system.iocache.replacements 47573 # number of replacements +system.iocache.tagsinuse 0.195398 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47588 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47589 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4994510051000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 0.146650 # Average occupied blocks per context -system.iocache.occ_percent::1 0.009166 # Average percentage of cache occupancy +system.iocache.warmup_cycle 4994542788000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 0.195398 # Average occupied blocks per context +system.iocache.occ_percent::1 0.012212 # Average percentage of cache occupancy system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits @@ -168,10 +168,10 @@ system.iocache.demand_misses::total 47627 # nu system.iocache.overall_misses::0 0 # number of overall misses system.iocache.overall_misses::1 47627 # number of overall misses system.iocache.overall_misses::total 47627 # number of overall misses -system.iocache.ReadReq_miss_latency 113785932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency 6369912160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency 6483698092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 6483698092 # number of overall miss cycles +system.iocache.ReadReq_miss_latency 113669932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency 6372391160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency 6486061092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 6486061092 # number of overall miss cycles system.iocache.ReadReq_accesses::1 907 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses) @@ -191,26 +191,26 @@ system.iocache.overall_miss_rate::0 no_value # mi system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 125453.067255 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 125325.173098 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 136342.297945 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 136395.358733 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 136134.925399 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 136184.540114 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 136134.925399 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 136184.540114 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 68669502 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 68679532 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11260 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11251 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6098.534813 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6104.304684 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 46667 # number of writebacks +system.iocache.writebacks 46668 # number of writebacks system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.iocache.overall_mshr_hits 0 # number of overall MSHR hits system.iocache.ReadReq_mshr_misses 907 # number of ReadReq MSHR misses @@ -218,10 +218,10 @@ system.iocache.WriteReq_mshr_misses 46720 # nu system.iocache.demand_mshr_misses 47627 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses 47627 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.ReadReq_mshr_miss_latency 66598982 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3940155856 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 4006754838 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 4006754838 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 66482982 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3942637876 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency 4009120858 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 4009120858 # number of overall MSHR miss cycles system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses @@ -235,10 +235,10 @@ system.iocache.demand_mshr_miss_rate::total inf # system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency 73427.764057 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 84335.527740 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 84127.802255 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 84127.802255 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 73299.869901 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 84388.653168 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 84177.480379 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 84177.480379 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -255,140 +255,141 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 449021643 # number of cpu cycles simulated +system.cpu.numCycles 449878562 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 91138491 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 91138491 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1248082 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 89857544 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 83686998 # Number of BTB hits +system.cpu.BPredUnit.lookups 91189820 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 91189820 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1250253 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 90006318 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 83822675 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 28288670 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 450771327 # Number of instructions fetch has processed -system.cpu.fetch.Branches 91138491 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 83686998 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 171087914 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6045536 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 191873 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 82674920 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 36392 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 54951 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 281 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9822160 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 542562 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4016 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 287044907 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.085924 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.403637 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28390554 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 451032028 # Number of instructions fetch has processed +system.cpu.fetch.Branches 91189820 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 83822675 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 171638033 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6092005 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 127923 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 86885537 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 36685 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 38090 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 283 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9866979 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 541048 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 3553 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 291873782 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.039474 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.398963 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 116472661 40.58% 40.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1490084 0.52% 41.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72800190 25.36% 66.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1427390 0.50% 66.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1806479 0.63% 67.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3992507 1.39% 68.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1571582 0.55% 69.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2063795 0.72% 70.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 85420219 29.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 120818032 41.39% 41.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1855546 0.64% 42.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72826244 24.95% 66.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1422491 0.49% 67.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1829890 0.63% 68.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4020066 1.38% 69.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1590838 0.55% 70.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1683069 0.58% 70.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 85827606 29.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 287044907 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.202971 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.003897 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 33370892 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 79040686 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 165533455 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4389968 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4709906 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 881886507 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 578 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4709906 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37547254 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 52554502 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10077381 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 165462513 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 16693351 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 877383155 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 14371 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 11668719 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2142745 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 879650717 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1723132927 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1723132383 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 544 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 843287047 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36363663 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 486686 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 487762 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 43318784 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19666821 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10717044 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1121000 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1013044 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 870450598 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 900193 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 866206507 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 178001 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 30597956 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 44655599 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 144106 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 287044907 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.017669 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.373774 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 291873782 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.202699 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.002564 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 33589176 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 83124342 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 166020087 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4383500 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4756677 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 883216023 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 571 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4756677 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37852860 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 55892656 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9911063 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 165583689 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 17876837 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 878703692 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 12652 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 12602978 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2126989 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 10 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 880098416 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1724229495 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1724229039 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 456 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 843418783 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 36679626 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 488930 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 489908 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 44000804 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19727758 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10753359 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1338256 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1089668 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 870922009 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1727938 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 867227375 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 177419 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 30993538 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 45221667 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 207753 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 291873782 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.971241 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.381572 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 82633676 28.79% 28.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 22379993 7.80% 36.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 14042555 4.89% 41.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 9676323 3.37% 44.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 79535811 27.71% 72.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 5032653 1.75% 74.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72954170 25.42% 99.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 636902 0.22% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 152824 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 86148709 29.52% 29.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 24105973 8.26% 37.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 13574297 4.65% 42.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 9676822 3.32% 45.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 79595279 27.27% 73.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 5022101 1.72% 74.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72958833 25.00% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 636421 0.22% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 155347 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 287044907 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 291873782 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 195893 8.77% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1841396 82.43% 91.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 196729 8.81% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 202428 8.97% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1851752 82.02% 90.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 203495 9.01% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 302784 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 830728417 95.90% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 306567 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 831752185 95.91% 95.94% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 95.94% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 95.94% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 95.94% # Type of FU issued @@ -417,253 +418,253 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 95.94% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 95.94% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 95.94% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 95.94% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25630184 2.96% 98.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9545122 1.10% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25621043 2.95% 98.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9547580 1.10% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 866206507 # Type of FU issued -system.cpu.iq.rate 1.929097 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2234018 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.002579 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2022023513 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 901959019 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 855369267 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 203 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 252 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 52 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 868137651 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 90 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1362479 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 867227375 # Type of FU issued +system.cpu.iq.rate 1.927692 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2257675 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.002603 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2028918942 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 903653765 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 856397776 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 194 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 210 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 50 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 869178395 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 88 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1343949 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4321864 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 17926 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11344 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2286443 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4393917 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 17180 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11337 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2321478 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7817280 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 160300 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7817249 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 160526 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4709906 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 33528904 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6021560 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 871350791 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 302780 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19666821 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10717077 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 894230 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 5567968 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 26441 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11344 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 900317 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 526461 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1426778 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 864071451 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25139822 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2135055 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4756677 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 34884624 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6122535 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 872649947 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 301193 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19727758 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10753386 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 894363 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 5389997 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 26295 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11337 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 906001 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 524480 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1430481 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 865094857 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25131798 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2132517 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 34444060 # number of memory reference insts executed -system.cpu.iew.exec_branches 86704764 # Number of branches executed -system.cpu.iew.exec_stores 9304238 # Number of stores executed -system.cpu.iew.exec_rate 1.924343 # Inst execution rate -system.cpu.iew.wb_sent 863434483 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 855369319 # cumulative count of insts written-back -system.cpu.iew.wb_producers 671433691 # num instructions producing a value -system.cpu.iew.wb_consumers 1171953644 # num instructions consuming a value +system.cpu.iew.exec_refs 34436194 # number of memory reference insts executed +system.cpu.iew.exec_branches 86723634 # Number of branches executed +system.cpu.iew.exec_stores 9304396 # Number of stores executed +system.cpu.iew.exec_rate 1.922952 # Inst execution rate +system.cpu.iew.wb_sent 864455877 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 856397826 # cumulative count of insts written-back +system.cpu.iew.wb_producers 671292665 # num instructions producing a value +system.cpu.iew.wb_consumers 1171999804 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.904962 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.572918 # average fanout of values written-back +system.cpu.iew.wb_rate 1.903620 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.572775 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 839904894 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 31338704 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 756085 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1254700 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 282350978 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.974684 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.863709 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 840808469 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 31735206 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1520183 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1254406 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 287133088 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.928288 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.869814 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 102836465 36.42% 36.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 12523164 4.44% 40.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4697520 1.66% 42.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 76975529 27.26% 69.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4042949 1.43% 71.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1857352 0.66% 71.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1067382 0.38% 72.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71607681 25.36% 97.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6742936 2.39% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 107529680 37.45% 37.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13316862 4.64% 42.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3946452 1.37% 43.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 76651474 26.70% 70.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4051645 1.41% 71.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1852261 0.65% 72.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1054561 0.37% 72.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71992194 25.07% 97.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6737959 2.35% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 282350978 # Number of insts commited each cycle -system.cpu.commit.count 839904894 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 287133088 # Number of insts commited each cycle +system.cpu.commit.count 840808469 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 23775588 # Number of memory references committed -system.cpu.commit.loads 15344954 # Number of loads committed -system.cpu.commit.membars 3541 # Number of memory barriers committed -system.cpu.commit.branches 85526796 # Number of branches committed +system.cpu.commit.refs 23765746 # Number of memory references committed +system.cpu.commit.loads 15333838 # Number of loads committed +system.cpu.commit.membars 781579 # Number of memory barriers committed +system.cpu.commit.branches 85539454 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 768518485 # Number of committed integer instructions. +system.cpu.commit.int_insts 768627958 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6742936 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6737959 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1146769000 # The number of ROB reads -system.cpu.rob.rob_writes 1747209492 # The number of ROB writes -system.cpu.timesIdled 3079387 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 161976736 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9841548887 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 839904894 # Number of Instructions Simulated -system.cpu.committedInsts_total 839904894 # Number of Instructions Simulated -system.cpu.cpi 0.534610 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.534610 # CPI: Total CPI of All Threads -system.cpu.ipc 1.870522 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.870522 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1407118516 # number of integer regfile reads -system.cpu.int_regfile_writes 857404874 # number of integer regfile writes -system.cpu.fp_regfile_reads 52 # number of floating regfile reads -system.cpu.misc_regfile_reads 282285829 # number of misc regfile reads -system.cpu.misc_regfile_writes 410057 # number of misc regfile writes -system.cpu.icache.replacements 1028866 # number of replacements -system.cpu.icache.tagsinuse 510.467349 # Cycle average of tags in use -system.cpu.icache.total_refs 8724446 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1029378 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8.475454 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 54553290000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 510.467349 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.997007 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 8724446 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8724446 # number of ReadReq hits -system.cpu.icache.demand_hits::0 8724446 # number of demand (read+write) hits +system.cpu.rob.rob_reads 1152856114 # The number of ROB reads +system.cpu.rob.rob_writes 1749856645 # The number of ROB writes +system.cpu.timesIdled 3066243 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 158004780 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9872474852 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 840808469 # Number of Instructions Simulated +system.cpu.committedInsts_total 840808469 # Number of Instructions Simulated +system.cpu.cpi 0.535055 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.535055 # CPI: Total CPI of All Threads +system.cpu.ipc 1.868968 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.868968 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1407444841 # number of integer regfile reads +system.cpu.int_regfile_writes 857665866 # number of integer regfile writes +system.cpu.fp_regfile_reads 50 # number of floating regfile reads +system.cpu.misc_regfile_reads 282350765 # number of misc regfile reads +system.cpu.misc_regfile_writes 410137 # number of misc regfile writes +system.cpu.icache.replacements 1031767 # number of replacements +system.cpu.icache.tagsinuse 510.488308 # Cycle average of tags in use +system.cpu.icache.total_refs 8766017 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1032279 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 8.491907 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 54591118000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 510.488308 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.997047 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::0 8766017 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8766017 # number of ReadReq hits +system.cpu.icache.demand_hits::0 8766017 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8724446 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 8724446 # number of overall hits +system.cpu.icache.demand_hits::total 8766017 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 8766017 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 8724446 # number of overall hits -system.cpu.icache.ReadReq_misses::0 1097711 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1097711 # number of ReadReq misses -system.cpu.icache.demand_misses::0 1097711 # number of demand (read+write) misses +system.cpu.icache.overall_hits::total 8766017 # number of overall hits +system.cpu.icache.ReadReq_misses::0 1100959 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1100959 # number of ReadReq misses +system.cpu.icache.demand_misses::0 1100959 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1097711 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 1097711 # number of overall misses +system.cpu.icache.demand_misses::total 1100959 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 1100959 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1097711 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 16447038991 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 16447038991 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 16447038991 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 9822157 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9822157 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 9822157 # number of demand (read+write) accesses +system.cpu.icache.overall_misses::total 1100959 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 16475831488 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 16475831488 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 16475831488 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 9866976 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9866976 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 9866976 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9822157 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 9822157 # number of overall (read+write) accesses +system.cpu.icache.demand_accesses::total 9866976 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 9866976 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9822157 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.111759 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.111759 # miss rate for demand accesses +system.cpu.icache.overall_accesses::total 9866976 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.111580 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.111580 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.111759 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.111580 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14983.031956 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::0 14964.981882 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14983.031956 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::0 14964.981882 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14983.031956 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 14964.981882 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2545992 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 2787490 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 258 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 276 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 9868.186047 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 10099.601449 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 1562 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 65787 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 65787 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 65787 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1031924 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1031924 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1031924 # number of overall MSHR misses +system.cpu.icache.writebacks 1565 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 66134 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 66134 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 66134 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 1034825 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 1034825 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 1034825 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 12476028992 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 12476028992 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 12476028992 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 12496503490 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 12496503490 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 12496503490 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.105061 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.104878 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.105061 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.104878 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.105061 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.104878 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 12090.065734 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 12090.065734 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 12090.065734 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12075.958244 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12075.958244 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12075.958244 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 14158 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.014381 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 26217 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 14168 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 1.850438 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5108050090000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::1 6.014381 # Average occupied blocks per context -system.cpu.itb_walker_cache.occ_percent::1 0.375899 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::1 26573 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 26573 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 8819 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.022437 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 26537 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 8831 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 3.004982 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5118899189000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::1 6.022437 # Average occupied blocks per context +system.cpu.itb_walker_cache.occ_percent::1 0.376402 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::1 26634 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 26634 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::1 3 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits system.cpu.itb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::1 26576 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 26576 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::1 26637 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 26637 # number of demand (read+write) hits system.cpu.itb_walker_cache.overall_hits::0 0 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::1 26576 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 26576 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::1 15025 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 15025 # number of ReadReq misses +system.cpu.itb_walker_cache.overall_hits::1 26637 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 26637 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::1 9699 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 9699 # number of ReadReq misses system.cpu.itb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::1 15025 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 15025 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::1 9699 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 9699 # number of demand (read+write) misses system.cpu.itb_walker_cache.overall_misses::0 0 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::1 15025 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 15025 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency 189764500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency 189764500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency 189764500 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::1 41598 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 41598 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.overall_misses::1 9699 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 9699 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency 124296000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency 124296000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency 124296000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::1 36333 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 36333 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::1 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::1 41601 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 41601 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::1 36336 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 36336 # number of demand (read+write) accesses system.cpu.itb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::1 41601 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 41601 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.361195 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.overall_accesses::1 36336 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 36336 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.266947 # miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::1 0.361169 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::1 0.266925 # miss rate for demand accesses system.cpu.itb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu.itb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::1 0.361169 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::1 0.266925 # miss rate for overall accesses system.cpu.itb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 12629.916805 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 12815.341788 # average ReadReq miss latency system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu.itb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::1 12629.916805 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::1 12815.341788 # average overall miss latency system.cpu.itb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu.itb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::1 12629.916805 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::1 12815.341788 # average overall miss latency system.cpu.itb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -673,83 +674,83 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks 2705 # number of writebacks +system.cpu.itb_walker_cache.writebacks 1368 # number of writebacks system.cpu.itb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.itb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.itb_walker_cache.ReadReq_mshr_misses 15025 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses 15025 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses 15025 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses 9699 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses 9699 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses 9699 # number of overall MSHR misses system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency 144320000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency 144320000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency 144320000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency 94849000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency 94849000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency 94849000 # number of overall MSHR miss cycles system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1 0.361195 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1 0.266947 # mshr miss rate for ReadReq accesses system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0.361169 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0.266925 # mshr miss rate for demand accesses system.cpu.itb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu.itb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0.361169 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0.266925 # mshr miss rate for overall accesses system.cpu.itb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency 9605.324459 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency 9605.324459 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency 9605.324459 # average overall mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency 9779.255593 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency 9779.255593 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency 9779.255593 # average overall mshr miss latency system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.itb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.itb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 144708 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 13.855241 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 146935 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 144723 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.015284 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5098934458000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::1 13.855241 # Average occupied blocks per context -system.cpu.dtb_walker_cache.occ_percent::1 0.865953 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::1 147187 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 147187 # number of ReadReq hits +system.cpu.dtb_walker_cache.replacements 145081 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 13.868389 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 150553 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 145096 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.037610 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5102657828000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::1 13.868389 # Average occupied blocks per context +system.cpu.dtb_walker_cache.occ_percent::1 0.866774 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::1 150554 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 150554 # number of ReadReq hits system.cpu.dtb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::1 147187 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 147187 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::1 150554 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 150554 # number of demand (read+write) hits system.cpu.dtb_walker_cache.overall_hits::0 0 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::1 147187 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 147187 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::1 145638 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 145638 # number of ReadReq misses +system.cpu.dtb_walker_cache.overall_hits::1 150554 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 150554 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::1 146024 # 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number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::1 292825 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 292825 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.overall_misses::1 146024 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 146024 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency 2047200500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency 2047200500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency 2047200500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::1 296578 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 296578 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::1 292825 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 292825 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::1 296578 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 296578 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::1 292825 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 292825 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.497355 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.overall_accesses::1 296578 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 296578 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.492363 # miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::1 0.497355 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::1 0.492363 # miss rate for demand accesses system.cpu.dtb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu.dtb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::1 0.497355 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::1 0.492363 # miss rate for overall accesses system.cpu.dtb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 13812.744613 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 14019.616638 # average ReadReq miss latency system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu.dtb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 13812.744613 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 14019.616638 # average overall miss latency system.cpu.dtb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu.dtb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 13812.744613 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 14019.616638 # average overall miss latency system.cpu.dtb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -759,136 +760,136 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # 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mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1 0.492363 # mshr miss rate for ReadReq accesses system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0.497355 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0.492363 # mshr miss rate for demand accesses system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0.497355 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0.492363 # mshr miss rate for overall accesses system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 10785.509276 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 10785.509276 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 10785.509276 # average overall mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 10992.460144 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 10992.460144 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 10992.460144 # average overall mshr miss latency system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dtb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1661747 # number of replacements -system.cpu.dcache.tagsinuse 511.998367 # Cycle average of tags in use -system.cpu.dcache.total_refs 17960054 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1662259 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 10.804606 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1663087 # number of replacements +system.cpu.dcache.tagsinuse 511.997625 # Cycle average of tags in use +system.cpu.dcache.total_refs 17982371 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1663599 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 10.809318 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 13135000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.998367 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999997 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 11390626 # 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number of WriteReq misses +system.cpu.dcache.demand_misses::0 4367738 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4364230 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 4364230 # number of overall misses +system.cpu.dcache.demand_misses::total 4367738 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::0 4367738 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 4364230 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 37598789500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 63471421475 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 101070210975 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 101070210975 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 13880972 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13880972 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 8421334 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8421334 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 22302306 # number of demand (read+write) accesses +system.cpu.dcache.overall_misses::total 4367738 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 37542071500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 63453033216 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 100995104716 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 100995104716 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::0 13905507 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13905507 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 8422560 # 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miss rate for demand accesses +system.cpu.dcache.overall_accesses::total 22328067 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.179234 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.222664 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::0 0.195616 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.195685 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.195616 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 15097.817532 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::0 15062.981576 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 33871.585154 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 33834.435792 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 23158.772790 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::0 23122.976863 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 23158.772790 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 23122.976863 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1083244649 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 6672500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 73213 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 1083233153 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 6672000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 73547 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 391 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 14795.796498 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 17065.217391 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14728.447836 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 17063.938619 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1547981 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1120147 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1577106 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 2697253 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 2697253 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1370199 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 296778 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1666977 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1666977 # number of overall MSHR misses +system.cpu.dcache.writebacks 1548983 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 1121085 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1578340 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 2699425 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 2699425 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1371255 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 297058 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1668313 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1668313 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 18186929000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 9757421649 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 27944350649 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 27944350649 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 86947016500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1386048000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 88333064500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.098711 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 18154950000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 9754920653 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 27909870653 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 27909870653 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 85210888500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1394917000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 86605805500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.098612 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.035241 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.035269 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.074745 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.074718 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.074745 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.074718 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13273.202652 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32877.846906 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 16763.489028 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 16763.489028 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13239.660019 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32838.437790 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 16729.397093 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 16729.397093 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal index 85136ebe7..6570dc326 100644 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal @@ -23,7 +23,7 @@ Built 1 zonelists. Total pages: 30458 Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
Initializing CPU#0
PID hash table entries: 512 (order: 9, 4096 bytes)
-time.c: Detected 2000.004 MHz processor.
+time.c: Detected 2000.000 MHz processor.
Console: colour dummy device 80x25
console handover: boot [earlyser0] -> real [ttyS0]
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
@@ -39,7 +39,7 @@ ACPI: Core revision 20070126 ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
ACPI: Unable to load the System Description Tables
Using local APIC timer interrupts.
-result 7812511
+result 7812497
Detected 7.812 MHz APIC timer.
NET: Registered protocol family 16
PCI: Using configuration type 1
diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini index df2fb6f73..103b3f085 100644 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -500,9 +500,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/mcf +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout index f9ce22b4b..5b6f3a1bd 100755 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout @@ -3,11 +3,10 @@ Redirecting stderr to build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing/sim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 16 2011 11:08:03 -gem5 started Nov 17 2011 13:09:16 +gem5 compiled Jan 9 2012 14:18:02 +gem5 started Jan 9 2012 14:29:08 gem5 executing on ribera.cs.wisc.edu command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing -tests Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt index 011648483..6fc7a3666 100644 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -3,10 +3,10 @@ sim_seconds 0.070313 # Number of seconds simulated sim_ticks 70312944500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125815 # Simulator instruction rate (inst/s) -host_tick_rate 31799589 # Simulator tick rate (ticks/s) -host_mem_usage 378944 # Number of bytes of host memory used -host_seconds 2211.13 # Real time elapsed on the host +host_inst_rate 109444 # Simulator instruction rate (inst/s) +host_tick_rate 27661822 # Simulator tick rate (ticks/s) +host_mem_usage 378996 # Number of bytes of host memory used +host_seconds 2541.88 # Real time elapsed on the host sim_insts 278192519 # Number of instructions simulated system.cpu.workload.num_syscalls 444 # Number of system calls system.cpu.numCycles 140625890 # number of cpu cycles simulated diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini index f21f47f4d..aaa5a7780 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -61,14 +62,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic +cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/mcf +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr index 94d399eab..ac4ad20a5 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr @@ -1,7 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 hack: be nice to actually delete the event here diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout index 0d61b002c..c929e4789 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout @@ -1,14 +1,12 @@ -M5 Simulator System +Redirecting stdout to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic/simout +Redirecting stderr to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 12:22:33 -M5 started Apr 19 2011 12:39:34 -M5 executing on maize -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic +gem5 compiled Jan 9 2012 14:18:02 +gem5 started Jan 9 2012 14:29:08 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt index ed3183ec3..0cce68f38 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3107267 # Simulator instruction rate (inst/s) -host_mem_usage 337076 # Number of bytes of host memory used -host_seconds 89.53 # Real time elapsed on the host -host_tick_rate 1887081425 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 278192520 # Number of instructions simulated sim_seconds 0.168950 # Number of seconds simulated sim_ticks 168950072000 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1147935 # Simulator instruction rate (inst/s) +host_tick_rate 697156581 # Simulator tick rate (ticks/s) +host_mem_usage 368676 # Number of bytes of host memory used +host_seconds 242.34 # Real time elapsed on the host +sim_insts 278192520 # Number of instructions simulated +system.cpu.workload.num_syscalls 444 # Number of system calls system.cpu.numCycles 337900145 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 337900145 # Number of busy cycles -system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses -system.cpu.num_fp_insts 40 # number of float instructions -system.cpu.num_fp_register_reads 40 # number of times the floating registers were read -system.cpu.num_fp_register_writes 26 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.num_insts 278192520 # Number of instructions executed system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls system.cpu.num_int_insts 278186228 # number of integer instructions +system.cpu.num_fp_insts 40 # number of float instructions system.cpu.num_int_register_reads 685043114 # number of times the integer registers were read system.cpu.num_int_register_writes 248344166 # number of times the integer registers were written -system.cpu.num_load_insts 90779388 # Number of load instructions +system.cpu.num_fp_register_reads 40 # number of times the floating registers were read +system.cpu.num_fp_register_writes 26 # number of times the floating registers were written system.cpu.num_mem_refs 122219139 # number of memory refs +system.cpu.num_load_insts 90779388 # Number of load instructions system.cpu.num_store_insts 31439751 # Number of store instructions -system.cpu.workload.num_syscalls 444 # Number of system calls +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 337900145 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini index 2184f1531..2ff958baf 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -164,14 +165,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing +cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/mcf +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simerr b/tests/long/10.mcf/ref/x86/linux/simple-timing/simerr index 94d399eab..ac4ad20a5 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simerr +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simerr @@ -1,7 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 hack: be nice to actually delete the event here diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout index 1d6e35c6c..07f15598f 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout @@ -1,14 +1,12 @@ -M5 Simulator System +Redirecting stdout to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing/simout +Redirecting stderr to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 12:22:33 -M5 started Apr 19 2011 12:41:14 -M5 executing on maize -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing +gem5 compiled Jan 9 2012 14:18:02 +gem5 started Jan 9 2012 14:29:08 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt index e994cf670..35887f197 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,223 +1,223 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1776708 # Simulator instruction rate (inst/s) -host_mem_usage 344820 # Number of bytes of host memory used -host_seconds 156.58 # Real time elapsed on the host -host_tick_rate 2363113199 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 278192520 # Number of instructions simulated sim_seconds 0.370011 # Number of seconds simulated sim_ticks 370010840000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 90779450 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 14713.502183 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11713.502183 # average ReadReq mshr miss latency +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 588786 # Simulator instruction rate (inst/s) +host_tick_rate 783116445 # Simulator tick rate (ticks/s) +host_mem_usage 377276 # Number of bytes of host memory used +host_seconds 472.49 # Real time elapsed on the host +sim_insts 278192520 # Number of instructions simulated +system.cpu.workload.num_syscalls 444 # Number of system calls +system.cpu.numCycles 740021680 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.num_insts 278192520 # Number of instructions executed +system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls +system.cpu.num_int_insts 278186228 # number of integer instructions +system.cpu.num_fp_insts 40 # number of float instructions +system.cpu.num_int_register_reads 685043114 # number of times the integer registers were read +system.cpu.num_int_register_writes 248344166 # number of times the integer registers were written +system.cpu.num_fp_register_reads 40 # number of times the floating registers were read +system.cpu.num_fp_register_writes 26 # number of times the floating registers were written +system.cpu.num_mem_refs 122219139 # number of memory refs +system.cpu.num_load_insts 90779388 # Number of load instructions +system.cpu.num_store_insts 31439751 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 740021680 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.icache.replacements 24 # number of replacements +system.cpu.icache.tagsinuse 666.191948 # Cycle average of tags in use +system.cpu.icache.total_refs 217695401 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 269425.001238 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 666.191948 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.325289 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 217695401 # number of ReadReq hits +system.cpu.icache.demand_hits 217695401 # number of demand (read+write) hits +system.cpu.icache.overall_hits 217695401 # number of overall hits +system.cpu.icache.ReadReq_misses 808 # number of ReadReq misses +system.cpu.icache.demand_misses 808 # number of demand (read+write) misses +system.cpu.icache.overall_misses 808 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 45248000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 45248000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 45248000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 217696209 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 217696209 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 217696209 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 808 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 808 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 808 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 42824000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 42824000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 42824000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 2062733 # number of replacements +system.cpu.dcache.tagsinuse 4076.661903 # Cycle average of tags in use +system.cpu.dcache.total_refs 120152372 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 58.133678 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 126200130000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4076.661903 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.995279 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits 88818730 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 28849058000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.021599 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1960720 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 22966898000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.021599 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1960720 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 30805.991952 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27805.977815 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 31333642 # number of WriteReq hits +system.cpu.dcache.demand_hits 120152372 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 120152372 # number of overall hits +system.cpu.dcache.ReadReq_misses 1960720 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 106109 # number of WriteReq misses +system.cpu.dcache.demand_misses 2066829 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2066829 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 28849058000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency 3268793000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 32117851000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 32117851000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 90779450 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 122219201 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 122219201 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.021599 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.003375 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 106109 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 2950464500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.003375 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 106109 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 58.133678 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate 0.016911 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.016911 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 14713.502183 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 30805.991952 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 15539.675029 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 15539.675029 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 122219201 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 15539.675029 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 12539.674303 # average overall mshr miss latency -system.cpu.dcache.demand_hits 120152372 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 32117851000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.016911 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2066829 # number of demand (read+write) misses +system.cpu.dcache.writebacks 1437080 # number of writebacks system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1960720 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 106109 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 2066829 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2066829 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 22966898000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2950464500 # number of WriteReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency 25917362500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 25917362500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.021599 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.003375 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.016911 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2066829 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 4076.661903 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.995279 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 122219201 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 15539.675029 # average overall miss latency +system.cpu.dcache.overall_mshr_miss_rate 0.016911 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11713.502183 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27805.977815 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12539.674303 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 12539.674303 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 120152372 # number of overall hits -system.cpu.dcache.overall_miss_latency 32117851000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.016911 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2066829 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 25917362500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.016911 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2066829 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 2062733 # number of replacements -system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks. +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4076.661903 # Cycle average of tags in use -system.cpu.dcache.total_refs 120152372 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 126200130000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 1437080 # number of writebacks -system.cpu.icache.ReadReq_accesses 217696209 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 217695401 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 45248000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 808 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 42824000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 808 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 269425.001238 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 217696209 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 217695401 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 45248000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses -system.cpu.icache.demand_misses 808 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 42824000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 808 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 666.191948 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.325289 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 217696209 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 217695401 # number of overall hits -system.cpu.icache.overall_miss_latency 45248000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses -system.cpu.icache.overall_misses 808 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 42824000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 808 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 24 # number of replacements -system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 666.191948 # Cycle average of tags in use -system.cpu.icache.total_refs 217695401 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 106109 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.694804 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 49212 # number of replacements +system.cpu.l2cache.tagsinuse 18614.603260 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3296079 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 77127 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 42.735735 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 6551.798271 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 12062.804989 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.199945 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.368128 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 1927411 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 1437080 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 63651 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 2207845500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.400136 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_hits 1991062 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 1991062 # number of overall hits +system.cpu.l2cache.ReadReq_misses 34117 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 42458 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1698320000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.400136 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 42458 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 1961528 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 1927411 # number of ReadReq hits +system.cpu.l2cache.demand_misses 76575 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 76575 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency 1774084000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.017393 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 34117 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1364680000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017393 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 34117 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_miss_latency 2207845500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3981929500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3981929500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 1961528 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 1437080 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 1437080 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 42.735735 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_accesses 106109 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 2067637 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 2067637 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.017393 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.400136 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.037035 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.037035 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.694804 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000.385243 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000.385243 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 2067637 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000.385243 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1991062 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3981929500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.037035 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 76575 # number of demand (read+write) misses +system.cpu.l2cache.writebacks 29460 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 34117 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 42458 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 76575 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 76575 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1364680000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1698320000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency 3063000000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 3063000000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017393 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.400136 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.037035 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 76575 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 6551.798271 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 12062.804989 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.199945 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.368128 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 2067637 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000.385243 # average overall miss latency +system.cpu.l2cache.overall_mshr_miss_rate 0.037035 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1991062 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3981929500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.037035 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 76575 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 3063000000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.037035 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 76575 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 49212 # number of replacements -system.cpu.l2cache.sampled_refs 77127 # Sample count of references to valid blocks. +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18614.603260 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3296079 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 29460 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 740021680 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 740021680 # Number of busy cycles -system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses -system.cpu.num_fp_insts 40 # number of float instructions -system.cpu.num_fp_register_reads 40 # number of times the floating registers were read -system.cpu.num_fp_register_writes 26 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 278192520 # Number of instructions executed -system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses -system.cpu.num_int_insts 278186228 # number of integer instructions -system.cpu.num_int_register_reads 685043114 # number of times the integer registers were read -system.cpu.num_int_register_writes 248344166 # number of times the integer registers were written -system.cpu.num_load_insts 90779388 # Number of load instructions -system.cpu.num_mem_refs 122219139 # number of memory refs -system.cpu.num_store_insts 31439751 # Number of store instructions -system.cpu.workload.num_syscalls 444 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini index 71df37b56..b2ef015f3 100644 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini @@ -500,9 +500,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/parser +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/20.parser/ref/x86/linux/o3-timing/simout index 7acfed5bd..f37768727 100755 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/simout @@ -3,11 +3,10 @@ Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 16 2011 11:08:03 -gem5 started Nov 17 2011 13:09:16 +gem5 compiled Jan 9 2012 14:18:02 +gem5 started Jan 9 2012 14:29:08 gem5 executing on ribera.cs.wisc.edu command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -tests Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -82,4 +81,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 494093841000 because target called exit() +Exiting @ tick 493912286000 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt index 548cdcdb0..556f62c4f 100644 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,149 +1,149 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.494094 # Number of seconds simulated -sim_ticks 494093841000 # Number of ticks simulated +sim_seconds 0.493912 # Number of seconds simulated +sim_ticks 493912286000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 111156 # Simulator instruction rate (inst/s) -host_tick_rate 35920075 # Simulator tick rate (ticks/s) -host_mem_usage 281020 # Number of bytes of host memory used -host_seconds 13755.37 # Real time elapsed on the host +host_inst_rate 108889 # Simulator instruction rate (inst/s) +host_tick_rate 35174673 # Simulator tick rate (ticks/s) +host_mem_usage 280548 # Number of bytes of host memory used +host_seconds 14041.70 # Real time elapsed on the host sim_insts 1528988756 # Number of instructions simulated system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 988187683 # number of cpu cycles simulated +system.cpu.numCycles 987824573 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 245753731 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 245753731 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 16579058 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 236460078 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 218454939 # Number of BTB hits +system.cpu.BPredUnit.lookups 245766486 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 245766486 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 16576996 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 236474058 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 218464201 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 205538766 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1343537923 # Number of instructions fetch has processed -system.cpu.fetch.Branches 245753731 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 218454939 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 436709904 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 120016352 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 218837683 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33103 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 345399 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 194719765 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 4085375 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 964635983 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.598912 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.317298 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 205503020 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1343384866 # Number of instructions fetch has processed +system.cpu.fetch.Branches 245766486 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 218464201 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 436676837 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 119986236 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 218554807 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32387 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 341323 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 194710374 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 4099618 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 964252463 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.599701 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.317490 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 531979476 55.15% 55.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 32383346 3.36% 58.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 38813168 4.02% 62.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 32534184 3.37% 65.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 21860326 2.27% 68.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 36455994 3.78% 71.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 49125826 5.09% 77.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 36953777 3.83% 80.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 184529886 19.13% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 531629837 55.13% 55.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 32377332 3.36% 58.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 38827894 4.03% 62.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 32536894 3.37% 65.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 21844251 2.27% 68.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 36448993 3.78% 71.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 49128972 5.10% 77.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 36937786 3.83% 80.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 184520504 19.14% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 964635983 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.248691 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.359598 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 264568111 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 174813294 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 373028079 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 49055371 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 103171128 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2446190376 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 103171128 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 301809231 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 40269862 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9996 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 383504038 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 135871728 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2393655047 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 2663 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 25553817 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 92121641 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 4 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2227336205 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5630423595 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5630180918 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 242677 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 964252463 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.248796 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.359943 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 264509435 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 174554141 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 373011587 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 49033211 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 103144089 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2445932072 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 103144089 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 301738657 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 40282868 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12225 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 383467875 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 135606749 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2393375507 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2559 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 25131978 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 92224846 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 8 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2227188673 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5629907069 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5629667957 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 239112 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1427299027 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 800037178 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1323 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1277 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 319257105 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 577954406 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 226554784 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 227345729 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 66055755 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2286934263 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 9822 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1922478378 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1310077 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 755451043 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1190251690 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 9269 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 964635983 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.992957 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.810982 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 799889646 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1309 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1288 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 318947403 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 577879232 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 226530900 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 227222440 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 65937432 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2286709085 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 12489 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1922370305 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1306641 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 755226802 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1190125426 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 11936 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 964252463 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.993638 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.811521 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 283040019 29.34% 29.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 160280005 16.62% 45.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 162996180 16.90% 62.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 148777682 15.42% 78.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 109013815 11.30% 89.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 60046720 6.22% 95.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 30822079 3.20% 99.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 8624231 0.89% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1035252 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 282911384 29.34% 29.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 160280603 16.62% 45.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 162550496 16.86% 62.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 148847741 15.44% 78.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 109081156 11.31% 89.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 60080329 6.23% 95.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 30822605 3.20% 99.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 8641604 0.90% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1036545 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 964635983 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 964252463 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2243375 14.67% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9951583 65.07% 79.74% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3098283 20.26% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2246339 14.60% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 10026447 65.19% 79.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3108042 20.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2418078 0.13% 0.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1274783906 66.31% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2420122 0.13% 0.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1274712167 66.31% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.44% # Type of FU issued @@ -169,85 +169,85 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.44% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 463737726 24.12% 90.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 181538665 9.44% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 463703127 24.12% 90.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 181534884 9.44% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1922478378 # Type of FU issued -system.cpu.iq.rate 1.945459 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15293241 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007955 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4826191069 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3042585561 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1874784055 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4988 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 82956 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 103 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1935351994 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1547 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 158191943 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1922370305 # Type of FU issued +system.cpu.iq.rate 1.946064 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15380828 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008001 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4825675637 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3042139517 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1874661917 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4905 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 81824 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 136 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1935329448 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1563 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 158391521 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 193852246 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 372238 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 283888 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 77394965 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 193777072 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 372742 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 283642 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 77371112 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2343 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 34 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2379 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 103171128 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 9041820 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1420232 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2286944085 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1121311 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 577954406 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 226555150 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6075 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1022506 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 29752 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 283888 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 15692203 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2347782 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18039985 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1889278448 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 454785721 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 33199930 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 103144089 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 9045659 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1404502 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2286721574 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1118432 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 577879232 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 226531297 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6081 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1006586 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 29974 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 283642 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 15693422 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2344063 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18037485 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1889150749 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 454748002 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 33219556 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 629316980 # number of memory reference insts executed -system.cpu.iew.exec_branches 176731992 # Number of branches executed -system.cpu.iew.exec_stores 174531259 # Number of stores executed -system.cpu.iew.exec_rate 1.911862 # Inst execution rate -system.cpu.iew.wb_sent 1882655317 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1874784158 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1440755706 # num instructions producing a value -system.cpu.iew.wb_consumers 2135030641 # num instructions consuming a value +system.cpu.iew.exec_refs 629271939 # number of memory reference insts executed +system.cpu.iew.exec_branches 176719729 # Number of branches executed +system.cpu.iew.exec_stores 174523937 # Number of stores executed +system.cpu.iew.exec_rate 1.912435 # Inst execution rate +system.cpu.iew.wb_sent 1882531239 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1874662053 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1440606287 # num instructions producing a value +system.cpu.iew.wb_consumers 2134778201 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.897194 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.674817 # average fanout of values written-back +system.cpu.iew.wb_rate 1.897768 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.674827 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 757965703 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 757743569 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16607079 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 861464855 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.774871 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.287572 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16604349 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 861108374 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.775605 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.288022 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 338524013 39.30% 39.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 210779915 24.47% 63.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 75257513 8.74% 72.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92637954 10.75% 83.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 34058407 3.95% 87.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27966548 3.25% 90.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15953506 1.85% 92.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 12303443 1.43% 93.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 53983556 6.27% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 338327816 39.29% 39.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 210551706 24.45% 63.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 75360819 8.75% 72.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92562974 10.75% 83.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 34054041 3.95% 87.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27955182 3.25% 90.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 16032820 1.86% 92.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 12266632 1.42% 93.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 53996384 6.27% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 861464855 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 861108374 # Number of insts commited each cycle system.cpu.commit.count 1528988756 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 533262345 # Number of memory references committed @@ -257,49 +257,49 @@ system.cpu.commit.branches 149758588 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 53983556 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 53996384 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3094435758 # The number of ROB reads -system.cpu.rob.rob_writes 4677260376 # The number of ROB writes -system.cpu.timesIdled 606046 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 23551700 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3093844315 # The number of ROB reads +system.cpu.rob.rob_writes 4676786954 # The number of ROB writes +system.cpu.timesIdled 606516 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 23572110 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1528988756 # Number of Instructions Simulated system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated -system.cpu.cpi 0.646301 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.646301 # CPI: Total CPI of All Threads -system.cpu.ipc 1.547266 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.547266 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3179235417 # number of integer regfile reads -system.cpu.int_regfile_writes 1744932190 # number of integer regfile writes -system.cpu.fp_regfile_reads 109 # number of floating regfile reads -system.cpu.fp_regfile_writes 3 # number of floating regfile writes -system.cpu.misc_regfile_reads 1039364909 # number of misc regfile reads -system.cpu.icache.replacements 9996 # number of replacements -system.cpu.icache.tagsinuse 975.733254 # Cycle average of tags in use -system.cpu.icache.total_refs 194489021 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 11497 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 16916.501783 # Average number of references to valid blocks. +system.cpu.cpi 0.646064 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.646064 # CPI: Total CPI of All Threads +system.cpu.ipc 1.547834 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.547834 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3179044858 # number of integer regfile reads +system.cpu.int_regfile_writes 1744829680 # number of integer regfile writes +system.cpu.fp_regfile_reads 145 # number of floating regfile reads +system.cpu.fp_regfile_writes 5 # number of floating regfile writes +system.cpu.misc_regfile_reads 1039286160 # number of misc regfile reads +system.cpu.icache.replacements 10045 # number of replacements +system.cpu.icache.tagsinuse 976.337758 # Cycle average of tags in use +system.cpu.icache.total_refs 194480398 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 11548 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 16841.045895 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 975.733254 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.476432 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 194495909 # number of ReadReq hits -system.cpu.icache.demand_hits 194495909 # number of demand (read+write) hits -system.cpu.icache.overall_hits 194495909 # number of overall hits -system.cpu.icache.ReadReq_misses 223856 # number of ReadReq misses -system.cpu.icache.demand_misses 223856 # number of demand (read+write) misses -system.cpu.icache.overall_misses 223856 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 1547338000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 1547338000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 1547338000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 194719765 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 194719765 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 194719765 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.001150 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.001150 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.001150 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 6912.202487 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 6912.202487 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 6912.202487 # average overall miss latency +system.cpu.icache.occ_blocks::0 976.337758 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.476727 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 194486608 # number of ReadReq hits +system.cpu.icache.demand_hits 194486608 # number of demand (read+write) hits +system.cpu.icache.overall_hits 194486608 # number of overall hits +system.cpu.icache.ReadReq_misses 223766 # number of ReadReq misses +system.cpu.icache.demand_misses 223766 # number of demand (read+write) misses +system.cpu.icache.overall_misses 223766 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 1539723000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 1539723000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 1539723000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 194710374 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 194710374 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 194710374 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.001149 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.001149 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.001149 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 6880.951530 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 6880.951530 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 6880.951530 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -309,136 +309,136 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 6 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 2117 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 2117 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 2117 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 221739 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 221739 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 221739 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 2071 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 2071 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 2071 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 221695 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 221695 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 221695 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 830917000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 830917000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 830917000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 824417000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 824417000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 824417000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.001139 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.001139 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.001139 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3747.274949 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3747.274949 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3747.274949 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 3718.699114 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 3718.699114 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 3718.699114 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2527207 # number of replacements -system.cpu.dcache.tagsinuse 4087.569371 # Cycle average of tags in use -system.cpu.dcache.total_refs 440821768 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2531303 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 174.148163 # Average number of references to valid blocks. +system.cpu.dcache.replacements 2527930 # number of replacements +system.cpu.dcache.tagsinuse 4087.566272 # Cycle average of tags in use +system.cpu.dcache.total_refs 440586260 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2532026 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 174.005425 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 2135798000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4087.569371 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.997942 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 292074612 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 147577545 # number of WriteReq hits -system.cpu.dcache.demand_hits 439652157 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 439652157 # number of overall hits -system.cpu.dcache.ReadReq_misses 3115587 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1582656 # number of WriteReq misses -system.cpu.dcache.demand_misses 4698243 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 4698243 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 51949082000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 37383634500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 89332716500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 89332716500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 295190199 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::0 4087.566272 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.997941 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 291836002 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 147579227 # number of WriteReq hits +system.cpu.dcache.demand_hits 439415229 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 439415229 # number of overall hits +system.cpu.dcache.ReadReq_misses 3119681 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1580974 # number of WriteReq misses +system.cpu.dcache.demand_misses 4700655 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 4700655 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 52079313500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 37355392500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 89434706000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 89434706000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 294955683 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 444350400 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 444350400 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.010555 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.010610 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.010573 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.010573 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 16673.930787 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 23620.821265 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 19014.068983 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 19014.068983 # average overall miss latency +system.cpu.dcache.demand_accesses 444115884 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 444115884 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.010577 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.010599 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.010584 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.010584 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 16693.794494 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 23628.087812 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 19026.009354 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 19026.009354 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 74500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 29000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 18625 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 14500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 2229206 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1355757 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 609338 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1965095 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1965095 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1759830 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 973318 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2733148 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2733148 # number of overall MSHR misses +system.cpu.dcache.writebacks 2229595 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 1359154 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 607660 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1966814 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1966814 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1760527 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 973314 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 2733841 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2733841 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 14896925000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 17174770000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 32071695000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 32071695000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 14908482500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 17169522000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 32078004500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 32078004500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.005962 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.005969 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.006525 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.006151 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.006151 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8464.979572 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17645.589622 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 11734.342597 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 11734.342597 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.006156 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.006156 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8468.193047 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17640.270252 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 11733.675989 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 11733.675989 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 574699 # number of replacements -system.cpu.l2cache.tagsinuse 21595.701500 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3193363 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 593876 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.377154 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 271431195000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 7794.557657 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13801.143843 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.237871 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.421177 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1432788 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 2229212 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits 1238 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits 524381 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 1957169 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1957169 # number of overall hits -system.cpu.l2cache.ReadReq_misses 338369 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 208965 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 247135 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 585504 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 585504 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 11556474000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency 9921000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 8477435500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 20033909500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 20033909500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 1771157 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 2229212 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 210203 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 771516 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 2542673 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 2542673 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.191044 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 0.994110 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.320324 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.230271 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.230271 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34153.465595 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency 47.476850 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34302.852692 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34216.520297 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34216.520297 # average overall miss latency +system.cpu.l2cache.replacements 574945 # number of replacements +system.cpu.l2cache.tagsinuse 21597.257673 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3194359 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 594122 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.376604 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 271429089000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 7797.131828 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13800.125845 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.237950 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.421146 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 1433279 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 2229601 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits 1240 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits 524400 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 1957679 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 1957679 # number of overall hits +system.cpu.l2cache.ReadReq_misses 338611 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 208876 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 247152 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 585763 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 585763 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 11564612500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 9756500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 8478074500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 20042687000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 20042687000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 1771890 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 2229601 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 210116 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 771552 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 2543442 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 2543442 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.191102 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate 0.994098 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.320331 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.230303 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.230303 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34153.091601 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 46.709531 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34303.078672 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34216.375906 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34216.375906 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -447,31 +447,31 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 411193 # number of writebacks +system.cpu.l2cache.writebacks 411265 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 338369 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 208965 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 247135 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 585504 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 585504 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 338611 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 208876 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 247152 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 585763 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 585763 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 10496162500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6478082000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 7666148000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 18162310500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 18162310500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 10503665500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6475353000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 7666739500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 18170405000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 18170405000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191044 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994110 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.320324 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.230271 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.230271 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.870319 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000.799177 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31020.082141 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31019.959727 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31019.959727 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191102 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994098 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.320331 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.230303 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.230303 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.859071 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000.943143 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31020.341733 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31020.062722 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31020.062722 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini index fdc891c59..da3b012b0 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -61,14 +62,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic +cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/parser +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/simerr b/tests/long/20.parser/ref/x86/linux/simple-atomic/simerr index 94d399eab..ac4ad20a5 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/simerr @@ -1,7 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 hack: be nice to actually delete the event here diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout index 190029619..d3e847fa3 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout @@ -1,14 +1,12 @@ -M5 Simulator System +Redirecting stdout to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic/simout +Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 12:22:33 -M5 started Apr 19 2011 12:30:34 -M5 executing on maize -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic +gem5 compiled Jan 9 2012 14:18:02 +gem5 started Jan 9 2012 14:29:08 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt index 3cf669902..c9073b3b2 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3416660 # Simulator instruction rate (inst/s) -host_mem_usage 206360 # Number of bytes of host memory used -host_seconds 447.51 # Real time elapsed on the host -host_tick_rate 1978121798 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1528988757 # Number of instructions simulated sim_seconds 0.885229 # Number of seconds simulated sim_ticks 885229360000 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1063398 # Simulator instruction rate (inst/s) +host_tick_rate 615669149 # Simulator tick rate (ticks/s) +host_mem_usage 237896 # Number of bytes of host memory used +host_seconds 1437.83 # Real time elapsed on the host +sim_insts 1528988757 # Number of instructions simulated +system.cpu.workload.num_syscalls 551 # Number of system calls system.cpu.numCycles 1770458721 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 1770458721 # Number of busy cycles -system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.num_insts 1528988757 # Number of instructions executed system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls system.cpu.num_int_insts 1528317615 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions system.cpu.num_int_register_reads 3581460239 # number of times the integer registers were read system.cpu.num_int_register_writes 1427299027 # number of times the integer registers were written -system.cpu.num_load_insts 384102160 # Number of load instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 533262345 # number of memory refs +system.cpu.num_load_insts 384102160 # Number of load instructions system.cpu.num_store_insts 149160185 # Number of store instructions -system.cpu.workload.num_syscalls 551 # Number of system calls +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 1770458721 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles ---------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini index 330cf56d3..e63456bf2 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -164,14 +165,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing +cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/parser +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simerr b/tests/long/20.parser/ref/x86/linux/simple-timing/simerr index 94d399eab..ac4ad20a5 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/simerr +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simerr @@ -1,7 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 hack: be nice to actually delete the event here diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/20.parser/ref/x86/linux/simple-timing/simout index b7abf2775..268de88f4 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simout @@ -1,14 +1,12 @@ -M5 Simulator System +Redirecting stdout to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing/simout +Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 12:22:33 -M5 started Apr 19 2011 12:27:05 -M5 executing on maize -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing +gem5 compiled Jan 9 2012 14:18:02 +gem5 started Jan 9 2012 14:29:08 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt index 9224e99d3..a96327ae0 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,223 +1,223 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2070048 # Simulator instruction rate (inst/s) -host_mem_usage 214112 # Number of bytes of host memory used -host_seconds 738.62 # Real time elapsed on the host -host_tick_rate 2245699490 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1528988757 # Number of instructions simulated sim_seconds 1.658730 # Number of seconds simulated sim_ticks 1658729604000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 384102189 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 22005.441660 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 19005.440502 # average ReadReq mshr miss latency +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 746220 # Simulator instruction rate (inst/s) +host_tick_rate 809539282 # Simulator tick rate (ticks/s) +host_mem_usage 246668 # Number of bytes of host memory used +host_seconds 2048.98 # Real time elapsed on the host +sim_insts 1528988757 # Number of instructions simulated +system.cpu.workload.num_syscalls 551 # Number of system calls +system.cpu.numCycles 3317459208 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.num_insts 1528988757 # Number of instructions executed +system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls +system.cpu.num_int_insts 1528317615 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 3581460239 # number of times the integer registers were read +system.cpu.num_int_register_writes 1427299027 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 533262345 # number of memory refs +system.cpu.num_load_insts 384102160 # Number of load instructions +system.cpu.num_store_insts 149160185 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 3317459208 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.icache.replacements 1253 # number of replacements +system.cpu.icache.tagsinuse 882.231489 # Cycle average of tags in use +system.cpu.icache.total_refs 1068344296 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 379653.267946 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 882.231489 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.430777 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 1068344296 # number of ReadReq hits +system.cpu.icache.demand_hits 1068344296 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1068344296 # number of overall hits +system.cpu.icache.ReadReq_misses 2814 # number of ReadReq misses +system.cpu.icache.demand_misses 2814 # number of demand (read+write) misses +system.cpu.icache.overall_misses 2814 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 136878000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 136878000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 136878000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 1068347110 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 1068347110 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 1068347110 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 48641.791045 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 48641.791045 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 48641.791045 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 2814 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 2814 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 2814 # 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average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 2514362 # number of replacements +system.cpu.dcache.tagsinuse 4086.472055 # Cycle average of tags in use +system.cpu.dcache.total_refs 530743932 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 210.741625 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 8216675000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4086.472055 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.997674 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits 382374775 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 38012508000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.004497 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1727414 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 32830264000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.004497 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1727414 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27169.175798 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24169.168845 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 148369157 # number of WriteReq hits +system.cpu.dcache.demand_hits 530743932 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 530743932 # number of overall hits +system.cpu.dcache.ReadReq_misses 1727414 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 791044 # number of WriteReq misses +system.cpu.dcache.demand_misses 2518458 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2518458 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 38012508000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency 21492013500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 59504521500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 59504521500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 384102189 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 533262390 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 533262390 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.004497 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.005303 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 791044 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 19118876000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.005303 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 791044 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 210.741625 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate 0.004723 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.004723 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 22005.441660 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 27169.175798 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 23627.363053 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 23627.363053 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 533262390 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 23627.363053 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 20627.360075 # average overall mshr miss latency -system.cpu.dcache.demand_hits 530743932 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 59504521500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.004723 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2518458 # number of demand (read+write) misses +system.cpu.dcache.writebacks 2223170 # number of writebacks system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1727414 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 791044 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 2518458 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2518458 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 32830264000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 19118876000 # number of WriteReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency 51949140000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 51949140000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.004497 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.005303 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.004723 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2518458 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 4086.472055 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.997674 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 533262390 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 23627.363053 # average overall miss latency +system.cpu.dcache.overall_mshr_miss_rate 0.004723 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 19005.440502 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24169.168845 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 20627.360075 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 20627.360075 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 530743932 # number of overall hits -system.cpu.dcache.overall_miss_latency 59504521500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.004723 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2518458 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 51949140000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.004723 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2518458 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 2514362 # number of replacements -system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks. +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4086.472055 # Cycle average of tags in use -system.cpu.dcache.total_refs 530743932 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 8216675000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 2223170 # number of writebacks -system.cpu.icache.ReadReq_accesses 1068347110 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 48641.791045 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 45641.791045 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1068344296 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 136878000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 2814 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 128436000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 2814 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 379653.267946 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1068347110 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 48641.791045 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 45641.791045 # average overall mshr miss latency -system.cpu.icache.demand_hits 1068344296 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 136878000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses -system.cpu.icache.demand_misses 2814 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 128436000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 2814 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 882.231489 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.430777 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 1068347110 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 48641.791045 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 45641.791045 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1068344296 # number of overall hits -system.cpu.icache.overall_miss_latency 136878000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses -system.cpu.icache.overall_misses 2814 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 128436000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 2814 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 1253 # number of replacements -system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 882.231489 # Cycle average of tags in use -system.cpu.icache.total_refs 1068344296 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 791044 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.024190 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 568906 # number of replacements +system.cpu.l2cache.tagsinuse 21228.193311 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3146531 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 587958 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.351625 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 896565143000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 7549.128601 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13679.064710 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.230381 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.417452 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 1398652 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 2223170 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 543011 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 12897722000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.313551 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_hits 1941663 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 1941663 # number of overall hits +system.cpu.l2cache.ReadReq_misses 331576 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 248033 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 9921320000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.313551 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 248033 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 1730228 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 1398652 # number of ReadReq hits +system.cpu.l2cache.demand_misses 579609 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 579609 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency 17241952000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.191637 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 331576 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 13263040000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191637 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 331576 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_miss_latency 12897722000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 30139674000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 30139674000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 1730228 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 2223170 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 2223170 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 5.351625 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_accesses 791044 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 2521272 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 2521272 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.191637 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.313551 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.229888 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.229888 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.024190 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000.010352 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000.010352 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 2521272 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000.010352 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1941663 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 30139674000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.229888 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 579609 # number of demand (read+write) misses +system.cpu.l2cache.writebacks 411709 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 331576 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 248033 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 579609 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 579609 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 13263040000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 9921320000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency 23184360000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 23184360000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191637 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.313551 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.229888 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 579609 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 7549.128601 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13679.064710 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.230381 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.417452 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 2521272 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000.010352 # average overall miss latency +system.cpu.l2cache.overall_mshr_miss_rate 0.229888 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1941663 # number of overall hits -system.cpu.l2cache.overall_miss_latency 30139674000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.229888 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 579609 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 23184360000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.229888 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 579609 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 568906 # number of replacements -system.cpu.l2cache.sampled_refs 587958 # Sample count of references to valid blocks. +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 21228.193311 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3146531 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 896565143000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 411709 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 3317459208 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 3317459208 # Number of busy cycles -system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 1528988757 # Number of instructions executed -system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses -system.cpu.num_int_insts 1528317615 # number of integer instructions -system.cpu.num_int_register_reads 3581460239 # number of times the integer registers were read -system.cpu.num_int_register_writes 1427299027 # number of times the integer registers were written -system.cpu.num_load_insts 384102160 # Number of load instructions -system.cpu.num_mem_refs 533262345 # number of memory refs -system.cpu.num_store_insts 149160185 # Number of store instructions -system.cpu.workload.num_syscalls 551 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini index 89aae9c00..862679185 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -61,12 +62,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic +cwd=build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr index 94d399eab..ac4ad20a5 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr @@ -1,7 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 hack: be nice to actually delete the event here diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout index fd345ce8f..bad0385b9 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout @@ -1,14 +1,12 @@ -M5 Simulator System +Redirecting stdout to build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic/simout +Redirecting stderr to build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 12:22:33 -M5 started Apr 19 2011 12:22:46 -M5 executing on maize -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic +gem5 compiled Jan 9 2012 14:18:02 +gem5 started Jan 9 2012 14:29:08 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index 3863ba265..9b17b524e 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2952357 # Simulator instruction rate (inst/s) -host_mem_usage 202444 # Number of bytes of host memory used -host_seconds 1587.50 # Real time elapsed on the host -host_tick_rate 1792761763 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4686862651 # Number of instructions simulated sim_seconds 2.846007 # Number of seconds simulated sim_ticks 2846007259500 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1508697 # Simulator instruction rate (inst/s) +host_tick_rate 916127309 # Simulator tick rate (ticks/s) +host_mem_usage 234076 # Number of bytes of host memory used +host_seconds 3106.56 # Real time elapsed on the host +sim_insts 4686862651 # Number of instructions simulated +system.cpu.workload.num_syscalls 46 # Number of system calls system.cpu.numCycles 5692014520 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 5692014520 # Number of busy cycles -system.cpu.num_conditional_control_insts 182173305 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.num_insts 4686862651 # Number of instructions executed system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 182173305 # number of instructions that are conditional controls system.cpu.num_int_insts 4686862580 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions system.cpu.num_int_register_reads 11558008181 # number of times the integer registers were read system.cpu.num_int_register_writes 4679057393 # number of times the integer registers were written -system.cpu.num_load_insts 1239184749 # Number of load instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 1677713086 # number of memory refs +system.cpu.num_load_insts 1239184749 # Number of load instructions system.cpu.num_store_insts 438528337 # Number of store instructions -system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 5692014520 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini index c75881c3f..90d473af2 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -164,12 +165,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing +cwd=build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simerr b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simerr index 94d399eab..ac4ad20a5 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simerr +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simerr @@ -1,7 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 hack: be nice to actually delete the event here diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout index 60300fa55..bfa3c0689 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout @@ -1,14 +1,12 @@ -M5 Simulator System +Redirecting stdout to build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing/simout +Redirecting stderr to build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 12:22:33 -M5 started Apr 19 2011 12:36:40 -M5 executing on maize -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing +gem5 compiled Jan 9 2012 14:18:02 +gem5 started Jan 9 2012 14:29:08 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt index e9ae83f48..75fcf4f7a 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,223 +1,223 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1878760 # Simulator instruction rate (inst/s) -host_mem_usage 210192 # Number of bytes of host memory used -host_seconds 2494.66 # Real time elapsed on the host -host_tick_rate 2374493636 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4686862651 # Number of instructions simulated sim_seconds 5.923548 # Number of seconds simulated sim_ticks 5923548078000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 1239184749 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 24617.504171 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21617.504171 # average ReadReq mshr miss latency +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 871353 # Simulator instruction rate (inst/s) +host_tick_rate 1101269643 # Simulator tick rate (ticks/s) +host_mem_usage 242804 # Number of bytes of host memory used +host_seconds 5378.84 # Real time elapsed on the host +sim_insts 4686862651 # Number of instructions simulated +system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.numCycles 11847096156 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.num_insts 4686862651 # Number of instructions executed +system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 182173305 # number of instructions that are conditional controls +system.cpu.num_int_insts 4686862580 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 11558008181 # number of times the integer registers were read +system.cpu.num_int_register_writes 4679057393 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 1677713086 # number of memory refs +system.cpu.num_load_insts 1239184749 # Number of load instructions +system.cpu.num_store_insts 438528337 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 11847096156 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.icache.replacements 10 # number of replacements +system.cpu.icache.tagsinuse 555.713137 # Cycle average of tags in use +system.cpu.icache.total_refs 4013232252 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5945529.262222 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 555.713137 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.271344 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 4013232252 # number of ReadReq hits +system.cpu.icache.demand_hits 4013232252 # number of demand (read+write) hits +system.cpu.icache.overall_hits 4013232252 # number of overall hits +system.cpu.icache.ReadReq_misses 675 # number of ReadReq misses +system.cpu.icache.demand_misses 675 # number of demand (read+write) misses +system.cpu.icache.overall_misses 675 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 37800000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 37800000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 37800000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 4013232927 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 4013232927 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 4013232927 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 675 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 675 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 675 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 35775000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 35775000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 35775000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 9108581 # number of replacements +system.cpu.dcache.tagsinuse 4084.662246 # Cycle average of tags in use +system.cpu.dcache.total_refs 1668600409 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 58862779000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4084.662246 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.997232 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits 1231961899 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 177808540000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.005829 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 7222850 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 156139990000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.005829 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 7222850 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 438528337 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 33796.256483 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30796.256483 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 436638510 # number of WriteReq hits +system.cpu.dcache.demand_hits 1668600409 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 1668600409 # number of overall hits +system.cpu.dcache.ReadReq_misses 7222850 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1889827 # number of WriteReq misses +system.cpu.dcache.demand_misses 9112677 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 9112677 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 177808540000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency 63869078000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 241677618000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 241677618000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1239184749 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 438528337 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 1677713086 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 1677713086 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.005829 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.004309 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1889827 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 58199597000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.004309 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1889827 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate 0.005432 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.005432 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 24617.504171 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 33796.256483 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 26521.034159 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 26521.034159 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 1677713086 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 26521.034159 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23521.034159 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1668600409 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 241677618000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.005432 # miss rate for demand accesses -system.cpu.dcache.demand_misses 9112677 # number of demand (read+write) misses +system.cpu.dcache.writebacks 3053391 # number of writebacks system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 7222850 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1889827 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 9112677 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 9112677 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 156139990000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 58199597000 # number of WriteReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency 214339587000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 214339587000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.005829 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.004309 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.005432 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 9112677 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 4084.662246 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.997232 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 1677713086 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 26521.034159 # average overall miss latency +system.cpu.dcache.overall_mshr_miss_rate 0.005432 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21617.504171 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30796.256483 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 23521.034159 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 23521.034159 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1668600409 # number of overall hits -system.cpu.dcache.overall_miss_latency 241677618000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.005432 # miss rate for overall accesses -system.cpu.dcache.overall_misses 9112677 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 214339587000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.005432 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 9112677 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 9108581 # number of replacements -system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks. +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4084.662246 # Cycle average of tags in use -system.cpu.dcache.total_refs 1668600409 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 58862779000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 3053391 # number of writebacks -system.cpu.icache.ReadReq_accesses 4013232927 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 4013232252 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 37800000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 675 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 35775000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 675 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 5945529.262222 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 4013232927 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 4013232252 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 37800000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses -system.cpu.icache.demand_misses 675 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 35775000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 675 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 555.713137 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.271344 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 4013232927 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 4013232252 # number of overall hits -system.cpu.icache.overall_miss_latency 37800000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses -system.cpu.icache.overall_misses 675 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 35775000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 675 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 10 # number of replacements -system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 555.713137 # Cycle average of tags in use -system.cpu.icache.total_refs 4013232252 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 1889827 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 2706631 # number of replacements +system.cpu.l2cache.tagsinuse 26507.350069 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7537629 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2732923 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.758083 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 1324806325000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 15478.805498 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 11028.544571 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.472376 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.336564 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 5396930 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 3053391 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 999077 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 46319000000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.471339 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_hits 6396007 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 6396007 # number of overall hits +system.cpu.l2cache.ReadReq_misses 1826595 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 890750 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 35630000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.471339 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 890750 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 7223525 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 5396930 # number of ReadReq hits +system.cpu.l2cache.demand_misses 2717345 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 2717345 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency 94982940000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.252868 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1826595 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 73063800000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.252868 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1826595 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_miss_latency 46319000000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 141301940000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 141301940000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 7223525 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 3053391 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 3053391 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.758083 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_accesses 1889827 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 9113352 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 9113352 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.252868 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.471339 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.298172 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.298172 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 9113352 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 6396007 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 141301940000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.298172 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 2717345 # number of demand (read+write) misses +system.cpu.l2cache.writebacks 1174631 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 1826595 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 890750 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 2717345 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 2717345 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 73063800000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 35630000000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency 108693800000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 108693800000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.252868 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.471339 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.298172 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 2717345 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 15478.805498 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 11028.544571 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.472376 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.336564 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 9113352 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_mshr_miss_rate 0.298172 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 6396007 # number of overall hits -system.cpu.l2cache.overall_miss_latency 141301940000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.298172 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 2717345 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 108693800000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.298172 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 2717345 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 2706631 # number of replacements -system.cpu.l2cache.sampled_refs 2732923 # Sample count of references to valid blocks. +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 26507.350069 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7537629 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 1324806325000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 1174631 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 11847096156 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 11847096156 # Number of busy cycles -system.cpu.num_conditional_control_insts 182173305 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 4686862651 # Number of instructions executed -system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses -system.cpu.num_int_insts 4686862580 # number of integer instructions -system.cpu.num_int_register_reads 11558008181 # number of times the integer registers were read -system.cpu.num_int_register_writes 4679057393 # number of times the integer registers were written -system.cpu.num_load_insts 1239184749 # Number of load instructions -system.cpu.num_mem_refs 1677713086 # number of memory refs -system.cpu.num_store_insts 438528337 # Number of store instructions -system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini index 8802a5811..d20296793 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/twolf +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout index ac0a4779d..a8f7791d3 100755 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout @@ -3,11 +3,12 @@ Redirecting stderr to build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/s gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 16 2011 11:08:03 -gem5 started Nov 17 2011 13:09:16 +gem5 compiled Jan 9 2012 14:18:02 +gem5 started Jan 9 2012 14:29:08 gem5 executing on ribera.cs.wisc.edu command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -tests +Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sav +Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt index 7b2ddaff9..f73117896 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -3,10 +3,10 @@ sim_seconds 0.096690 # Number of seconds simulated sim_ticks 96689893000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 89575 # Simulator instruction rate (inst/s) -host_tick_rate 39125952 # Simulator tick rate (ticks/s) -host_mem_usage 253168 # Number of bytes of host memory used -host_seconds 2471.25 # Real time elapsed on the host +host_inst_rate 71082 # Simulator instruction rate (inst/s) +host_tick_rate 31048201 # Simulator tick rate (ticks/s) +host_mem_usage 253148 # Number of bytes of host memory used +host_seconds 3114.19 # Real time elapsed on the host sim_insts 221363017 # Number of instructions simulated system.cpu.workload.num_syscalls 400 # Number of system calls system.cpu.numCycles 193379787 # number of cpu cycles simulated diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini index adbeb371c..22a2b62b1 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -61,12 +62,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic +cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/twolf +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr index 94d399eab..ac4ad20a5 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr @@ -1,7 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout index 6d11a44d3..d0fe2b96b 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout @@ -1,16 +1,14 @@ -M5 Simulator System +Redirecting stdout to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/simout +Redirecting stderr to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 12:22:33 -M5 started Apr 19 2011 12:38:23 -M5 executing on maize -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2 +gem5 compiled Jan 9 2012 14:18:02 +gem5 started Jan 9 2012 14:29:08 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic +Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sav +Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt index 80e0c67c1..727d7b7f0 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3098099 # Simulator instruction rate (inst/s) -host_mem_usage 209904 # Number of bytes of host memory used -host_seconds 71.45 # Real time elapsed on the host -host_tick_rate 1838915708 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 221363018 # Number of instructions simulated sim_seconds 0.131393 # Number of seconds simulated sim_ticks 131393100000 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 733183 # Simulator instruction rate (inst/s) +host_tick_rate 435191133 # Simulator tick rate (ticks/s) +host_mem_usage 241232 # Number of bytes of host memory used +host_seconds 301.92 # Real time elapsed on the host +sim_insts 221363018 # Number of instructions simulated +system.cpu.workload.num_syscalls 400 # Number of system calls system.cpu.numCycles 262786201 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 262786201 # Number of busy cycles -system.cpu.num_conditional_control_insts 8268471 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses -system.cpu.num_fp_insts 2162459 # number of float instructions -system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read -system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.num_insts 221363018 # Number of instructions executed system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 8268471 # number of instructions that are conditional controls system.cpu.num_int_insts 220339607 # number of integer instructions +system.cpu.num_fp_insts 2162459 # number of float instructions system.cpu.num_int_register_reads 567557364 # number of times the integer registers were read system.cpu.num_int_register_writes 232532006 # number of times the integer registers were written -system.cpu.num_load_insts 56649590 # Number of load instructions +system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read +system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written system.cpu.num_mem_refs 77165306 # number of memory refs +system.cpu.num_load_insts 56649590 # Number of load instructions system.cpu.num_store_insts 20515716 # Number of store instructions -system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 262786201 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini index 040454ea4..2acc29c81 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -164,12 +165,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing +cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/twolf +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simerr b/tests/long/70.twolf/ref/x86/linux/simple-timing/simerr index 94d399eab..ac4ad20a5 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simerr +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simerr @@ -1,7 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout index ac8ab44c7..a9cb69d9f 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout @@ -1,16 +1,14 @@ -M5 Simulator System +Redirecting stdout to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/simout +Redirecting stderr to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 12:22:33 -M5 started Apr 19 2011 12:30:33 -M5 executing on maize -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sav -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sv2 +gem5 compiled Jan 9 2012 14:18:02 +gem5 started Jan 9 2012 14:29:08 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing +Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sav +Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt index b2588e568..d8ed7223d 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,223 +1,223 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1944621 # Simulator instruction rate (inst/s) -host_mem_usage 217656 # Number of bytes of host memory used -host_seconds 113.83 # Real time elapsed on the host -host_tick_rate 2204625935 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 221363018 # Number of instructions simulated sim_seconds 0.250961 # Number of seconds simulated sim_ticks 250960631000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 56682008 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 55107.033639 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52105.504587 # average ReadReq mshr miss latency +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 461238 # Simulator instruction rate (inst/s) +host_tick_rate 522908265 # Simulator tick rate (ticks/s) +host_mem_usage 250008 # Number of bytes of host memory used +host_seconds 479.93 # Real time elapsed on the host +sim_insts 221363018 # Number of instructions simulated +system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu.numCycles 501921262 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.num_insts 221363018 # Number of instructions executed +system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 8268471 # number of instructions that are conditional controls +system.cpu.num_int_insts 220339607 # number of integer instructions +system.cpu.num_fp_insts 2162459 # number of float instructions +system.cpu.num_int_register_reads 567557364 # number of times the integer registers were read +system.cpu.num_int_register_writes 232532006 # number of times the integer registers were written +system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read +system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written +system.cpu.num_mem_refs 77165306 # number of memory refs +system.cpu.num_load_insts 56649590 # Number of load instructions +system.cpu.num_store_insts 20515716 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 501921262 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.icache.replacements 2836 # number of replacements +system.cpu.icache.tagsinuse 1455.289108 # Cycle average of tags in use +system.cpu.icache.total_refs 173489718 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 36959.888794 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 1455.289108 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.710590 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 173489718 # number of ReadReq hits +system.cpu.icache.demand_hits 173489718 # number of demand (read+write) hits +system.cpu.icache.overall_hits 173489718 # number of overall hits +system.cpu.icache.ReadReq_misses 4694 # number of ReadReq misses +system.cpu.icache.demand_misses 4694 # number of demand (read+write) misses +system.cpu.icache.overall_misses 4694 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 185041500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 185041500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 185041500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 173494412 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 173494412 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 173494412 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000027 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000027 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 39420.856412 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 39420.856412 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 39420.856412 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 4694 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 4694 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 4694 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 170928000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 170928000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 170928000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000027 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000027 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000027 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 36414.145718 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 41 # number of replacements +system.cpu.dcache.tagsinuse 1363.451495 # Cycle average of tags in use +system.cpu.dcache.total_refs 77195833 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 40522.746982 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 1363.451495 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.332874 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits 56681681 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 18020000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 327 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 17038500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 327 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 55920.152091 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52920.152091 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 20514152 # number of WriteReq hits +system.cpu.dcache.demand_hits 77195833 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 77195833 # number of overall hits +system.cpu.dcache.ReadReq_misses 327 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1578 # number of WriteReq misses +system.cpu.dcache.demand_misses 1905 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1905 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 18020000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency 88242000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 106262000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 106262000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 56682008 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 77197738 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 77197738 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.000077 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1578 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 83508000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000077 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1578 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 40522.746982 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 55107.033639 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 55920.152091 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 55780.577428 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 55780.577428 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 77197738 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 55780.577428 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52780.314961 # average overall mshr miss latency -system.cpu.dcache.demand_hits 77195833 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 106262000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1905 # number of demand (read+write) misses +system.cpu.dcache.writebacks 7 # number of writebacks system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 327 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1578 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1905 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1905 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 17038500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 83508000 # number of WriteReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency 100546500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 100546500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000077 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1905 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 1363.451495 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.332874 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 77197738 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 55780.577428 # average overall miss latency +system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52105.504587 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52920.152091 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 52780.314961 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 52780.314961 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 77195833 # number of overall hits -system.cpu.dcache.overall_miss_latency 106262000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1905 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 100546500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1905 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 41 # number of replacements -system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks. +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1363.451495 # Cycle average of tags in use -system.cpu.dcache.total_refs 77195833 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 7 # number of writebacks -system.cpu.icache.ReadReq_accesses 173494412 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 39420.856412 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 36414.145718 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 173489718 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 185041500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 4694 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 170928000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000027 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 4694 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 36959.888794 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 173494412 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 39420.856412 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency -system.cpu.icache.demand_hits 173489718 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 185041500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000027 # miss rate for demand accesses -system.cpu.icache.demand_misses 4694 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 170928000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000027 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 4694 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 1455.289108 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.710590 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 173494412 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 39420.856412 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 173489718 # number of overall hits -system.cpu.icache.overall_miss_latency 185041500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000027 # miss rate for overall accesses -system.cpu.icache.overall_misses 4694 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 170928000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000027 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 4694 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 2836 # number of replacements -system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1455.289108 # Cycle average of tags in use -system.cpu.icache.total_refs 173489718 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 1578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 2058.168190 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1861 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3164 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.588180 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 2058.146434 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 0.021756 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.062810 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000001 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 1861 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 7 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 3 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 81900000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.998099 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_hits 1864 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 1864 # number of overall hits +system.cpu.l2cache.ReadReq_misses 3160 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 1575 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 63000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.998099 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1575 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 5021 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52004.905063 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 1861 # number of ReadReq hits +system.cpu.l2cache.demand_misses 4735 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 4735 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency 164335500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.629357 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 3160 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 126400000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.629357 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 3160 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_miss_latency 81900000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 246235500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 246235500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 5021 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 7 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 7 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.588180 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_accesses 1578 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 6599 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 6599 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.629357 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.998099 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.717533 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.717533 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52004.905063 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52003.273495 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52003.273495 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 6599 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52003.273495 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1864 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 246235500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.717533 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 4735 # number of demand (read+write) misses +system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 3160 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 1575 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 4735 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 4735 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 126400000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 63000000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency 189400000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 189400000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.629357 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.998099 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.717533 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 4735 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 2058.146434 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 0.021756 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.062810 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000001 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 6599 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52003.273495 # average overall miss latency +system.cpu.l2cache.overall_mshr_miss_rate 0.717533 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1864 # number of overall hits -system.cpu.l2cache.overall_miss_latency 246235500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.717533 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 4735 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 189400000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.717533 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 4735 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 3164 # Sample count of references to valid blocks. +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2058.168190 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1861 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 501921262 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 501921262 # Number of busy cycles -system.cpu.num_conditional_control_insts 8268471 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses -system.cpu.num_fp_insts 2162459 # number of float instructions -system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read -system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 221363018 # Number of instructions executed -system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses -system.cpu.num_int_insts 220339607 # number of integer instructions -system.cpu.num_int_register_reads 567557364 # number of times the integer registers were read -system.cpu.num_int_register_writes 232532006 # number of times the integer registers were written -system.cpu.num_load_insts 56649590 # Number of load instructions -system.cpu.num_mem_refs 77165306 # number of memory refs -system.cpu.num_store_insts 20515716 # Number of store instructions -system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |